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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.10 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1151
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T146 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.702990765 Aug 23 10:44:54 PM UTC 24 Aug 23 10:44:57 PM UTC 24 100313040 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.322158783 Aug 23 10:44:45 PM UTC 24 Aug 23 10:44:57 PM UTC 24 199825986 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.519130722 Aug 23 10:44:56 PM UTC 24 Aug 23 10:44:59 PM UTC 24 52165953 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.1077219478 Aug 23 10:44:41 PM UTC 24 Aug 23 10:45:00 PM UTC 24 3409030014 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.1555577463 Aug 23 10:44:58 PM UTC 24 Aug 23 10:45:00 PM UTC 24 36334817 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2475548116 Aug 23 10:44:56 PM UTC 24 Aug 23 10:45:00 PM UTC 24 152856196 ps
T1038 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.2598370303 Aug 23 10:45:00 PM UTC 24 Aug 23 10:45:01 PM UTC 24 51435123 ps
T1039 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.837013934 Aug 23 10:45:01 PM UTC 24 Aug 23 10:45:02 PM UTC 24 13437080 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.3697719777 Aug 23 10:44:49 PM UTC 24 Aug 23 10:45:03 PM UTC 24 577053227 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3927844344 Aug 23 10:45:01 PM UTC 24 Aug 23 10:45:03 PM UTC 24 33187015 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.2942679668 Aug 23 10:45:01 PM UTC 24 Aug 23 10:45:03 PM UTC 24 33946628 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.30089564 Aug 23 10:45:02 PM UTC 24 Aug 23 10:45:04 PM UTC 24 152785947 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3812564892 Aug 23 10:45:04 PM UTC 24 Aug 23 10:45:06 PM UTC 24 43821470 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1673562604 Aug 23 10:44:37 PM UTC 24 Aug 23 10:45:07 PM UTC 24 1680927516 ps
T1040 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1368995352 Aug 23 10:45:04 PM UTC 24 Aug 23 10:45:07 PM UTC 24 619073590 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.45218254 Aug 23 10:44:55 PM UTC 24 Aug 23 10:45:08 PM UTC 24 6985739857 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.3297705222 Aug 23 10:45:05 PM UTC 24 Aug 23 10:45:10 PM UTC 24 190568562 ps
T1041 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.3816476014 Aug 23 10:45:08 PM UTC 24 Aug 23 10:45:10 PM UTC 24 12721040 ps
T1042 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.4217390740 Aug 23 10:45:08 PM UTC 24 Aug 23 10:45:10 PM UTC 24 13751319 ps
T1043 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.1396266621 Aug 23 10:45:08 PM UTC 24 Aug 23 10:45:10 PM UTC 24 120784822 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.434484033 Aug 23 10:45:10 PM UTC 24 Aug 23 10:45:12 PM UTC 24 86985032 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.4122195292 Aug 23 10:45:10 PM UTC 24 Aug 23 10:45:13 PM UTC 24 120589735 ps
T1044 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3610961067 Aug 23 10:45:03 PM UTC 24 Aug 23 10:45:14 PM UTC 24 608353238 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.3965928582 Aug 23 10:44:58 PM UTC 24 Aug 23 10:45:15 PM UTC 24 318033656 ps
T1045 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.853500228 Aug 23 10:44:55 PM UTC 24 Aug 23 10:45:15 PM UTC 24 3603315584 ps
T1046 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1160190239 Aug 23 10:45:14 PM UTC 24 Aug 23 10:45:16 PM UTC 24 48276706 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.3936965901 Aug 23 10:45:03 PM UTC 24 Aug 23 10:45:17 PM UTC 24 1457864843 ps
T1047 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.3826981742 Aug 23 10:45:16 PM UTC 24 Aug 23 10:45:17 PM UTC 24 75167982 ps
T1048 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2289556939 Aug 23 10:45:14 PM UTC 24 Aug 23 10:45:18 PM UTC 24 192415453 ps
T1049 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.3394743403 Aug 23 10:45:12 PM UTC 24 Aug 23 10:45:19 PM UTC 24 322781022 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.355291271 Aug 23 10:45:15 PM UTC 24 Aug 23 10:45:20 PM UTC 24 208249929 ps
T1050 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.1373259689 Aug 23 10:45:17 PM UTC 24 Aug 23 10:45:20 PM UTC 24 272802762 ps
T1051 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2250430731 Aug 23 10:45:17 PM UTC 24 Aug 23 10:45:21 PM UTC 24 599973193 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.1773291518 Aug 23 10:45:18 PM UTC 24 Aug 23 10:45:21 PM UTC 24 386136900 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1633351306 Aug 23 10:45:18 PM UTC 24 Aug 23 10:45:22 PM UTC 24 148365488 ps
T1052 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.1716486358 Aug 23 10:45:20 PM UTC 24 Aug 23 10:45:22 PM UTC 24 45523136 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2506385264 Aug 23 10:45:21 PM UTC 24 Aug 23 10:45:23 PM UTC 24 208155346 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.2736641971 Aug 23 10:45:20 PM UTC 24 Aug 23 10:45:23 PM UTC 24 74604997 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3366780957 Aug 23 10:45:20 PM UTC 24 Aug 23 10:45:24 PM UTC 24 134953586 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.1825189490 Aug 23 10:45:22 PM UTC 24 Aug 23 10:45:24 PM UTC 24 303119442 ps
T1053 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.1636969408 Aug 23 10:45:23 PM UTC 24 Aug 23 10:45:25 PM UTC 24 19365612 ps
T1054 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.301557828 Aug 23 10:45:23 PM UTC 24 Aug 23 10:45:25 PM UTC 24 120908431 ps
T1055 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.856784814 Aug 23 10:45:23 PM UTC 24 Aug 23 10:45:26 PM UTC 24 427700403 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.1358304306 Aug 23 10:45:07 PM UTC 24 Aug 23 10:45:26 PM UTC 24 4069320731 ps
T1056 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.807469692 Aug 23 10:45:24 PM UTC 24 Aug 23 10:45:26 PM UTC 24 47194483 ps
T1057 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.3614485553 Aug 23 10:45:25 PM UTC 24 Aug 23 10:45:27 PM UTC 24 156381397 ps
T1058 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.3288647084 Aug 23 10:45:25 PM UTC 24 Aug 23 10:45:28 PM UTC 24 128356521 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.497455740 Aug 23 10:45:24 PM UTC 24 Aug 23 10:45:28 PM UTC 24 64553311 ps
T1059 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.1860007923 Aug 23 10:45:28 PM UTC 24 Aug 23 10:45:29 PM UTC 24 26952282 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.1349974396 Aug 23 10:45:26 PM UTC 24 Aug 23 10:45:29 PM UTC 24 211186736 ps
T1060 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3434115593 Aug 23 10:45:25 PM UTC 24 Aug 23 10:45:30 PM UTC 24 129572094 ps
T1061 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2834729558 Aug 23 10:45:26 PM UTC 24 Aug 23 10:45:30 PM UTC 24 221098474 ps
T1062 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.426957623 Aug 23 10:45:28 PM UTC 24 Aug 23 10:45:31 PM UTC 24 1528724566 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.3473105014 Aug 23 10:45:25 PM UTC 24 Aug 23 10:45:31 PM UTC 24 413030175 ps
T1063 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2298174664 Aug 23 10:45:29 PM UTC 24 Aug 23 10:45:32 PM UTC 24 387758174 ps
T1064 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.256093975 Aug 23 10:45:29 PM UTC 24 Aug 23 10:45:32 PM UTC 24 114009276 ps
T1065 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.935806018 Aug 23 10:45:31 PM UTC 24 Aug 23 10:45:33 PM UTC 24 13101485 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.1002298709 Aug 23 10:45:22 PM UTC 24 Aug 23 10:45:33 PM UTC 24 789611536 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.3782610357 Aug 23 10:45:19 PM UTC 24 Aug 23 10:45:33 PM UTC 24 9057248644 ps
T1066 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.2335933863 Aug 23 10:45:30 PM UTC 24 Aug 23 10:45:34 PM UTC 24 244182139 ps
T1067 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.1861534380 Aug 23 10:45:31 PM UTC 24 Aug 23 10:45:34 PM UTC 24 110172558 ps
T1068 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.2191955626 Aug 23 10:45:34 PM UTC 24 Aug 23 10:45:35 PM UTC 24 113136838 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.3749025975 Aug 23 10:45:16 PM UTC 24 Aug 23 10:45:36 PM UTC 24 12382680034 ps
T1069 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1879390118 Aug 23 10:45:32 PM UTC 24 Aug 23 10:45:36 PM UTC 24 88568173 ps
T1070 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.745258405 Aug 23 10:45:32 PM UTC 24 Aug 23 10:45:36 PM UTC 24 45261292 ps
T1071 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.580641374 Aug 23 10:45:10 PM UTC 24 Aug 23 10:45:37 PM UTC 24 547708513 ps
T1072 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3420424283 Aug 23 10:45:32 PM UTC 24 Aug 23 10:45:37 PM UTC 24 385676403 ps
T1073 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.51701508 Aug 23 10:45:35 PM UTC 24 Aug 23 10:45:37 PM UTC 24 27568968 ps
T1074 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.3173518719 Aug 23 10:45:36 PM UTC 24 Aug 23 10:45:38 PM UTC 24 35635758 ps
T1075 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.495091667 Aug 23 10:45:35 PM UTC 24 Aug 23 10:45:38 PM UTC 24 154877818 ps
T1076 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3293518017 Aug 23 10:45:35 PM UTC 24 Aug 23 10:45:38 PM UTC 24 82105546 ps
T1077 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.310815775 Aug 23 10:45:35 PM UTC 24 Aug 23 10:45:39 PM UTC 24 561090006 ps
T1078 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.4278391773 Aug 23 10:45:36 PM UTC 24 Aug 23 10:45:39 PM UTC 24 337321884 ps
T1079 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.2947164464 Aug 23 10:45:39 PM UTC 24 Aug 23 10:45:41 PM UTC 24 16876204 ps
T1080 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1116855630 Aug 23 10:45:37 PM UTC 24 Aug 23 10:45:41 PM UTC 24 95850948 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.2534530441 Aug 23 10:45:34 PM UTC 24 Aug 23 10:45:41 PM UTC 24 321795278 ps
T1081 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3414861303 Aug 23 10:45:37 PM UTC 24 Aug 23 10:45:42 PM UTC 24 393151421 ps
T1082 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.4260491901 Aug 23 10:45:39 PM UTC 24 Aug 23 10:45:42 PM UTC 24 101695565 ps
T1083 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3355367527 Aug 23 10:45:39 PM UTC 24 Aug 23 10:45:42 PM UTC 24 144189290 ps
T1084 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.2791170033 Aug 23 10:45:39 PM UTC 24 Aug 23 10:45:43 PM UTC 24 377739454 ps
T1085 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.4048113662 Aug 23 10:45:42 PM UTC 24 Aug 23 10:45:43 PM UTC 24 49200868 ps
T1086 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3386231134 Aug 23 10:45:39 PM UTC 24 Aug 23 10:45:43 PM UTC 24 189758424 ps
T1087 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.1518339270 Aug 23 10:45:42 PM UTC 24 Aug 23 10:45:44 PM UTC 24 217112323 ps
T1088 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.500280330 Aug 23 10:45:40 PM UTC 24 Aug 23 10:45:45 PM UTC 24 395147012 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3904015526 Aug 23 10:45:30 PM UTC 24 Aug 23 10:45:46 PM UTC 24 1181644816 ps
T1089 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.1950639347 Aug 23 10:45:44 PM UTC 24 Aug 23 10:45:46 PM UTC 24 52030809 ps
T1090 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.2391014188 Aug 23 10:45:43 PM UTC 24 Aug 23 10:45:46 PM UTC 24 93421444 ps
T1091 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.2340474145 Aug 23 10:45:40 PM UTC 24 Aug 23 10:45:47 PM UTC 24 402423779 ps
T1092 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.1622079257 Aug 23 10:45:44 PM UTC 24 Aug 23 10:45:47 PM UTC 24 378767070 ps
T1093 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.991441250 Aug 23 10:45:43 PM UTC 24 Aug 23 10:45:47 PM UTC 24 167382095 ps
T1094 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.696856915 Aug 23 10:45:43 PM UTC 24 Aug 23 10:45:48 PM UTC 24 199975020 ps
T1095 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4180059815 Aug 23 10:45:44 PM UTC 24 Aug 23 10:45:48 PM UTC 24 196049750 ps
T1096 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.3566034561 Aug 23 10:45:47 PM UTC 24 Aug 23 10:45:49 PM UTC 24 13057967 ps
T1097 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.2580786267 Aug 23 10:45:28 PM UTC 24 Aug 23 10:45:49 PM UTC 24 4517688601 ps
T1098 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.3736945428 Aug 23 10:45:43 PM UTC 24 Aug 23 10:45:50 PM UTC 24 361922437 ps
T1099 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.3389676340 Aug 23 10:45:47 PM UTC 24 Aug 23 10:45:50 PM UTC 24 30169910 ps
T1100 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.1351784777 Aug 23 10:45:46 PM UTC 24 Aug 23 10:45:50 PM UTC 24 294530438 ps
T1101 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1045499319 Aug 23 10:45:46 PM UTC 24 Aug 23 10:45:50 PM UTC 24 109977199 ps
T1102 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.2863172671 Aug 23 10:45:39 PM UTC 24 Aug 23 10:45:50 PM UTC 24 192571363 ps
T1103 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.287691242 Aug 23 10:45:49 PM UTC 24 Aug 23 10:45:50 PM UTC 24 136030160 ps
T1104 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3420333843 Aug 23 10:45:47 PM UTC 24 Aug 23 10:45:51 PM UTC 24 106881783 ps
T1105 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.1033100777 Aug 23 10:45:49 PM UTC 24 Aug 23 10:45:52 PM UTC 24 745527410 ps
T1106 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.541597891 Aug 23 10:45:49 PM UTC 24 Aug 23 10:45:52 PM UTC 24 387999955 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.539443993 Aug 23 10:45:36 PM UTC 24 Aug 23 10:45:52 PM UTC 24 1084812963 ps
T1107 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2542024326 Aug 23 10:45:48 PM UTC 24 Aug 23 10:45:52 PM UTC 24 91560017 ps
T1108 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.24366058 Aug 23 10:45:50 PM UTC 24 Aug 23 10:45:52 PM UTC 24 480681933 ps
T1109 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.3472279215 Aug 23 10:45:52 PM UTC 24 Aug 23 10:45:53 PM UTC 24 47885245 ps
T1110 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1045672098 Aug 23 10:45:50 PM UTC 24 Aug 23 10:45:54 PM UTC 24 137486432 ps
T1111 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.3144863193 Aug 23 10:45:52 PM UTC 24 Aug 23 10:45:54 PM UTC 24 213020608 ps
T1112 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.171710708 Aug 23 10:45:54 PM UTC 24 Aug 23 10:45:55 PM UTC 24 13564952 ps
T1113 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2574706987 Aug 23 10:45:52 PM UTC 24 Aug 23 10:45:55 PM UTC 24 210351545 ps
T1114 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.3439815504 Aug 23 10:45:54 PM UTC 24 Aug 23 10:45:56 PM UTC 24 67533128 ps
T1115 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2648743308 Aug 23 10:45:52 PM UTC 24 Aug 23 10:45:56 PM UTC 24 604141511 ps
T1116 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.2737958908 Aug 23 10:45:52 PM UTC 24 Aug 23 10:45:56 PM UTC 24 1226647300 ps
T1117 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4135525596 Aug 23 10:45:54 PM UTC 24 Aug 23 10:45:56 PM UTC 24 51005554 ps
T1118 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.53261485 Aug 23 10:45:55 PM UTC 24 Aug 23 10:45:57 PM UTC 24 248214119 ps
T1119 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.3288443707 Aug 23 10:45:58 PM UTC 24 Aug 23 10:46:00 PM UTC 24 37546230 ps
T1120 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.2990428346 Aug 23 10:45:58 PM UTC 24 Aug 23 10:46:00 PM UTC 24 18672055 ps
T1121 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1209627432 Aug 23 10:45:54 PM UTC 24 Aug 23 10:45:57 PM UTC 24 79408390 ps
T1122 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.2510923601 Aug 23 10:45:55 PM UTC 24 Aug 23 10:45:57 PM UTC 24 55999563 ps
T1123 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.347294720 Aug 23 10:45:55 PM UTC 24 Aug 23 10:45:57 PM UTC 24 16323926 ps
T1124 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.1829459815 Aug 23 10:45:55 PM UTC 24 Aug 23 10:45:57 PM UTC 24 17751994 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.705295290 Aug 23 10:45:47 PM UTC 24 Aug 23 10:45:57 PM UTC 24 822644319 ps
T1125 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.2203449929 Aug 23 10:45:52 PM UTC 24 Aug 23 10:45:58 PM UTC 24 874257423 ps
T1126 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.294227571 Aug 23 10:45:58 PM UTC 24 Aug 23 10:46:00 PM UTC 24 123346868 ps
T1127 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.3230312953 Aug 23 10:45:58 PM UTC 24 Aug 23 10:46:00 PM UTC 24 11252838 ps
T1128 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.4161685856 Aug 23 10:45:58 PM UTC 24 Aug 23 10:46:00 PM UTC 24 31960188 ps
T1129 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.224306661 Aug 23 10:45:58 PM UTC 24 Aug 23 10:46:00 PM UTC 24 102480474 ps
T1130 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.3035964033 Aug 23 10:45:58 PM UTC 24 Aug 23 10:46:00 PM UTC 24 14670539 ps
T1131 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.2795880540 Aug 23 10:45:58 PM UTC 24 Aug 23 10:46:00 PM UTC 24 46548248 ps
T1132 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.344980510 Aug 23 10:45:54 PM UTC 24 Aug 23 10:46:00 PM UTC 24 217441599 ps
T1133 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.1936073753 Aug 23 10:45:58 PM UTC 24 Aug 23 10:46:00 PM UTC 24 56066949 ps
T1134 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.3526372005 Aug 23 10:45:58 PM UTC 24 Aug 23 10:46:00 PM UTC 24 41056605 ps
T1135 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.868805753 Aug 23 10:45:58 PM UTC 24 Aug 23 10:46:00 PM UTC 24 27037625 ps
T1136 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.3710800285 Aug 23 10:45:58 PM UTC 24 Aug 23 10:46:00 PM UTC 24 16692111 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.2288697108 Aug 23 10:45:49 PM UTC 24 Aug 23 10:46:00 PM UTC 24 835248403 ps
T1137 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.1289778097 Aug 23 10:46:00 PM UTC 24 Aug 23 10:46:02 PM UTC 24 16406059 ps
T1138 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.1528822048 Aug 23 10:46:00 PM UTC 24 Aug 23 10:46:02 PM UTC 24 15509590 ps
T1139 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.3141461689 Aug 23 10:46:00 PM UTC 24 Aug 23 10:46:02 PM UTC 24 12621185 ps
T1140 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.2842991251 Aug 23 10:46:00 PM UTC 24 Aug 23 10:46:02 PM UTC 24 22512143 ps
T1141 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.1689066251 Aug 23 10:45:52 PM UTC 24 Aug 23 10:46:03 PM UTC 24 402291034 ps
T1142 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.1817801201 Aug 23 10:46:04 PM UTC 24 Aug 23 10:46:05 PM UTC 24 18881555 ps
T1143 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.1031799961 Aug 23 10:46:04 PM UTC 24 Aug 23 10:46:05 PM UTC 24 149485220 ps
T1144 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.1676046305 Aug 23 10:46:04 PM UTC 24 Aug 23 10:46:05 PM UTC 24 11412823 ps
T1145 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.4154931176 Aug 23 10:46:04 PM UTC 24 Aug 23 10:46:05 PM UTC 24 22354632 ps
T1146 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.3442110257 Aug 23 10:46:04 PM UTC 24 Aug 23 10:46:06 PM UTC 24 14436075 ps
T1147 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.1839936862 Aug 23 10:46:04 PM UTC 24 Aug 23 10:46:06 PM UTC 24 47086275 ps
T1148 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.2428179855 Aug 23 10:46:04 PM UTC 24 Aug 23 10:46:06 PM UTC 24 17425414 ps
T1149 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.3650483752 Aug 23 10:46:04 PM UTC 24 Aug 23 10:46:06 PM UTC 24 48015620 ps
T1150 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.2264254111 Aug 23 10:46:04 PM UTC 24 Aug 23 10:46:06 PM UTC 24 15211892 ps
T1151 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.2169970071 Aug 23 10:46:04 PM UTC 24 Aug 23 10:46:06 PM UTC 24 13651341 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.1725724314
Short name T10
Test name
Test status
Simulation time 42951273 ps
CPU time 2.11 seconds
Started Aug 23 10:21:53 PM UTC 24
Finished Aug 23 10:21:56 PM UTC 24
Peak memory 242168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725724314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1725724314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.3158429357
Short name T37
Test name
Test status
Simulation time 8425854040 ps
CPU time 80.3 seconds
Started Aug 23 10:21:54 PM UTC 24
Finished Aug 23 10:23:16 PM UTC 24
Peak memory 278756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158429357 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.3158429357
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.2879311828
Short name T53
Test name
Test status
Simulation time 1247156764 ps
CPU time 12.6 seconds
Started Aug 23 10:21:57 PM UTC 24
Finished Aug 23 10:22:11 PM UTC 24
Peak memory 261960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879311828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2879311828
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.1909982677
Short name T28
Test name
Test status
Simulation time 1386682541 ps
CPU time 10.08 seconds
Started Aug 23 10:21:52 PM UTC 24
Finished Aug 23 10:22:03 PM UTC 24
Peak memory 227828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909982677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1909982677
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.1427533398
Short name T183
Test name
Test status
Simulation time 42153176033 ps
CPU time 182.37 seconds
Started Aug 23 10:24:38 PM UTC 24
Finished Aug 23 10:27:43 PM UTC 24
Peak memory 301320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427533398 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.1427533398
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.4017984013
Short name T121
Test name
Test status
Simulation time 1059999334 ps
CPU time 19.09 seconds
Started Aug 23 10:44:34 PM UTC 24
Finished Aug 23 10:44:55 PM UTC 24
Peak memory 226200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017984013 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.4017984013
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.3677659267
Short name T21
Test name
Test status
Simulation time 1509950700 ps
CPU time 4.07 seconds
Started Aug 23 10:22:01 PM UTC 24
Finished Aug 23 10:22:06 PM UTC 24
Peak memory 231596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677659267 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.3677659267
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.4006227020
Short name T39
Test name
Test status
Simulation time 29284870915 ps
CPU time 65.98 seconds
Started Aug 23 10:23:34 PM UTC 24
Finished Aug 23 10:24:42 PM UTC 24
Peak memory 251908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006227020 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.4006227020
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.108813389
Short name T56
Test name
Test status
Simulation time 4712841289 ps
CPU time 23.9 seconds
Started Aug 23 10:22:18 PM UTC 24
Finished Aug 23 10:22:43 PM UTC 24
Peak memory 264336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108813389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.108813389
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.1399944166
Short name T65
Test name
Test status
Simulation time 7695936805 ps
CPU time 87.71 seconds
Started Aug 23 10:22:04 PM UTC 24
Finished Aug 23 10:23:34 PM UTC 24
Peak memory 276744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399944166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.1399944166
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.2887471892
Short name T177
Test name
Test status
Simulation time 19875720193 ps
CPU time 185.98 seconds
Started Aug 23 10:25:13 PM UTC 24
Finished Aug 23 10:28:21 PM UTC 24
Peak memory 278532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887471892 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.2887471892
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.1369931258
Short name T1
Test name
Test status
Simulation time 32261082 ps
CPU time 0.62 seconds
Started Aug 23 10:21:51 PM UTC 24
Finished Aug 23 10:21:53 PM UTC 24
Peak memory 226840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369931258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1369931258
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.1864603502
Short name T223
Test name
Test status
Simulation time 64100969146 ps
CPU time 238.93 seconds
Started Aug 23 10:22:22 PM UTC 24
Finished Aug 23 10:26:25 PM UTC 24
Peak memory 282852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864603502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1864603502
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.627125893
Short name T154
Test name
Test status
Simulation time 10223230632 ps
CPU time 132.86 seconds
Started Aug 23 10:23:03 PM UTC 24
Finished Aug 23 10:25:18 PM UTC 24
Peak memory 280588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627125893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.627125893
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.3467256064
Short name T9
Test name
Test status
Simulation time 75103864 ps
CPU time 0.84 seconds
Started Aug 23 10:21:54 PM UTC 24
Finished Aug 23 10:21:56 PM UTC 24
Peak memory 257680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467256064 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3467256064
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.3021793177
Short name T49
Test name
Test status
Simulation time 17442380012 ps
CPU time 131.77 seconds
Started Aug 23 10:22:04 PM UTC 24
Finished Aug 23 10:24:19 PM UTC 24
Peak memory 264208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021793177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3021793177
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.59036292
Short name T40
Test name
Test status
Simulation time 28898471426 ps
CPU time 291.78 seconds
Started Aug 23 10:21:54 PM UTC 24
Finished Aug 23 10:26:49 PM UTC 24
Peak memory 276492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59036292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.59036292
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.963735783
Short name T120
Test name
Test status
Simulation time 373512380 ps
CPU time 4.08 seconds
Started Aug 23 10:44:46 PM UTC 24
Finished Aug 23 10:44:51 PM UTC 24
Peak memory 224284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963735783 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.963735783
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.3307479513
Short name T216
Test name
Test status
Simulation time 74166409124 ps
CPU time 627.32 seconds
Started Aug 23 10:23:06 PM UTC 24
Finished Aug 23 10:33:40 PM UTC 24
Peak memory 278536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307479513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.3307479513
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.2048452619
Short name T233
Test name
Test status
Simulation time 13083064631 ps
CPU time 75.25 seconds
Started Aug 23 10:26:38 PM UTC 24
Finished Aug 23 10:27:55 PM UTC 24
Peak memory 264192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048452619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.2048452619
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3098066392
Short name T99
Test name
Test status
Simulation time 23350914 ps
CPU time 1.14 seconds
Started Aug 23 10:44:43 PM UTC 24
Finished Aug 23 10:44:45 PM UTC 24
Peak memory 212852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098066392 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.3098066392
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.2447834474
Short name T103
Test name
Test status
Simulation time 29096723839 ps
CPU time 29.4 seconds
Started Aug 23 10:23:37 PM UTC 24
Finished Aug 23 10:24:08 PM UTC 24
Peak memory 227804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447834474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2447834474
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.2000838787
Short name T19
Test name
Test status
Simulation time 1420105850 ps
CPU time 4.22 seconds
Started Aug 23 10:21:57 PM UTC 24
Finished Aug 23 10:22:03 PM UTC 24
Peak memory 235344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000838787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2000838787
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.3092914145
Short name T4
Test name
Test status
Simulation time 246595212 ps
CPU time 0.94 seconds
Started Aug 23 10:21:51 PM UTC 24
Finished Aug 23 10:21:54 PM UTC 24
Peak memory 228912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092914145 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_parity.3092914145
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.614662003
Short name T318
Test name
Test status
Simulation time 101659849777 ps
CPU time 436.99 seconds
Started Aug 23 10:31:16 PM UTC 24
Finished Aug 23 10:38:38 PM UTC 24
Peak memory 276512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614662003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.614662003
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.2811682884
Short name T187
Test name
Test status
Simulation time 10959414759 ps
CPU time 109.98 seconds
Started Aug 23 10:23:01 PM UTC 24
Finished Aug 23 10:24:53 PM UTC 24
Peak memory 264404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811682884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.2811682884
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.3738267119
Short name T210
Test name
Test status
Simulation time 24196652485 ps
CPU time 61.27 seconds
Started Aug 23 10:31:43 PM UTC 24
Finished Aug 23 10:32:46 PM UTC 24
Peak memory 262172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738267119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.3738267119
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.486877672
Short name T29
Test name
Test status
Simulation time 7548694143 ps
CPU time 13.25 seconds
Started Aug 23 10:21:52 PM UTC 24
Finished Aug 23 10:22:06 PM UTC 24
Peak memory 227828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486877672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.486877672
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.2595527805
Short name T294
Test name
Test status
Simulation time 186867375232 ps
CPU time 301.15 seconds
Started Aug 23 10:27:17 PM UTC 24
Finished Aug 23 10:32:22 PM UTC 24
Peak memory 264140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595527805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2595527805
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.3761915461
Short name T274
Test name
Test status
Simulation time 3129794544 ps
CPU time 60.37 seconds
Started Aug 23 10:37:15 PM UTC 24
Finished Aug 23 10:38:17 PM UTC 24
Peak memory 278752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761915461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.3761915461
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.1031603912
Short name T72
Test name
Test status
Simulation time 58226732820 ps
CPU time 237.11 seconds
Started Aug 23 10:22:36 PM UTC 24
Finished Aug 23 10:26:37 PM UTC 24
Peak memory 282660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031603912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1031603912
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.3749025975
Short name T193
Test name
Test status
Simulation time 12382680034 ps
CPU time 18.59 seconds
Started Aug 23 10:45:16 PM UTC 24
Finished Aug 23 10:45:36 PM UTC 24
Peak memory 224196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749025975 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.3749025975
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1386759506
Short name T277
Test name
Test status
Simulation time 320273632379 ps
CPU time 645.13 seconds
Started Aug 23 10:24:37 PM UTC 24
Finished Aug 23 10:35:29 PM UTC 24
Peak memory 278600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386759506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.1386759506
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.2086686215
Short name T209
Test name
Test status
Simulation time 76873441075 ps
CPU time 478.09 seconds
Started Aug 23 10:24:31 PM UTC 24
Finished Aug 23 10:32:34 PM UTC 24
Peak memory 278472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086686215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.2086686215
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.2243659397
Short name T114
Test name
Test status
Simulation time 358898890726 ps
CPU time 428.36 seconds
Started Aug 23 10:21:53 PM UTC 24
Finished Aug 23 10:29:06 PM UTC 24
Peak memory 276428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243659397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.2243659397
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.1824221323
Short name T93
Test name
Test status
Simulation time 26011434 ps
CPU time 0.63 seconds
Started Aug 23 10:22:07 PM UTC 24
Finished Aug 23 10:22:09 PM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824221323 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1824221323
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.4009930816
Short name T140
Test name
Test status
Simulation time 10710524767 ps
CPU time 32.52 seconds
Started Aug 23 10:22:01 PM UTC 24
Finished Aug 23 10:22:34 PM UTC 24
Peak memory 245860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009930816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4009930816
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.798046563
Short name T211
Test name
Test status
Simulation time 111949637745 ps
CPU time 187.93 seconds
Started Aug 23 10:27:19 PM UTC 24
Finished Aug 23 10:30:30 PM UTC 24
Peak memory 245484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798046563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.798046563
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.494330039
Short name T335
Test name
Test status
Simulation time 35420621206 ps
CPU time 318 seconds
Started Aug 23 10:34:37 PM UTC 24
Finished Aug 23 10:39:59 PM UTC 24
Peak memory 266340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494330039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.494330039
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/28.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_stress_all.583460579
Short name T494
Test name
Test status
Simulation time 8841390591 ps
CPU time 64.86 seconds
Started Aug 23 10:28:07 PM UTC 24
Finished Aug 23 10:29:14 PM UTC 24
Peak memory 251924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583460579 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.583460579
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.1764228576
Short name T50
Test name
Test status
Simulation time 49560319439 ps
CPU time 130.93 seconds
Started Aug 23 10:22:23 PM UTC 24
Finished Aug 23 10:24:37 PM UTC 24
Peak memory 266440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764228576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.1764228576
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.2737958908
Short name T1116
Test name
Test status
Simulation time 1226647300 ps
CPU time 3.12 seconds
Started Aug 23 10:45:52 PM UTC 24
Finished Aug 23 10:45:56 PM UTC 24
Peak memory 224268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737958908 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.2737958908
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.3965928582
Short name T192
Test name
Test status
Simulation time 318033656 ps
CPU time 16.14 seconds
Started Aug 23 10:44:58 PM UTC 24
Finished Aug 23 10:45:15 PM UTC 24
Peak memory 224136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965928582 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.3965928582
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_all.2983115096
Short name T204
Test name
Test status
Simulation time 1138928982 ps
CPU time 23.73 seconds
Started Aug 23 10:26:59 PM UTC 24
Finished Aug 23 10:27:24 PM UTC 24
Peak memory 268136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983115096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2983115096
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode.242848953
Short name T342
Test name
Test status
Simulation time 812126246 ps
CPU time 12.72 seconds
Started Aug 23 10:29:38 PM UTC 24
Finished Aug 23 10:29:52 PM UTC 24
Peak memory 247908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242848953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.242848953
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/21.spi_device_stress_all.4150281287
Short name T302
Test name
Test status
Simulation time 8494636716 ps
CPU time 29.04 seconds
Started Aug 23 10:30:54 PM UTC 24
Finished Aug 23 10:31:25 PM UTC 24
Peak memory 235472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150281287 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.4150281287
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/21.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_all.1384371928
Short name T316
Test name
Test status
Simulation time 75572794393 ps
CPU time 466.75 seconds
Started Aug 23 10:31:37 PM UTC 24
Finished Aug 23 10:39:29 PM UTC 24
Peak memory 282572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384371928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1384371928
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/23.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.1130466428
Short name T250
Test name
Test status
Simulation time 20265327274 ps
CPU time 120.93 seconds
Started Aug 23 10:31:34 PM UTC 24
Finished Aug 23 10:33:38 PM UTC 24
Peak memory 276424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130466428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.1130466428
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode.420862772
Short name T345
Test name
Test status
Simulation time 4083297521 ps
CPU time 43.65 seconds
Started Aug 23 10:39:13 PM UTC 24
Finished Aug 23 10:39:59 PM UTC 24
Peak memory 262112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420862772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.420862772
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/37.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.1206312524
Short name T67
Test name
Test status
Simulation time 114476989251 ps
CPU time 185.21 seconds
Started Aug 23 10:22:01 PM UTC 24
Finished Aug 23 10:25:09 PM UTC 24
Peak memory 266224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206312524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1206312524
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.612169208
Short name T263
Test name
Test status
Simulation time 18941549454 ps
CPU time 161.91 seconds
Started Aug 23 10:26:12 PM UTC 24
Finished Aug 23 10:28:56 PM UTC 24
Peak memory 268328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612169208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.612169208
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.146265309
Short name T348
Test name
Test status
Simulation time 1067898738 ps
CPU time 7.61 seconds
Started Aug 23 10:26:03 PM UTC 24
Finished Aug 23 10:26:11 PM UTC 24
Peak memory 245608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146265309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.146265309
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.1184060127
Short name T313
Test name
Test status
Simulation time 125560030059 ps
CPU time 436.05 seconds
Started Aug 23 10:28:38 PM UTC 24
Finished Aug 23 10:35:59 PM UTC 24
Peak memory 268332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184060127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1184060127
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_all.2927685702
Short name T373
Test name
Test status
Simulation time 3590442281 ps
CPU time 10.31 seconds
Started Aug 23 10:36:32 PM UTC 24
Finished Aug 23 10:36:44 PM UTC 24
Peak memory 228092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927685702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2927685702
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/32.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.2417237769
Short name T329
Test name
Test status
Simulation time 43617092886 ps
CPU time 223.82 seconds
Started Aug 23 10:37:19 PM UTC 24
Finished Aug 23 10:41:06 PM UTC 24
Peak memory 284896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417237769 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.2417237769
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/33.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.3962032888
Short name T311
Test name
Test status
Simulation time 140968740062 ps
CPU time 168.08 seconds
Started Aug 23 10:42:53 PM UTC 24
Finished Aug 23 10:45:45 PM UTC 24
Peak memory 266188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962032888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3962032888
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/45.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.2964986620
Short name T119
Test name
Test status
Simulation time 138762141 ps
CPU time 3.33 seconds
Started Aug 23 10:44:40 PM UTC 24
Finished Aug 23 10:44:44 PM UTC 24
Peak memory 224252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964986620 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2964986620
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2768714924
Short name T98
Test name
Test status
Simulation time 27781671 ps
CPU time 1.15 seconds
Started Aug 23 10:44:36 PM UTC 24
Finished Aug 23 10:44:39 PM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768714924 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.2768714924
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.705295290
Short name T132
Test name
Test status
Simulation time 822644319 ps
CPU time 9.37 seconds
Started Aug 23 10:45:47 PM UTC 24
Finished Aug 23 10:45:57 PM UTC 24
Peak memory 226020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705295290 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.705295290
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.2931516370
Short name T2
Test name
Test status
Simulation time 41578289 ps
CPU time 0.73 seconds
Started Aug 23 10:21:51 PM UTC 24
Finished Aug 23 10:21:53 PM UTC 24
Peak memory 215652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931516370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2931516370
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1720300541
Short name T144
Test name
Test status
Simulation time 1519182344 ps
CPU time 12.93 seconds
Started Aug 23 10:44:37 PM UTC 24
Finished Aug 23 10:44:52 PM UTC 24
Peak memory 224068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720300541 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.1720300541
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1673562604
Short name T150
Test name
Test status
Simulation time 1680927516 ps
CPU time 28.3 seconds
Started Aug 23 10:44:37 PM UTC 24
Finished Aug 23 10:45:07 PM UTC 24
Peak memory 224248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673562604 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.1673562604
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3544729553
Short name T118
Test name
Test status
Simulation time 94858922 ps
CPU time 1.32 seconds
Started Aug 23 10:44:40 PM UTC 24
Finished Aug 23 10:44:42 PM UTC 24
Peak memory 225060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3544729553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.spi_device_csr_mem_rw_with_rand_reset.3544729553
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2636298557
Short name T142
Test name
Test status
Simulation time 175752352 ps
CPU time 2.03 seconds
Started Aug 23 10:44:36 PM UTC 24
Finished Aug 23 10:44:40 PM UTC 24
Peak memory 224136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636298557 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2636298557
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2724464550
Short name T1031
Test name
Test status
Simulation time 11151204 ps
CPU time 0.59 seconds
Started Aug 23 10:44:34 PM UTC 24
Finished Aug 23 10:44:36 PM UTC 24
Peak memory 211784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724464550 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2724464550
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.3234485151
Short name T141
Test name
Test status
Simulation time 915637942 ps
CPU time 1.77 seconds
Started Aug 23 10:44:36 PM UTC 24
Finished Aug 23 10:44:39 PM UTC 24
Peak memory 222224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234485151 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.3234485151
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2010294706
Short name T1032
Test name
Test status
Simulation time 12727751 ps
CPU time 0.56 seconds
Started Aug 23 10:44:35 PM UTC 24
Finished Aug 23 10:44:37 PM UTC 24
Peak memory 211384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010294706 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.2010294706
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1075834420
Short name T166
Test name
Test status
Simulation time 999782613 ps
CPU time 2.66 seconds
Started Aug 23 10:44:39 PM UTC 24
Finished Aug 23 10:44:42 PM UTC 24
Peak memory 224036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075834420 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstanding.1075834420
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.2963129219
Short name T117
Test name
Test status
Simulation time 751362436 ps
CPU time 3.99 seconds
Started Aug 23 10:44:32 PM UTC 24
Finished Aug 23 10:44:37 PM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963129219 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2963129219
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.322158783
Short name T147
Test name
Test status
Simulation time 199825986 ps
CPU time 10.97 seconds
Started Aug 23 10:44:45 PM UTC 24
Finished Aug 23 10:44:57 PM UTC 24
Peak memory 214028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322158783 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.322158783
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2655464334
Short name T1037
Test name
Test status
Simulation time 645225507 ps
CPU time 10.49 seconds
Started Aug 23 10:44:44 PM UTC 24
Finished Aug 23 10:44:56 PM UTC 24
Peak memory 224068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655464334 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.2655464334
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2766332306
Short name T137
Test name
Test status
Simulation time 357003872 ps
CPU time 2.02 seconds
Started Aug 23 10:44:46 PM UTC 24
Finished Aug 23 10:44:49 PM UTC 24
Peak memory 227512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2766332306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.spi_device_csr_mem_rw_with_rand_reset.2766332306
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2681332354
Short name T167
Test name
Test status
Simulation time 79661069 ps
CPU time 1.55 seconds
Started Aug 23 10:44:43 PM UTC 24
Finished Aug 23 10:44:45 PM UTC 24
Peak memory 222884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681332354 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2681332354
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.2344514459
Short name T1033
Test name
Test status
Simulation time 20236143 ps
CPU time 0.63 seconds
Started Aug 23 10:44:41 PM UTC 24
Finished Aug 23 10:44:42 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344514459 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2344514459
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.2195562986
Short name T143
Test name
Test status
Simulation time 62638793 ps
CPU time 1.72 seconds
Started Aug 23 10:44:43 PM UTC 24
Finished Aug 23 10:44:46 PM UTC 24
Peak memory 222928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195562986 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.2195562986
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.442883370
Short name T1034
Test name
Test status
Simulation time 11335653 ps
CPU time 0.56 seconds
Started Aug 23 10:44:42 PM UTC 24
Finished Aug 23 10:44:43 PM UTC 24
Peak memory 211448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442883370 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.442883370
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3198309822
Short name T168
Test name
Test status
Simulation time 77060379 ps
CPU time 1.61 seconds
Started Aug 23 10:44:46 PM UTC 24
Finished Aug 23 10:44:49 PM UTC 24
Peak memory 223648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198309822 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstanding.3198309822
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.1077219478
Short name T122
Test name
Test status
Simulation time 3409030014 ps
CPU time 17.94 seconds
Started Aug 23 10:44:41 PM UTC 24
Finished Aug 23 10:45:00 PM UTC 24
Peak memory 224356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077219478 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.1077219478
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1879390118
Short name T1069
Test name
Test status
Simulation time 88568173 ps
CPU time 2.11 seconds
Started Aug 23 10:45:32 PM UTC 24
Finished Aug 23 10:45:36 PM UTC 24
Peak memory 228064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1879390118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
10.spi_device_csr_mem_rw_with_rand_reset.1879390118
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.1861534380
Short name T1067
Test name
Test status
Simulation time 110172558 ps
CPU time 1.52 seconds
Started Aug 23 10:45:31 PM UTC 24
Finished Aug 23 10:45:34 PM UTC 24
Peak memory 212652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861534380 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.1861534380
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.935806018
Short name T1065
Test name
Test status
Simulation time 13101485 ps
CPU time 0.63 seconds
Started Aug 23 10:45:31 PM UTC 24
Finished Aug 23 10:45:33 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935806018 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.935806018
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.745258405
Short name T1070
Test name
Test status
Simulation time 45261292 ps
CPU time 2.39 seconds
Started Aug 23 10:45:32 PM UTC 24
Finished Aug 23 10:45:36 PM UTC 24
Peak memory 224136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745258405 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstanding.745258405
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.2335933863
Short name T1066
Test name
Test status
Simulation time 244182139 ps
CPU time 2.51 seconds
Started Aug 23 10:45:30 PM UTC 24
Finished Aug 23 10:45:34 PM UTC 24
Peak memory 225760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335933863 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.2335933863
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3904015526
Short name T191
Test name
Test status
Simulation time 1181644816 ps
CPU time 14.75 seconds
Started Aug 23 10:45:30 PM UTC 24
Finished Aug 23 10:45:46 PM UTC 24
Peak memory 223608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904015526 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.3904015526
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.495091667
Short name T1075
Test name
Test status
Simulation time 154877818 ps
CPU time 2.38 seconds
Started Aug 23 10:45:35 PM UTC 24
Finished Aug 23 10:45:38 PM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=495091667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
11.spi_device_csr_mem_rw_with_rand_reset.495091667
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.51701508
Short name T1073
Test name
Test status
Simulation time 27568968 ps
CPU time 1.3 seconds
Started Aug 23 10:45:35 PM UTC 24
Finished Aug 23 10:45:37 PM UTC 24
Peak memory 222864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51701508 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.51701508
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.2191955626
Short name T1068
Test name
Test status
Simulation time 113136838 ps
CPU time 0.6 seconds
Started Aug 23 10:45:34 PM UTC 24
Finished Aug 23 10:45:35 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191955626 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.2191955626
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3293518017
Short name T1076
Test name
Test status
Simulation time 82105546 ps
CPU time 2.4 seconds
Started Aug 23 10:45:35 PM UTC 24
Finished Aug 23 10:45:38 PM UTC 24
Peak memory 224072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293518017 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstanding.3293518017
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3420424283
Short name T1072
Test name
Test status
Simulation time 385676403 ps
CPU time 3.74 seconds
Started Aug 23 10:45:32 PM UTC 24
Finished Aug 23 10:45:37 PM UTC 24
Peak memory 226336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420424283 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.3420424283
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.2534530441
Short name T199
Test name
Test status
Simulation time 321795278 ps
CPU time 6.41 seconds
Started Aug 23 10:45:34 PM UTC 24
Finished Aug 23 10:45:41 PM UTC 24
Peak memory 224068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534530441 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.2534530441
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1116855630
Short name T1080
Test name
Test status
Simulation time 95850948 ps
CPU time 2.36 seconds
Started Aug 23 10:45:37 PM UTC 24
Finished Aug 23 10:45:41 PM UTC 24
Peak memory 226168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1116855630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
12.spi_device_csr_mem_rw_with_rand_reset.1116855630
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.4278391773
Short name T1078
Test name
Test status
Simulation time 337321884 ps
CPU time 2.18 seconds
Started Aug 23 10:45:36 PM UTC 24
Finished Aug 23 10:45:39 PM UTC 24
Peak memory 224080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278391773 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.4278391773
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.3173518719
Short name T1074
Test name
Test status
Simulation time 35635758 ps
CPU time 0.62 seconds
Started Aug 23 10:45:36 PM UTC 24
Finished Aug 23 10:45:38 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173518719 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.3173518719
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3414861303
Short name T1081
Test name
Test status
Simulation time 393151421 ps
CPU time 3.76 seconds
Started Aug 23 10:45:37 PM UTC 24
Finished Aug 23 10:45:42 PM UTC 24
Peak memory 224332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414861303 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstanding.3414861303
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.310815775
Short name T1077
Test name
Test status
Simulation time 561090006 ps
CPU time 2.6 seconds
Started Aug 23 10:45:35 PM UTC 24
Finished Aug 23 10:45:39 PM UTC 24
Peak memory 226500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310815775 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.310815775
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.539443993
Short name T194
Test name
Test status
Simulation time 1084812963 ps
CPU time 14.54 seconds
Started Aug 23 10:45:36 PM UTC 24
Finished Aug 23 10:45:52 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539443993 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.539443993
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3355367527
Short name T1083
Test name
Test status
Simulation time 144189290 ps
CPU time 2.33 seconds
Started Aug 23 10:45:39 PM UTC 24
Finished Aug 23 10:45:42 PM UTC 24
Peak memory 226188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3355367527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
13.spi_device_csr_mem_rw_with_rand_reset.3355367527
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.4260491901
Short name T1082
Test name
Test status
Simulation time 101695565 ps
CPU time 2.34 seconds
Started Aug 23 10:45:39 PM UTC 24
Finished Aug 23 10:45:42 PM UTC 24
Peak memory 224144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260491901 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.4260491901
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.2947164464
Short name T1079
Test name
Test status
Simulation time 16876204 ps
CPU time 0.66 seconds
Started Aug 23 10:45:39 PM UTC 24
Finished Aug 23 10:45:41 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947164464 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.2947164464
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3386231134
Short name T1086
Test name
Test status
Simulation time 189758424 ps
CPU time 3.36 seconds
Started Aug 23 10:45:39 PM UTC 24
Finished Aug 23 10:45:43 PM UTC 24
Peak memory 224096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386231134 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstanding.3386231134
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.2791170033
Short name T1084
Test name
Test status
Simulation time 377739454 ps
CPU time 3.06 seconds
Started Aug 23 10:45:39 PM UTC 24
Finished Aug 23 10:45:43 PM UTC 24
Peak memory 226024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791170033 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.2791170033
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.2863172671
Short name T1102
Test name
Test status
Simulation time 192571363 ps
CPU time 10.04 seconds
Started Aug 23 10:45:39 PM UTC 24
Finished Aug 23 10:45:50 PM UTC 24
Peak memory 225728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863172671 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.2863172671
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.991441250
Short name T1093
Test name
Test status
Simulation time 167382095 ps
CPU time 3.14 seconds
Started Aug 23 10:45:43 PM UTC 24
Finished Aug 23 10:45:47 PM UTC 24
Peak memory 226168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=991441250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
14.spi_device_csr_mem_rw_with_rand_reset.991441250
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.1518339270
Short name T1087
Test name
Test status
Simulation time 217112323 ps
CPU time 1.53 seconds
Started Aug 23 10:45:42 PM UTC 24
Finished Aug 23 10:45:44 PM UTC 24
Peak memory 222872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518339270 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.1518339270
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.4048113662
Short name T1085
Test name
Test status
Simulation time 49200868 ps
CPU time 0.65 seconds
Started Aug 23 10:45:42 PM UTC 24
Finished Aug 23 10:45:43 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048113662 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.4048113662
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.696856915
Short name T1094
Test name
Test status
Simulation time 199975020 ps
CPU time 3.66 seconds
Started Aug 23 10:45:43 PM UTC 24
Finished Aug 23 10:45:48 PM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696856915 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstanding.696856915
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.500280330
Short name T1088
Test name
Test status
Simulation time 395147012 ps
CPU time 4 seconds
Started Aug 23 10:45:40 PM UTC 24
Finished Aug 23 10:45:45 PM UTC 24
Peak memory 226564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500280330 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.500280330
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.2340474145
Short name T1091
Test name
Test status
Simulation time 402423779 ps
CPU time 5.23 seconds
Started Aug 23 10:45:40 PM UTC 24
Finished Aug 23 10:45:47 PM UTC 24
Peak memory 224264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340474145 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.2340474145
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1045499319
Short name T1101
Test name
Test status
Simulation time 109977199 ps
CPU time 3.15 seconds
Started Aug 23 10:45:46 PM UTC 24
Finished Aug 23 10:45:50 PM UTC 24
Peak memory 228316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1045499319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
15.spi_device_csr_mem_rw_with_rand_reset.1045499319
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.1622079257
Short name T1092
Test name
Test status
Simulation time 378767070 ps
CPU time 1.59 seconds
Started Aug 23 10:45:44 PM UTC 24
Finished Aug 23 10:45:47 PM UTC 24
Peak memory 222892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622079257 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.1622079257
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.1950639347
Short name T1089
Test name
Test status
Simulation time 52030809 ps
CPU time 0.66 seconds
Started Aug 23 10:45:44 PM UTC 24
Finished Aug 23 10:45:46 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950639347 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.1950639347
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4180059815
Short name T1095
Test name
Test status
Simulation time 196049750 ps
CPU time 2.31 seconds
Started Aug 23 10:45:44 PM UTC 24
Finished Aug 23 10:45:48 PM UTC 24
Peak memory 224072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180059815 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstanding.4180059815
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.2391014188
Short name T1090
Test name
Test status
Simulation time 93421444 ps
CPU time 2.26 seconds
Started Aug 23 10:45:43 PM UTC 24
Finished Aug 23 10:45:46 PM UTC 24
Peak memory 224512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391014188 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.2391014188
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.3736945428
Short name T1098
Test name
Test status
Simulation time 361922437 ps
CPU time 5.44 seconds
Started Aug 23 10:45:43 PM UTC 24
Finished Aug 23 10:45:50 PM UTC 24
Peak memory 226204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736945428 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.3736945428
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2542024326
Short name T1107
Test name
Test status
Simulation time 91560017 ps
CPU time 2.24 seconds
Started Aug 23 10:45:48 PM UTC 24
Finished Aug 23 10:45:52 PM UTC 24
Peak memory 226084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2542024326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.spi_device_csr_mem_rw_with_rand_reset.2542024326
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.3389676340
Short name T1099
Test name
Test status
Simulation time 30169910 ps
CPU time 1.72 seconds
Started Aug 23 10:45:47 PM UTC 24
Finished Aug 23 10:45:50 PM UTC 24
Peak memory 222872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389676340 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.3389676340
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.3566034561
Short name T1096
Test name
Test status
Simulation time 13057967 ps
CPU time 0.63 seconds
Started Aug 23 10:45:47 PM UTC 24
Finished Aug 23 10:45:49 PM UTC 24
Peak memory 211364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566034561 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.3566034561
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3420333843
Short name T1104
Test name
Test status
Simulation time 106881783 ps
CPU time 2.39 seconds
Started Aug 23 10:45:47 PM UTC 24
Finished Aug 23 10:45:51 PM UTC 24
Peak memory 224144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420333843 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstanding.3420333843
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.1351784777
Short name T1100
Test name
Test status
Simulation time 294530438 ps
CPU time 3.05 seconds
Started Aug 23 10:45:46 PM UTC 24
Finished Aug 23 10:45:50 PM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351784777 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.1351784777
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1045672098
Short name T1110
Test name
Test status
Simulation time 137486432 ps
CPU time 3.02 seconds
Started Aug 23 10:45:50 PM UTC 24
Finished Aug 23 10:45:54 PM UTC 24
Peak memory 228296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1045672098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
17.spi_device_csr_mem_rw_with_rand_reset.1045672098
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.1033100777
Short name T1105
Test name
Test status
Simulation time 745527410 ps
CPU time 1.94 seconds
Started Aug 23 10:45:49 PM UTC 24
Finished Aug 23 10:45:52 PM UTC 24
Peak memory 222892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033100777 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.1033100777
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.287691242
Short name T1103
Test name
Test status
Simulation time 136030160 ps
CPU time 0.6 seconds
Started Aug 23 10:45:49 PM UTC 24
Finished Aug 23 10:45:50 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287691242 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.287691242
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.24366058
Short name T1108
Test name
Test status
Simulation time 480681933 ps
CPU time 1.47 seconds
Started Aug 23 10:45:50 PM UTC 24
Finished Aug 23 10:45:52 PM UTC 24
Peak memory 213300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24366058 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstanding.24366058
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.541597891
Short name T1106
Test name
Test status
Simulation time 387999955 ps
CPU time 2.12 seconds
Started Aug 23 10:45:49 PM UTC 24
Finished Aug 23 10:45:52 PM UTC 24
Peak memory 226336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541597891 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.541597891
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.2288697108
Short name T198
Test name
Test status
Simulation time 835248403 ps
CPU time 10.72 seconds
Started Aug 23 10:45:49 PM UTC 24
Finished Aug 23 10:46:00 PM UTC 24
Peak memory 226120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288697108 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.2288697108
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2574706987
Short name T1113
Test name
Test status
Simulation time 210351545 ps
CPU time 2.28 seconds
Started Aug 23 10:45:52 PM UTC 24
Finished Aug 23 10:45:55 PM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2574706987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
18.spi_device_csr_mem_rw_with_rand_reset.2574706987
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.3144863193
Short name T1111
Test name
Test status
Simulation time 213020608 ps
CPU time 1.61 seconds
Started Aug 23 10:45:52 PM UTC 24
Finished Aug 23 10:45:54 PM UTC 24
Peak memory 212652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144863193 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.3144863193
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.3472279215
Short name T1109
Test name
Test status
Simulation time 47885245 ps
CPU time 0.61 seconds
Started Aug 23 10:45:52 PM UTC 24
Finished Aug 23 10:45:53 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472279215 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.3472279215
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2648743308
Short name T1115
Test name
Test status
Simulation time 604141511 ps
CPU time 2.9 seconds
Started Aug 23 10:45:52 PM UTC 24
Finished Aug 23 10:45:56 PM UTC 24
Peak memory 224364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648743308 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstanding.2648743308
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.2203449929
Short name T1125
Test name
Test status
Simulation time 874257423 ps
CPU time 4.79 seconds
Started Aug 23 10:45:52 PM UTC 24
Finished Aug 23 10:45:58 PM UTC 24
Peak memory 226340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203449929 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.2203449929
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.1689066251
Short name T1141
Test name
Test status
Simulation time 402291034 ps
CPU time 9.94 seconds
Started Aug 23 10:45:52 PM UTC 24
Finished Aug 23 10:46:03 PM UTC 24
Peak memory 226184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689066251 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.1689066251
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4135525596
Short name T1117
Test name
Test status
Simulation time 51005554 ps
CPU time 1.42 seconds
Started Aug 23 10:45:54 PM UTC 24
Finished Aug 23 10:45:56 PM UTC 24
Peak memory 222992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4135525596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
19.spi_device_csr_mem_rw_with_rand_reset.4135525596
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.3439815504
Short name T1114
Test name
Test status
Simulation time 67533128 ps
CPU time 1.02 seconds
Started Aug 23 10:45:54 PM UTC 24
Finished Aug 23 10:45:56 PM UTC 24
Peak memory 222872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439815504 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.3439815504
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.171710708
Short name T1112
Test name
Test status
Simulation time 13564952 ps
CPU time 0.63 seconds
Started Aug 23 10:45:54 PM UTC 24
Finished Aug 23 10:45:55 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171710708 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.171710708
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1209627432
Short name T1121
Test name
Test status
Simulation time 79408390 ps
CPU time 2.18 seconds
Started Aug 23 10:45:54 PM UTC 24
Finished Aug 23 10:45:57 PM UTC 24
Peak memory 224132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209627432 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstanding.1209627432
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.344980510
Short name T1132
Test name
Test status
Simulation time 217441599 ps
CPU time 5.26 seconds
Started Aug 23 10:45:54 PM UTC 24
Finished Aug 23 10:46:00 PM UTC 24
Peak memory 226396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344980510 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.344980510
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.853500228
Short name T1045
Test name
Test status
Simulation time 3603315584 ps
CPU time 18.88 seconds
Started Aug 23 10:44:55 PM UTC 24
Finished Aug 23 10:45:15 PM UTC 24
Peak memory 213896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853500228 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.853500228
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.45218254
Short name T151
Test name
Test status
Simulation time 6985739857 ps
CPU time 11.27 seconds
Started Aug 23 10:44:55 PM UTC 24
Finished Aug 23 10:45:08 PM UTC 24
Peak memory 216272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45218254 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.45218254
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3327258886
Short name T100
Test name
Test status
Simulation time 273281168 ps
CPU time 0.78 seconds
Started Aug 23 10:44:53 PM UTC 24
Finished Aug 23 10:44:55 PM UTC 24
Peak memory 213056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327258886 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.3327258886
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.519130722
Short name T134
Test name
Test status
Simulation time 52165953 ps
CPU time 1.46 seconds
Started Aug 23 10:44:56 PM UTC 24
Finished Aug 23 10:44:59 PM UTC 24
Peak memory 222996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=519130722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.spi_device_csr_mem_rw_with_rand_reset.519130722
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.702990765
Short name T146
Test name
Test status
Simulation time 100313040 ps
CPU time 1.07 seconds
Started Aug 23 10:44:54 PM UTC 24
Finished Aug 23 10:44:57 PM UTC 24
Peak memory 222860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702990765 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.702990765
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.3549527034
Short name T1035
Test name
Test status
Simulation time 47182860 ps
CPU time 0.61 seconds
Started Aug 23 10:44:50 PM UTC 24
Finished Aug 23 10:44:52 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549527034 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3549527034
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.1284752463
Short name T145
Test name
Test status
Simulation time 61529286 ps
CPU time 1.12 seconds
Started Aug 23 10:44:52 PM UTC 24
Finished Aug 23 10:44:55 PM UTC 24
Peak memory 222928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284752463 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.1284752463
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.1308126853
Short name T1036
Test name
Test status
Simulation time 41182022 ps
CPU time 0.56 seconds
Started Aug 23 10:44:52 PM UTC 24
Finished Aug 23 10:44:54 PM UTC 24
Peak memory 211384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308126853 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.1308126853
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2475548116
Short name T171
Test name
Test status
Simulation time 152856196 ps
CPU time 2.82 seconds
Started Aug 23 10:44:56 PM UTC 24
Finished Aug 23 10:45:00 PM UTC 24
Peak memory 224132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475548116 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstanding.2475548116
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.3697719777
Short name T123
Test name
Test status
Simulation time 577053227 ps
CPU time 11.97 seconds
Started Aug 23 10:44:49 PM UTC 24
Finished Aug 23 10:45:03 PM UTC 24
Peak memory 232236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697719777 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.3697719777
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.2510923601
Short name T1122
Test name
Test status
Simulation time 55999563 ps
CPU time 0.66 seconds
Started Aug 23 10:45:55 PM UTC 24
Finished Aug 23 10:45:57 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510923601 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.2510923601
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/20.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.53261485
Short name T1118
Test name
Test status
Simulation time 248214119 ps
CPU time 0.63 seconds
Started Aug 23 10:45:55 PM UTC 24
Finished Aug 23 10:45:57 PM UTC 24
Peak memory 211464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53261485 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.53261485
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/21.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.1829459815
Short name T1124
Test name
Test status
Simulation time 17751994 ps
CPU time 0.66 seconds
Started Aug 23 10:45:55 PM UTC 24
Finished Aug 23 10:45:57 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829459815 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.1829459815
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/22.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.347294720
Short name T1123
Test name
Test status
Simulation time 16323926 ps
CPU time 0.65 seconds
Started Aug 23 10:45:55 PM UTC 24
Finished Aug 23 10:45:57 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347294720 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.347294720
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/23.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.4161685856
Short name T1128
Test name
Test status
Simulation time 31960188 ps
CPU time 0.63 seconds
Started Aug 23 10:45:58 PM UTC 24
Finished Aug 23 10:46:00 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161685856 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.4161685856
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/24.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.3035964033
Short name T1130
Test name
Test status
Simulation time 14670539 ps
CPU time 0.65 seconds
Started Aug 23 10:45:58 PM UTC 24
Finished Aug 23 10:46:00 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035964033 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.3035964033
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/25.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.3230312953
Short name T1127
Test name
Test status
Simulation time 11252838 ps
CPU time 0.63 seconds
Started Aug 23 10:45:58 PM UTC 24
Finished Aug 23 10:46:00 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230312953 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.3230312953
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/26.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.2795880540
Short name T1131
Test name
Test status
Simulation time 46548248 ps
CPU time 0.64 seconds
Started Aug 23 10:45:58 PM UTC 24
Finished Aug 23 10:46:00 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795880540 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.2795880540
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/27.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.1936073753
Short name T1133
Test name
Test status
Simulation time 56066949 ps
CPU time 0.74 seconds
Started Aug 23 10:45:58 PM UTC 24
Finished Aug 23 10:46:00 PM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936073753 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.1936073753
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/28.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.3288443707
Short name T1119
Test name
Test status
Simulation time 37546230 ps
CPU time 0.62 seconds
Started Aug 23 10:45:58 PM UTC 24
Finished Aug 23 10:46:00 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288443707 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.3288443707
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/29.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.3936965901
Short name T172
Test name
Test status
Simulation time 1457864843 ps
CPU time 12.99 seconds
Started Aug 23 10:45:03 PM UTC 24
Finished Aug 23 10:45:17 PM UTC 24
Peak memory 213784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936965901 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.3936965901
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3610961067
Short name T1044
Test name
Test status
Simulation time 608353238 ps
CPU time 10.25 seconds
Started Aug 23 10:45:03 PM UTC 24
Finished Aug 23 10:45:14 PM UTC 24
Peak memory 213832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610961067 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.3610961067
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3927844344
Short name T101
Test name
Test status
Simulation time 33187015 ps
CPU time 1.01 seconds
Started Aug 23 10:45:01 PM UTC 24
Finished Aug 23 10:45:03 PM UTC 24
Peak memory 213308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927844344 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.3927844344
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3812564892
Short name T138
Test name
Test status
Simulation time 43821470 ps
CPU time 1.24 seconds
Started Aug 23 10:45:04 PM UTC 24
Finished Aug 23 10:45:06 PM UTC 24
Peak memory 222992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3812564892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.spi_device_csr_mem_rw_with_rand_reset.3812564892
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.30089564
Short name T149
Test name
Test status
Simulation time 152785947 ps
CPU time 0.99 seconds
Started Aug 23 10:45:02 PM UTC 24
Finished Aug 23 10:45:04 PM UTC 24
Peak memory 212648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30089564 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.30089564
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.2598370303
Short name T1038
Test name
Test status
Simulation time 51435123 ps
CPU time 0.6 seconds
Started Aug 23 10:45:00 PM UTC 24
Finished Aug 23 10:45:01 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598370303 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2598370303
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.2942679668
Short name T148
Test name
Test status
Simulation time 33946628 ps
CPU time 1.06 seconds
Started Aug 23 10:45:01 PM UTC 24
Finished Aug 23 10:45:03 PM UTC 24
Peak memory 222928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942679668 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.2942679668
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.837013934
Short name T1039
Test name
Test status
Simulation time 13437080 ps
CPU time 0.56 seconds
Started Aug 23 10:45:01 PM UTC 24
Finished Aug 23 10:45:02 PM UTC 24
Peak memory 211448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837013934 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.837013934
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1368995352
Short name T1040
Test name
Test status
Simulation time 619073590 ps
CPU time 2.48 seconds
Started Aug 23 10:45:04 PM UTC 24
Finished Aug 23 10:45:07 PM UTC 24
Peak memory 224212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368995352 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstanding.1368995352
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.1555577463
Short name T126
Test name
Test status
Simulation time 36334817 ps
CPU time 1.63 seconds
Started Aug 23 10:44:58 PM UTC 24
Finished Aug 23 10:45:00 PM UTC 24
Peak memory 223020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555577463 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1555577463
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.294227571
Short name T1126
Test name
Test status
Simulation time 123346868 ps
CPU time 0.66 seconds
Started Aug 23 10:45:58 PM UTC 24
Finished Aug 23 10:46:00 PM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294227571 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.294227571
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/30.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.3710800285
Short name T1136
Test name
Test status
Simulation time 16692111 ps
CPU time 0.73 seconds
Started Aug 23 10:45:58 PM UTC 24
Finished Aug 23 10:46:00 PM UTC 24
Peak memory 211516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710800285 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.3710800285
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/31.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.2990428346
Short name T1120
Test name
Test status
Simulation time 18672055 ps
CPU time 0.65 seconds
Started Aug 23 10:45:58 PM UTC 24
Finished Aug 23 10:46:00 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990428346 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.2990428346
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/32.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.224306661
Short name T1129
Test name
Test status
Simulation time 102480474 ps
CPU time 0.58 seconds
Started Aug 23 10:45:58 PM UTC 24
Finished Aug 23 10:46:00 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224306661 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.224306661
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/33.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.3526372005
Short name T1134
Test name
Test status
Simulation time 41056605 ps
CPU time 0.59 seconds
Started Aug 23 10:45:58 PM UTC 24
Finished Aug 23 10:46:00 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526372005 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.3526372005
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/34.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.868805753
Short name T1135
Test name
Test status
Simulation time 27037625 ps
CPU time 0.62 seconds
Started Aug 23 10:45:58 PM UTC 24
Finished Aug 23 10:46:00 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868805753 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.868805753
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/35.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.1289778097
Short name T1137
Test name
Test status
Simulation time 16406059 ps
CPU time 0.66 seconds
Started Aug 23 10:46:00 PM UTC 24
Finished Aug 23 10:46:02 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289778097 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.1289778097
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/36.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.1528822048
Short name T1138
Test name
Test status
Simulation time 15509590 ps
CPU time 0.61 seconds
Started Aug 23 10:46:00 PM UTC 24
Finished Aug 23 10:46:02 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528822048 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.1528822048
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/37.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.2842991251
Short name T1140
Test name
Test status
Simulation time 22512143 ps
CPU time 0.65 seconds
Started Aug 23 10:46:00 PM UTC 24
Finished Aug 23 10:46:02 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842991251 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.2842991251
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/38.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.3141461689
Short name T1139
Test name
Test status
Simulation time 12621185 ps
CPU time 0.62 seconds
Started Aug 23 10:46:00 PM UTC 24
Finished Aug 23 10:46:02 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141461689 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.3141461689
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/39.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.3394743403
Short name T1049
Test name
Test status
Simulation time 322781022 ps
CPU time 6.68 seconds
Started Aug 23 10:45:12 PM UTC 24
Finished Aug 23 10:45:19 PM UTC 24
Peak memory 213896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394743403 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.3394743403
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.580641374
Short name T1071
Test name
Test status
Simulation time 547708513 ps
CPU time 25 seconds
Started Aug 23 10:45:10 PM UTC 24
Finished Aug 23 10:45:37 PM UTC 24
Peak memory 213836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580641374 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.580641374
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.434484033
Short name T152
Test name
Test status
Simulation time 86985032 ps
CPU time 0.98 seconds
Started Aug 23 10:45:10 PM UTC 24
Finished Aug 23 10:45:12 PM UTC 24
Peak memory 213668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434484033 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.434484033
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1160190239
Short name T1046
Test name
Test status
Simulation time 48276706 ps
CPU time 1.33 seconds
Started Aug 23 10:45:14 PM UTC 24
Finished Aug 23 10:45:16 PM UTC 24
Peak memory 225036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1160190239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.spi_device_csr_mem_rw_with_rand_reset.1160190239
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.4122195292
Short name T153
Test name
Test status
Simulation time 120589735 ps
CPU time 1.17 seconds
Started Aug 23 10:45:10 PM UTC 24
Finished Aug 23 10:45:13 PM UTC 24
Peak memory 212644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122195292 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4122195292
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.4217390740
Short name T1042
Test name
Test status
Simulation time 13751319 ps
CPU time 0.59 seconds
Started Aug 23 10:45:08 PM UTC 24
Finished Aug 23 10:45:10 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217390740 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.4217390740
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.1396266621
Short name T1043
Test name
Test status
Simulation time 120784822 ps
CPU time 1.05 seconds
Started Aug 23 10:45:08 PM UTC 24
Finished Aug 23 10:45:10 PM UTC 24
Peak memory 222928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396266621 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.1396266621
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.3816476014
Short name T1041
Test name
Test status
Simulation time 12721040 ps
CPU time 0.57 seconds
Started Aug 23 10:45:08 PM UTC 24
Finished Aug 23 10:45:10 PM UTC 24
Peak memory 211384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816476014 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.3816476014
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2289556939
Short name T1048
Test name
Test status
Simulation time 192415453 ps
CPU time 3.11 seconds
Started Aug 23 10:45:14 PM UTC 24
Finished Aug 23 10:45:18 PM UTC 24
Peak memory 224116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289556939 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstanding.2289556939
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.3297705222
Short name T128
Test name
Test status
Simulation time 190568562 ps
CPU time 3.81 seconds
Started Aug 23 10:45:05 PM UTC 24
Finished Aug 23 10:45:10 PM UTC 24
Peak memory 224488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297705222 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3297705222
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.1358304306
Short name T182
Test name
Test status
Simulation time 4069320731 ps
CPU time 18.06 seconds
Started Aug 23 10:45:07 PM UTC 24
Finished Aug 23 10:45:26 PM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358304306 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.1358304306
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.1817801201
Short name T1142
Test name
Test status
Simulation time 18881555 ps
CPU time 0.63 seconds
Started Aug 23 10:46:04 PM UTC 24
Finished Aug 23 10:46:05 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817801201 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.1817801201
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/40.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.4154931176
Short name T1145
Test name
Test status
Simulation time 22354632 ps
CPU time 0.65 seconds
Started Aug 23 10:46:04 PM UTC 24
Finished Aug 23 10:46:05 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154931176 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.4154931176
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/41.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.1676046305
Short name T1144
Test name
Test status
Simulation time 11412823 ps
CPU time 0.6 seconds
Started Aug 23 10:46:04 PM UTC 24
Finished Aug 23 10:46:05 PM UTC 24
Peak memory 211384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676046305 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.1676046305
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/42.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.1031799961
Short name T1143
Test name
Test status
Simulation time 149485220 ps
CPU time 0.6 seconds
Started Aug 23 10:46:04 PM UTC 24
Finished Aug 23 10:46:05 PM UTC 24
Peak memory 211516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031799961 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.1031799961
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/43.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.3442110257
Short name T1146
Test name
Test status
Simulation time 14436075 ps
CPU time 0.65 seconds
Started Aug 23 10:46:04 PM UTC 24
Finished Aug 23 10:46:06 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442110257 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.3442110257
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/44.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.1839936862
Short name T1147
Test name
Test status
Simulation time 47086275 ps
CPU time 0.68 seconds
Started Aug 23 10:46:04 PM UTC 24
Finished Aug 23 10:46:06 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839936862 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.1839936862
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/45.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.2428179855
Short name T1148
Test name
Test status
Simulation time 17425414 ps
CPU time 0.64 seconds
Started Aug 23 10:46:04 PM UTC 24
Finished Aug 23 10:46:06 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428179855 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.2428179855
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/46.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.3650483752
Short name T1149
Test name
Test status
Simulation time 48015620 ps
CPU time 0.62 seconds
Started Aug 23 10:46:04 PM UTC 24
Finished Aug 23 10:46:06 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650483752 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.3650483752
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/47.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.2264254111
Short name T1150
Test name
Test status
Simulation time 15211892 ps
CPU time 0.62 seconds
Started Aug 23 10:46:04 PM UTC 24
Finished Aug 23 10:46:06 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264254111 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.2264254111
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/48.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.2169970071
Short name T1151
Test name
Test status
Simulation time 13651341 ps
CPU time 0.6 seconds
Started Aug 23 10:46:04 PM UTC 24
Finished Aug 23 10:46:06 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169970071 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.2169970071
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/49.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1633351306
Short name T136
Test name
Test status
Simulation time 148365488 ps
CPU time 2.67 seconds
Started Aug 23 10:45:18 PM UTC 24
Finished Aug 23 10:45:22 PM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1633351306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
5.spi_device_csr_mem_rw_with_rand_reset.1633351306
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.1373259689
Short name T1050
Test name
Test status
Simulation time 272802762 ps
CPU time 1.76 seconds
Started Aug 23 10:45:17 PM UTC 24
Finished Aug 23 10:45:20 PM UTC 24
Peak memory 223000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373259689 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1373259689
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.3826981742
Short name T1047
Test name
Test status
Simulation time 75167982 ps
CPU time 0.64 seconds
Started Aug 23 10:45:16 PM UTC 24
Finished Aug 23 10:45:17 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826981742 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3826981742
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2250430731
Short name T1051
Test name
Test status
Simulation time 599973193 ps
CPU time 3.15 seconds
Started Aug 23 10:45:17 PM UTC 24
Finished Aug 23 10:45:21 PM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250430731 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstanding.2250430731
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.355291271
Short name T129
Test name
Test status
Simulation time 208249929 ps
CPU time 3.91 seconds
Started Aug 23 10:45:15 PM UTC 24
Finished Aug 23 10:45:20 PM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355291271 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.355291271
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2506385264
Short name T135
Test name
Test status
Simulation time 208155346 ps
CPU time 1.47 seconds
Started Aug 23 10:45:21 PM UTC 24
Finished Aug 23 10:45:23 PM UTC 24
Peak memory 222992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2506385264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
6.spi_device_csr_mem_rw_with_rand_reset.2506385264
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.2736641971
Short name T173
Test name
Test status
Simulation time 74604997 ps
CPU time 1.65 seconds
Started Aug 23 10:45:20 PM UTC 24
Finished Aug 23 10:45:23 PM UTC 24
Peak memory 214888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736641971 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2736641971
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.1716486358
Short name T1052
Test name
Test status
Simulation time 45523136 ps
CPU time 0.61 seconds
Started Aug 23 10:45:20 PM UTC 24
Finished Aug 23 10:45:22 PM UTC 24
Peak memory 211020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716486358 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1716486358
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3366780957
Short name T174
Test name
Test status
Simulation time 134953586 ps
CPU time 2.52 seconds
Started Aug 23 10:45:20 PM UTC 24
Finished Aug 23 10:45:24 PM UTC 24
Peak memory 224144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366780957 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstanding.3366780957
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.1773291518
Short name T130
Test name
Test status
Simulation time 386136900 ps
CPU time 2.21 seconds
Started Aug 23 10:45:18 PM UTC 24
Finished Aug 23 10:45:21 PM UTC 24
Peak memory 226296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773291518 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1773291518
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.3782610357
Short name T196
Test name
Test status
Simulation time 9057248644 ps
CPU time 13.03 seconds
Started Aug 23 10:45:19 PM UTC 24
Finished Aug 23 10:45:33 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782610357 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.3782610357
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.807469692
Short name T1056
Test name
Test status
Simulation time 47194483 ps
CPU time 1.32 seconds
Started Aug 23 10:45:24 PM UTC 24
Finished Aug 23 10:45:26 PM UTC 24
Peak memory 222992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=807469692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
7.spi_device_csr_mem_rw_with_rand_reset.807469692
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.856784814
Short name T1055
Test name
Test status
Simulation time 427700403 ps
CPU time 1.96 seconds
Started Aug 23 10:45:23 PM UTC 24
Finished Aug 23 10:45:26 PM UTC 24
Peak memory 222940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856784814 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.856784814
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.1636969408
Short name T1053
Test name
Test status
Simulation time 19365612 ps
CPU time 0.62 seconds
Started Aug 23 10:45:23 PM UTC 24
Finished Aug 23 10:45:25 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636969408 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1636969408
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.301557828
Short name T1054
Test name
Test status
Simulation time 120908431 ps
CPU time 1.46 seconds
Started Aug 23 10:45:23 PM UTC 24
Finished Aug 23 10:45:25 PM UTC 24
Peak memory 225188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301557828 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstanding.301557828
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.1825189490
Short name T127
Test name
Test status
Simulation time 303119442 ps
CPU time 1.73 seconds
Started Aug 23 10:45:22 PM UTC 24
Finished Aug 23 10:45:24 PM UTC 24
Peak memory 225068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825189490 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1825189490
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.1002298709
Short name T195
Test name
Test status
Simulation time 789611536 ps
CPU time 10.59 seconds
Started Aug 23 10:45:22 PM UTC 24
Finished Aug 23 10:45:33 PM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002298709 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.1002298709
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2834729558
Short name T1061
Test name
Test status
Simulation time 221098474 ps
CPU time 2.77 seconds
Started Aug 23 10:45:26 PM UTC 24
Finished Aug 23 10:45:30 PM UTC 24
Peak memory 226248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2834729558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
8.spi_device_csr_mem_rw_with_rand_reset.2834729558
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.3288647084
Short name T1058
Test name
Test status
Simulation time 128356521 ps
CPU time 1.69 seconds
Started Aug 23 10:45:25 PM UTC 24
Finished Aug 23 10:45:28 PM UTC 24
Peak memory 222864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288647084 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3288647084
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.3614485553
Short name T1057
Test name
Test status
Simulation time 156381397 ps
CPU time 0.68 seconds
Started Aug 23 10:45:25 PM UTC 24
Finished Aug 23 10:45:27 PM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614485553 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3614485553
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3434115593
Short name T1060
Test name
Test status
Simulation time 129572094 ps
CPU time 3.33 seconds
Started Aug 23 10:45:25 PM UTC 24
Finished Aug 23 10:45:30 PM UTC 24
Peak memory 224112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434115593 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstanding.3434115593
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.497455740
Short name T131
Test name
Test status
Simulation time 64553311 ps
CPU time 3.38 seconds
Started Aug 23 10:45:24 PM UTC 24
Finished Aug 23 10:45:28 PM UTC 24
Peak memory 224544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497455740 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.497455740
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.3473105014
Short name T197
Test name
Test status
Simulation time 413030175 ps
CPU time 5.09 seconds
Started Aug 23 10:45:25 PM UTC 24
Finished Aug 23 10:45:31 PM UTC 24
Peak memory 226188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473105014 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.3473105014
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2298174664
Short name T1063
Test name
Test status
Simulation time 387758174 ps
CPU time 2.15 seconds
Started Aug 23 10:45:29 PM UTC 24
Finished Aug 23 10:45:32 PM UTC 24
Peak memory 226180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2298174664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
9.spi_device_csr_mem_rw_with_rand_reset.2298174664
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.426957623
Short name T1062
Test name
Test status
Simulation time 1528724566 ps
CPU time 2.37 seconds
Started Aug 23 10:45:28 PM UTC 24
Finished Aug 23 10:45:31 PM UTC 24
Peak memory 224320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426957623 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.426957623
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.1860007923
Short name T1059
Test name
Test status
Simulation time 26952282 ps
CPU time 0.63 seconds
Started Aug 23 10:45:28 PM UTC 24
Finished Aug 23 10:45:29 PM UTC 24
Peak memory 210352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860007923 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1860007923
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.256093975
Short name T1064
Test name
Test status
Simulation time 114009276 ps
CPU time 2.42 seconds
Started Aug 23 10:45:29 PM UTC 24
Finished Aug 23 10:45:32 PM UTC 24
Peak memory 224140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256093975 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstanding.256093975
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.1349974396
Short name T133
Test name
Test status
Simulation time 211186736 ps
CPU time 1.76 seconds
Started Aug 23 10:45:26 PM UTC 24
Finished Aug 23 10:45:29 PM UTC 24
Peak memory 223256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349974396 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1349974396
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.2580786267
Short name T1097
Test name
Test status
Simulation time 4517688601 ps
CPU time 20.14 seconds
Started Aug 23 10:45:28 PM UTC 24
Finished Aug 23 10:45:49 PM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580786267 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.2580786267
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.72389891
Short name T6
Test name
Test status
Simulation time 13994801 ps
CPU time 0.61 seconds
Started Aug 23 10:21:54 PM UTC 24
Finished Aug 23 10:21:56 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72389891 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.72389891
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.3282754564
Short name T227
Test name
Test status
Simulation time 105399340528 ps
CPU time 195.33 seconds
Started Aug 23 10:21:54 PM UTC 24
Finished Aug 23 10:25:12 PM UTC 24
Peak memory 280320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282754564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3282754564
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.944240947
Short name T97
Test name
Test status
Simulation time 112028837670 ps
CPU time 194.01 seconds
Started Aug 23 10:21:54 PM UTC 24
Finished Aug 23 10:25:11 PM UTC 24
Peak memory 264004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944240947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.944240947
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.3668214394
Short name T11
Test name
Test status
Simulation time 558784343 ps
CPU time 3.73 seconds
Started Aug 23 10:21:53 PM UTC 24
Finished Aug 23 10:21:58 PM UTC 24
Peak memory 235364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668214394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3668214394
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.169871208
Short name T7
Test name
Test status
Simulation time 161548246 ps
CPU time 1.95 seconds
Started Aug 23 10:21:53 PM UTC 24
Finished Aug 23 10:21:56 PM UTC 24
Peak memory 233608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169871208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.169871208
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.3475086216
Short name T18
Test name
Test status
Simulation time 1166795021 ps
CPU time 8.54 seconds
Started Aug 23 10:21:53 PM UTC 24
Finished Aug 23 10:22:02 PM UTC 24
Peak memory 251752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475086216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3475086216
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2339798149
Short name T16
Test name
Test status
Simulation time 400264776 ps
CPU time 6.04 seconds
Started Aug 23 10:21:53 PM UTC 24
Finished Aug 23 10:22:00 PM UTC 24
Peak memory 245520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339798149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.2339798149
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.923578562
Short name T14
Test name
Test status
Simulation time 529054867 ps
CPU time 5.5 seconds
Started Aug 23 10:21:53 PM UTC 24
Finished Aug 23 10:21:59 PM UTC 24
Peak memory 251748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923578562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.923578562
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.2843514910
Short name T13
Test name
Test status
Simulation time 876622086 ps
CPU time 5.06 seconds
Started Aug 23 10:21:53 PM UTC 24
Finished Aug 23 10:21:59 PM UTC 24
Peak memory 231604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843514910 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.2843514910
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.3174146145
Short name T5
Test name
Test status
Simulation time 92546387 ps
CPU time 0.98 seconds
Started Aug 23 10:21:53 PM UTC 24
Finished Aug 23 10:21:55 PM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174146145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3174146145
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.2210999376
Short name T3
Test name
Test status
Simulation time 12302259 ps
CPU time 0.6 seconds
Started Aug 23 10:21:52 PM UTC 24
Finished Aug 23 10:21:53 PM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210999376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2210999376
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.3085023982
Short name T55
Test name
Test status
Simulation time 8559052362 ps
CPU time 23.27 seconds
Started Aug 23 10:21:53 PM UTC 24
Finished Aug 23 10:22:17 PM UTC 24
Peak memory 245640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085023982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3085023982
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/0.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1997973323
Short name T88
Test name
Test status
Simulation time 10232787685 ps
CPU time 12.53 seconds
Started Aug 23 10:22:00 PM UTC 24
Finished Aug 23 10:22:14 PM UTC 24
Peak memory 245928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997973323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1997973323
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.376120205
Short name T8
Test name
Test status
Simulation time 17476046 ps
CPU time 0.7 seconds
Started Aug 23 10:21:54 PM UTC 24
Finished Aug 23 10:21:56 PM UTC 24
Peak memory 215800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376120205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.376120205
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.1492091754
Short name T57
Test name
Test status
Simulation time 14146232834 ps
CPU time 53.87 seconds
Started Aug 23 10:22:01 PM UTC 24
Finished Aug 23 10:22:56 PM UTC 24
Peak memory 266188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492091754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.1492091754
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.453836604
Short name T110
Test name
Test status
Simulation time 73285314783 ps
CPU time 51.68 seconds
Started Aug 23 10:21:58 PM UTC 24
Finished Aug 23 10:22:52 PM UTC 24
Peak memory 245960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453836604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.453836604
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.2057697044
Short name T27
Test name
Test status
Simulation time 38834741 ps
CPU time 0.98 seconds
Started Aug 23 10:21:54 PM UTC 24
Finished Aug 23 10:21:56 PM UTC 24
Peak memory 229148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057697044 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_parity.2057697044
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.1555746823
Short name T20
Test name
Test status
Simulation time 1386840842 ps
CPU time 5.27 seconds
Started Aug 23 10:21:57 PM UTC 24
Finished Aug 23 10:22:04 PM UTC 24
Peak memory 235284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555746823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.1555746823
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.3707789688
Short name T22
Test name
Test status
Simulation time 234648556 ps
CPU time 0.93 seconds
Started Aug 23 10:22:05 PM UTC 24
Finished Aug 23 10:22:07 PM UTC 24
Peak memory 257680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707789688 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3707789688
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.1215164722
Short name T36
Test name
Test status
Simulation time 7368760180 ps
CPU time 68.77 seconds
Started Aug 23 10:22:04 PM UTC 24
Finished Aug 23 10:23:15 PM UTC 24
Peak memory 278560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215164722 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.1215164722
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.3230910698
Short name T44
Test name
Test status
Simulation time 6320976458 ps
CPU time 32.06 seconds
Started Aug 23 10:21:56 PM UTC 24
Finished Aug 23 10:22:30 PM UTC 24
Peak memory 227956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230910698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3230910698
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.2363185567
Short name T17
Test name
Test status
Simulation time 4285699534 ps
CPU time 3.96 seconds
Started Aug 23 10:21:55 PM UTC 24
Finished Aug 23 10:22:00 PM UTC 24
Peak memory 227856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363185567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2363185567
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.1293182436
Short name T15
Test name
Test status
Simulation time 88728859 ps
CPU time 2.17 seconds
Started Aug 23 10:21:56 PM UTC 24
Finished Aug 23 10:21:59 PM UTC 24
Peak memory 228020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293182436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1293182436
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.219976973
Short name T12
Test name
Test status
Simulation time 357231004 ps
CPU time 0.88 seconds
Started Aug 23 10:21:56 PM UTC 24
Finished Aug 23 10:21:58 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219976973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.219976973
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.3082890784
Short name T23
Test name
Test status
Simulation time 547408706 ps
CPU time 9.09 seconds
Started Aug 23 10:21:58 PM UTC 24
Finished Aug 23 10:22:09 PM UTC 24
Peak memory 251876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082890784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3082890784
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/1.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.401485597
Short name T413
Test name
Test status
Simulation time 112488303 ps
CPU time 0.58 seconds
Started Aug 23 10:26:20 PM UTC 24
Finished Aug 23 10:26:21 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401485597 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.401485597
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.1844999969
Short name T267
Test name
Test status
Simulation time 1199863496 ps
CPU time 4.51 seconds
Started Aug 23 10:25:57 PM UTC 24
Finished Aug 23 10:26:03 PM UTC 24
Peak memory 245592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844999969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1844999969
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.1095960099
Short name T407
Test name
Test status
Simulation time 21795802 ps
CPU time 0.7 seconds
Started Aug 23 10:25:39 PM UTC 24
Finished Aug 23 10:25:41 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095960099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1095960099
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.1859253012
Short name T222
Test name
Test status
Simulation time 5114235821 ps
CPU time 46.18 seconds
Started Aug 23 10:26:09 PM UTC 24
Finished Aug 23 10:26:56 PM UTC 24
Peak memory 262120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859253012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1859253012
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.3922168185
Short name T352
Test name
Test status
Simulation time 3223314322 ps
CPU time 41.49 seconds
Started Aug 23 10:26:18 PM UTC 24
Finished Aug 23 10:27:01 PM UTC 24
Peak memory 262404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922168185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.3922168185
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.2790094650
Short name T201
Test name
Test status
Simulation time 20775875865 ps
CPU time 62.8 seconds
Started Aug 23 10:26:03 PM UTC 24
Finished Aug 23 10:27:07 PM UTC 24
Peak memory 268232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790094650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.2790094650
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.1622800519
Short name T218
Test name
Test status
Simulation time 192231252 ps
CPU time 2.16 seconds
Started Aug 23 10:25:52 PM UTC 24
Finished Aug 23 10:25:55 PM UTC 24
Peak memory 235596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622800519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1622800519
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.1471346588
Short name T288
Test name
Test status
Simulation time 7806494353 ps
CPU time 25.01 seconds
Started Aug 23 10:25:54 PM UTC 24
Finished Aug 23 10:26:21 PM UTC 24
Peak memory 245676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471346588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1471346588
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.31677582
Short name T408
Test name
Test status
Simulation time 97495571 ps
CPU time 0.88 seconds
Started Aug 23 10:25:42 PM UTC 24
Finished Aug 23 10:25:44 PM UTC 24
Peak memory 229144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31677582 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mem_parity.31677582
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.4281945422
Short name T308
Test name
Test status
Simulation time 959219752 ps
CPU time 6.94 seconds
Started Aug 23 10:25:48 PM UTC 24
Finished Aug 23 10:25:56 PM UTC 24
Peak memory 245576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281945422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.4281945422
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.2727237219
Short name T239
Test name
Test status
Simulation time 25308031403 ps
CPU time 12.55 seconds
Started Aug 23 10:25:48 PM UTC 24
Finished Aug 23 10:26:02 PM UTC 24
Peak memory 245904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727237219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2727237219
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.1947470420
Short name T412
Test name
Test status
Simulation time 6568224970 ps
CPU time 12.62 seconds
Started Aug 23 10:26:04 PM UTC 24
Finished Aug 23 10:26:17 PM UTC 24
Peak memory 233844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947470420 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.1947470420
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.2107271977
Short name T175
Test name
Test status
Simulation time 63060822 ps
CPU time 0.89 seconds
Started Aug 23 10:26:19 PM UTC 24
Finished Aug 23 10:26:21 PM UTC 24
Peak memory 216436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107271977 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.2107271977
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.222018762
Short name T366
Test name
Test status
Simulation time 2581645414 ps
CPU time 6.07 seconds
Started Aug 23 10:25:45 PM UTC 24
Finished Aug 23 10:25:52 PM UTC 24
Peak memory 228092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222018762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.222018762
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.3365105136
Short name T409
Test name
Test status
Simulation time 209678322 ps
CPU time 1.36 seconds
Started Aug 23 10:25:43 PM UTC 24
Finished Aug 23 10:25:45 PM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365105136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3365105136
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.1983788519
Short name T371
Test name
Test status
Simulation time 47433939 ps
CPU time 0.74 seconds
Started Aug 23 10:25:46 PM UTC 24
Finished Aug 23 10:25:48 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983788519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1983788519
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.3934302683
Short name T410
Test name
Test status
Simulation time 517967415 ps
CPU time 0.77 seconds
Started Aug 23 10:25:46 PM UTC 24
Finished Aug 23 10:25:48 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934302683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3934302683
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.407600964
Short name T259
Test name
Test status
Simulation time 1395613635 ps
CPU time 3.66 seconds
Started Aug 23 10:25:56 PM UTC 24
Finished Aug 23 10:26:01 PM UTC 24
Peak memory 235524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407600964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.407600964
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/10.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.3923220842
Short name T82
Test name
Test status
Simulation time 19515891 ps
CPU time 0.65 seconds
Started Aug 23 10:26:40 PM UTC 24
Finished Aug 23 10:26:41 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923220842 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.3923220842
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.1407415295
Short name T79
Test name
Test status
Simulation time 1121169782 ps
CPU time 6.86 seconds
Started Aug 23 10:26:31 PM UTC 24
Finished Aug 23 10:26:39 PM UTC 24
Peak memory 245548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407415295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1407415295
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.2350440526
Short name T414
Test name
Test status
Simulation time 17597803 ps
CPU time 0.7 seconds
Started Aug 23 10:26:22 PM UTC 24
Finished Aug 23 10:26:24 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350440526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2350440526
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.2707031540
Short name T258
Test name
Test status
Simulation time 7049520939 ps
CPU time 32.23 seconds
Started Aug 23 10:26:37 PM UTC 24
Finished Aug 23 10:27:10 PM UTC 24
Peak memory 262120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707031540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2707031540
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.3841990778
Short name T470
Test name
Test status
Simulation time 69169372462 ps
CPU time 118.34 seconds
Started Aug 23 10:26:37 PM UTC 24
Finished Aug 23 10:28:37 PM UTC 24
Peak memory 264204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841990778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3841990778
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.1202542605
Short name T420
Test name
Test status
Simulation time 251269290 ps
CPU time 2.44 seconds
Started Aug 23 10:26:32 PM UTC 24
Finished Aug 23 10:26:36 PM UTC 24
Peak memory 245800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202542605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1202542605
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.1547369777
Short name T200
Test name
Test status
Simulation time 7499908223 ps
CPU time 58.14 seconds
Started Aug 23 10:26:33 PM UTC 24
Finished Aug 23 10:27:33 PM UTC 24
Peak memory 278472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547369777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.1547369777
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.3927534056
Short name T230
Test name
Test status
Simulation time 525665467 ps
CPU time 3.89 seconds
Started Aug 23 10:26:26 PM UTC 24
Finished Aug 23 10:26:31 PM UTC 24
Peak memory 245540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927534056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3927534056
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.3893608838
Short name T83
Test name
Test status
Simulation time 919448922 ps
CPU time 14.18 seconds
Started Aug 23 10:26:27 PM UTC 24
Finished Aug 23 10:26:43 PM UTC 24
Peak memory 245868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893608838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3893608838
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.2834703718
Short name T415
Test name
Test status
Simulation time 256750989 ps
CPU time 0.9 seconds
Started Aug 23 10:26:22 PM UTC 24
Finished Aug 23 10:26:24 PM UTC 24
Peak memory 229148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834703718 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mem_parity.2834703718
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.2469075367
Short name T78
Test name
Test status
Simulation time 3411918398 ps
CPU time 11.73 seconds
Started Aug 23 10:26:26 PM UTC 24
Finished Aug 23 10:26:39 PM UTC 24
Peak memory 245640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469075367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.2469075367
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.3494903610
Short name T303
Test name
Test status
Simulation time 1286357985 ps
CPU time 5.79 seconds
Started Aug 23 10:26:25 PM UTC 24
Finished Aug 23 10:26:32 PM UTC 24
Peak memory 235280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494903610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3494903610
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.2333799833
Short name T425
Test name
Test status
Simulation time 9960061077 ps
CPU time 14.66 seconds
Started Aug 23 10:26:35 PM UTC 24
Finished Aug 23 10:26:51 PM UTC 24
Peak memory 231800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333799833 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.2333799833
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.1475962643
Short name T245
Test name
Test status
Simulation time 6145447419 ps
CPU time 74.15 seconds
Started Aug 23 10:26:39 PM UTC 24
Finished Aug 23 10:27:54 PM UTC 24
Peak memory 262376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475962643 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.1475962643
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.2469127364
Short name T416
Test name
Test status
Simulation time 226376336 ps
CPU time 1.57 seconds
Started Aug 23 10:26:22 PM UTC 24
Finished Aug 23 10:26:25 PM UTC 24
Peak memory 227964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469127364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2469127364
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.2524941011
Short name T419
Test name
Test status
Simulation time 20559641815 ps
CPU time 11.28 seconds
Started Aug 23 10:26:22 PM UTC 24
Finished Aug 23 10:26:34 PM UTC 24
Peak memory 230004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524941011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2524941011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.3783162131
Short name T418
Test name
Test status
Simulation time 25543087 ps
CPU time 0.6 seconds
Started Aug 23 10:26:25 PM UTC 24
Finished Aug 23 10:26:27 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783162131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3783162131
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.2487123091
Short name T417
Test name
Test status
Simulation time 623019361 ps
CPU time 0.73 seconds
Started Aug 23 10:26:24 PM UTC 24
Finished Aug 23 10:26:26 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487123091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2487123091
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.1736506576
Short name T421
Test name
Test status
Simulation time 442739355 ps
CPU time 7.48 seconds
Started Aug 23 10:26:27 PM UTC 24
Finished Aug 23 10:26:36 PM UTC 24
Peak memory 245580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736506576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1736506576
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/11.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.2036804689
Short name T428
Test name
Test status
Simulation time 65052640 ps
CPU time 0.62 seconds
Started Aug 23 10:27:05 PM UTC 24
Finished Aug 23 10:27:06 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036804689 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.2036804689
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.4042839106
Short name T306
Test name
Test status
Simulation time 1817896873 ps
CPU time 10.61 seconds
Started Aug 23 10:26:52 PM UTC 24
Finished Aug 23 10:27:04 PM UTC 24
Peak memory 245540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042839106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.4042839106
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.1433184048
Short name T81
Test name
Test status
Simulation time 18722676 ps
CPU time 0.64 seconds
Started Aug 23 10:26:40 PM UTC 24
Finished Aug 23 10:26:41 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433184048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1433184048
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.144676763
Short name T355
Test name
Test status
Simulation time 2341082884 ps
CPU time 19.29 seconds
Started Aug 23 10:27:01 PM UTC 24
Finished Aug 23 10:27:22 PM UTC 24
Peak memory 235536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144676763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.144676763
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.2557507249
Short name T569
Test name
Test status
Simulation time 138650973297 ps
CPU time 258.11 seconds
Started Aug 23 10:27:02 PM UTC 24
Finished Aug 23 10:31:23 PM UTC 24
Peak memory 278788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557507249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.2557507249
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.2734274822
Short name T427
Test name
Test status
Simulation time 39455018 ps
CPU time 2.24 seconds
Started Aug 23 10:26:57 PM UTC 24
Finished Aug 23 10:27:01 PM UTC 24
Peak memory 245808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734274822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2734274822
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.379585175
Short name T202
Test name
Test status
Simulation time 3990320186 ps
CPU time 38.17 seconds
Started Aug 23 10:26:58 PM UTC 24
Finished Aug 23 10:27:38 PM UTC 24
Peak memory 262348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379585175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.379585175
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.2666128559
Short name T269
Test name
Test status
Simulation time 2529446277 ps
CPU time 7.41 seconds
Started Aug 23 10:26:49 PM UTC 24
Finished Aug 23 10:26:58 PM UTC 24
Peak memory 235496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666128559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2666128559
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.2476218864
Short name T301
Test name
Test status
Simulation time 426163975 ps
CPU time 5.99 seconds
Started Aug 23 10:26:50 PM UTC 24
Finished Aug 23 10:26:57 PM UTC 24
Peak memory 245544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476218864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2476218864
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.621464550
Short name T84
Test name
Test status
Simulation time 16454159 ps
CPU time 0.85 seconds
Started Aug 23 10:26:41 PM UTC 24
Finished Aug 23 10:26:43 PM UTC 24
Peak memory 229208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621464550 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mem_parity.621464550
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.1983418728
Short name T424
Test name
Test status
Simulation time 107548833 ps
CPU time 1.96 seconds
Started Aug 23 10:26:47 PM UTC 24
Finished Aug 23 10:26:50 PM UTC 24
Peak memory 233988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983418728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.1983418728
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1695043816
Short name T307
Test name
Test status
Simulation time 7242249113 ps
CPU time 16.57 seconds
Started Aug 23 10:26:45 PM UTC 24
Finished Aug 23 10:27:03 PM UTC 24
Peak memory 245648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695043816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1695043816
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.4062224257
Short name T432
Test name
Test status
Simulation time 3068954634 ps
CPU time 11.73 seconds
Started Aug 23 10:26:58 PM UTC 24
Finished Aug 23 10:27:11 PM UTC 24
Peak memory 231928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062224257 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.4062224257
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.1346237798
Short name T176
Test name
Test status
Simulation time 63126691 ps
CPU time 0.91 seconds
Started Aug 23 10:27:04 PM UTC 24
Finished Aug 23 10:27:05 PM UTC 24
Peak memory 216536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346237798 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.1346237798
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.3860077375
Short name T365
Test name
Test status
Simulation time 6023165008 ps
CPU time 28.28 seconds
Started Aug 23 10:26:42 PM UTC 24
Finished Aug 23 10:27:11 PM UTC 24
Peak memory 227920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860077375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3860077375
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.240423701
Short name T423
Test name
Test status
Simulation time 2488711560 ps
CPU time 5.76 seconds
Started Aug 23 10:26:42 PM UTC 24
Finished Aug 23 10:26:49 PM UTC 24
Peak memory 227824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240423701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.240423701
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.3341034686
Short name T422
Test name
Test status
Simulation time 232152364 ps
CPU time 2.36 seconds
Started Aug 23 10:26:43 PM UTC 24
Finished Aug 23 10:26:46 PM UTC 24
Peak memory 227772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341034686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3341034686
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.3833375688
Short name T85
Test name
Test status
Simulation time 156088553 ps
CPU time 0.68 seconds
Started Aug 23 10:26:43 PM UTC 24
Finished Aug 23 10:26:45 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833375688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3833375688
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.717717633
Short name T426
Test name
Test status
Simulation time 765251904 ps
CPU time 6.07 seconds
Started Aug 23 10:26:51 PM UTC 24
Finished Aug 23 10:26:58 PM UTC 24
Peak memory 235324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717717633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.717717633
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/12.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_alert_test.2233213653
Short name T436
Test name
Test status
Simulation time 15108399 ps
CPU time 0.61 seconds
Started Aug 23 10:27:25 PM UTC 24
Finished Aug 23 10:27:27 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233213653 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.2233213653
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_cfg_cmd.3144190310
Short name T268
Test name
Test status
Simulation time 9223336837 ps
CPU time 11.91 seconds
Started Aug 23 10:27:13 PM UTC 24
Finished Aug 23 10:27:26 PM UTC 24
Peak memory 235496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144190310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3144190310
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.323206562
Short name T429
Test name
Test status
Simulation time 52698128 ps
CPU time 0.66 seconds
Started Aug 23 10:27:05 PM UTC 24
Finished Aug 23 10:27:06 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323206562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.323206562
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.3604996143
Short name T369
Test name
Test status
Simulation time 14887181822 ps
CPU time 41.67 seconds
Started Aug 23 10:27:21 PM UTC 24
Finished Aug 23 10:28:04 PM UTC 24
Peak memory 262276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604996143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.3604996143
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode.1880649578
Short name T453
Test name
Test status
Simulation time 7690370569 ps
CPU time 45.76 seconds
Started Aug 23 10:27:15 PM UTC 24
Finished Aug 23 10:28:02 PM UTC 24
Peak memory 245712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880649578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1880649578
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.1538331918
Short name T435
Test name
Test status
Simulation time 11172360 ps
CPU time 0.64 seconds
Started Aug 23 10:27:17 PM UTC 24
Finished Aug 23 10:27:19 PM UTC 24
Peak memory 225560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538331918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.1538331918
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_intercept.2535711940
Short name T434
Test name
Test status
Simulation time 796798357 ps
CPU time 3.06 seconds
Started Aug 23 10:27:12 PM UTC 24
Finished Aug 23 10:27:16 PM UTC 24
Peak memory 245580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535711940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2535711940
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mailbox.3979099133
Short name T282
Test name
Test status
Simulation time 1075158384 ps
CPU time 6.99 seconds
Started Aug 23 10:27:12 PM UTC 24
Finished Aug 23 10:27:20 PM UTC 24
Peak memory 245736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979099133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3979099133
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.3398489450
Short name T430
Test name
Test status
Simulation time 96007352 ps
CPU time 0.88 seconds
Started Aug 23 10:27:06 PM UTC 24
Finished Aug 23 10:27:08 PM UTC 24
Peak memory 229208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398489450 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mem_parity.3398489450
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.1565614670
Short name T319
Test name
Test status
Simulation time 237625651 ps
CPU time 4.39 seconds
Started Aug 23 10:27:11 PM UTC 24
Finished Aug 23 10:27:16 PM UTC 24
Peak memory 245552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565614670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.1565614670
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.2285044591
Short name T285
Test name
Test status
Simulation time 118359941 ps
CPU time 2 seconds
Started Aug 23 10:27:11 PM UTC 24
Finished Aug 23 10:27:14 PM UTC 24
Peak memory 244920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285044591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2285044591
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.1179093041
Short name T438
Test name
Test status
Simulation time 1324977702 ps
CPU time 10.97 seconds
Started Aug 23 10:27:17 PM UTC 24
Finished Aug 23 10:27:29 PM UTC 24
Peak memory 231660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179093041 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.1179093041
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.259077620
Short name T178
Test name
Test status
Simulation time 44755390346 ps
CPU time 284.58 seconds
Started Aug 23 10:27:22 PM UTC 24
Finished Aug 23 10:32:10 PM UTC 24
Peak memory 276512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259077620 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.259077620
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_all.1524164680
Short name T357
Test name
Test status
Simulation time 7787020132 ps
CPU time 37.67 seconds
Started Aug 23 10:27:07 PM UTC 24
Finished Aug 23 10:27:46 PM UTC 24
Peak memory 227892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524164680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1524164680
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.3978148331
Short name T433
Test name
Test status
Simulation time 609114183 ps
CPU time 3.73 seconds
Started Aug 23 10:27:07 PM UTC 24
Finished Aug 23 10:27:12 PM UTC 24
Peak memory 227880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978148331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3978148331
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.854984478
Short name T368
Test name
Test status
Simulation time 324101432 ps
CPU time 2.22 seconds
Started Aug 23 10:27:09 PM UTC 24
Finished Aug 23 10:27:12 PM UTC 24
Peak memory 228020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854984478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.854984478
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.4123521549
Short name T431
Test name
Test status
Simulation time 97699183 ps
CPU time 0.66 seconds
Started Aug 23 10:27:08 PM UTC 24
Finished Aug 23 10:27:09 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123521549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.4123521549
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/13.spi_device_upload.1995908585
Short name T284
Test name
Test status
Simulation time 791559434 ps
CPU time 3.17 seconds
Started Aug 23 10:27:12 PM UTC 24
Finished Aug 23 10:27:16 PM UTC 24
Peak memory 245800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995908585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1995908585
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/13.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/14.spi_device_alert_test.3781750446
Short name T446
Test name
Test status
Simulation time 13028885 ps
CPU time 0.6 seconds
Started Aug 23 10:27:47 PM UTC 24
Finished Aug 23 10:27:49 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781750446 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.3781750446
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/14.spi_device_cfg_cmd.2899715169
Short name T444
Test name
Test status
Simulation time 1269195929 ps
CPU time 4.99 seconds
Started Aug 23 10:27:40 PM UTC 24
Finished Aug 23 10:27:46 PM UTC 24
Peak memory 235340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899715169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2899715169
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/14.spi_device_csb_read.1495274282
Short name T437
Test name
Test status
Simulation time 22549554 ps
CPU time 0.7 seconds
Started Aug 23 10:27:26 PM UTC 24
Finished Aug 23 10:27:28 PM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495274282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1495274282
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_all.2473082561
Short name T264
Test name
Test status
Simulation time 36719641664 ps
CPU time 143.96 seconds
Started Aug 23 10:27:43 PM UTC 24
Finished Aug 23 10:30:10 PM UTC 24
Peak memory 266188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473082561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2473082561
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.3835176625
Short name T234
Test name
Test status
Simulation time 13405996186 ps
CPU time 76.59 seconds
Started Aug 23 10:27:43 PM UTC 24
Finished Aug 23 10:29:02 PM UTC 24
Peak memory 264204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835176625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3835176625
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.2271716014
Short name T260
Test name
Test status
Simulation time 30993558985 ps
CPU time 238.07 seconds
Started Aug 23 10:27:46 PM UTC 24
Finished Aug 23 10:31:48 PM UTC 24
Peak memory 266248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271716014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.2271716014
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode.3016308878
Short name T346
Test name
Test status
Simulation time 646883666 ps
CPU time 4.1 seconds
Started Aug 23 10:27:41 PM UTC 24
Finished Aug 23 10:27:47 PM UTC 24
Peak memory 235336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016308878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3016308878
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.2297607348
Short name T607
Test name
Test status
Simulation time 50909074053 ps
CPU time 314.54 seconds
Started Aug 23 10:27:41 PM UTC 24
Finished Aug 23 10:33:00 PM UTC 24
Peak memory 262216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297607348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.2297607348
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/14.spi_device_intercept.1626006407
Short name T279
Test name
Test status
Simulation time 790046301 ps
CPU time 2.88 seconds
Started Aug 23 10:27:36 PM UTC 24
Finished Aug 23 10:27:40 PM UTC 24
Peak memory 235284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626006407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1626006407
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mailbox.4189899785
Short name T220
Test name
Test status
Simulation time 649344663 ps
CPU time 4.5 seconds
Started Aug 23 10:27:37 PM UTC 24
Finished Aug 23 10:27:42 PM UTC 24
Peak memory 251752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189899785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.4189899785
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mem_parity.2999214699
Short name T439
Test name
Test status
Simulation time 27014943 ps
CPU time 0.93 seconds
Started Aug 23 10:27:28 PM UTC 24
Finished Aug 23 10:27:30 PM UTC 24
Peak memory 229148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999214699 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mem_parity.2999214699
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.801449146
Short name T249
Test name
Test status
Simulation time 887016806 ps
CPU time 5.95 seconds
Started Aug 23 10:27:34 PM UTC 24
Finished Aug 23 10:27:41 PM UTC 24
Peak memory 235468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801449146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.801449146
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.3988884814
Short name T304
Test name
Test status
Simulation time 711875565 ps
CPU time 5.66 seconds
Started Aug 23 10:27:34 PM UTC 24
Finished Aug 23 10:27:41 PM UTC 24
Peak memory 235404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988884814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3988884814
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.230198238
Short name T445
Test name
Test status
Simulation time 718600693 ps
CPU time 4 seconds
Started Aug 23 10:27:42 PM UTC 24
Finished Aug 23 10:27:48 PM UTC 24
Peak memory 233908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230198238 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.230198238
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.2345306394
Short name T447
Test name
Test status
Simulation time 42978910 ps
CPU time 0.83 seconds
Started Aug 23 10:27:47 PM UTC 24
Finished Aug 23 10:27:49 PM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345306394 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.2345306394
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_all.3024528086
Short name T443
Test name
Test status
Simulation time 521801019 ps
CPU time 5.41 seconds
Started Aug 23 10:27:30 PM UTC 24
Finished Aug 23 10:27:36 PM UTC 24
Peak memory 227848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024528086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3024528086
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.632859152
Short name T440
Test name
Test status
Simulation time 592067594 ps
CPU time 2.11 seconds
Started Aug 23 10:27:29 PM UTC 24
Finished Aug 23 10:27:32 PM UTC 24
Peak memory 227960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632859152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.632859152
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_rw.3573234537
Short name T442
Test name
Test status
Simulation time 33042395 ps
CPU time 0.98 seconds
Started Aug 23 10:27:33 PM UTC 24
Finished Aug 23 10:27:35 PM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573234537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3573234537
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.2187985852
Short name T441
Test name
Test status
Simulation time 102604958 ps
CPU time 0.64 seconds
Started Aug 23 10:27:31 PM UTC 24
Finished Aug 23 10:27:33 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187985852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2187985852
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/14.spi_device_upload.3321006874
Short name T255
Test name
Test status
Simulation time 3964559124 ps
CPU time 14.18 seconds
Started Aug 23 10:27:39 PM UTC 24
Finished Aug 23 10:27:54 PM UTC 24
Peak memory 262316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321006874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3321006874
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/14.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_alert_test.2209499795
Short name T459
Test name
Test status
Simulation time 24893544 ps
CPU time 0.63 seconds
Started Aug 23 10:28:11 PM UTC 24
Finished Aug 23 10:28:13 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209499795 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.2209499795
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_cfg_cmd.1016437149
Short name T454
Test name
Test status
Simulation time 51068695 ps
CPU time 2.16 seconds
Started Aug 23 10:28:01 PM UTC 24
Finished Aug 23 10:28:04 PM UTC 24
Peak memory 245740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016437149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1016437149
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_csb_read.3304340758
Short name T448
Test name
Test status
Simulation time 64975438 ps
CPU time 0.65 seconds
Started Aug 23 10:27:48 PM UTC 24
Finished Aug 23 10:27:50 PM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304340758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3304340758
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_all.1771664141
Short name T247
Test name
Test status
Simulation time 9432873669 ps
CPU time 76.45 seconds
Started Aug 23 10:28:05 PM UTC 24
Finished Aug 23 10:29:23 PM UTC 24
Peak memory 251852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771664141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1771664141
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.565404027
Short name T516
Test name
Test status
Simulation time 5369540784 ps
CPU time 91.33 seconds
Started Aug 23 10:28:05 PM UTC 24
Finished Aug 23 10:29:38 PM UTC 24
Peak memory 268292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565404027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.565404027
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.1509406503
Short name T492
Test name
Test status
Simulation time 9150352213 ps
CPU time 63.84 seconds
Started Aug 23 10:28:07 PM UTC 24
Finished Aug 23 10:29:13 PM UTC 24
Peak memory 245764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509406503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.1509406503
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode.3717241573
Short name T458
Test name
Test status
Simulation time 277319453 ps
CPU time 7.56 seconds
Started Aug 23 10:28:02 PM UTC 24
Finished Aug 23 10:28:11 PM UTC 24
Peak memory 245772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717241573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3717241573
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.140679306
Short name T485
Test name
Test status
Simulation time 19425432713 ps
CPU time 57.81 seconds
Started Aug 23 10:28:03 PM UTC 24
Finished Aug 23 10:29:03 PM UTC 24
Peak memory 252040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140679306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.140679306
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_intercept.2236620419
Short name T229
Test name
Test status
Simulation time 698547475 ps
CPU time 4.66 seconds
Started Aug 23 10:27:56 PM UTC 24
Finished Aug 23 10:28:01 PM UTC 24
Peak memory 245676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236620419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2236620419
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mailbox.831319086
Short name T456
Test name
Test status
Simulation time 1347716419 ps
CPU time 7.26 seconds
Started Aug 23 10:27:58 PM UTC 24
Finished Aug 23 10:28:06 PM UTC 24
Peak memory 249644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831319086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.831319086
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mem_parity.9485774
Short name T449
Test name
Test status
Simulation time 67334466 ps
CPU time 0.93 seconds
Started Aug 23 10:27:49 PM UTC 24
Finished Aug 23 10:27:51 PM UTC 24
Peak memory 229152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9485774 -assert n
opostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mem_parity.9485774
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.3148522234
Short name T296
Test name
Test status
Simulation time 17079420842 ps
CPU time 18.74 seconds
Started Aug 23 10:27:56 PM UTC 24
Finished Aug 23 10:28:16 PM UTC 24
Peak memory 235400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148522234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.3148522234
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.1719472144
Short name T253
Test name
Test status
Simulation time 156743652 ps
CPU time 2.92 seconds
Started Aug 23 10:27:56 PM UTC 24
Finished Aug 23 10:28:00 PM UTC 24
Peak memory 245580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719472144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1719472144
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.1897170010
Short name T461
Test name
Test status
Simulation time 2588107716 ps
CPU time 7.82 seconds
Started Aug 23 10:28:05 PM UTC 24
Finished Aug 23 10:28:14 PM UTC 24
Peak memory 231796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897170010 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.1897170010
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_all.3495187504
Short name T363
Test name
Test status
Simulation time 1823593808 ps
CPU time 14.71 seconds
Started Aug 23 10:27:50 PM UTC 24
Finished Aug 23 10:28:06 PM UTC 24
Peak memory 228116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495187504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3495187504
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.3265515574
Short name T451
Test name
Test status
Simulation time 1132958704 ps
CPU time 6.76 seconds
Started Aug 23 10:27:49 PM UTC 24
Finished Aug 23 10:27:57 PM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265515574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3265515574
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_rw.1566036660
Short name T452
Test name
Test status
Simulation time 2394225373 ps
CPU time 1.9 seconds
Started Aug 23 10:27:56 PM UTC 24
Finished Aug 23 10:27:59 PM UTC 24
Peak memory 228080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566036660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1566036660
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.3676161970
Short name T450
Test name
Test status
Simulation time 139933300 ps
CPU time 0.93 seconds
Started Aug 23 10:27:52 PM UTC 24
Finished Aug 23 10:27:55 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676161970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3676161970
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/15.spi_device_upload.3083288267
Short name T455
Test name
Test status
Simulation time 579571754 ps
CPU time 3.53 seconds
Started Aug 23 10:28:00 PM UTC 24
Finished Aug 23 10:28:05 PM UTC 24
Peak memory 235528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083288267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3083288267
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/15.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_alert_test.3932323028
Short name T473
Test name
Test status
Simulation time 15819115 ps
CPU time 0.64 seconds
Started Aug 23 10:28:40 PM UTC 24
Finished Aug 23 10:28:42 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932323028 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.3932323028
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_cfg_cmd.1403578693
Short name T280
Test name
Test status
Simulation time 2812921633 ps
CPU time 9.97 seconds
Started Aug 23 10:28:28 PM UTC 24
Finished Aug 23 10:28:39 PM UTC 24
Peak memory 235472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403578693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1403578693
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_csb_read.2517837033
Short name T460
Test name
Test status
Simulation time 30363903 ps
CPU time 0.67 seconds
Started Aug 23 10:28:11 PM UTC 24
Finished Aug 23 10:28:13 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517837033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2517837033
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_all.1345154254
Short name T471
Test name
Test status
Simulation time 36093735 ps
CPU time 0.66 seconds
Started Aug 23 10:28:38 PM UTC 24
Finished Aug 23 10:28:39 PM UTC 24
Peak memory 225676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345154254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1345154254
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2204179103
Short name T482
Test name
Test status
Simulation time 771004325 ps
CPU time 14.61 seconds
Started Aug 23 10:28:40 PM UTC 24
Finished Aug 23 10:28:56 PM UTC 24
Peak memory 245700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204179103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.2204179103
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode.709314250
Short name T468
Test name
Test status
Simulation time 340297732 ps
CPU time 2.35 seconds
Started Aug 23 10:28:29 PM UTC 24
Finished Aug 23 10:28:32 PM UTC 24
Peak memory 235404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709314250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.709314250
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.432375768
Short name T469
Test name
Test status
Simulation time 136131542 ps
CPU time 0.78 seconds
Started Aug 23 10:28:33 PM UTC 24
Finished Aug 23 10:28:35 PM UTC 24
Peak memory 225672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432375768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.432375768
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_intercept.3457661678
Short name T217
Test name
Test status
Simulation time 1986140712 ps
CPU time 14.08 seconds
Started Aug 23 10:28:21 PM UTC 24
Finished Aug 23 10:28:37 PM UTC 24
Peak memory 235340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457661678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3457661678
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mailbox.2566502076
Short name T466
Test name
Test status
Simulation time 217679917 ps
CPU time 3.57 seconds
Started Aug 23 10:28:23 PM UTC 24
Finished Aug 23 10:28:27 PM UTC 24
Peak memory 245608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566502076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2566502076
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mem_parity.3042653091
Short name T462
Test name
Test status
Simulation time 43897776 ps
CPU time 0.82 seconds
Started Aug 23 10:28:13 PM UTC 24
Finished Aug 23 10:28:15 PM UTC 24
Peak memory 229148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042653091 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mem_parity.3042653091
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.1880624991
Short name T246
Test name
Test status
Simulation time 4891869245 ps
CPU time 17.38 seconds
Started Aug 23 10:28:20 PM UTC 24
Finished Aug 23 10:28:39 PM UTC 24
Peak memory 249768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880624991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.1880624991
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.635326737
Short name T464
Test name
Test status
Simulation time 120978830 ps
CPU time 1.92 seconds
Started Aug 23 10:28:17 PM UTC 24
Finished Aug 23 10:28:20 PM UTC 24
Peak memory 244680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635326737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.635326737
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.3926585693
Short name T472
Test name
Test status
Simulation time 229666987 ps
CPU time 3.99 seconds
Started Aug 23 10:28:36 PM UTC 24
Finished Aug 23 10:28:41 PM UTC 24
Peak memory 233716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926585693 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.3926585693
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.1390831604
Short name T474
Test name
Test status
Simulation time 64387605 ps
CPU time 0.79 seconds
Started Aug 23 10:28:40 PM UTC 24
Finished Aug 23 10:28:42 PM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390831604 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.1390831604
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_all.2439596043
Short name T351
Test name
Test status
Simulation time 28262572650 ps
CPU time 36.01 seconds
Started Aug 23 10:28:14 PM UTC 24
Finished Aug 23 10:28:52 PM UTC 24
Peak memory 228156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439596043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2439596043
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.332346633
Short name T465
Test name
Test status
Simulation time 4818517302 ps
CPU time 6.98 seconds
Started Aug 23 10:28:13 PM UTC 24
Finished Aug 23 10:28:21 PM UTC 24
Peak memory 228088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332346633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.332346633
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_rw.2976078902
Short name T367
Test name
Test status
Simulation time 1475848304 ps
CPU time 2.26 seconds
Started Aug 23 10:28:16 PM UTC 24
Finished Aug 23 10:28:20 PM UTC 24
Peak memory 227832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976078902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2976078902
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.2245387105
Short name T463
Test name
Test status
Simulation time 341573983 ps
CPU time 0.75 seconds
Started Aug 23 10:28:15 PM UTC 24
Finished Aug 23 10:28:17 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245387105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2245387105
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/16.spi_device_upload.3624077756
Short name T467
Test name
Test status
Simulation time 632412800 ps
CPU time 4.53 seconds
Started Aug 23 10:28:23 PM UTC 24
Finished Aug 23 10:28:28 PM UTC 24
Peak memory 245548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624077756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3624077756
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/16.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/17.spi_device_alert_test.3114594899
Short name T489
Test name
Test status
Simulation time 25137254 ps
CPU time 0.62 seconds
Started Aug 23 10:29:07 PM UTC 24
Finished Aug 23 10:29:09 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114594899 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.3114594899
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/17.spi_device_cfg_cmd.895963772
Short name T113
Test name
Test status
Simulation time 287026135 ps
CPU time 1.85 seconds
Started Aug 23 10:28:57 PM UTC 24
Finished Aug 23 10:28:59 PM UTC 24
Peak memory 234700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895963772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.895963772
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/17.spi_device_csb_read.2599321351
Short name T475
Test name
Test status
Simulation time 13235403 ps
CPU time 0.64 seconds
Started Aug 23 10:28:42 PM UTC 24
Finished Aug 23 10:28:44 PM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599321351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2599321351
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_all.723398147
Short name T244
Test name
Test status
Simulation time 5607063092 ps
CPU time 27.37 seconds
Started Aug 23 10:29:03 PM UTC 24
Finished Aug 23 10:29:31 PM UTC 24
Peak memory 251844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723398147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.723398147
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.2339025594
Short name T503
Test name
Test status
Simulation time 11493159167 ps
CPU time 21.7 seconds
Started Aug 23 10:29:03 PM UTC 24
Finished Aug 23 10:29:26 PM UTC 24
Peak memory 232124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339025594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2339025594
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.1688119281
Short name T547
Test name
Test status
Simulation time 19839927927 ps
CPU time 106.2 seconds
Started Aug 23 10:29:04 PM UTC 24
Finished Aug 23 10:30:52 PM UTC 24
Peak memory 264192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688119281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.1688119281
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode.2927682097
Short name T497
Test name
Test status
Simulation time 24614215435 ps
CPU time 19.19 seconds
Started Aug 23 10:28:57 PM UTC 24
Finished Aug 23 10:29:17 PM UTC 24
Peak memory 245244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927682097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2927682097
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.3493117528
Short name T502
Test name
Test status
Simulation time 6099972890 ps
CPU time 24.65 seconds
Started Aug 23 10:28:59 PM UTC 24
Finished Aug 23 10:29:25 PM UTC 24
Peak memory 251848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493117528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.3493117528
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/17.spi_device_intercept.2881525306
Short name T481
Test name
Test status
Simulation time 412388523 ps
CPU time 1.93 seconds
Started Aug 23 10:28:52 PM UTC 24
Finished Aug 23 10:28:55 PM UTC 24
Peak memory 233872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881525306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2881525306
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mailbox.2194870596
Short name T523
Test name
Test status
Simulation time 29549205708 ps
CPU time 61.32 seconds
Started Aug 23 10:28:54 PM UTC 24
Finished Aug 23 10:29:57 PM UTC 24
Peak memory 245652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194870596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2194870596
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mem_parity.1364129369
Short name T476
Test name
Test status
Simulation time 33765974 ps
CPU time 0.93 seconds
Started Aug 23 10:28:42 PM UTC 24
Finished Aug 23 10:28:44 PM UTC 24
Peak memory 229208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364129369 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mem_parity.1364129369
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.1844874000
Short name T483
Test name
Test status
Simulation time 1491224601 ps
CPU time 5.53 seconds
Started Aug 23 10:28:51 PM UTC 24
Finished Aug 23 10:28:58 PM UTC 24
Peak memory 245576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844874000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.1844874000
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.950342698
Short name T480
Test name
Test status
Simulation time 4613012036 ps
CPU time 4.12 seconds
Started Aug 23 10:28:48 PM UTC 24
Finished Aug 23 10:28:53 PM UTC 24
Peak memory 235416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950342698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.950342698
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.4232608316
Short name T488
Test name
Test status
Simulation time 391140893 ps
CPU time 6.12 seconds
Started Aug 23 10:29:01 PM UTC 24
Finished Aug 23 10:29:08 PM UTC 24
Peak memory 233684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232608316 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.4232608316
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/17.spi_device_stress_all.3690822500
Short name T487
Test name
Test status
Simulation time 37531946 ps
CPU time 0.83 seconds
Started Aug 23 10:29:06 PM UTC 24
Finished Aug 23 10:29:08 PM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690822500 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.3690822500
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_all.2402507841
Short name T486
Test name
Test status
Simulation time 4670495148 ps
CPU time 19.73 seconds
Started Aug 23 10:28:44 PM UTC 24
Finished Aug 23 10:29:05 PM UTC 24
Peak memory 227988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402507841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2402507841
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.463585226
Short name T478
Test name
Test status
Simulation time 1377969159 ps
CPU time 4.78 seconds
Started Aug 23 10:28:42 PM UTC 24
Finished Aug 23 10:28:48 PM UTC 24
Peak memory 227828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463585226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.463585226
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_rw.1907775124
Short name T479
Test name
Test status
Simulation time 59193098 ps
CPU time 1.51 seconds
Started Aug 23 10:28:48 PM UTC 24
Finished Aug 23 10:28:51 PM UTC 24
Peak memory 227964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907775124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1907775124
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.423380488
Short name T477
Test name
Test status
Simulation time 95822996 ps
CPU time 0.83 seconds
Started Aug 23 10:28:45 PM UTC 24
Finished Aug 23 10:28:47 PM UTC 24
Peak memory 215924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423380488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.423380488
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/17.spi_device_upload.1959287767
Short name T484
Test name
Test status
Simulation time 1184182742 ps
CPU time 4.72 seconds
Started Aug 23 10:28:56 PM UTC 24
Finished Aug 23 10:29:02 PM UTC 24
Peak memory 245708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959287767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1959287767
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/17.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/18.spi_device_alert_test.2147765894
Short name T506
Test name
Test status
Simulation time 66847630 ps
CPU time 0.62 seconds
Started Aug 23 10:29:29 PM UTC 24
Finished Aug 23 10:29:30 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147765894 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.2147765894
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/18.spi_device_cfg_cmd.98815175
Short name T501
Test name
Test status
Simulation time 1383516218 ps
CPU time 2.58 seconds
Started Aug 23 10:29:19 PM UTC 24
Finished Aug 23 10:29:23 PM UTC 24
Peak memory 245620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98815175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.98815175
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/18.spi_device_csb_read.2822903892
Short name T490
Test name
Test status
Simulation time 19996054 ps
CPU time 0.67 seconds
Started Aug 23 10:29:09 PM UTC 24
Finished Aug 23 10:29:11 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822903892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2822903892
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_all.3079202101
Short name T528
Test name
Test status
Simulation time 33345833804 ps
CPU time 50.91 seconds
Started Aug 23 10:29:24 PM UTC 24
Finished Aug 23 10:30:16 PM UTC 24
Peak memory 249832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079202101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3079202101
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.1929157075
Short name T262
Test name
Test status
Simulation time 5804231648 ps
CPU time 66.08 seconds
Started Aug 23 10:29:24 PM UTC 24
Finished Aug 23 10:30:31 PM UTC 24
Peak memory 266280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929157075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1929157075
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.2429951216
Short name T509
Test name
Test status
Simulation time 465015105 ps
CPU time 6.23 seconds
Started Aug 23 10:29:26 PM UTC 24
Finished Aug 23 10:29:33 PM UTC 24
Peak memory 229856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429951216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.2429951216
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode.1959085975
Short name T505
Test name
Test status
Simulation time 1994704040 ps
CPU time 6.11 seconds
Started Aug 23 10:29:21 PM UTC 24
Finished Aug 23 10:29:29 PM UTC 24
Peak memory 245584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959085975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1959085975
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.2641388384
Short name T557
Test name
Test status
Simulation time 59409854457 ps
CPU time 96.94 seconds
Started Aug 23 10:29:21 PM UTC 24
Finished Aug 23 10:31:00 PM UTC 24
Peak memory 262088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641388384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.2641388384
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/18.spi_device_intercept.3941087945
Short name T498
Test name
Test status
Simulation time 595400368 ps
CPU time 3.09 seconds
Started Aug 23 10:29:14 PM UTC 24
Finished Aug 23 10:29:18 PM UTC 24
Peak memory 245740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941087945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3941087945
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mailbox.1178956688
Short name T299
Test name
Test status
Simulation time 10405430236 ps
CPU time 23.64 seconds
Started Aug 23 10:29:16 PM UTC 24
Finished Aug 23 10:29:41 PM UTC 24
Peak memory 245648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178956688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1178956688
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mem_parity.3983310747
Short name T491
Test name
Test status
Simulation time 17207159 ps
CPU time 0.87 seconds
Started Aug 23 10:29:09 PM UTC 24
Finished Aug 23 10:29:11 PM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983310747 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mem_parity.3983310747
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.1751877058
Short name T500
Test name
Test status
Simulation time 1357109677 ps
CPU time 7.23 seconds
Started Aug 23 10:29:14 PM UTC 24
Finished Aug 23 10:29:23 PM UTC 24
Peak memory 245708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751877058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.1751877058
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.2085614767
Short name T504
Test name
Test status
Simulation time 3198770622 ps
CPU time 12.74 seconds
Started Aug 23 10:29:14 PM UTC 24
Finished Aug 23 10:29:28 PM UTC 24
Peak memory 245900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085614767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2085614767
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.1800654905
Short name T511
Test name
Test status
Simulation time 922643688 ps
CPU time 9.4 seconds
Started Aug 23 10:29:23 PM UTC 24
Finished Aug 23 10:29:34 PM UTC 24
Peak memory 231860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800654905 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.1800654905
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.1016896821
Short name T655
Test name
Test status
Simulation time 92509665042 ps
CPU time 319.7 seconds
Started Aug 23 10:29:27 PM UTC 24
Finished Aug 23 10:34:50 PM UTC 24
Peak memory 266252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016896821 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.1016896821
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_all.2664738249
Short name T359
Test name
Test status
Simulation time 1462676642 ps
CPU time 7.56 seconds
Started Aug 23 10:29:12 PM UTC 24
Finished Aug 23 10:29:21 PM UTC 24
Peak memory 227336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664738249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2664738249
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.4088603075
Short name T493
Test name
Test status
Simulation time 440540416 ps
CPU time 3.35 seconds
Started Aug 23 10:29:09 PM UTC 24
Finished Aug 23 10:29:13 PM UTC 24
Peak memory 227496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088603075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.4088603075
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_rw.2072427998
Short name T496
Test name
Test status
Simulation time 22531797 ps
CPU time 1.08 seconds
Started Aug 23 10:29:13 PM UTC 24
Finished Aug 23 10:29:15 PM UTC 24
Peak memory 227928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072427998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2072427998
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.3081871730
Short name T495
Test name
Test status
Simulation time 77479188 ps
CPU time 0.78 seconds
Started Aug 23 10:29:12 PM UTC 24
Finished Aug 23 10:29:14 PM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081871730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3081871730
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/18.spi_device_upload.688354221
Short name T499
Test name
Test status
Simulation time 216216339 ps
CPU time 1.85 seconds
Started Aug 23 10:29:17 PM UTC 24
Finished Aug 23 10:29:20 PM UTC 24
Peak memory 233872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688354221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.688354221
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/18.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_alert_test.2519878655
Short name T521
Test name
Test status
Simulation time 44468702 ps
CPU time 0.61 seconds
Started Aug 23 10:29:55 PM UTC 24
Finished Aug 23 10:29:56 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519878655 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.2519878655
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_cfg_cmd.478814833
Short name T517
Test name
Test status
Simulation time 1110388630 ps
CPU time 4.38 seconds
Started Aug 23 10:29:37 PM UTC 24
Finished Aug 23 10:29:43 PM UTC 24
Peak memory 235408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478814833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.478814833
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_csb_read.3707694729
Short name T507
Test name
Test status
Simulation time 16096010 ps
CPU time 0.69 seconds
Started Aug 23 10:29:30 PM UTC 24
Finished Aug 23 10:29:31 PM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707694729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3707694729
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_all.748687401
Short name T237
Test name
Test status
Simulation time 204431747598 ps
CPU time 338.78 seconds
Started Aug 23 10:29:42 PM UTC 24
Finished Aug 23 10:35:26 PM UTC 24
Peak memory 284744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748687401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.748687401
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.1913842911
Short name T560
Test name
Test status
Simulation time 12350296849 ps
CPU time 81.49 seconds
Started Aug 23 10:29:43 PM UTC 24
Finished Aug 23 10:31:07 PM UTC 24
Peak memory 268488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913842911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1913842911
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.3813132018
Short name T358
Test name
Test status
Simulation time 6199701667 ps
CPU time 65.12 seconds
Started Aug 23 10:29:47 PM UTC 24
Finished Aug 23 10:30:54 PM UTC 24
Peak memory 251972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813132018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.3813132018
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.2352937473
Short name T205
Test name
Test status
Simulation time 1092309333 ps
CPU time 13.59 seconds
Started Aug 23 10:29:39 PM UTC 24
Finished Aug 23 10:29:54 PM UTC 24
Peak memory 245596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352937473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.2352937473
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_intercept.1104641177
Short name T281
Test name
Test status
Simulation time 231591554 ps
CPU time 4.76 seconds
Started Aug 23 10:29:35 PM UTC 24
Finished Aug 23 10:29:41 PM UTC 24
Peak memory 235340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104641177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1104641177
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mailbox.1989603120
Short name T543
Test name
Test status
Simulation time 41726247615 ps
CPU time 68.77 seconds
Started Aug 23 10:29:36 PM UTC 24
Finished Aug 23 10:30:47 PM UTC 24
Peak memory 245704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989603120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1989603120
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mem_parity.3181557792
Short name T508
Test name
Test status
Simulation time 83284772 ps
CPU time 0.91 seconds
Started Aug 23 10:29:30 PM UTC 24
Finished Aug 23 10:29:32 PM UTC 24
Peak memory 229204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181557792 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mem_parity.3181557792
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.1031070438
Short name T515
Test name
Test status
Simulation time 500845541 ps
CPU time 2.32 seconds
Started Aug 23 10:29:34 PM UTC 24
Finished Aug 23 10:29:37 PM UTC 24
Peak memory 245768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031070438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.1031070438
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.2470705463
Short name T520
Test name
Test status
Simulation time 8837111565 ps
CPU time 20.24 seconds
Started Aug 23 10:29:34 PM UTC 24
Finished Aug 23 10:29:55 PM UTC 24
Peak memory 251792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470705463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2470705463
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.1935892304
Short name T518
Test name
Test status
Simulation time 249191920 ps
CPU time 4.05 seconds
Started Aug 23 10:29:41 PM UTC 24
Finished Aug 23 10:29:47 PM UTC 24
Peak memory 231672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935892304 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.1935892304
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_stress_all.1449967539
Short name T354
Test name
Test status
Simulation time 2386645344 ps
CPU time 48.96 seconds
Started Aug 23 10:29:53 PM UTC 24
Finished Aug 23 10:30:43 PM UTC 24
Peak memory 262348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449967539 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.1449967539
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_all.3088915511
Short name T513
Test name
Test status
Simulation time 2288663090 ps
CPU time 3.63 seconds
Started Aug 23 10:29:32 PM UTC 24
Finished Aug 23 10:29:37 PM UTC 24
Peak memory 227960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088915511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3088915511
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.773635253
Short name T514
Test name
Test status
Simulation time 2547953333 ps
CPU time 4.84 seconds
Started Aug 23 10:29:31 PM UTC 24
Finished Aug 23 10:29:37 PM UTC 24
Peak memory 227800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773635253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.773635253
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_rw.53702079
Short name T512
Test name
Test status
Simulation time 309073087 ps
CPU time 1.48 seconds
Started Aug 23 10:29:33 PM UTC 24
Finished Aug 23 10:29:35 PM UTC 24
Peak memory 228028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53702079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_devi
ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.53702079
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.443431459
Short name T510
Test name
Test status
Simulation time 48451395 ps
CPU time 0.75 seconds
Started Aug 23 10:29:32 PM UTC 24
Finished Aug 23 10:29:34 PM UTC 24
Peak memory 215924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443431459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.443431459
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/19.spi_device_upload.905723428
Short name T519
Test name
Test status
Simulation time 4220847505 ps
CPU time 14.91 seconds
Started Aug 23 10:29:37 PM UTC 24
Finished Aug 23 10:29:54 PM UTC 24
Peak memory 245700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905723428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.905723428
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/19.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.2313576178
Short name T94
Test name
Test status
Simulation time 33285525 ps
CPU time 0.6 seconds
Started Aug 23 10:22:26 PM UTC 24
Finished Aug 23 10:22:28 PM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313576178 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2313576178
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.1992968339
Short name T102
Test name
Test status
Simulation time 6496400080 ps
CPU time 14.77 seconds
Started Aug 23 10:22:14 PM UTC 24
Finished Aug 23 10:22:30 PM UTC 24
Peak memory 245648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992968339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1992968339
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.2710211317
Short name T30
Test name
Test status
Simulation time 33179812 ps
CPU time 0.71 seconds
Started Aug 23 10:22:07 PM UTC 24
Finished Aug 23 10:22:09 PM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710211317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2710211317
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.2010302056
Short name T66
Test name
Test status
Simulation time 38867632732 ps
CPU time 90.77 seconds
Started Aug 23 10:22:21 PM UTC 24
Finished Aug 23 10:23:53 PM UTC 24
Peak memory 266192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010302056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2010302056
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.943393559
Short name T51
Test name
Test status
Simulation time 2047874570 ps
CPU time 12.76 seconds
Started Aug 23 10:22:15 PM UTC 24
Finished Aug 23 10:22:29 PM UTC 24
Peak memory 245732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943393559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.943393559
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.2060835722
Short name T58
Test name
Test status
Simulation time 526599964 ps
CPU time 7.44 seconds
Started Aug 23 10:22:11 PM UTC 24
Finished Aug 23 10:22:20 PM UTC 24
Peak memory 245584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060835722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2060835722
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.1597692860
Short name T108
Test name
Test status
Simulation time 46989745350 ps
CPU time 32.63 seconds
Started Aug 23 10:22:12 PM UTC 24
Finished Aug 23 10:22:46 PM UTC 24
Peak memory 235404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597692860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1597692860
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.3642175971
Short name T43
Test name
Test status
Simulation time 45847555 ps
CPU time 0.92 seconds
Started Aug 23 10:22:07 PM UTC 24
Finished Aug 23 10:22:09 PM UTC 24
Peak memory 229208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642175971 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_parity.3642175971
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.2357266123
Short name T54
Test name
Test status
Simulation time 5455002558 ps
CPU time 4.98 seconds
Started Aug 23 10:22:10 PM UTC 24
Finished Aug 23 10:22:17 PM UTC 24
Peak memory 235656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357266123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.2357266123
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.1549688959
Short name T60
Test name
Test status
Simulation time 80715574136 ps
CPU time 12.16 seconds
Started Aug 23 10:22:10 PM UTC 24
Finished Aug 23 10:22:24 PM UTC 24
Peak memory 245900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549688959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1549688959
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.3721544843
Short name T46
Test name
Test status
Simulation time 1842176211 ps
CPU time 6.27 seconds
Started Aug 23 10:22:18 PM UTC 24
Finished Aug 23 10:22:25 PM UTC 24
Peak memory 233680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721544843 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.3721544843
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.1620096911
Short name T25
Test name
Test status
Simulation time 83208488 ps
CPU time 0.81 seconds
Started Aug 23 10:22:24 PM UTC 24
Finished Aug 23 10:22:27 PM UTC 24
Peak memory 257680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620096911 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1620096911
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.2634807006
Short name T24
Test name
Test status
Simulation time 77832162 ps
CPU time 0.77 seconds
Started Aug 23 10:22:23 PM UTC 24
Finished Aug 23 10:22:25 PM UTC 24
Peak memory 215888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634807006 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.2634807006
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.1945042042
Short name T34
Test name
Test status
Simulation time 1962337128 ps
CPU time 11.71 seconds
Started Aug 23 10:22:09 PM UTC 24
Finished Aug 23 10:22:23 PM UTC 24
Peak memory 227768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945042042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1945042042
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.2983231228
Short name T33
Test name
Test status
Simulation time 1481432784 ps
CPU time 3.34 seconds
Started Aug 23 10:22:08 PM UTC 24
Finished Aug 23 10:22:13 PM UTC 24
Peak memory 227772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983231228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2983231228
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.1255012140
Short name T32
Test name
Test status
Simulation time 69630735 ps
CPU time 1.28 seconds
Started Aug 23 10:22:10 PM UTC 24
Finished Aug 23 10:22:13 PM UTC 24
Peak memory 226928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255012140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1255012140
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.1372774523
Short name T31
Test name
Test status
Simulation time 825059423 ps
CPU time 0.83 seconds
Started Aug 23 10:22:09 PM UTC 24
Finished Aug 23 10:22:12 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372774523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1372774523
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.2173353161
Short name T59
Test name
Test status
Simulation time 1678008024 ps
CPU time 13.03 seconds
Started Aug 23 10:22:14 PM UTC 24
Finished Aug 23 10:22:28 PM UTC 24
Peak memory 247816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173353161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2173353161
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/2.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/20.spi_device_alert_test.2863833243
Short name T534
Test name
Test status
Simulation time 93209991 ps
CPU time 0.64 seconds
Started Aug 23 10:30:31 PM UTC 24
Finished Aug 23 10:30:33 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863833243 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.2863833243
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/20.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/20.spi_device_cfg_cmd.2813990129
Short name T531
Test name
Test status
Simulation time 1115125233 ps
CPU time 12.43 seconds
Started Aug 23 10:30:08 PM UTC 24
Finished Aug 23 10:30:22 PM UTC 24
Peak memory 235404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813990129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2813990129
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/20.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/20.spi_device_csb_read.1980587088
Short name T522
Test name
Test status
Simulation time 59916893 ps
CPU time 0.65 seconds
Started Aug 23 10:29:55 PM UTC 24
Finished Aug 23 10:29:56 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980587088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1980587088
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/20.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_all.2870158594
Short name T312
Test name
Test status
Simulation time 60292371316 ps
CPU time 222.15 seconds
Started Aug 23 10:30:22 PM UTC 24
Finished Aug 23 10:34:07 PM UTC 24
Peak memory 268236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870158594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2870158594
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/20.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.4178263802
Short name T256
Test name
Test status
Simulation time 10158164958 ps
CPU time 50.39 seconds
Started Aug 23 10:30:23 PM UTC 24
Finished Aug 23 10:31:15 PM UTC 24
Peak memory 252108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178263802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.4178263802
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.2866884271
Short name T540
Test name
Test status
Simulation time 2111541149 ps
CPU time 14.32 seconds
Started Aug 23 10:30:24 PM UTC 24
Finished Aug 23 10:30:40 PM UTC 24
Peak memory 229880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866884271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.2866884271
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode.2877932057
Short name T548
Test name
Test status
Simulation time 7309600306 ps
CPU time 41.53 seconds
Started Aug 23 10:30:10 PM UTC 24
Finished Aug 23 10:30:53 PM UTC 24
Peak memory 245700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877932057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2877932057
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/20.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.2504512550
Short name T571
Test name
Test status
Simulation time 5839583700 ps
CPU time 67.16 seconds
Started Aug 23 10:30:17 PM UTC 24
Finished Aug 23 10:31:26 PM UTC 24
Peak memory 268232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504512550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.2504512550
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/20.spi_device_intercept.2027493898
Short name T254
Test name
Test status
Simulation time 317392077 ps
CPU time 3.73 seconds
Started Aug 23 10:30:01 PM UTC 24
Finished Aug 23 10:30:06 PM UTC 24
Peak memory 245740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027493898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2027493898
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/20.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/20.spi_device_mailbox.713361252
Short name T536
Test name
Test status
Simulation time 8702837753 ps
CPU time 29.98 seconds
Started Aug 23 10:30:03 PM UTC 24
Finished Aug 23 10:30:35 PM UTC 24
Peak memory 245648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713361252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.713361252
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/20.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.2847953933
Short name T527
Test name
Test status
Simulation time 54524909 ps
CPU time 1.87 seconds
Started Aug 23 10:29:59 PM UTC 24
Finished Aug 23 10:30:02 PM UTC 24
Peak memory 244676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847953933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.2847953933
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/20.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.3806232019
Short name T272
Test name
Test status
Simulation time 3782682398 ps
CPU time 7.01 seconds
Started Aug 23 10:29:59 PM UTC 24
Finished Aug 23 10:30:07 PM UTC 24
Peak memory 247724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806232019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3806232019
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/20.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.2944081901
Short name T530
Test name
Test status
Simulation time 759488525 ps
CPU time 3.27 seconds
Started Aug 23 10:30:17 PM UTC 24
Finished Aug 23 10:30:22 PM UTC 24
Peak memory 233936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944081901 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.2944081901
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/20.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/20.spi_device_stress_all.1998122490
Short name T533
Test name
Test status
Simulation time 173182786 ps
CPU time 0.74 seconds
Started Aug 23 10:30:30 PM UTC 24
Finished Aug 23 10:30:32 PM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998122490 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.1998122490
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/20.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_all.4037747255
Short name T524
Test name
Test status
Simulation time 23675819 ps
CPU time 0.63 seconds
Started Aug 23 10:29:57 PM UTC 24
Finished Aug 23 10:29:58 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037747255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.4037747255
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/20.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.1873559056
Short name T532
Test name
Test status
Simulation time 37782489714 ps
CPU time 25.7 seconds
Started Aug 23 10:29:57 PM UTC 24
Finished Aug 23 10:30:24 PM UTC 24
Peak memory 229948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873559056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1873559056
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/20.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_rw.1606625494
Short name T526
Test name
Test status
Simulation time 13297753 ps
CPU time 0.72 seconds
Started Aug 23 10:29:58 PM UTC 24
Finished Aug 23 10:30:00 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606625494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1606625494
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/20.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.2131114217
Short name T525
Test name
Test status
Simulation time 86082710 ps
CPU time 0.73 seconds
Started Aug 23 10:29:57 PM UTC 24
Finished Aug 23 10:29:58 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131114217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2131114217
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/20.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/20.spi_device_upload.2627925285
Short name T529
Test name
Test status
Simulation time 4335289673 ps
CPU time 8.28 seconds
Started Aug 23 10:30:07 PM UTC 24
Finished Aug 23 10:30:16 PM UTC 24
Peak memory 245928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627925285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2627925285
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/20.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/21.spi_device_alert_test.458357860
Short name T550
Test name
Test status
Simulation time 16252436 ps
CPU time 0.63 seconds
Started Aug 23 10:30:55 PM UTC 24
Finished Aug 23 10:30:57 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458357860 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.458357860
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/21.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/21.spi_device_cfg_cmd.2174923851
Short name T283
Test name
Test status
Simulation time 2166797712 ps
CPU time 11.26 seconds
Started Aug 23 10:30:43 PM UTC 24
Finished Aug 23 10:30:55 PM UTC 24
Peak memory 245808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174923851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2174923851
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/21.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/21.spi_device_csb_read.3550400938
Short name T535
Test name
Test status
Simulation time 44406069 ps
CPU time 0.65 seconds
Started Aug 23 10:30:32 PM UTC 24
Finished Aug 23 10:30:34 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550400938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3550400938
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/21.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_all.3059749780
Short name T340
Test name
Test status
Simulation time 241077023171 ps
CPU time 391.68 seconds
Started Aug 23 10:30:50 PM UTC 24
Finished Aug 23 10:37:26 PM UTC 24
Peak memory 262084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059749780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3059749780
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/21.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.4113075340
Short name T604
Test name
Test status
Simulation time 32644753729 ps
CPU time 121.77 seconds
Started Aug 23 10:30:52 PM UTC 24
Finished Aug 23 10:32:56 PM UTC 24
Peak memory 251912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113075340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.4113075340
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.132510576
Short name T602
Test name
Test status
Simulation time 11621360750 ps
CPU time 117.09 seconds
Started Aug 23 10:30:53 PM UTC 24
Finished Aug 23 10:32:52 PM UTC 24
Peak memory 262152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132510576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.132510576
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode.1482409340
Short name T553
Test name
Test status
Simulation time 756766877 ps
CPU time 13.02 seconds
Started Aug 23 10:30:44 PM UTC 24
Finished Aug 23 10:30:58 PM UTC 24
Peak memory 261996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482409340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1482409340
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/21.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.842473880
Short name T573
Test name
Test status
Simulation time 4289995829 ps
CPU time 40.93 seconds
Started Aug 23 10:30:47 PM UTC 24
Finished Aug 23 10:31:29 PM UTC 24
Peak memory 262120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842473880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.842473880
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/21.spi_device_intercept.3226564640
Short name T545
Test name
Test status
Simulation time 2402319848 ps
CPU time 9.62 seconds
Started Aug 23 10:30:39 PM UTC 24
Finished Aug 23 10:30:49 PM UTC 24
Peak memory 235600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226564640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3226564640
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/21.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/21.spi_device_mailbox.1601863419
Short name T300
Test name
Test status
Simulation time 8786550654 ps
CPU time 49.16 seconds
Started Aug 23 10:30:41 PM UTC 24
Finished Aug 23 10:31:32 PM UTC 24
Peak memory 252072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601863419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1601863419
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/21.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.3294770457
Short name T293
Test name
Test status
Simulation time 981978352 ps
CPU time 2.55 seconds
Started Aug 23 10:30:39 PM UTC 24
Finished Aug 23 10:30:42 PM UTC 24
Peak memory 245796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294770457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.3294770457
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/21.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.265946041
Short name T541
Test name
Test status
Simulation time 56364906 ps
CPU time 2.14 seconds
Started Aug 23 10:30:38 PM UTC 24
Finished Aug 23 10:30:41 PM UTC 24
Peak memory 245588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265946041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.265946041
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/21.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.1242446843
Short name T549
Test name
Test status
Simulation time 3599130057 ps
CPU time 4.08 seconds
Started Aug 23 10:30:49 PM UTC 24
Finished Aug 23 10:30:54 PM UTC 24
Peak memory 233844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242446843 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.1242446843
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/21.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_all.3416398169
Short name T544
Test name
Test status
Simulation time 14838552515 ps
CPU time 13.44 seconds
Started Aug 23 10:30:34 PM UTC 24
Finished Aug 23 10:30:48 PM UTC 24
Peak memory 232084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416398169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3416398169
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/21.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.3766543392
Short name T539
Test name
Test status
Simulation time 962424564 ps
CPU time 3.48 seconds
Started Aug 23 10:30:34 PM UTC 24
Finished Aug 23 10:30:38 PM UTC 24
Peak memory 227788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766543392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3766543392
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/21.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_rw.1931992647
Short name T538
Test name
Test status
Simulation time 52045806 ps
CPU time 1.03 seconds
Started Aug 23 10:30:36 PM UTC 24
Finished Aug 23 10:30:38 PM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931992647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1931992647
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/21.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.4217841158
Short name T537
Test name
Test status
Simulation time 120203708 ps
CPU time 0.82 seconds
Started Aug 23 10:30:35 PM UTC 24
Finished Aug 23 10:30:37 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217841158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.4217841158
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/21.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/21.spi_device_upload.2206479876
Short name T546
Test name
Test status
Simulation time 1394753917 ps
CPU time 8.03 seconds
Started Aug 23 10:30:42 PM UTC 24
Finished Aug 23 10:30:51 PM UTC 24
Peak memory 235340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206479876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2206479876
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/21.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/22.spi_device_alert_test.1761117744
Short name T566
Test name
Test status
Simulation time 15684709 ps
CPU time 0.65 seconds
Started Aug 23 10:31:19 PM UTC 24
Finished Aug 23 10:31:21 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761117744 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.1761117744
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/22.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/22.spi_device_cfg_cmd.300797620
Short name T563
Test name
Test status
Simulation time 3205288969 ps
CPU time 9.6 seconds
Started Aug 23 10:31:05 PM UTC 24
Finished Aug 23 10:31:15 PM UTC 24
Peak memory 245732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300797620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.300797620
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/22.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/22.spi_device_csb_read.728790596
Short name T551
Test name
Test status
Simulation time 57351394 ps
CPU time 0.66 seconds
Started Aug 23 10:30:55 PM UTC 24
Finished Aug 23 10:30:57 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728790596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.728790596
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/22.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_all.3207337259
Short name T224
Test name
Test status
Simulation time 130741234236 ps
CPU time 331.83 seconds
Started Aug 23 10:31:11 PM UTC 24
Finished Aug 23 10:36:47 PM UTC 24
Peak memory 284840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207337259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3207337259
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/22.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.2020233542
Short name T42
Test name
Test status
Simulation time 30863118474 ps
CPU time 102.69 seconds
Started Aug 23 10:31:15 PM UTC 24
Finished Aug 23 10:33:00 PM UTC 24
Peak memory 266448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020233542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2020233542
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/22.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode.2473832941
Short name T564
Test name
Test status
Simulation time 3360242198 ps
CPU time 9.35 seconds
Started Aug 23 10:31:08 PM UTC 24
Finished Aug 23 10:31:18 PM UTC 24
Peak memory 235464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473832941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2473832941
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/22.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.1698802659
Short name T337
Test name
Test status
Simulation time 317892275846 ps
CPU time 314.82 seconds
Started Aug 23 10:31:08 PM UTC 24
Finished Aug 23 10:36:26 PM UTC 24
Peak memory 262116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698802659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.1698802659
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/22.spi_device_intercept.2465160376
Short name T559
Test name
Test status
Simulation time 1322635728 ps
CPU time 6.07 seconds
Started Aug 23 10:31:00 PM UTC 24
Finished Aug 23 10:31:07 PM UTC 24
Peak memory 235368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465160376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2465160376
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/22.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/22.spi_device_mailbox.719330316
Short name T558
Test name
Test status
Simulation time 305535886 ps
CPU time 1.77 seconds
Started Aug 23 10:31:01 PM UTC 24
Finished Aug 23 10:31:03 PM UTC 24
Peak memory 234132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719330316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.719330316
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/22.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.3401308239
Short name T561
Test name
Test status
Simulation time 4152310124 ps
CPU time 8.65 seconds
Started Aug 23 10:31:00 PM UTC 24
Finished Aug 23 10:31:09 PM UTC 24
Peak memory 245896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401308239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.3401308239
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/22.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.1628027652
Short name T286
Test name
Test status
Simulation time 15060996947 ps
CPU time 10.83 seconds
Started Aug 23 10:30:59 PM UTC 24
Finished Aug 23 10:31:10 PM UTC 24
Peak memory 245712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628027652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1628027652
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/22.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.382994304
Short name T562
Test name
Test status
Simulation time 385063532 ps
CPU time 3.59 seconds
Started Aug 23 10:31:10 PM UTC 24
Finished Aug 23 10:31:15 PM UTC 24
Peak memory 231732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382994304 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.382994304
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/22.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.3419414516
Short name T314
Test name
Test status
Simulation time 222314614548 ps
CPU time 459.17 seconds
Started Aug 23 10:31:16 PM UTC 24
Finished Aug 23 10:39:00 PM UTC 24
Peak memory 284872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419414516 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.3419414516
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/22.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_all.3712543554
Short name T554
Test name
Test status
Simulation time 10422456 ps
CPU time 0.6 seconds
Started Aug 23 10:30:57 PM UTC 24
Finished Aug 23 10:30:59 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712543554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3712543554
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/22.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.3212719311
Short name T552
Test name
Test status
Simulation time 50809271 ps
CPU time 0.62 seconds
Started Aug 23 10:30:56 PM UTC 24
Finished Aug 23 10:30:58 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212719311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3212719311
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/22.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_rw.968212047
Short name T556
Test name
Test status
Simulation time 18765660 ps
CPU time 0.61 seconds
Started Aug 23 10:30:58 PM UTC 24
Finished Aug 23 10:31:00 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968212047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.968212047
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/22.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.3522246936
Short name T555
Test name
Test status
Simulation time 31426279 ps
CPU time 0.71 seconds
Started Aug 23 10:30:57 PM UTC 24
Finished Aug 23 10:30:59 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522246936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3522246936
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/22.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/22.spi_device_upload.907759981
Short name T565
Test name
Test status
Simulation time 26214162223 ps
CPU time 18.87 seconds
Started Aug 23 10:31:01 PM UTC 24
Finished Aug 23 10:31:21 PM UTC 24
Peak memory 235472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907759981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.907759981
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/22.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_alert_test.37380131
Short name T580
Test name
Test status
Simulation time 43272961 ps
CPU time 0.63 seconds
Started Aug 23 10:31:48 PM UTC 24
Finished Aug 23 10:31:50 PM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37380131 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.37380131
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/23.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_cfg_cmd.573557038
Short name T582
Test name
Test status
Simulation time 7066309969 ps
CPU time 19.52 seconds
Started Aug 23 10:31:33 PM UTC 24
Finished Aug 23 10:31:54 PM UTC 24
Peak memory 245680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573557038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.573557038
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/23.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_csb_read.2477357588
Short name T568
Test name
Test status
Simulation time 30846061 ps
CPU time 0.67 seconds
Started Aug 23 10:31:21 PM UTC 24
Finished Aug 23 10:31:23 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477357588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2477357588
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/23.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.2393809896
Short name T221
Test name
Test status
Simulation time 976777413 ps
CPU time 22.92 seconds
Started Aug 23 10:31:38 PM UTC 24
Finished Aug 23 10:32:02 PM UTC 24
Peak memory 245772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393809896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2393809896
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode.2451001866
Short name T579
Test name
Test status
Simulation time 1141087056 ps
CPU time 11.85 seconds
Started Aug 23 10:31:34 PM UTC 24
Finished Aug 23 10:31:47 PM UTC 24
Peak memory 245572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451001866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2451001866
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/23.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_intercept.2647118715
Short name T276
Test name
Test status
Simulation time 2791864331 ps
CPU time 5.49 seconds
Started Aug 23 10:31:27 PM UTC 24
Finished Aug 23 10:31:33 PM UTC 24
Peak memory 245708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647118715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2647118715
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/23.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_mailbox.2367102009
Short name T575
Test name
Test status
Simulation time 2596979299 ps
CPU time 5.69 seconds
Started Aug 23 10:31:30 PM UTC 24
Finished Aug 23 10:31:37 PM UTC 24
Peak memory 244508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367102009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2367102009
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/23.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.10172097
Short name T295
Test name
Test status
Simulation time 1511877577 ps
CPU time 5.58 seconds
Started Aug 23 10:31:27 PM UTC 24
Finished Aug 23 10:31:33 PM UTC 24
Peak memory 245552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10172097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.10172097
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/23.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.3358866997
Short name T572
Test name
Test status
Simulation time 66748207 ps
CPU time 2 seconds
Started Aug 23 10:31:25 PM UTC 24
Finished Aug 23 10:31:29 PM UTC 24
Peak memory 244948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358866997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3358866997
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/23.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.4027374446
Short name T578
Test name
Test status
Simulation time 1126342020 ps
CPU time 7.82 seconds
Started Aug 23 10:31:35 PM UTC 24
Finished Aug 23 10:31:44 PM UTC 24
Peak memory 231800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027374446 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.4027374446
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/23.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.2097474408
Short name T542
Test name
Test status
Simulation time 3913170237 ps
CPU time 16.44 seconds
Started Aug 23 10:31:45 PM UTC 24
Finished Aug 23 10:32:03 PM UTC 24
Peak memory 252044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097474408 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.2097474408
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/23.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_all.463405254
Short name T577
Test name
Test status
Simulation time 9834473107 ps
CPU time 17.53 seconds
Started Aug 23 10:31:23 PM UTC 24
Finished Aug 23 10:31:42 PM UTC 24
Peak memory 227900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463405254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.463405254
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/23.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.3033121300
Short name T567
Test name
Test status
Simulation time 26907610 ps
CPU time 0.6 seconds
Started Aug 23 10:31:21 PM UTC 24
Finished Aug 23 10:31:23 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033121300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3033121300
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/23.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_rw.956839839
Short name T576
Test name
Test status
Simulation time 6540356075 ps
CPU time 11.12 seconds
Started Aug 23 10:31:24 PM UTC 24
Finished Aug 23 10:31:37 PM UTC 24
Peak memory 228024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956839839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.956839839
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/23.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.793786760
Short name T570
Test name
Test status
Simulation time 139842214 ps
CPU time 0.71 seconds
Started Aug 23 10:31:23 PM UTC 24
Finished Aug 23 10:31:25 PM UTC 24
Peak memory 215924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793786760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.793786760
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/23.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/23.spi_device_upload.4226993133
Short name T574
Test name
Test status
Simulation time 2246569255 ps
CPU time 2.61 seconds
Started Aug 23 10:31:31 PM UTC 24
Finished Aug 23 10:31:34 PM UTC 24
Peak memory 245736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226993133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.4226993133
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/23.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/24.spi_device_alert_test.2734900792
Short name T593
Test name
Test status
Simulation time 22027913 ps
CPU time 0.61 seconds
Started Aug 23 10:32:23 PM UTC 24
Finished Aug 23 10:32:25 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734900792 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.2734900792
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/24.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/24.spi_device_cfg_cmd.1667959298
Short name T589
Test name
Test status
Simulation time 617264791 ps
CPU time 3.53 seconds
Started Aug 23 10:32:08 PM UTC 24
Finished Aug 23 10:32:12 PM UTC 24
Peak memory 235368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667959298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1667959298
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/24.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/24.spi_device_csb_read.892235656
Short name T581
Test name
Test status
Simulation time 15579042 ps
CPU time 0.68 seconds
Started Aug 23 10:31:48 PM UTC 24
Finished Aug 23 10:31:50 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892235656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.892235656
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/24.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.96517904
Short name T636
Test name
Test status
Simulation time 60243705884 ps
CPU time 109.18 seconds
Started Aug 23 10:32:13 PM UTC 24
Finished Aug 23 10:34:04 PM UTC 24
Peak memory 262096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96517904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.96517904
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/24.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.1407981439
Short name T317
Test name
Test status
Simulation time 10204979030 ps
CPU time 98.07 seconds
Started Aug 23 10:32:13 PM UTC 24
Finished Aug 23 10:33:53 PM UTC 24
Peak memory 284660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407981439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1407981439
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.2343111630
Short name T328
Test name
Test status
Simulation time 153880976864 ps
CPU time 318.04 seconds
Started Aug 23 10:32:16 PM UTC 24
Finished Aug 23 10:37:38 PM UTC 24
Peak memory 264192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343111630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.2343111630
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.1211159603
Short name T590
Test name
Test status
Simulation time 32849267 ps
CPU time 1.82 seconds
Started Aug 23 10:32:10 PM UTC 24
Finished Aug 23 10:32:12 PM UTC 24
Peak memory 234788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211159603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1211159603
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/24.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.2730286554
Short name T598
Test name
Test status
Simulation time 6436751312 ps
CPU time 34.3 seconds
Started Aug 23 10:32:11 PM UTC 24
Finished Aug 23 10:32:46 PM UTC 24
Peak memory 262084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730286554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.2730286554
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/24.spi_device_intercept.2539199144
Short name T213
Test name
Test status
Simulation time 539287855 ps
CPU time 4.38 seconds
Started Aug 23 10:32:03 PM UTC 24
Finished Aug 23 10:32:09 PM UTC 24
Peak memory 245580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539199144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2539199144
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/24.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/24.spi_device_mailbox.148190923
Short name T591
Test name
Test status
Simulation time 1844144430 ps
CPU time 10.11 seconds
Started Aug 23 10:32:03 PM UTC 24
Finished Aug 23 10:32:15 PM UTC 24
Peak memory 251724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148190923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.148190923
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/24.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.207213378
Short name T587
Test name
Test status
Simulation time 4230388081 ps
CPU time 3.99 seconds
Started Aug 23 10:32:01 PM UTC 24
Finished Aug 23 10:32:07 PM UTC 24
Peak memory 235408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207213378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.207213378
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/24.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.2536051523
Short name T586
Test name
Test status
Simulation time 980945036 ps
CPU time 3.11 seconds
Started Aug 23 10:32:00 PM UTC 24
Finished Aug 23 10:32:05 PM UTC 24
Peak memory 245612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536051523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2536051523
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/24.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.3301601818
Short name T592
Test name
Test status
Simulation time 3795737378 ps
CPU time 4.97 seconds
Started Aug 23 10:32:12 PM UTC 24
Finished Aug 23 10:32:18 PM UTC 24
Peak memory 231992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301601818 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.3301601818
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/24.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/24.spi_device_stress_all.1233536072
Short name T179
Test name
Test status
Simulation time 7572055826 ps
CPU time 44.81 seconds
Started Aug 23 10:32:19 PM UTC 24
Finished Aug 23 10:33:05 PM UTC 24
Peak memory 262152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233536072 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.1233536072
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/24.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_all.928638676
Short name T584
Test name
Test status
Simulation time 1402578686 ps
CPU time 8.11 seconds
Started Aug 23 10:31:50 PM UTC 24
Finished Aug 23 10:31:59 PM UTC 24
Peak memory 227800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928638676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.928638676
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/24.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.3140366114
Short name T588
Test name
Test status
Simulation time 41914498190 ps
CPU time 18.36 seconds
Started Aug 23 10:31:50 PM UTC 24
Finished Aug 23 10:32:10 PM UTC 24
Peak memory 227836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140366114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3140366114
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/24.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_rw.2073400211
Short name T585
Test name
Test status
Simulation time 78278701 ps
CPU time 2.55 seconds
Started Aug 23 10:31:57 PM UTC 24
Finished Aug 23 10:32:01 PM UTC 24
Peak memory 228064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073400211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2073400211
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/24.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.230500100
Short name T583
Test name
Test status
Simulation time 34410830 ps
CPU time 0.73 seconds
Started Aug 23 10:31:54 PM UTC 24
Finished Aug 23 10:31:56 PM UTC 24
Peak memory 215924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230500100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.230500100
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/24.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/24.spi_device_upload.19063537
Short name T236
Test name
Test status
Simulation time 48850126223 ps
CPU time 34.48 seconds
Started Aug 23 10:32:05 PM UTC 24
Finished Aug 23 10:32:41 PM UTC 24
Peak memory 245736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19063537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_devi
ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.19063537
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/24.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/25.spi_device_alert_test.3637923928
Short name T606
Test name
Test status
Simulation time 41698818 ps
CPU time 0.6 seconds
Started Aug 23 10:32:57 PM UTC 24
Finished Aug 23 10:32:58 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637923928 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.3637923928
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/25.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/25.spi_device_cfg_cmd.2471963631
Short name T603
Test name
Test status
Simulation time 1992943669 ps
CPU time 4.89 seconds
Started Aug 23 10:32:47 PM UTC 24
Finished Aug 23 10:32:53 PM UTC 24
Peak memory 235352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471963631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2471963631
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/25.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/25.spi_device_csb_read.1293128710
Short name T594
Test name
Test status
Simulation time 69900739 ps
CPU time 0.68 seconds
Started Aug 23 10:32:25 PM UTC 24
Finished Aug 23 10:32:27 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293128710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1293128710
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/25.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_all.3765586760
Short name T620
Test name
Test status
Simulation time 3306715418 ps
CPU time 39.42 seconds
Started Aug 23 10:32:53 PM UTC 24
Finished Aug 23 10:33:33 PM UTC 24
Peak memory 262092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765586760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3765586760
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/25.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.954149214
Short name T696
Test name
Test status
Simulation time 100109740112 ps
CPU time 191.65 seconds
Started Aug 23 10:32:54 PM UTC 24
Finished Aug 23 10:36:08 PM UTC 24
Peak memory 262284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954149214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.954149214
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.1996740975
Short name T627
Test name
Test status
Simulation time 18840191581 ps
CPU time 52.52 seconds
Started Aug 23 10:32:54 PM UTC 24
Finished Aug 23 10:33:48 PM UTC 24
Peak memory 235588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996740975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.1996740975
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode.3819847613
Short name T629
Test name
Test status
Simulation time 4998215994 ps
CPU time 61.02 seconds
Started Aug 23 10:32:48 PM UTC 24
Finished Aug 23 10:33:51 PM UTC 24
Peak memory 262120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819847613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3819847613
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/25.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.3093800032
Short name T669
Test name
Test status
Simulation time 21505711081 ps
CPU time 142.93 seconds
Started Aug 23 10:32:52 PM UTC 24
Finished Aug 23 10:35:17 PM UTC 24
Peak memory 262088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093800032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.3093800032
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/25.spi_device_intercept.2071159937
Short name T600
Test name
Test status
Simulation time 224759880 ps
CPU time 3.18 seconds
Started Aug 23 10:32:46 PM UTC 24
Finished Aug 23 10:32:51 PM UTC 24
Peak memory 235276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071159937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2071159937
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/25.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/25.spi_device_mailbox.2248740375
Short name T625
Test name
Test status
Simulation time 35350486895 ps
CPU time 55.67 seconds
Started Aug 23 10:32:46 PM UTC 24
Finished Aug 23 10:33:44 PM UTC 24
Peak memory 245740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248740375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2248740375
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/25.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.2328176346
Short name T599
Test name
Test status
Simulation time 1205072584 ps
CPU time 2.95 seconds
Started Aug 23 10:32:42 PM UTC 24
Finished Aug 23 10:32:46 PM UTC 24
Peak memory 242232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328176346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.2328176346
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/25.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.4248739057
Short name T601
Test name
Test status
Simulation time 3530063240 ps
CPU time 10.62 seconds
Started Aug 23 10:32:40 PM UTC 24
Finished Aug 23 10:32:52 PM UTC 24
Peak memory 235436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248739057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.4248739057
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/25.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.3886774238
Short name T605
Test name
Test status
Simulation time 329166542 ps
CPU time 2.76 seconds
Started Aug 23 10:32:53 PM UTC 24
Finished Aug 23 10:32:56 PM UTC 24
Peak memory 231608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886774238 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.3886774238
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/25.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.803380915
Short name T322
Test name
Test status
Simulation time 134927391174 ps
CPU time 519.06 seconds
Started Aug 23 10:32:57 PM UTC 24
Finished Aug 23 10:41:42 PM UTC 24
Peak memory 278536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803380915 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.803380915
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/25.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_all.2760356980
Short name T356
Test name
Test status
Simulation time 10640647346 ps
CPU time 12.03 seconds
Started Aug 23 10:32:32 PM UTC 24
Finished Aug 23 10:32:45 PM UTC 24
Peak memory 227960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760356980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2760356980
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/25.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.370714870
Short name T595
Test name
Test status
Simulation time 413471912 ps
CPU time 2.88 seconds
Started Aug 23 10:32:27 PM UTC 24
Finished Aug 23 10:32:31 PM UTC 24
Peak memory 227892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370714870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.370714870
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/25.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_rw.4098660002
Short name T597
Test name
Test status
Simulation time 22128295 ps
CPU time 0.82 seconds
Started Aug 23 10:32:37 PM UTC 24
Finished Aug 23 10:32:39 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098660002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.4098660002
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/25.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.3719784125
Short name T596
Test name
Test status
Simulation time 568251272 ps
CPU time 0.68 seconds
Started Aug 23 10:32:35 PM UTC 24
Finished Aug 23 10:32:37 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719784125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3719784125
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/25.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/25.spi_device_upload.2974094721
Short name T226
Test name
Test status
Simulation time 235457499 ps
CPU time 3.7 seconds
Started Aug 23 10:32:47 PM UTC 24
Finished Aug 23 10:32:52 PM UTC 24
Peak memory 245740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974094721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2974094721
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/25.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/26.spi_device_alert_test.3926991257
Short name T621
Test name
Test status
Simulation time 30578890 ps
CPU time 0.61 seconds
Started Aug 23 10:33:35 PM UTC 24
Finished Aug 23 10:33:37 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926991257 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.3926991257
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/26.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/26.spi_device_cfg_cmd.1906779401
Short name T615
Test name
Test status
Simulation time 93026544 ps
CPU time 1.62 seconds
Started Aug 23 10:33:08 PM UTC 24
Finished Aug 23 10:33:11 PM UTC 24
Peak memory 233696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906779401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1906779401
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/26.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/26.spi_device_csb_read.3003586659
Short name T608
Test name
Test status
Simulation time 20786803 ps
CPU time 0.73 seconds
Started Aug 23 10:32:59 PM UTC 24
Finished Aug 23 10:33:01 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003586659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3003586659
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/26.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.2495916084
Short name T635
Test name
Test status
Simulation time 13685531295 ps
CPU time 38.54 seconds
Started Aug 23 10:33:24 PM UTC 24
Finished Aug 23 10:34:04 PM UTC 24
Peak memory 264396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495916084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2495916084
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/26.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.3861935353
Short name T320
Test name
Test status
Simulation time 138961469667 ps
CPU time 274.01 seconds
Started Aug 23 10:33:27 PM UTC 24
Finished Aug 23 10:38:04 PM UTC 24
Peak memory 262148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861935353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3861935353
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.3999402304
Short name T664
Test name
Test status
Simulation time 9551418939 ps
CPU time 96.1 seconds
Started Aug 23 10:33:29 PM UTC 24
Finished Aug 23 10:35:07 PM UTC 24
Peak memory 268548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999402304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.3999402304
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode.1228606281
Short name T343
Test name
Test status
Simulation time 1845512793 ps
CPU time 21.66 seconds
Started Aug 23 10:33:11 PM UTC 24
Finished Aug 23 10:33:34 PM UTC 24
Peak memory 251752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228606281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1228606281
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/26.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.1051561991
Short name T619
Test name
Test status
Simulation time 1830089794 ps
CPU time 13.99 seconds
Started Aug 23 10:33:12 PM UTC 24
Finished Aug 23 10:33:28 PM UTC 24
Peak memory 247624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051561991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.1051561991
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/26.spi_device_intercept.439685706
Short name T614
Test name
Test status
Simulation time 99973049 ps
CPU time 1.8 seconds
Started Aug 23 10:33:05 PM UTC 24
Finished Aug 23 10:33:08 PM UTC 24
Peak memory 239828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439685706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.439685706
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/26.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/26.spi_device_mailbox.3854718928
Short name T252
Test name
Test status
Simulation time 289777965 ps
CPU time 5.93 seconds
Started Aug 23 10:33:06 PM UTC 24
Finished Aug 23 10:33:13 PM UTC 24
Peak memory 235284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854718928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3854718928
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/26.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.2813619580
Short name T617
Test name
Test status
Simulation time 12956437361 ps
CPU time 16.88 seconds
Started Aug 23 10:33:05 PM UTC 24
Finished Aug 23 10:33:23 PM UTC 24
Peak memory 251916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813619580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.2813619580
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/26.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.3347992407
Short name T613
Test name
Test status
Simulation time 173657345 ps
CPU time 1.81 seconds
Started Aug 23 10:33:04 PM UTC 24
Finished Aug 23 10:33:07 PM UTC 24
Peak memory 234668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347992407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3347992407
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/26.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.2973084739
Short name T618
Test name
Test status
Simulation time 931273246 ps
CPU time 9.9 seconds
Started Aug 23 10:33:14 PM UTC 24
Finished Aug 23 10:33:25 PM UTC 24
Peak memory 231800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973084739 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.2973084739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/26.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.526662289
Short name T653
Test name
Test status
Simulation time 7888940773 ps
CPU time 71.5 seconds
Started Aug 23 10:33:35 PM UTC 24
Finished Aug 23 10:34:48 PM UTC 24
Peak memory 262400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526662289 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.526662289
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/26.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_all.716897160
Short name T609
Test name
Test status
Simulation time 57373819 ps
CPU time 0.6 seconds
Started Aug 23 10:33:00 PM UTC 24
Finished Aug 23 10:33:02 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716897160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.716897160
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/26.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.2174173835
Short name T612
Test name
Test status
Simulation time 1185415691 ps
CPU time 3.69 seconds
Started Aug 23 10:33:00 PM UTC 24
Finished Aug 23 10:33:05 PM UTC 24
Peak memory 227700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174173835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2174173835
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/26.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_rw.1172924008
Short name T611
Test name
Test status
Simulation time 110472501 ps
CPU time 1.43 seconds
Started Aug 23 10:33:02 PM UTC 24
Finished Aug 23 10:33:05 PM UTC 24
Peak memory 228104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172924008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1172924008
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/26.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.4028647627
Short name T610
Test name
Test status
Simulation time 180362132 ps
CPU time 0.84 seconds
Started Aug 23 10:33:01 PM UTC 24
Finished Aug 23 10:33:03 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028647627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.4028647627
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/26.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/26.spi_device_upload.2218756276
Short name T616
Test name
Test status
Simulation time 892455186 ps
CPU time 2.87 seconds
Started Aug 23 10:33:07 PM UTC 24
Finished Aug 23 10:33:11 PM UTC 24
Peak memory 235316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218756276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2218756276
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/26.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/27.spi_device_alert_test.2288087311
Short name T638
Test name
Test status
Simulation time 14112628 ps
CPU time 0.63 seconds
Started Aug 23 10:34:05 PM UTC 24
Finished Aug 23 10:34:06 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288087311 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.2288087311
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/27.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/27.spi_device_cfg_cmd.3135555112
Short name T642
Test name
Test status
Simulation time 4432834326 ps
CPU time 21.66 seconds
Started Aug 23 10:33:52 PM UTC 24
Finished Aug 23 10:34:15 PM UTC 24
Peak memory 234888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135555112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3135555112
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/27.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/27.spi_device_csb_read.2220606684
Short name T622
Test name
Test status
Simulation time 135465318 ps
CPU time 0.65 seconds
Started Aug 23 10:33:38 PM UTC 24
Finished Aug 23 10:33:40 PM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220606684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2220606684
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/27.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.219689602
Short name T323
Test name
Test status
Simulation time 168353672144 ps
CPU time 287.89 seconds
Started Aug 23 10:33:54 PM UTC 24
Finished Aug 23 10:38:46 PM UTC 24
Peak memory 264164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219689602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.219689602
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/27.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.1720780147
Short name T648
Test name
Test status
Simulation time 19824552854 ps
CPU time 38.31 seconds
Started Aug 23 10:33:56 PM UTC 24
Finished Aug 23 10:34:36 PM UTC 24
Peak memory 262156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720780147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1720780147
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.2360642328
Short name T206
Test name
Test status
Simulation time 3526325620 ps
CPU time 60.6 seconds
Started Aug 23 10:34:02 PM UTC 24
Finished Aug 23 10:35:04 PM UTC 24
Peak memory 266244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360642328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.2360642328
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode.3086522656
Short name T633
Test name
Test status
Simulation time 60292398 ps
CPU time 2.56 seconds
Started Aug 23 10:33:52 PM UTC 24
Finished Aug 23 10:33:56 PM UTC 24
Peak memory 234680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086522656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3086522656
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/27.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.3588398750
Short name T339
Test name
Test status
Simulation time 50286798768 ps
CPU time 334.01 seconds
Started Aug 23 10:33:52 PM UTC 24
Finished Aug 23 10:39:31 PM UTC 24
Peak memory 262248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588398750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.3588398750
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/27.spi_device_intercept.1906551531
Short name T628
Test name
Test status
Simulation time 121402018 ps
CPU time 1.86 seconds
Started Aug 23 10:33:47 PM UTC 24
Finished Aug 23 10:33:50 PM UTC 24
Peak memory 244676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906551531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1906551531
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/27.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/27.spi_device_mailbox.172992654
Short name T657
Test name
Test status
Simulation time 8865091606 ps
CPU time 65.8 seconds
Started Aug 23 10:33:48 PM UTC 24
Finished Aug 23 10:34:56 PM UTC 24
Peak memory 245712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172992654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.172992654
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/27.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.2112788151
Short name T630
Test name
Test status
Simulation time 2178347705 ps
CPU time 5.72 seconds
Started Aug 23 10:33:44 PM UTC 24
Finished Aug 23 10:33:51 PM UTC 24
Peak memory 245676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112788151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.2112788151
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/27.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.3786504129
Short name T632
Test name
Test status
Simulation time 2155949314 ps
CPU time 8.65 seconds
Started Aug 23 10:33:44 PM UTC 24
Finished Aug 23 10:33:54 PM UTC 24
Peak memory 245628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786504129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3786504129
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/27.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.3681483347
Short name T634
Test name
Test status
Simulation time 939481084 ps
CPU time 6.77 seconds
Started Aug 23 10:33:53 PM UTC 24
Finished Aug 23 10:34:01 PM UTC 24
Peak memory 231732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681483347 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.3681483347
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/27.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.1503708686
Short name T334
Test name
Test status
Simulation time 29884757381 ps
CPU time 94.55 seconds
Started Aug 23 10:34:05 PM UTC 24
Finished Aug 23 10:35:41 PM UTC 24
Peak memory 264200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503708686 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.1503708686
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/27.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_all.2926903901
Short name T623
Test name
Test status
Simulation time 48959463 ps
CPU time 0.61 seconds
Started Aug 23 10:33:41 PM UTC 24
Finished Aug 23 10:33:43 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926903901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2926903901
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/27.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.2327232236
Short name T631
Test name
Test status
Simulation time 10173385588 ps
CPU time 11.44 seconds
Started Aug 23 10:33:39 PM UTC 24
Finished Aug 23 10:33:52 PM UTC 24
Peak memory 228180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327232236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2327232236
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/27.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_rw.3078390863
Short name T626
Test name
Test status
Simulation time 385461000 ps
CPU time 1.46 seconds
Started Aug 23 10:33:44 PM UTC 24
Finished Aug 23 10:33:47 PM UTC 24
Peak memory 228024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078390863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3078390863
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/27.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.161139275
Short name T624
Test name
Test status
Simulation time 76092182 ps
CPU time 0.84 seconds
Started Aug 23 10:33:41 PM UTC 24
Finished Aug 23 10:33:43 PM UTC 24
Peak memory 215924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161139275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.161139275
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/27.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/27.spi_device_upload.1673844926
Short name T637
Test name
Test status
Simulation time 1848537611 ps
CPU time 13.57 seconds
Started Aug 23 10:33:51 PM UTC 24
Finished Aug 23 10:34:06 PM UTC 24
Peak memory 245804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673844926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1673844926
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/27.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/28.spi_device_alert_test.3016233633
Short name T654
Test name
Test status
Simulation time 77414892 ps
CPU time 0.63 seconds
Started Aug 23 10:34:48 PM UTC 24
Finished Aug 23 10:34:50 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016233633 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.3016233633
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/28.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/28.spi_device_cfg_cmd.1043279127
Short name T646
Test name
Test status
Simulation time 462859365 ps
CPU time 4.89 seconds
Started Aug 23 10:34:29 PM UTC 24
Finished Aug 23 10:34:35 PM UTC 24
Peak memory 235280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043279127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1043279127
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/28.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/28.spi_device_csb_read.1163785898
Short name T639
Test name
Test status
Simulation time 37504970 ps
CPU time 0.66 seconds
Started Aug 23 10:34:07 PM UTC 24
Finished Aug 23 10:34:08 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163785898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1163785898
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/28.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_all.3035189541
Short name T726
Test name
Test status
Simulation time 21592399119 ps
CPU time 144.31 seconds
Started Aug 23 10:34:37 PM UTC 24
Finished Aug 23 10:37:04 PM UTC 24
Peak memory 261664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035189541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3035189541
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/28.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.2908168702
Short name T73
Test name
Test status
Simulation time 84990452692 ps
CPU time 280 seconds
Started Aug 23 10:34:43 PM UTC 24
Finished Aug 23 10:39:27 PM UTC 24
Peak memory 268288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908168702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.2908168702
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode.1059882204
Short name T651
Test name
Test status
Simulation time 894319220 ps
CPU time 5.48 seconds
Started Aug 23 10:34:36 PM UTC 24
Finished Aug 23 10:34:43 PM UTC 24
Peak memory 245584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059882204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1059882204
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/28.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.1980672989
Short name T674
Test name
Test status
Simulation time 8176075459 ps
CPU time 50.86 seconds
Started Aug 23 10:34:36 PM UTC 24
Finished Aug 23 10:35:29 PM UTC 24
Peak memory 276680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980672989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.1980672989
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/28.spi_device_intercept.2450629992
Short name T643
Test name
Test status
Simulation time 99263033 ps
CPU time 2.45 seconds
Started Aug 23 10:34:22 PM UTC 24
Finished Aug 23 10:34:26 PM UTC 24
Peak memory 229884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450629992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2450629992
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/28.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/28.spi_device_mailbox.769739568
Short name T650
Test name
Test status
Simulation time 4671270243 ps
CPU time 9.61 seconds
Started Aug 23 10:34:26 PM UTC 24
Finished Aug 23 10:34:37 PM UTC 24
Peak memory 235532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769739568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.769739568
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/28.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.220297107
Short name T336
Test name
Test status
Simulation time 583666498 ps
CPU time 4.69 seconds
Started Aug 23 10:34:16 PM UTC 24
Finished Aug 23 10:34:22 PM UTC 24
Peak memory 245584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220297107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.220297107
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/28.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.3255157732
Short name T644
Test name
Test status
Simulation time 7312496803 ps
CPU time 11.59 seconds
Started Aug 23 10:34:14 PM UTC 24
Finished Aug 23 10:34:27 PM UTC 24
Peak memory 251844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255157732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3255157732
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/28.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.702220231
Short name T652
Test name
Test status
Simulation time 3373095619 ps
CPU time 6.91 seconds
Started Aug 23 10:34:37 PM UTC 24
Finished Aug 23 10:34:45 PM UTC 24
Peak memory 231612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702220231 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.702220231
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/28.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.60061794
Short name T784
Test name
Test status
Simulation time 60658761818 ps
CPU time 245.28 seconds
Started Aug 23 10:34:46 PM UTC 24
Finished Aug 23 10:38:55 PM UTC 24
Peak memory 264200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60061794 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.60061794
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/28.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_all.547310525
Short name T647
Test name
Test status
Simulation time 19701219724 ps
CPU time 26.8 seconds
Started Aug 23 10:34:08 PM UTC 24
Finished Aug 23 10:34:36 PM UTC 24
Peak memory 227932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547310525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.547310525
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/28.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.2616646744
Short name T645
Test name
Test status
Simulation time 31943212125 ps
CPU time 20.2 seconds
Started Aug 23 10:34:07 PM UTC 24
Finished Aug 23 10:34:28 PM UTC 24
Peak memory 227836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616646744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2616646744
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/28.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_rw.2900308142
Short name T641
Test name
Test status
Simulation time 89416654 ps
CPU time 0.74 seconds
Started Aug 23 10:34:12 PM UTC 24
Finished Aug 23 10:34:14 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900308142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2900308142
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/28.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.4189608796
Short name T640
Test name
Test status
Simulation time 223922540 ps
CPU time 0.76 seconds
Started Aug 23 10:34:09 PM UTC 24
Finished Aug 23 10:34:11 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189608796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.4189608796
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/28.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/28.spi_device_upload.2550379236
Short name T649
Test name
Test status
Simulation time 14152659108 ps
CPU time 8.27 seconds
Started Aug 23 10:34:27 PM UTC 24
Finished Aug 23 10:34:37 PM UTC 24
Peak memory 245648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550379236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2550379236
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/28.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/29.spi_device_alert_test.4105935219
Short name T672
Test name
Test status
Simulation time 37614350 ps
CPU time 0.6 seconds
Started Aug 23 10:35:22 PM UTC 24
Finished Aug 23 10:35:24 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105935219 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.4105935219
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/29.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/29.spi_device_cfg_cmd.971818054
Short name T666
Test name
Test status
Simulation time 600783505 ps
CPU time 3.28 seconds
Started Aug 23 10:35:07 PM UTC 24
Finished Aug 23 10:35:12 PM UTC 24
Peak memory 235344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971818054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.971818054
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/29.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/29.spi_device_csb_read.1883005056
Short name T656
Test name
Test status
Simulation time 21922593 ps
CPU time 0.66 seconds
Started Aug 23 10:34:50 PM UTC 24
Finished Aug 23 10:34:52 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883005056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1883005056
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/29.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.860649296
Short name T724
Test name
Test status
Simulation time 42631348706 ps
CPU time 99.27 seconds
Started Aug 23 10:35:17 PM UTC 24
Finished Aug 23 10:36:58 PM UTC 24
Peak memory 261932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860649296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.860649296
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/29.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.1576609283
Short name T273
Test name
Test status
Simulation time 11443199878 ps
CPU time 79.68 seconds
Started Aug 23 10:35:17 PM UTC 24
Finished Aug 23 10:36:39 PM UTC 24
Peak memory 262128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576609283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1576609283
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.1544282531
Short name T680
Test name
Test status
Simulation time 23543320403 ps
CPU time 25.35 seconds
Started Aug 23 10:35:17 PM UTC 24
Finished Aug 23 10:35:44 PM UTC 24
Peak memory 245796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544282531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.1544282531
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode.3458284604
Short name T670
Test name
Test status
Simulation time 1000710879 ps
CPU time 8.99 seconds
Started Aug 23 10:35:08 PM UTC 24
Finished Aug 23 10:35:18 PM UTC 24
Peak memory 235532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458284604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3458284604
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/29.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.2414167848
Short name T701
Test name
Test status
Simulation time 106175928099 ps
CPU time 69.37 seconds
Started Aug 23 10:35:12 PM UTC 24
Finished Aug 23 10:36:23 PM UTC 24
Peak memory 262180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414167848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.2414167848
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/29.spi_device_intercept.106368940
Short name T665
Test name
Test status
Simulation time 659384958 ps
CPU time 5.08 seconds
Started Aug 23 10:35:05 PM UTC 24
Finished Aug 23 10:35:11 PM UTC 24
Peak memory 235372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106368940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.106368940
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/29.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/29.spi_device_mailbox.3371114136
Short name T685
Test name
Test status
Simulation time 4358841112 ps
CPU time 42.88 seconds
Started Aug 23 10:35:07 PM UTC 24
Finished Aug 23 10:35:52 PM UTC 24
Peak memory 235600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371114136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3371114136
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/29.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.4043476061
Short name T663
Test name
Test status
Simulation time 98793300 ps
CPU time 1.73 seconds
Started Aug 23 10:35:03 PM UTC 24
Finished Aug 23 10:35:06 PM UTC 24
Peak memory 235052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043476061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.4043476061
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/29.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.2007789413
Short name T662
Test name
Test status
Simulation time 97075206 ps
CPU time 1.75 seconds
Started Aug 23 10:35:03 PM UTC 24
Finished Aug 23 10:35:06 PM UTC 24
Peak memory 234168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007789413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2007789413
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/29.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.2830457090
Short name T667
Test name
Test status
Simulation time 153310829 ps
CPU time 3.06 seconds
Started Aug 23 10:35:12 PM UTC 24
Finished Aug 23 10:35:16 PM UTC 24
Peak memory 231800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830457090 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.2830457090
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/29.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/29.spi_device_stress_all.3938484567
Short name T671
Test name
Test status
Simulation time 159692922 ps
CPU time 0.88 seconds
Started Aug 23 10:35:19 PM UTC 24
Finished Aug 23 10:35:21 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938484567 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.3938484567
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/29.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_all.374404971
Short name T661
Test name
Test status
Simulation time 3106522919 ps
CPU time 12.22 seconds
Started Aug 23 10:34:53 PM UTC 24
Finished Aug 23 10:35:06 PM UTC 24
Peak memory 227900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374404971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.374404971
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/29.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.1828788449
Short name T660
Test name
Test status
Simulation time 6099441399 ps
CPU time 10.76 seconds
Started Aug 23 10:34:51 PM UTC 24
Finished Aug 23 10:35:02 PM UTC 24
Peak memory 227828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828788449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1828788449
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/29.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_rw.635679809
Short name T659
Test name
Test status
Simulation time 519999621 ps
CPU time 0.81 seconds
Started Aug 23 10:35:00 PM UTC 24
Finished Aug 23 10:35:02 PM UTC 24
Peak memory 215992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635679809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.635679809
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/29.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.1575170647
Short name T658
Test name
Test status
Simulation time 319899912 ps
CPU time 0.83 seconds
Started Aug 23 10:34:57 PM UTC 24
Finished Aug 23 10:34:59 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575170647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1575170647
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/29.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/29.spi_device_upload.2086281259
Short name T668
Test name
Test status
Simulation time 5869319441 ps
CPU time 8.22 seconds
Started Aug 23 10:35:07 PM UTC 24
Finished Aug 23 10:35:17 PM UTC 24
Peak memory 235404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086281259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2086281259
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/29.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.2728430845
Short name T95
Test name
Test status
Simulation time 21277142 ps
CPU time 0.61 seconds
Started Aug 23 10:22:44 PM UTC 24
Finished Aug 23 10:22:45 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728430845 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2728430845
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.2450837141
Short name T91
Test name
Test status
Simulation time 399567401 ps
CPU time 3.29 seconds
Started Aug 23 10:22:34 PM UTC 24
Finished Aug 23 10:22:39 PM UTC 24
Peak memory 245516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450837141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2450837141
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.3310560679
Short name T180
Test name
Test status
Simulation time 18735556 ps
CPU time 0.71 seconds
Started Aug 23 10:22:26 PM UTC 24
Finished Aug 23 10:22:28 PM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310560679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3310560679
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.3288285493
Short name T188
Test name
Test status
Simulation time 71411517741 ps
CPU time 149.93 seconds
Started Aug 23 10:22:36 PM UTC 24
Finished Aug 23 10:25:09 PM UTC 24
Peak memory 278476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288285493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3288285493
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.392932751
Short name T64
Test name
Test status
Simulation time 87912137839 ps
CPU time 50.89 seconds
Started Aug 23 10:22:39 PM UTC 24
Finished Aug 23 10:23:32 PM UTC 24
Peak memory 251940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392932751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.392932751
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.1877851047
Short name T52
Test name
Test status
Simulation time 99524903 ps
CPU time 3.9 seconds
Started Aug 23 10:22:34 PM UTC 24
Finished Aug 23 10:22:39 PM UTC 24
Peak memory 245596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877851047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1877851047
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.1704222536
Short name T47
Test name
Test status
Simulation time 16050273598 ps
CPU time 101.28 seconds
Started Aug 23 10:22:34 PM UTC 24
Finished Aug 23 10:24:18 PM UTC 24
Peak memory 247948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704222536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.1704222536
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.383014087
Short name T115
Test name
Test status
Simulation time 343936982 ps
CPU time 2.18 seconds
Started Aug 23 10:22:30 PM UTC 24
Finished Aug 23 10:22:33 PM UTC 24
Peak memory 235276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383014087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.383014087
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.2767532634
Short name T109
Test name
Test status
Simulation time 23753559020 ps
CPU time 18.26 seconds
Started Aug 23 10:22:30 PM UTC 24
Finished Aug 23 10:22:50 PM UTC 24
Peak memory 245644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767532634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2767532634
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.1669853592
Short name T45
Test name
Test status
Simulation time 15842936 ps
CPU time 0.86 seconds
Started Aug 23 10:22:27 PM UTC 24
Finished Aug 23 10:22:29 PM UTC 24
Peak memory 229208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669853592 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_parity.1669853592
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.4106635122
Short name T139
Test name
Test status
Simulation time 1128373091 ps
CPU time 2.27 seconds
Started Aug 23 10:22:30 PM UTC 24
Finished Aug 23 10:22:33 PM UTC 24
Peak memory 245772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106635122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.4106635122
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.57609488
Short name T61
Test name
Test status
Simulation time 268411573 ps
CPU time 5.1 seconds
Started Aug 23 10:22:29 PM UTC 24
Finished Aug 23 10:22:35 PM UTC 24
Peak memory 235312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57609488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.57609488
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.321476221
Short name T107
Test name
Test status
Simulation time 2708329843 ps
CPU time 7.11 seconds
Started Aug 23 10:22:35 PM UTC 24
Finished Aug 23 10:22:44 PM UTC 24
Peak memory 234104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321476221 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.321476221
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.2811687828
Short name T26
Test name
Test status
Simulation time 128866169 ps
CPU time 0.85 seconds
Started Aug 23 10:22:41 PM UTC 24
Finished Aug 23 10:22:42 PM UTC 24
Peak memory 257680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811687828 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2811687828
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.1429744313
Short name T96
Test name
Test status
Simulation time 94093565052 ps
CPU time 149.6 seconds
Started Aug 23 10:22:39 PM UTC 24
Finished Aug 23 10:25:12 PM UTC 24
Peak memory 268292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429744313 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.1429744313
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.3346518378
Short name T69
Test name
Test status
Simulation time 6631580390 ps
CPU time 33.92 seconds
Started Aug 23 10:22:29 PM UTC 24
Finished Aug 23 10:23:04 PM UTC 24
Peak memory 231860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346518378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3346518378
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.2479161134
Short name T104
Test name
Test status
Simulation time 2907600522 ps
CPU time 4.9 seconds
Started Aug 23 10:22:27 PM UTC 24
Finished Aug 23 10:22:33 PM UTC 24
Peak memory 228040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479161134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2479161134
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.1706448595
Short name T68
Test name
Test status
Simulation time 198515607 ps
CPU time 8.28 seconds
Started Aug 23 10:22:29 PM UTC 24
Finished Aug 23 10:22:38 PM UTC 24
Peak memory 227624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706448595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1706448595
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.1870609211
Short name T181
Test name
Test status
Simulation time 33019820 ps
CPU time 0.6 seconds
Started Aug 23 10:22:29 PM UTC 24
Finished Aug 23 10:22:31 PM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870609211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1870609211
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.2597520838
Short name T62
Test name
Test status
Simulation time 236553177 ps
CPU time 2.76 seconds
Started Aug 23 10:22:31 PM UTC 24
Finished Aug 23 10:22:35 PM UTC 24
Peak memory 245536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597520838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2597520838
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/3.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/30.spi_device_alert_test.3298963731
Short name T688
Test name
Test status
Simulation time 187281869 ps
CPU time 0.65 seconds
Started Aug 23 10:35:56 PM UTC 24
Finished Aug 23 10:35:58 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298963731 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.3298963731
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/30.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/30.spi_device_cfg_cmd.2822628125
Short name T682
Test name
Test status
Simulation time 506683007 ps
CPU time 5.16 seconds
Started Aug 23 10:35:42 PM UTC 24
Finished Aug 23 10:35:48 PM UTC 24
Peak memory 235280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822628125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2822628125
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/30.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/30.spi_device_csb_read.3970683677
Short name T673
Test name
Test status
Simulation time 24008298 ps
CPU time 0.67 seconds
Started Aug 23 10:35:25 PM UTC 24
Finished Aug 23 10:35:27 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970683677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3970683677
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/30.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_all.2962457016
Short name T326
Test name
Test status
Simulation time 5301750144 ps
CPU time 58.42 seconds
Started Aug 23 10:35:49 PM UTC 24
Finished Aug 23 10:36:49 PM UTC 24
Peak memory 268364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962457016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2962457016
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/30.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.3291600667
Short name T711
Test name
Test status
Simulation time 3545400955 ps
CPU time 55.65 seconds
Started Aug 23 10:35:50 PM UTC 24
Finished Aug 23 10:36:47 PM UTC 24
Peak memory 262180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291600667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3291600667
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/30.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.3617496055
Short name T338
Test name
Test status
Simulation time 879002963715 ps
CPU time 439.5 seconds
Started Aug 23 10:35:50 PM UTC 24
Finished Aug 23 10:43:15 PM UTC 24
Peak memory 268288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617496055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.3617496055
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode.638012302
Short name T689
Test name
Test status
Simulation time 5062604288 ps
CPU time 11.86 seconds
Started Aug 23 10:35:45 PM UTC 24
Finished Aug 23 10:35:58 PM UTC 24
Peak memory 235464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638012302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.638012302
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/30.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.1364948814
Short name T684
Test name
Test status
Simulation time 398585191 ps
CPU time 3.12 seconds
Started Aug 23 10:35:45 PM UTC 24
Finished Aug 23 10:35:49 PM UTC 24
Peak memory 235336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364948814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.1364948814
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/30.spi_device_intercept.3042066514
Short name T679
Test name
Test status
Simulation time 94913003 ps
CPU time 1.84 seconds
Started Aug 23 10:35:37 PM UTC 24
Finished Aug 23 10:35:40 PM UTC 24
Peak memory 233960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042066514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3042066514
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/30.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/30.spi_device_mailbox.2586820587
Short name T214
Test name
Test status
Simulation time 3194065832 ps
CPU time 6.38 seconds
Started Aug 23 10:35:39 PM UTC 24
Finished Aug 23 10:35:46 PM UTC 24
Peak memory 235596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586820587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2586820587
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/30.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.509910099
Short name T678
Test name
Test status
Simulation time 624720503 ps
CPU time 3.77 seconds
Started Aug 23 10:35:33 PM UTC 24
Finished Aug 23 10:35:37 PM UTC 24
Peak memory 245768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509910099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.509910099
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/30.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.2825205168
Short name T677
Test name
Test status
Simulation time 1048858859 ps
CPU time 3.8 seconds
Started Aug 23 10:35:32 PM UTC 24
Finished Aug 23 10:35:36 PM UTC 24
Peak memory 245580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825205168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2825205168
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/30.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.4070779508
Short name T687
Test name
Test status
Simulation time 3935502343 ps
CPU time 9.41 seconds
Started Aug 23 10:35:47 PM UTC 24
Finished Aug 23 10:35:57 PM UTC 24
Peak memory 231728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070779508 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.4070779508
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/30.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.2800546156
Short name T733
Test name
Test status
Simulation time 44960848082 ps
CPU time 80 seconds
Started Aug 23 10:35:52 PM UTC 24
Finished Aug 23 10:37:14 PM UTC 24
Peak memory 245704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800546156 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.2800546156
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/30.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_all.2394022695
Short name T683
Test name
Test status
Simulation time 3806370455 ps
CPU time 19.35 seconds
Started Aug 23 10:35:28 PM UTC 24
Finished Aug 23 10:35:49 PM UTC 24
Peak memory 228024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394022695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2394022695
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/30.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.2493896213
Short name T681
Test name
Test status
Simulation time 15627271055 ps
CPU time 16.15 seconds
Started Aug 23 10:35:26 PM UTC 24
Finished Aug 23 10:35:44 PM UTC 24
Peak memory 228028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493896213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2493896213
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/30.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_rw.3039552835
Short name T676
Test name
Test status
Simulation time 133982769 ps
CPU time 0.97 seconds
Started Aug 23 10:35:29 PM UTC 24
Finished Aug 23 10:35:31 PM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039552835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3039552835
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/30.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.583984655
Short name T675
Test name
Test status
Simulation time 106481926 ps
CPU time 0.73 seconds
Started Aug 23 10:35:29 PM UTC 24
Finished Aug 23 10:35:31 PM UTC 24
Peak memory 215924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583984655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.583984655
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/30.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/30.spi_device_upload.1606493776
Short name T686
Test name
Test status
Simulation time 4737940677 ps
CPU time 13.36 seconds
Started Aug 23 10:35:41 PM UTC 24
Finished Aug 23 10:35:55 PM UTC 24
Peak memory 235408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606493776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1606493776
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/30.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/31.spi_device_alert_test.865125136
Short name T706
Test name
Test status
Simulation time 36081313 ps
CPU time 0.61 seconds
Started Aug 23 10:36:30 PM UTC 24
Finished Aug 23 10:36:32 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865125136 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.865125136
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/31.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/31.spi_device_cfg_cmd.3563246240
Short name T698
Test name
Test status
Simulation time 37072316 ps
CPU time 1.85 seconds
Started Aug 23 10:36:09 PM UTC 24
Finished Aug 23 10:36:12 PM UTC 24
Peak memory 244920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563246240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3563246240
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/31.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/31.spi_device_csb_read.379669513
Short name T691
Test name
Test status
Simulation time 30003723 ps
CPU time 0.66 seconds
Started Aug 23 10:35:58 PM UTC 24
Finished Aug 23 10:36:00 PM UTC 24
Peak memory 215704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379669513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.379669513
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/31.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_all.1762860245
Short name T702
Test name
Test status
Simulation time 438557491 ps
CPU time 8.26 seconds
Started Aug 23 10:36:19 PM UTC 24
Finished Aug 23 10:36:28 PM UTC 24
Peak memory 251724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762860245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1762860245
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/31.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.3195841556
Short name T203
Test name
Test status
Simulation time 4574180252 ps
CPU time 15.06 seconds
Started Aug 23 10:36:24 PM UTC 24
Finished Aug 23 10:36:40 PM UTC 24
Peak memory 235532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195841556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3195841556
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.402111360
Short name T950
Test name
Test status
Simulation time 50552556591 ps
CPU time 408.54 seconds
Started Aug 23 10:36:27 PM UTC 24
Finished Aug 23 10:43:20 PM UTC 24
Peak memory 280616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402111360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.402111360
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode.4227337261
Short name T700
Test name
Test status
Simulation time 1687781467 ps
CPU time 6.97 seconds
Started Aug 23 10:36:10 PM UTC 24
Finished Aug 23 10:36:18 PM UTC 24
Peak memory 235536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227337261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.4227337261
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/31.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.2242543249
Short name T327
Test name
Test status
Simulation time 14916688489 ps
CPU time 132.73 seconds
Started Aug 23 10:36:13 PM UTC 24
Finished Aug 23 10:38:28 PM UTC 24
Peak memory 278500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242543249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.2242543249
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/31.spi_device_intercept.270360115
Short name T705
Test name
Test status
Simulation time 15902742069 ps
CPU time 27.78 seconds
Started Aug 23 10:36:02 PM UTC 24
Finished Aug 23 10:36:31 PM UTC 24
Peak memory 235404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270360115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.270360115
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/31.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/31.spi_device_mailbox.1985140849
Short name T708
Test name
Test status
Simulation time 97027664430 ps
CPU time 29.68 seconds
Started Aug 23 10:36:05 PM UTC 24
Finished Aug 23 10:36:36 PM UTC 24
Peak memory 235464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985140849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1985140849
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/31.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.1396171652
Short name T695
Test name
Test status
Simulation time 499925812 ps
CPU time 3.07 seconds
Started Aug 23 10:36:01 PM UTC 24
Finished Aug 23 10:36:06 PM UTC 24
Peak memory 245576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396171652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.1396171652
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/31.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.16952966
Short name T694
Test name
Test status
Simulation time 210000866 ps
CPU time 3.5 seconds
Started Aug 23 10:36:00 PM UTC 24
Finished Aug 23 10:36:05 PM UTC 24
Peak memory 235272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16952966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.16952966
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/31.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.1563418768
Short name T703
Test name
Test status
Simulation time 2874675363 ps
CPU time 9.99 seconds
Started Aug 23 10:36:18 PM UTC 24
Finished Aug 23 10:36:29 PM UTC 24
Peak memory 233864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563418768 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.1563418768
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/31.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.2157214245
Short name T704
Test name
Test status
Simulation time 268832635 ps
CPU time 0.95 seconds
Started Aug 23 10:36:29 PM UTC 24
Finished Aug 23 10:36:31 PM UTC 24
Peak memory 216440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157214245 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.2157214245
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/31.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_all.2902523839
Short name T699
Test name
Test status
Simulation time 7592491149 ps
CPU time 17.96 seconds
Started Aug 23 10:35:58 PM UTC 24
Finished Aug 23 10:36:17 PM UTC 24
Peak memory 227900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902523839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2902523839
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/31.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.853886432
Short name T690
Test name
Test status
Simulation time 39579751 ps
CPU time 0.64 seconds
Started Aug 23 10:35:58 PM UTC 24
Finished Aug 23 10:36:00 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853886432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.853886432
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/31.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_rw.98139415
Short name T693
Test name
Test status
Simulation time 12618292 ps
CPU time 0.61 seconds
Started Aug 23 10:36:00 PM UTC 24
Finished Aug 23 10:36:02 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98139415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_devi
ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.98139415
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/31.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.2545765637
Short name T692
Test name
Test status
Simulation time 322784916 ps
CPU time 0.76 seconds
Started Aug 23 10:35:59 PM UTC 24
Finished Aug 23 10:36:01 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545765637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2545765637
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/31.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/31.spi_device_upload.3119493221
Short name T697
Test name
Test status
Simulation time 518459869 ps
CPU time 1.82 seconds
Started Aug 23 10:36:07 PM UTC 24
Finished Aug 23 10:36:09 PM UTC 24
Peak memory 234128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119493221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3119493221
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/31.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/32.spi_device_alert_test.503865206
Short name T720
Test name
Test status
Simulation time 16555690 ps
CPU time 0.61 seconds
Started Aug 23 10:36:53 PM UTC 24
Finished Aug 23 10:36:55 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503865206 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.503865206
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/32.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/32.spi_device_cfg_cmd.3091439561
Short name T718
Test name
Test status
Simulation time 392504377 ps
CPU time 4.48 seconds
Started Aug 23 10:36:48 PM UTC 24
Finished Aug 23 10:36:53 PM UTC 24
Peak memory 245676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091439561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3091439561
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/32.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/32.spi_device_csb_read.1741363252
Short name T707
Test name
Test status
Simulation time 16695348 ps
CPU time 0.69 seconds
Started Aug 23 10:36:32 PM UTC 24
Finished Aug 23 10:36:34 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741363252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1741363252
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/32.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_all.1778432294
Short name T749
Test name
Test status
Simulation time 11222068877 ps
CPU time 58.82 seconds
Started Aug 23 10:36:49 PM UTC 24
Finished Aug 23 10:37:49 PM UTC 24
Peak memory 274664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778432294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1778432294
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/32.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.3475108818
Short name T921
Test name
Test status
Simulation time 76893306298 ps
CPU time 342.59 seconds
Started Aug 23 10:36:49 PM UTC 24
Finished Aug 23 10:42:36 PM UTC 24
Peak memory 284712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475108818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3475108818
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.2156641559
Short name T747
Test name
Test status
Simulation time 30299111313 ps
CPU time 52.48 seconds
Started Aug 23 10:36:50 PM UTC 24
Finished Aug 23 10:37:44 PM UTC 24
Peak memory 262432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156641559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.2156641559
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode.315825086
Short name T717
Test name
Test status
Simulation time 142556085 ps
CPU time 2.12 seconds
Started Aug 23 10:36:49 PM UTC 24
Finished Aug 23 10:36:52 PM UTC 24
Peak memory 245604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315825086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.315825086
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/32.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.3892959322
Short name T943
Test name
Test status
Simulation time 60767409605 ps
CPU time 378.09 seconds
Started Aug 23 10:36:49 PM UTC 24
Finished Aug 23 10:43:11 PM UTC 24
Peak memory 268232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892959322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.3892959322
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/32.spi_device_intercept.3636300447
Short name T727
Test name
Test status
Simulation time 18382494082 ps
CPU time 23.49 seconds
Started Aug 23 10:36:40 PM UTC 24
Finished Aug 23 10:37:05 PM UTC 24
Peak memory 245736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636300447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3636300447
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/32.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/32.spi_device_mailbox.1780793539
Short name T716
Test name
Test status
Simulation time 4733673211 ps
CPU time 6.2 seconds
Started Aug 23 10:36:41 PM UTC 24
Finished Aug 23 10:36:49 PM UTC 24
Peak memory 235496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780793539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1780793539
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/32.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.4066339414
Short name T715
Test name
Test status
Simulation time 4834523294 ps
CPU time 7.66 seconds
Started Aug 23 10:36:39 PM UTC 24
Finished Aug 23 10:36:48 PM UTC 24
Peak memory 235460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066339414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.4066339414
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/32.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.3792955451
Short name T712
Test name
Test status
Simulation time 6677863884 ps
CPU time 8.23 seconds
Started Aug 23 10:36:38 PM UTC 24
Finished Aug 23 10:36:48 PM UTC 24
Peak memory 235408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792955451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3792955451
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/32.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.386394772
Short name T719
Test name
Test status
Simulation time 267676687 ps
CPU time 3.72 seconds
Started Aug 23 10:36:49 PM UTC 24
Finished Aug 23 10:36:54 PM UTC 24
Peak memory 234024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386394772 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.386394772
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/32.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.233285095
Short name T315
Test name
Test status
Simulation time 45178684445 ps
CPU time 142.35 seconds
Started Aug 23 10:36:50 PM UTC 24
Finished Aug 23 10:39:15 PM UTC 24
Peak memory 278528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233285095 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.233285095
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/32.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.509601350
Short name T714
Test name
Test status
Simulation time 7045528697 ps
CPU time 14.48 seconds
Started Aug 23 10:36:32 PM UTC 24
Finished Aug 23 10:36:48 PM UTC 24
Peak memory 227916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509601350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.509601350
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/32.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_rw.731167742
Short name T710
Test name
Test status
Simulation time 25210194 ps
CPU time 0.93 seconds
Started Aug 23 10:36:37 PM UTC 24
Finished Aug 23 10:36:39 PM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731167742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.731167742
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/32.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.633816704
Short name T709
Test name
Test status
Simulation time 429183401 ps
CPU time 0.78 seconds
Started Aug 23 10:36:35 PM UTC 24
Finished Aug 23 10:36:37 PM UTC 24
Peak memory 215924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633816704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.633816704
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/32.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/32.spi_device_upload.2002344825
Short name T713
Test name
Test status
Simulation time 357290620 ps
CPU time 2.05 seconds
Started Aug 23 10:36:44 PM UTC 24
Finished Aug 23 10:36:48 PM UTC 24
Peak memory 235212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002344825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2002344825
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/32.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_alert_test.2039366726
Short name T736
Test name
Test status
Simulation time 13047531 ps
CPU time 0.62 seconds
Started Aug 23 10:37:19 PM UTC 24
Finished Aug 23 10:37:20 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039366726 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.2039366726
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/33.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_cfg_cmd.1708972976
Short name T731
Test name
Test status
Simulation time 299078952 ps
CPU time 2.87 seconds
Started Aug 23 10:37:06 PM UTC 24
Finished Aug 23 10:37:10 PM UTC 24
Peak memory 235280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708972976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1708972976
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/33.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_csb_read.2905672404
Short name T722
Test name
Test status
Simulation time 48779149 ps
CPU time 0.69 seconds
Started Aug 23 10:36:54 PM UTC 24
Finished Aug 23 10:36:56 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905672404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2905672404
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/33.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_all.1074494239
Short name T734
Test name
Test status
Simulation time 1047800245 ps
CPU time 4.99 seconds
Started Aug 23 10:37:12 PM UTC 24
Finished Aug 23 10:37:18 PM UTC 24
Peak memory 235368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074494239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1074494239
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/33.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.551457994
Short name T760
Test name
Test status
Simulation time 12759131476 ps
CPU time 59.93 seconds
Started Aug 23 10:37:12 PM UTC 24
Finished Aug 23 10:38:13 PM UTC 24
Peak memory 262284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551457994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.551457994
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode.486646218
Short name T344
Test name
Test status
Simulation time 666314411 ps
CPU time 13.9 seconds
Started Aug 23 10:37:06 PM UTC 24
Finished Aug 23 10:37:21 PM UTC 24
Peak memory 261984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486646218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.486646218
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/33.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.3670592942
Short name T781
Test name
Test status
Simulation time 28978592195 ps
CPU time 100.01 seconds
Started Aug 23 10:37:07 PM UTC 24
Finished Aug 23 10:38:49 PM UTC 24
Peak memory 264136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670592942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.3670592942
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_intercept.111160130
Short name T732
Test name
Test status
Simulation time 1208825691 ps
CPU time 9.83 seconds
Started Aug 23 10:37:00 PM UTC 24
Finished Aug 23 10:37:11 PM UTC 24
Peak memory 235280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111160130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.111160130
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/33.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_mailbox.1041505572
Short name T729
Test name
Test status
Simulation time 216325148 ps
CPU time 2.2 seconds
Started Aug 23 10:37:03 PM UTC 24
Finished Aug 23 10:37:07 PM UTC 24
Peak memory 235472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041505572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1041505572
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/33.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.35174537
Short name T292
Test name
Test status
Simulation time 290770099 ps
CPU time 2.72 seconds
Started Aug 23 10:36:59 PM UTC 24
Finished Aug 23 10:37:03 PM UTC 24
Peak memory 245588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35174537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.35174537
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/33.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.737456170
Short name T728
Test name
Test status
Simulation time 2814001450 ps
CPU time 6.44 seconds
Started Aug 23 10:36:58 PM UTC 24
Finished Aug 23 10:37:06 PM UTC 24
Peak memory 245716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737456170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.737456170
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/33.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.2025527203
Short name T735
Test name
Test status
Simulation time 4657535914 ps
CPU time 7.18 seconds
Started Aug 23 10:37:09 PM UTC 24
Finished Aug 23 10:37:18 PM UTC 24
Peak memory 231864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025527203 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.2025527203
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/33.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_all.2241073084
Short name T730
Test name
Test status
Simulation time 1355741777 ps
CPU time 11.59 seconds
Started Aug 23 10:36:56 PM UTC 24
Finished Aug 23 10:37:09 PM UTC 24
Peak memory 227800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241073084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2241073084
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/33.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.1608373101
Short name T721
Test name
Test status
Simulation time 12724867 ps
CPU time 0.6 seconds
Started Aug 23 10:36:54 PM UTC 24
Finished Aug 23 10:36:56 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608373101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1608373101
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/33.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_rw.481914006
Short name T725
Test name
Test status
Simulation time 32585382 ps
CPU time 0.99 seconds
Started Aug 23 10:36:57 PM UTC 24
Finished Aug 23 10:36:59 PM UTC 24
Peak memory 216712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481914006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.481914006
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/33.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.1088660548
Short name T723
Test name
Test status
Simulation time 70811020 ps
CPU time 0.67 seconds
Started Aug 23 10:36:56 PM UTC 24
Finished Aug 23 10:36:58 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088660548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1088660548
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/33.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/33.spi_device_upload.1567982151
Short name T744
Test name
Test status
Simulation time 124816588950 ps
CPU time 32.75 seconds
Started Aug 23 10:37:04 PM UTC 24
Finished Aug 23 10:37:39 PM UTC 24
Peak memory 245676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567982151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1567982151
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/33.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/34.spi_device_alert_test.1407041306
Short name T751
Test name
Test status
Simulation time 14394317 ps
CPU time 0.61 seconds
Started Aug 23 10:37:50 PM UTC 24
Finished Aug 23 10:37:51 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407041306 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.1407041306
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/34.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/34.spi_device_cfg_cmd.1188384658
Short name T750
Test name
Test status
Simulation time 5123989546 ps
CPU time 10.78 seconds
Started Aug 23 10:37:37 PM UTC 24
Finished Aug 23 10:37:49 PM UTC 24
Peak memory 234896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188384658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1188384658
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/34.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/34.spi_device_csb_read.4282487345
Short name T737
Test name
Test status
Simulation time 22204924 ps
CPU time 0.67 seconds
Started Aug 23 10:37:21 PM UTC 24
Finished Aug 23 10:37:22 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282487345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.4282487345
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/34.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_all.3322409214
Short name T756
Test name
Test status
Simulation time 13869472543 ps
CPU time 22.55 seconds
Started Aug 23 10:37:43 PM UTC 24
Finished Aug 23 10:38:06 PM UTC 24
Peak memory 252072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322409214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3322409214
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/34.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.1166019422
Short name T74
Test name
Test status
Simulation time 35653232884 ps
CPU time 105.57 seconds
Started Aug 23 10:37:45 PM UTC 24
Finished Aug 23 10:39:32 PM UTC 24
Peak memory 278732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166019422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1166019422
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/34.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.1813225900
Short name T946
Test name
Test status
Simulation time 48559454860 ps
CPU time 325.43 seconds
Started Aug 23 10:37:47 PM UTC 24
Finished Aug 23 10:43:16 PM UTC 24
Peak memory 266240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813225900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.1813225900
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode.3577357820
Short name T347
Test name
Test status
Simulation time 11665403469 ps
CPU time 33.53 seconds
Started Aug 23 10:37:38 PM UTC 24
Finished Aug 23 10:38:13 PM UTC 24
Peak memory 245900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577357820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3577357820
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/34.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.699009777
Short name T753
Test name
Test status
Simulation time 15329325451 ps
CPU time 16.67 seconds
Started Aug 23 10:37:39 PM UTC 24
Finished Aug 23 10:37:57 PM UTC 24
Peak memory 262284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699009777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.699009777
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/34.spi_device_intercept.186620700
Short name T743
Test name
Test status
Simulation time 406772293 ps
CPU time 4.78 seconds
Started Aug 23 10:37:30 PM UTC 24
Finished Aug 23 10:37:36 PM UTC 24
Peak memory 235340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186620700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.186620700
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/34.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/34.spi_device_mailbox.1157069971
Short name T746
Test name
Test status
Simulation time 1033821235 ps
CPU time 8.46 seconds
Started Aug 23 10:37:32 PM UTC 24
Finished Aug 23 10:37:42 PM UTC 24
Peak memory 251692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157069971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1157069971
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/34.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.514961335
Short name T325
Test name
Test status
Simulation time 1110698456 ps
CPU time 5.47 seconds
Started Aug 23 10:37:30 PM UTC 24
Finished Aug 23 10:37:37 PM UTC 24
Peak memory 247628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514961335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.514961335
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/34.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.2762974703
Short name T742
Test name
Test status
Simulation time 58025864 ps
CPU time 1.78 seconds
Started Aug 23 10:37:28 PM UTC 24
Finished Aug 23 10:37:31 PM UTC 24
Peak memory 233988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762974703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2762974703
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/34.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.1444165108
Short name T748
Test name
Test status
Simulation time 616368377 ps
CPU time 3.04 seconds
Started Aug 23 10:37:41 PM UTC 24
Finished Aug 23 10:37:46 PM UTC 24
Peak memory 231668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444165108 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.1444165108
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/34.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.2510611686
Short name T822
Test name
Test status
Simulation time 35549034259 ps
CPU time 130.64 seconds
Started Aug 23 10:37:50 PM UTC 24
Finished Aug 23 10:40:02 PM UTC 24
Peak memory 262156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510611686 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.2510611686
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/34.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_all.2028570341
Short name T738
Test name
Test status
Simulation time 1599076762 ps
CPU time 3.6 seconds
Started Aug 23 10:37:23 PM UTC 24
Finished Aug 23 10:37:28 PM UTC 24
Peak memory 228016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028570341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2028570341
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/34.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.3491962556
Short name T739
Test name
Test status
Simulation time 3383519181 ps
CPU time 4.87 seconds
Started Aug 23 10:37:22 PM UTC 24
Finished Aug 23 10:37:28 PM UTC 24
Peak memory 228072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491962556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3491962556
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/34.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_rw.1283929739
Short name T741
Test name
Test status
Simulation time 10486054 ps
CPU time 0.65 seconds
Started Aug 23 10:37:28 PM UTC 24
Finished Aug 23 10:37:30 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283929739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1283929739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/34.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.553414345
Short name T740
Test name
Test status
Simulation time 388459656 ps
CPU time 0.74 seconds
Started Aug 23 10:37:27 PM UTC 24
Finished Aug 23 10:37:29 PM UTC 24
Peak memory 215924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553414345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.553414345
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/34.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/34.spi_device_upload.3769247259
Short name T745
Test name
Test status
Simulation time 262852061 ps
CPU time 2.79 seconds
Started Aug 23 10:37:37 PM UTC 24
Finished Aug 23 10:37:41 PM UTC 24
Peak memory 234632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769247259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3769247259
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/34.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/35.spi_device_alert_test.3605037516
Short name T769
Test name
Test status
Simulation time 16826955 ps
CPU time 0.57 seconds
Started Aug 23 10:38:25 PM UTC 24
Finished Aug 23 10:38:26 PM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605037516 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.3605037516
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/35.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/35.spi_device_cfg_cmd.1902819624
Short name T765
Test name
Test status
Simulation time 491441455 ps
CPU time 6.22 seconds
Started Aug 23 10:38:14 PM UTC 24
Finished Aug 23 10:38:22 PM UTC 24
Peak memory 235340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902819624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1902819624
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/35.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/35.spi_device_csb_read.3542080738
Short name T752
Test name
Test status
Simulation time 54745558 ps
CPU time 0.67 seconds
Started Aug 23 10:37:52 PM UTC 24
Finished Aug 23 10:37:54 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542080738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3542080738
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/35.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.1081428436
Short name T764
Test name
Test status
Simulation time 36608394 ps
CPU time 0.64 seconds
Started Aug 23 10:38:18 PM UTC 24
Finished Aug 23 10:38:20 PM UTC 24
Peak memory 225676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081428436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1081428436
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/35.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.2519479927
Short name T808
Test name
Test status
Simulation time 22573896119 ps
CPU time 77 seconds
Started Aug 23 10:38:19 PM UTC 24
Finished Aug 23 10:39:38 PM UTC 24
Peak memory 262376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519479927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2519479927
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.1105573983
Short name T853
Test name
Test status
Simulation time 19314501128 ps
CPU time 138.61 seconds
Started Aug 23 10:38:20 PM UTC 24
Finished Aug 23 10:40:41 PM UTC 24
Peak memory 268320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105573983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.1105573983
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode.3948143417
Short name T763
Test name
Test status
Simulation time 1904960047 ps
CPU time 3.66 seconds
Started Aug 23 10:38:14 PM UTC 24
Finished Aug 23 10:38:19 PM UTC 24
Peak memory 245604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948143417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3948143417
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/35.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.3058418941
Short name T762
Test name
Test status
Simulation time 23921588 ps
CPU time 0.65 seconds
Started Aug 23 10:38:16 PM UTC 24
Finished Aug 23 10:38:18 PM UTC 24
Peak memory 225676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058418941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.3058418941
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/35.spi_device_intercept.449041371
Short name T761
Test name
Test status
Simulation time 838538465 ps
CPU time 6.5 seconds
Started Aug 23 10:38:08 PM UTC 24
Finished Aug 23 10:38:16 PM UTC 24
Peak memory 235592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449041371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.449041371
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/35.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/35.spi_device_mailbox.65786631
Short name T767
Test name
Test status
Simulation time 1054118786 ps
CPU time 13.46 seconds
Started Aug 23 10:38:10 PM UTC 24
Finished Aug 23 10:38:25 PM UTC 24
Peak memory 235540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65786631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.65786631
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/35.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.1304008326
Short name T333
Test name
Test status
Simulation time 5167050110 ps
CPU time 16.45 seconds
Started Aug 23 10:38:07 PM UTC 24
Finished Aug 23 10:38:25 PM UTC 24
Peak memory 251848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304008326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.1304008326
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/35.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.3436216776
Short name T759
Test name
Test status
Simulation time 855147461 ps
CPU time 6 seconds
Started Aug 23 10:38:05 PM UTC 24
Finished Aug 23 10:38:12 PM UTC 24
Peak memory 235304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436216776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3436216776
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/35.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.1680488151
Short name T766
Test name
Test status
Simulation time 1333420535 ps
CPU time 4.95 seconds
Started Aug 23 10:38:17 PM UTC 24
Finished Aug 23 10:38:23 PM UTC 24
Peak memory 233928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680488151 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.1680488151
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/35.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.1745587645
Short name T949
Test name
Test status
Simulation time 32515931855 ps
CPU time 291.06 seconds
Started Aug 23 10:38:23 PM UTC 24
Finished Aug 23 10:43:17 PM UTC 24
Peak memory 282840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745587645 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.1745587645
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/35.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_all.3452312120
Short name T754
Test name
Test status
Simulation time 945620972 ps
CPU time 2.89 seconds
Started Aug 23 10:37:58 PM UTC 24
Finished Aug 23 10:38:02 PM UTC 24
Peak memory 229820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452312120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3452312120
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/35.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.1142169276
Short name T758
Test name
Test status
Simulation time 19831885284 ps
CPU time 14.05 seconds
Started Aug 23 10:37:54 PM UTC 24
Finished Aug 23 10:38:09 PM UTC 24
Peak memory 229904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142169276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1142169276
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/35.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_rw.4163231112
Short name T757
Test name
Test status
Simulation time 112221249 ps
CPU time 0.84 seconds
Started Aug 23 10:38:05 PM UTC 24
Finished Aug 23 10:38:07 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163231112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.4163231112
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/35.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.3108123953
Short name T755
Test name
Test status
Simulation time 63532050 ps
CPU time 0.63 seconds
Started Aug 23 10:38:03 PM UTC 24
Finished Aug 23 10:38:05 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108123953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3108123953
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/35.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/35.spi_device_upload.1142328866
Short name T768
Test name
Test status
Simulation time 12287119334 ps
CPU time 11.46 seconds
Started Aug 23 10:38:13 PM UTC 24
Finished Aug 23 10:38:26 PM UTC 24
Peak memory 245928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142328866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1142328866
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/35.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/36.spi_device_alert_test.1234758086
Short name T782
Test name
Test status
Simulation time 24238578 ps
CPU time 0.63 seconds
Started Aug 23 10:38:50 PM UTC 24
Finished Aug 23 10:38:52 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234758086 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.1234758086
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/36.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/36.spi_device_cfg_cmd.1927596504
Short name T778
Test name
Test status
Simulation time 223151930 ps
CPU time 2.71 seconds
Started Aug 23 10:38:34 PM UTC 24
Finished Aug 23 10:38:38 PM UTC 24
Peak memory 235280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927596504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1927596504
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/36.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/36.spi_device_csb_read.1076240388
Short name T770
Test name
Test status
Simulation time 12684002 ps
CPU time 0.65 seconds
Started Aug 23 10:38:26 PM UTC 24
Finished Aug 23 10:38:27 PM UTC 24
Peak memory 215184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076240388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1076240388
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/36.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_all.3953418075
Short name T789
Test name
Test status
Simulation time 4893373165 ps
CPU time 30.97 seconds
Started Aug 23 10:38:39 PM UTC 24
Finished Aug 23 10:39:12 PM UTC 24
Peak memory 247756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953418075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3953418075
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/36.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.4233565330
Short name T819
Test name
Test status
Simulation time 48796854817 ps
CPU time 77.54 seconds
Started Aug 23 10:38:42 PM UTC 24
Finished Aug 23 10:40:02 PM UTC 24
Peak memory 251884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233565330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.4233565330
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/36.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.4259964880
Short name T331
Test name
Test status
Simulation time 24831197375 ps
CPU time 177.58 seconds
Started Aug 23 10:38:46 PM UTC 24
Finished Aug 23 10:41:47 PM UTC 24
Peak memory 268228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259964880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.4259964880
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode.4195905464
Short name T779
Test name
Test status
Simulation time 1687082144 ps
CPU time 4.15 seconds
Started Aug 23 10:38:36 PM UTC 24
Finished Aug 23 10:38:41 PM UTC 24
Peak memory 235308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195905464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.4195905464
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/36.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.1457501066
Short name T856
Test name
Test status
Simulation time 76695825604 ps
CPU time 123.42 seconds
Started Aug 23 10:38:38 PM UTC 24
Finished Aug 23 10:40:44 PM UTC 24
Peak memory 262280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457501066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.1457501066
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/36.spi_device_intercept.2573914022
Short name T775
Test name
Test status
Simulation time 278976394 ps
CPU time 1.8 seconds
Started Aug 23 10:38:30 PM UTC 24
Finished Aug 23 10:38:33 PM UTC 24
Peak memory 234956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573914022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2573914022
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/36.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/36.spi_device_mailbox.3680601055
Short name T795
Test name
Test status
Simulation time 14604799261 ps
CPU time 49.4 seconds
Started Aug 23 10:38:30 PM UTC 24
Finished Aug 23 10:39:21 PM UTC 24
Peak memory 251820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680601055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3680601055
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/36.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.2337927943
Short name T774
Test name
Test status
Simulation time 36877422 ps
CPU time 1.69 seconds
Started Aug 23 10:38:29 PM UTC 24
Finished Aug 23 10:38:32 PM UTC 24
Peak memory 244920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337927943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.2337927943
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/36.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.1322062255
Short name T275
Test name
Test status
Simulation time 7199242782 ps
CPU time 19.56 seconds
Started Aug 23 10:38:29 PM UTC 24
Finished Aug 23 10:38:50 PM UTC 24
Peak memory 245672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322062255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1322062255
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/36.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.2511202298
Short name T780
Test name
Test status
Simulation time 3413541247 ps
CPU time 7.23 seconds
Started Aug 23 10:38:38 PM UTC 24
Finished Aug 23 10:38:46 PM UTC 24
Peak memory 233844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511202298 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.2511202298
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/36.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.2076340854
Short name T1029
Test name
Test status
Simulation time 196748720216 ps
CPU time 678.04 seconds
Started Aug 23 10:38:47 PM UTC 24
Finished Aug 23 10:50:13 PM UTC 24
Peak memory 296960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076340854 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.2076340854
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/36.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_all.4084187011
Short name T776
Test name
Test status
Simulation time 3186979847 ps
CPU time 7.76 seconds
Started Aug 23 10:38:27 PM UTC 24
Finished Aug 23 10:38:36 PM UTC 24
Peak memory 227900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084187011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.4084187011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/36.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.748542683
Short name T772
Test name
Test status
Simulation time 2148527693 ps
CPU time 2.33 seconds
Started Aug 23 10:38:26 PM UTC 24
Finished Aug 23 10:38:29 PM UTC 24
Peak memory 227860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748542683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.748542683
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/36.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_rw.1057581936
Short name T773
Test name
Test status
Simulation time 38958710 ps
CPU time 0.59 seconds
Started Aug 23 10:38:28 PM UTC 24
Finished Aug 23 10:38:29 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057581936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1057581936
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/36.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.3686504118
Short name T771
Test name
Test status
Simulation time 66592721 ps
CPU time 0.73 seconds
Started Aug 23 10:38:27 PM UTC 24
Finished Aug 23 10:38:29 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686504118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3686504118
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/36.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/36.spi_device_upload.1135979215
Short name T777
Test name
Test status
Simulation time 4061789252 ps
CPU time 4.65 seconds
Started Aug 23 10:38:32 PM UTC 24
Finished Aug 23 10:38:38 PM UTC 24
Peak memory 245736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135979215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1135979215
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/36.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/37.spi_device_alert_test.2935848219
Short name T799
Test name
Test status
Simulation time 14049442 ps
CPU time 0.59 seconds
Started Aug 23 10:39:24 PM UTC 24
Finished Aug 23 10:39:25 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935848219 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.2935848219
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/37.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/37.spi_device_cfg_cmd.2040947856
Short name T793
Test name
Test status
Simulation time 37770098 ps
CPU time 1.73 seconds
Started Aug 23 10:39:13 PM UTC 24
Finished Aug 23 10:39:16 PM UTC 24
Peak memory 244888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040947856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2040947856
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/37.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/37.spi_device_csb_read.3650761520
Short name T783
Test name
Test status
Simulation time 25063403 ps
CPU time 0.67 seconds
Started Aug 23 10:38:50 PM UTC 24
Finished Aug 23 10:38:52 PM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650761520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3650761520
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/37.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.3376899620
Short name T796
Test name
Test status
Simulation time 2422817705 ps
CPU time 5.36 seconds
Started Aug 23 10:39:16 PM UTC 24
Finished Aug 23 10:39:23 PM UTC 24
Peak memory 245736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376899620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3376899620
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/37.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.871466289
Short name T824
Test name
Test status
Simulation time 10641469509 ps
CPU time 46.87 seconds
Started Aug 23 10:39:17 PM UTC 24
Finished Aug 23 10:40:06 PM UTC 24
Peak memory 268316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871466289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.871466289
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/37.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1182995909
Short name T1018
Test name
Test status
Simulation time 47374214468 ps
CPU time 358.29 seconds
Started Aug 23 10:39:17 PM UTC 24
Finished Aug 23 10:45:20 PM UTC 24
Peak memory 276484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182995909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.1182995909
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.3572428029
Short name T792
Test name
Test status
Simulation time 16670509 ps
CPU time 0.64 seconds
Started Aug 23 10:39:13 PM UTC 24
Finished Aug 23 10:39:15 PM UTC 24
Peak memory 225676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572428029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.3572428029
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/37.spi_device_intercept.4162126715
Short name T794
Test name
Test status
Simulation time 5346385770 ps
CPU time 9.92 seconds
Started Aug 23 10:39:06 PM UTC 24
Finished Aug 23 10:39:17 PM UTC 24
Peak memory 244572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162126715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4162126715
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/37.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/37.spi_device_mailbox.774909793
Short name T801
Test name
Test status
Simulation time 2542629460 ps
CPU time 14.82 seconds
Started Aug 23 10:39:11 PM UTC 24
Finished Aug 23 10:39:27 PM UTC 24
Peak memory 245648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774909793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.774909793
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/37.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.646833784
Short name T791
Test name
Test status
Simulation time 1219023586 ps
CPU time 10.9 seconds
Started Aug 23 10:39:01 PM UTC 24
Finished Aug 23 10:39:13 PM UTC 24
Peak memory 245644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646833784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.646833784
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/37.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.106808728
Short name T787
Test name
Test status
Simulation time 600142784 ps
CPU time 3.58 seconds
Started Aug 23 10:39:01 PM UTC 24
Finished Aug 23 10:39:05 PM UTC 24
Peak memory 245588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106808728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.106808728
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/37.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.573043899
Short name T797
Test name
Test status
Simulation time 3371035014 ps
CPU time 7.6 seconds
Started Aug 23 10:39:15 PM UTC 24
Finished Aug 23 10:39:24 PM UTC 24
Peak memory 233972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573043899 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.573043899
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/37.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.555987405
Short name T1030
Test name
Test status
Simulation time 1655998132799 ps
CPU time 729.21 seconds
Started Aug 23 10:39:21 PM UTC 24
Finished Aug 23 10:51:38 PM UTC 24
Peak memory 284704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555987405 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.555987405
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/37.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_all.342104145
Short name T788
Test name
Test status
Simulation time 19735530949 ps
CPU time 16.01 seconds
Started Aug 23 10:38:53 PM UTC 24
Finished Aug 23 10:39:10 PM UTC 24
Peak memory 227960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342104145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.342104145
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/37.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.4054454647
Short name T790
Test name
Test status
Simulation time 27938508977 ps
CPU time 17.31 seconds
Started Aug 23 10:38:53 PM UTC 24
Finished Aug 23 10:39:12 PM UTC 24
Peak memory 228028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054454647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.4054454647
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/37.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_rw.2731529373
Short name T786
Test name
Test status
Simulation time 12674425 ps
CPU time 0.6 seconds
Started Aug 23 10:38:59 PM UTC 24
Finished Aug 23 10:39:01 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731529373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2731529373
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/37.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.485919879
Short name T785
Test name
Test status
Simulation time 25643577 ps
CPU time 0.67 seconds
Started Aug 23 10:38:56 PM UTC 24
Finished Aug 23 10:38:58 PM UTC 24
Peak memory 215924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485919879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.485919879
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/37.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/37.spi_device_upload.3327822549
Short name T798
Test name
Test status
Simulation time 6308989063 ps
CPU time 11.2 seconds
Started Aug 23 10:39:12 PM UTC 24
Finished Aug 23 10:39:25 PM UTC 24
Peak memory 262060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327822549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3327822549
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/37.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/38.spi_device_alert_test.1146114635
Short name T811
Test name
Test status
Simulation time 94585702 ps
CPU time 0.6 seconds
Started Aug 23 10:39:45 PM UTC 24
Finished Aug 23 10:39:47 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146114635 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.1146114635
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/38.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/38.spi_device_cfg_cmd.1798194897
Short name T806
Test name
Test status
Simulation time 166907979 ps
CPU time 1.98 seconds
Started Aug 23 10:39:33 PM UTC 24
Finished Aug 23 10:39:36 PM UTC 24
Peak memory 244920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798194897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1798194897
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/38.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/38.spi_device_csb_read.1914368978
Short name T800
Test name
Test status
Simulation time 31172903 ps
CPU time 0.65 seconds
Started Aug 23 10:39:25 PM UTC 24
Finished Aug 23 10:39:26 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914368978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1914368978
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/38.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_all.1578069926
Short name T897
Test name
Test status
Simulation time 101981233586 ps
CPU time 136.31 seconds
Started Aug 23 10:39:38 PM UTC 24
Finished Aug 23 10:41:57 PM UTC 24
Peak memory 266184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578069926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1578069926
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/38.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.3825930843
Short name T836
Test name
Test status
Simulation time 2388671596 ps
CPU time 34.25 seconds
Started Aug 23 10:39:39 PM UTC 24
Finished Aug 23 10:40:15 PM UTC 24
Peak memory 262156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825930843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3825930843
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/38.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.1585845120
Short name T895
Test name
Test status
Simulation time 71399917833 ps
CPU time 126.23 seconds
Started Aug 23 10:39:40 PM UTC 24
Finished Aug 23 10:41:49 PM UTC 24
Peak memory 262148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585845120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.1585845120
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode.3753714722
Short name T817
Test name
Test status
Simulation time 1707875629 ps
CPU time 23.34 seconds
Started Aug 23 10:39:33 PM UTC 24
Finished Aug 23 10:39:58 PM UTC 24
Peak memory 235332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753714722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3753714722
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/38.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.2623790456
Short name T321
Test name
Test status
Simulation time 24699848247 ps
CPU time 57.11 seconds
Started Aug 23 10:39:34 PM UTC 24
Finished Aug 23 10:40:33 PM UTC 24
Peak memory 262084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623790456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.2623790456
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/38.spi_device_intercept.1295126649
Short name T805
Test name
Test status
Simulation time 141029124 ps
CPU time 2.71 seconds
Started Aug 23 10:39:30 PM UTC 24
Finished Aug 23 10:39:34 PM UTC 24
Peak memory 245548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295126649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1295126649
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/38.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/38.spi_device_mailbox.1474254702
Short name T818
Test name
Test status
Simulation time 3534846761 ps
CPU time 29.88 seconds
Started Aug 23 10:39:30 PM UTC 24
Finished Aug 23 10:40:01 PM UTC 24
Peak memory 235692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474254702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1474254702
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/38.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.1150657973
Short name T814
Test name
Test status
Simulation time 12110406271 ps
CPU time 19.31 seconds
Started Aug 23 10:39:29 PM UTC 24
Finished Aug 23 10:39:49 PM UTC 24
Peak memory 252040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150657973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.1150657973
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/38.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.1200013785
Short name T812
Test name
Test status
Simulation time 13400883157 ps
CPU time 19.69 seconds
Started Aug 23 10:39:28 PM UTC 24
Finished Aug 23 10:39:49 PM UTC 24
Peak memory 245772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200013785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1200013785
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/38.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.3190315246
Short name T810
Test name
Test status
Simulation time 523496899 ps
CPU time 6.58 seconds
Started Aug 23 10:39:37 PM UTC 24
Finished Aug 23 10:39:45 PM UTC 24
Peak memory 233756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190315246 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.3190315246
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/38.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.2407653371
Short name T1012
Test name
Test status
Simulation time 314432963636 ps
CPU time 286.8 seconds
Started Aug 23 10:39:45 PM UTC 24
Finished Aug 23 10:44:36 PM UTC 24
Peak memory 268496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407653371 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.2407653371
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/38.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_all.1384084268
Short name T807
Test name
Test status
Simulation time 15100896085 ps
CPU time 10.97 seconds
Started Aug 23 10:39:26 PM UTC 24
Finished Aug 23 10:39:38 PM UTC 24
Peak memory 227900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384084268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1384084268
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/38.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.1664932372
Short name T804
Test name
Test status
Simulation time 6158336257 ps
CPU time 5.3 seconds
Started Aug 23 10:39:26 PM UTC 24
Finished Aug 23 10:39:32 PM UTC 24
Peak memory 228080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664932372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1664932372
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/38.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_rw.2615348011
Short name T803
Test name
Test status
Simulation time 41873113 ps
CPU time 0.76 seconds
Started Aug 23 10:39:28 PM UTC 24
Finished Aug 23 10:39:30 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615348011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2615348011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/38.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.3266807654
Short name T802
Test name
Test status
Simulation time 88889531 ps
CPU time 0.6 seconds
Started Aug 23 10:39:27 PM UTC 24
Finished Aug 23 10:39:28 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266807654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3266807654
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/38.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/38.spi_device_upload.1993691285
Short name T809
Test name
Test status
Simulation time 1581231065 ps
CPU time 7.46 seconds
Started Aug 23 10:39:31 PM UTC 24
Finished Aug 23 10:39:40 PM UTC 24
Peak memory 245588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993691285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1993691285
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/38.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/39.spi_device_alert_test.2958335266
Short name T831
Test name
Test status
Simulation time 40297836 ps
CPU time 0.63 seconds
Started Aug 23 10:40:08 PM UTC 24
Finished Aug 23 10:40:10 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958335266 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.2958335266
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/39.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/39.spi_device_cfg_cmd.2519691735
Short name T826
Test name
Test status
Simulation time 2837528202 ps
CPU time 3.76 seconds
Started Aug 23 10:40:02 PM UTC 24
Finished Aug 23 10:40:07 PM UTC 24
Peak memory 235388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519691735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2519691735
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/39.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/39.spi_device_csb_read.2948108704
Short name T813
Test name
Test status
Simulation time 36400478 ps
CPU time 0.65 seconds
Started Aug 23 10:39:47 PM UTC 24
Finished Aug 23 10:39:49 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948108704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2948108704
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/39.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.2203692314
Short name T926
Test name
Test status
Simulation time 24323405088 ps
CPU time 157.85 seconds
Started Aug 23 10:40:06 PM UTC 24
Finished Aug 23 10:42:46 PM UTC 24
Peak memory 252044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203692314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2203692314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/39.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.3508141008
Short name T845
Test name
Test status
Simulation time 2430479582 ps
CPU time 20.5 seconds
Started Aug 23 10:40:06 PM UTC 24
Finished Aug 23 10:40:28 PM UTC 24
Peak memory 251944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508141008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3508141008
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/39.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.573690904
Short name T228
Test name
Test status
Simulation time 1136646801 ps
CPU time 27.1 seconds
Started Aug 23 10:40:06 PM UTC 24
Finished Aug 23 10:40:35 PM UTC 24
Peak memory 262092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573690904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.573690904
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.4119297724
Short name T846
Test name
Test status
Simulation time 4001730274 ps
CPU time 29.69 seconds
Started Aug 23 10:40:03 PM UTC 24
Finished Aug 23 10:40:34 PM UTC 24
Peak memory 264140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119297724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.4119297724
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/39.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.3092185895
Short name T840
Test name
Test status
Simulation time 844201296 ps
CPU time 14.91 seconds
Started Aug 23 10:40:03 PM UTC 24
Finished Aug 23 10:40:19 PM UTC 24
Peak memory 261984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092185895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.3092185895
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/39.spi_device_intercept.1793512404
Short name T830
Test name
Test status
Simulation time 3230895230 ps
CPU time 9.1 seconds
Started Aug 23 10:40:00 PM UTC 24
Finished Aug 23 10:40:10 PM UTC 24
Peak memory 245676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793512404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1793512404
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/39.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/39.spi_device_mailbox.3888758672
Short name T823
Test name
Test status
Simulation time 616357743 ps
CPU time 4.03 seconds
Started Aug 23 10:40:00 PM UTC 24
Finished Aug 23 10:40:05 PM UTC 24
Peak memory 245584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888758672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3888758672
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/39.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.710966112
Short name T821
Test name
Test status
Simulation time 1058945595 ps
CPU time 1.99 seconds
Started Aug 23 10:39:59 PM UTC 24
Finished Aug 23 10:40:02 PM UTC 24
Peak memory 234696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710966112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.710966112
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/39.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.1027994974
Short name T832
Test name
Test status
Simulation time 22978805556 ps
CPU time 14.08 seconds
Started Aug 23 10:39:56 PM UTC 24
Finished Aug 23 10:40:11 PM UTC 24
Peak memory 245712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027994974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1027994974
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/39.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.677494053
Short name T828
Test name
Test status
Simulation time 516208481 ps
CPU time 4.23 seconds
Started Aug 23 10:40:03 PM UTC 24
Finished Aug 23 10:40:08 PM UTC 24
Peak memory 233684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677494053 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.677494053
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/39.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.2859192353
Short name T886
Test name
Test status
Simulation time 25849121095 ps
CPU time 83.38 seconds
Started Aug 23 10:40:07 PM UTC 24
Finished Aug 23 10:41:32 PM UTC 24
Peak memory 278476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859192353 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.2859192353
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/39.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.3865815366
Short name T820
Test name
Test status
Simulation time 4827809649 ps
CPU time 11.13 seconds
Started Aug 23 10:39:50 PM UTC 24
Finished Aug 23 10:40:02 PM UTC 24
Peak memory 227892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865815366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3865815366
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/39.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.3258638118
Short name T827
Test name
Test status
Simulation time 12021529227 ps
CPU time 16.63 seconds
Started Aug 23 10:39:50 PM UTC 24
Finished Aug 23 10:40:07 PM UTC 24
Peak memory 227836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258638118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3258638118
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/39.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_rw.1841801275
Short name T816
Test name
Test status
Simulation time 92589278 ps
CPU time 0.8 seconds
Started Aug 23 10:39:53 PM UTC 24
Finished Aug 23 10:39:55 PM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841801275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1841801275
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/39.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.3387463748
Short name T815
Test name
Test status
Simulation time 37887080 ps
CPU time 0.74 seconds
Started Aug 23 10:39:51 PM UTC 24
Finished Aug 23 10:39:52 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387463748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3387463748
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/39.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/39.spi_device_upload.1047713035
Short name T825
Test name
Test status
Simulation time 130329465 ps
CPU time 2.81 seconds
Started Aug 23 10:40:02 PM UTC 24
Finished Aug 23 10:40:06 PM UTC 24
Peak memory 235368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047713035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1047713035
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/39.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.1935517983
Short name T377
Test name
Test status
Simulation time 16970714 ps
CPU time 0.58 seconds
Started Aug 23 10:23:11 PM UTC 24
Finished Aug 23 10:23:13 PM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935517983 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1935517983
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.4288102387
Short name T92
Test name
Test status
Simulation time 294162976 ps
CPU time 4.01 seconds
Started Aug 23 10:22:57 PM UTC 24
Finished Aug 23 10:23:02 PM UTC 24
Peak memory 245924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288102387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.4288102387
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.3351101785
Short name T374
Test name
Test status
Simulation time 12170400 ps
CPU time 0.66 seconds
Started Aug 23 10:22:44 PM UTC 24
Finished Aug 23 10:22:45 PM UTC 24
Peak memory 215800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351101785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3351101785
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.342562403
Short name T190
Test name
Test status
Simulation time 28484383823 ps
CPU time 193.14 seconds
Started Aug 23 10:23:03 PM UTC 24
Finished Aug 23 10:26:19 PM UTC 24
Peak memory 268424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342562403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.342562403
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.2326250633
Short name T124
Test name
Test status
Simulation time 982675227 ps
CPU time 12.48 seconds
Started Aug 23 10:22:57 PM UTC 24
Finished Aug 23 10:23:11 PM UTC 24
Peak memory 235364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326250633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2326250633
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.3288541847
Short name T184
Test name
Test status
Simulation time 5266423194 ps
CPU time 11.87 seconds
Started Aug 23 10:22:50 PM UTC 24
Finished Aug 23 10:23:03 PM UTC 24
Peak memory 235728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288541847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3288541847
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.1538306392
Short name T111
Test name
Test status
Simulation time 3447617041 ps
CPU time 26.51 seconds
Started Aug 23 10:22:50 PM UTC 24
Finished Aug 23 10:23:18 PM UTC 24
Peak memory 235464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538306392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1538306392
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.2918528184
Short name T375
Test name
Test status
Simulation time 44152179 ps
CPU time 0.89 seconds
Started Aug 23 10:22:45 PM UTC 24
Finished Aug 23 10:22:47 PM UTC 24
Peak memory 229208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918528184 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_parity.2918528184
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.1279584465
Short name T63
Test name
Test status
Simulation time 1492104511 ps
CPU time 6.82 seconds
Started Aug 23 10:22:49 PM UTC 24
Finished Aug 23 10:22:57 PM UTC 24
Peak memory 261968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279584465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.1279584465
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.2908689118
Short name T116
Test name
Test status
Simulation time 15582863948 ps
CPU time 11.95 seconds
Started Aug 23 10:22:48 PM UTC 24
Finished Aug 23 10:23:01 PM UTC 24
Peak memory 235060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908689118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2908689118
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.1023242030
Short name T125
Test name
Test status
Simulation time 219090514 ps
CPU time 4.18 seconds
Started Aug 23 10:23:02 PM UTC 24
Finished Aug 23 10:23:07 PM UTC 24
Peak memory 234116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023242030 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.1023242030
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.2448017694
Short name T35
Test name
Test status
Simulation time 722343367 ps
CPU time 0.88 seconds
Started Aug 23 10:23:09 PM UTC 24
Finished Aug 23 10:23:11 PM UTC 24
Peak memory 257680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448017694 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2448017694
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.1859770486
Short name T38
Test name
Test status
Simulation time 8535642865 ps
CPU time 17.92 seconds
Started Aug 23 10:23:06 PM UTC 24
Finished Aug 23 10:23:25 PM UTC 24
Peak memory 235192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859770486 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.1859770486
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.1359726425
Short name T376
Test name
Test status
Simulation time 14518915 ps
CPU time 0.62 seconds
Started Aug 23 10:22:46 PM UTC 24
Finished Aug 23 10:22:47 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359726425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1359726425
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2216540007
Short name T106
Test name
Test status
Simulation time 5389587326 ps
CPU time 13.85 seconds
Started Aug 23 10:22:46 PM UTC 24
Finished Aug 23 10:23:01 PM UTC 24
Peak memory 227884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216540007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2216540007
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.1961849219
Short name T71
Test name
Test status
Simulation time 17641137 ps
CPU time 0.67 seconds
Started Aug 23 10:22:48 PM UTC 24
Finished Aug 23 10:22:50 PM UTC 24
Peak memory 215640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961849219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1961849219
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.3636128012
Short name T105
Test name
Test status
Simulation time 345273126 ps
CPU time 0.76 seconds
Started Aug 23 10:22:47 PM UTC 24
Finished Aug 23 10:22:49 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636128012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3636128012
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.3689712359
Short name T86
Test name
Test status
Simulation time 34931968787 ps
CPU time 30.4 seconds
Started Aug 23 10:22:53 PM UTC 24
Finished Aug 23 10:23:25 PM UTC 24
Peak memory 245644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689712359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3689712359
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/4.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.2604348675
Short name T848
Test name
Test status
Simulation time 14331287 ps
CPU time 0.64 seconds
Started Aug 23 10:40:35 PM UTC 24
Finished Aug 23 10:40:37 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604348675 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.2604348675
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/40.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/40.spi_device_cfg_cmd.774044745
Short name T842
Test name
Test status
Simulation time 1512551817 ps
CPU time 2.76 seconds
Started Aug 23 10:40:19 PM UTC 24
Finished Aug 23 10:40:23 PM UTC 24
Peak memory 235468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774044745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.774044745
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/40.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/40.spi_device_csb_read.3631754825
Short name T833
Test name
Test status
Simulation time 86077939 ps
CPU time 0.63 seconds
Started Aug 23 10:40:09 PM UTC 24
Finished Aug 23 10:40:11 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631754825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3631754825
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/40.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.604206407
Short name T922
Test name
Test status
Simulation time 77923384782 ps
CPU time 129.9 seconds
Started Aug 23 10:40:25 PM UTC 24
Finished Aug 23 10:42:37 PM UTC 24
Peak memory 264196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604206407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.604206407
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/40.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.3273215288
Short name T330
Test name
Test status
Simulation time 14893296656 ps
CPU time 68.69 seconds
Started Aug 23 10:40:29 PM UTC 24
Finished Aug 23 10:41:40 PM UTC 24
Peak memory 268296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273215288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3273215288
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.908823051
Short name T1023
Test name
Test status
Simulation time 238399626476 ps
CPU time 341.13 seconds
Started Aug 23 10:40:29 PM UTC 24
Finished Aug 23 10:46:14 PM UTC 24
Peak memory 282608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908823051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.908823051
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.919025561
Short name T857
Test name
Test status
Simulation time 10984401534 ps
CPU time 24.05 seconds
Started Aug 23 10:40:20 PM UTC 24
Finished Aug 23 10:40:45 PM UTC 24
Peak memory 245960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919025561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.919025561
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/40.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.269136924
Short name T873
Test name
Test status
Simulation time 2199607630 ps
CPU time 40.06 seconds
Started Aug 23 10:40:20 PM UTC 24
Finished Aug 23 10:41:01 PM UTC 24
Peak memory 262116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269136924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.269136924
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/40.spi_device_intercept.906417762
Short name T841
Test name
Test status
Simulation time 199749204 ps
CPU time 2.58 seconds
Started Aug 23 10:40:16 PM UTC 24
Finished Aug 23 10:40:19 PM UTC 24
Peak memory 235456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906417762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.906417762
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/40.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.3713098491
Short name T844
Test name
Test status
Simulation time 349707118 ps
CPU time 8.92 seconds
Started Aug 23 10:40:18 PM UTC 24
Finished Aug 23 10:40:28 PM UTC 24
Peak memory 251852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713098491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3713098491
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/40.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.135706623
Short name T838
Test name
Test status
Simulation time 400934091 ps
CPU time 1.83 seconds
Started Aug 23 10:40:15 PM UTC 24
Finished Aug 23 10:40:18 PM UTC 24
Peak memory 233600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135706623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.135706623
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/40.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.4161007878
Short name T837
Test name
Test status
Simulation time 182315464 ps
CPU time 2.61 seconds
Started Aug 23 10:40:14 PM UTC 24
Finished Aug 23 10:40:17 PM UTC 24
Peak memory 245580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161007878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4161007878
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/40.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.771685486
Short name T850
Test name
Test status
Simulation time 3368682769 ps
CPU time 13.72 seconds
Started Aug 23 10:40:23 PM UTC 24
Finished Aug 23 10:40:38 PM UTC 24
Peak memory 234040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771685486 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.771685486
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/40.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.886785984
Short name T847
Test name
Test status
Simulation time 322903147 ps
CPU time 0.85 seconds
Started Aug 23 10:40:34 PM UTC 24
Finished Aug 23 10:40:36 PM UTC 24
Peak memory 216920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886785984 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.886785984
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/40.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.2143601391
Short name T863
Test name
Test status
Simulation time 171467807446 ps
CPU time 36.75 seconds
Started Aug 23 10:40:11 PM UTC 24
Finished Aug 23 10:40:50 PM UTC 24
Peak memory 227428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143601391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2143601391
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/40.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.3401407869
Short name T839
Test name
Test status
Simulation time 2108232838 ps
CPU time 6.32 seconds
Started Aug 23 10:40:10 PM UTC 24
Finished Aug 23 10:40:18 PM UTC 24
Peak memory 227756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401407869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3401407869
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/40.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_rw.1040228499
Short name T835
Test name
Test status
Simulation time 71682338 ps
CPU time 0.79 seconds
Started Aug 23 10:40:12 PM UTC 24
Finished Aug 23 10:40:13 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040228499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1040228499
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/40.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.2660523251
Short name T834
Test name
Test status
Simulation time 170644790 ps
CPU time 0.69 seconds
Started Aug 23 10:40:12 PM UTC 24
Finished Aug 23 10:40:13 PM UTC 24
Peak memory 214636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660523251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2660523251
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/40.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.2548912605
Short name T843
Test name
Test status
Simulation time 3981625792 ps
CPU time 4.76 seconds
Started Aug 23 10:40:19 PM UTC 24
Finished Aug 23 10:40:25 PM UTC 24
Peak memory 235496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548912605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2548912605
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/40.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.988975765
Short name T869
Test name
Test status
Simulation time 44334262 ps
CPU time 0.63 seconds
Started Aug 23 10:40:51 PM UTC 24
Finished Aug 23 10:40:53 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988975765 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.988975765
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/41.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.105330298
Short name T862
Test name
Test status
Simulation time 429689579 ps
CPU time 3.12 seconds
Started Aug 23 10:40:45 PM UTC 24
Finished Aug 23 10:40:49 PM UTC 24
Peak memory 245608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105330298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.105330298
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/41.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.2976187529
Short name T849
Test name
Test status
Simulation time 20910459 ps
CPU time 0.72 seconds
Started Aug 23 10:40:35 PM UTC 24
Finished Aug 23 10:40:37 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976187529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2976187529
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/41.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.3492983023
Short name T865
Test name
Test status
Simulation time 31608058 ps
CPU time 0.67 seconds
Started Aug 23 10:40:49 PM UTC 24
Finished Aug 23 10:40:51 PM UTC 24
Peak memory 225676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492983023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3492983023
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/41.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.1698787188
Short name T951
Test name
Test status
Simulation time 133767725405 ps
CPU time 149.44 seconds
Started Aug 23 10:40:49 PM UTC 24
Finished Aug 23 10:43:21 PM UTC 24
Peak memory 268300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698787188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1698787188
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.2207463159
Short name T165
Test name
Test status
Simulation time 9734323764 ps
CPU time 45.25 seconds
Started Aug 23 10:40:50 PM UTC 24
Finished Aug 23 10:41:37 PM UTC 24
Peak memory 262176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207463159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.2207463159
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.2410420710
Short name T866
Test name
Test status
Simulation time 428919442 ps
CPU time 5.18 seconds
Started Aug 23 10:40:46 PM UTC 24
Finished Aug 23 10:40:52 PM UTC 24
Peak memory 245412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410420710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2410420710
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/41.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.846785519
Short name T874
Test name
Test status
Simulation time 16028629210 ps
CPU time 21.16 seconds
Started Aug 23 10:40:46 PM UTC 24
Finished Aug 23 10:41:08 PM UTC 24
Peak memory 251532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846785519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.846785519
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.831863554
Short name T859
Test name
Test status
Simulation time 155346658 ps
CPU time 3.49 seconds
Started Aug 23 10:40:43 PM UTC 24
Finished Aug 23 10:40:47 PM UTC 24
Peak memory 235276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831863554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.831863554
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/41.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.2114916949
Short name T858
Test name
Test status
Simulation time 187654941 ps
CPU time 1.8 seconds
Started Aug 23 10:40:43 PM UTC 24
Finished Aug 23 10:40:45 PM UTC 24
Peak memory 234716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114916949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2114916949
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/41.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.1264444769
Short name T860
Test name
Test status
Simulation time 35742761577 ps
CPU time 6.74 seconds
Started Aug 23 10:40:40 PM UTC 24
Finished Aug 23 10:40:48 PM UTC 24
Peak memory 245732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264444769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.1264444769
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/41.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.92497724
Short name T855
Test name
Test status
Simulation time 311811753 ps
CPU time 1.91 seconds
Started Aug 23 10:40:39 PM UTC 24
Finished Aug 23 10:40:42 PM UTC 24
Peak memory 235192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92497724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.92497724
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/41.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.329479459
Short name T868
Test name
Test status
Simulation time 175570217 ps
CPU time 3.84 seconds
Started Aug 23 10:40:48 PM UTC 24
Finished Aug 23 10:40:53 PM UTC 24
Peak memory 233748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329479459 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.329479459
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/41.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.2367870025
Short name T75
Test name
Test status
Simulation time 31744900056 ps
CPU time 192.28 seconds
Started Aug 23 10:40:51 PM UTC 24
Finished Aug 23 10:44:06 PM UTC 24
Peak memory 278564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367870025 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.2367870025
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/41.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.486559344
Short name T861
Test name
Test status
Simulation time 21071745489 ps
CPU time 9.98 seconds
Started Aug 23 10:40:37 PM UTC 24
Finished Aug 23 10:40:48 PM UTC 24
Peak memory 232252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486559344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.486559344
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/41.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.3748310730
Short name T852
Test name
Test status
Simulation time 886535339 ps
CPU time 1.79 seconds
Started Aug 23 10:40:37 PM UTC 24
Finished Aug 23 10:40:40 PM UTC 24
Peak memory 226668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748310730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3748310730
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/41.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.2694932474
Short name T854
Test name
Test status
Simulation time 767697224 ps
CPU time 2.05 seconds
Started Aug 23 10:40:38 PM UTC 24
Finished Aug 23 10:40:42 PM UTC 24
Peak memory 227964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694932474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2694932474
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/41.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.1129446768
Short name T851
Test name
Test status
Simulation time 39189375 ps
CPU time 0.67 seconds
Started Aug 23 10:40:37 PM UTC 24
Finished Aug 23 10:40:39 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129446768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1129446768
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/41.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.973368760
Short name T864
Test name
Test status
Simulation time 5367918774 ps
CPU time 5.64 seconds
Started Aug 23 10:40:44 PM UTC 24
Finished Aug 23 10:40:50 PM UTC 24
Peak memory 245736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973368760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.973368760
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/41.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.356183669
Short name T884
Test name
Test status
Simulation time 43298853 ps
CPU time 0.63 seconds
Started Aug 23 10:41:22 PM UTC 24
Finished Aug 23 10:41:24 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356183669 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.356183669
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/42.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.2018090341
Short name T877
Test name
Test status
Simulation time 1289352694 ps
CPU time 3.34 seconds
Started Aug 23 10:41:09 PM UTC 24
Finished Aug 23 10:41:13 PM UTC 24
Peak memory 245520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018090341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2018090341
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/42.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.3237600898
Short name T867
Test name
Test status
Simulation time 15701118 ps
CPU time 0.67 seconds
Started Aug 23 10:40:51 PM UTC 24
Finished Aug 23 10:40:53 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237600898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3237600898
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/42.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.1011914165
Short name T341
Test name
Test status
Simulation time 45193459731 ps
CPU time 278.02 seconds
Started Aug 23 10:41:15 PM UTC 24
Finished Aug 23 10:45:57 PM UTC 24
Peak memory 278476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011914165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1011914165
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/42.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.412310544
Short name T899
Test name
Test status
Simulation time 35383051452 ps
CPU time 38.5 seconds
Started Aug 23 10:41:19 PM UTC 24
Finished Aug 23 10:41:59 PM UTC 24
Peak memory 230016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412310544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.412310544
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.408249617
Short name T907
Test name
Test status
Simulation time 27061321364 ps
CPU time 48.22 seconds
Started Aug 23 10:41:19 PM UTC 24
Finished Aug 23 10:42:09 PM UTC 24
Peak memory 264200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408249617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.408249617
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.1144946426
Short name T876
Test name
Test status
Simulation time 501948671 ps
CPU time 2.97 seconds
Started Aug 23 10:41:09 PM UTC 24
Finished Aug 23 10:41:13 PM UTC 24
Peak memory 235344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144946426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1144946426
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/42.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.3082823417
Short name T908
Test name
Test status
Simulation time 3821322607 ps
CPU time 55.46 seconds
Started Aug 23 10:41:14 PM UTC 24
Finished Aug 23 10:42:11 PM UTC 24
Peak memory 262152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082823417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.3082823417
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.2623916446
Short name T875
Test name
Test status
Simulation time 1135702927 ps
CPU time 9.1 seconds
Started Aug 23 10:40:57 PM UTC 24
Finished Aug 23 10:41:08 PM UTC 24
Peak memory 245548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623916446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2623916446
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/42.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.2481227763
Short name T882
Test name
Test status
Simulation time 16788868809 ps
CPU time 17.71 seconds
Started Aug 23 10:41:02 PM UTC 24
Finished Aug 23 10:41:21 PM UTC 24
Peak memory 235664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481227763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2481227763
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/42.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.3533587548
Short name T880
Test name
Test status
Simulation time 7542713326 ps
CPU time 20.05 seconds
Started Aug 23 10:40:56 PM UTC 24
Finished Aug 23 10:41:18 PM UTC 24
Peak memory 245964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533587548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.3533587548
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/42.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.696313124
Short name T878
Test name
Test status
Simulation time 2847131649 ps
CPU time 15.93 seconds
Started Aug 23 10:40:56 PM UTC 24
Finished Aug 23 10:41:14 PM UTC 24
Peak memory 262292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696313124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.696313124
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/42.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.3615963388
Short name T883
Test name
Test status
Simulation time 2124788923 ps
CPU time 8.01 seconds
Started Aug 23 10:41:14 PM UTC 24
Finished Aug 23 10:41:23 PM UTC 24
Peak memory 231668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615963388 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.3615963388
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/42.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.1064533010
Short name T1026
Test name
Test status
Simulation time 405998860353 ps
CPU time 366.35 seconds
Started Aug 23 10:41:21 PM UTC 24
Finished Aug 23 10:47:32 PM UTC 24
Peak memory 268296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064533010 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.1064533010
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/42.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.155682324
Short name T879
Test name
Test status
Simulation time 3007018416 ps
CPU time 22.84 seconds
Started Aug 23 10:40:53 PM UTC 24
Finished Aug 23 10:41:18 PM UTC 24
Peak memory 227988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155682324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.155682324
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/42.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.1158200430
Short name T872
Test name
Test status
Simulation time 288843587 ps
CPU time 1.75 seconds
Started Aug 23 10:40:53 PM UTC 24
Finished Aug 23 10:40:56 PM UTC 24
Peak memory 227984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158200430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1158200430
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/42.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.2326869906
Short name T871
Test name
Test status
Simulation time 42302230 ps
CPU time 0.79 seconds
Started Aug 23 10:40:53 PM UTC 24
Finished Aug 23 10:40:56 PM UTC 24
Peak memory 215628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326869906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2326869906
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/42.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.1969130
Short name T870
Test name
Test status
Simulation time 49809498 ps
CPU time 0.69 seconds
Started Aug 23 10:40:53 PM UTC 24
Finished Aug 23 10:40:55 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM
_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1969130
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/42.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.3908337327
Short name T881
Test name
Test status
Simulation time 2976408879 ps
CPU time 12.33 seconds
Started Aug 23 10:41:07 PM UTC 24
Finished Aug 23 10:41:20 PM UTC 24
Peak memory 245648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908337327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3908337327
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/42.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.3929175398
Short name T900
Test name
Test status
Simulation time 11228128 ps
CPU time 0.6 seconds
Started Aug 23 10:41:58 PM UTC 24
Finished Aug 23 10:41:59 PM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929175398 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.3929175398
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/43.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.1788508884
Short name T892
Test name
Test status
Simulation time 141530083 ps
CPU time 2.47 seconds
Started Aug 23 10:41:42 PM UTC 24
Finished Aug 23 10:41:46 PM UTC 24
Peak memory 230016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788508884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1788508884
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/43.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.628046775
Short name T885
Test name
Test status
Simulation time 132005678 ps
CPU time 0.68 seconds
Started Aug 23 10:41:24 PM UTC 24
Finished Aug 23 10:41:26 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628046775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.628046775
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/43.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.2606643240
Short name T976
Test name
Test status
Simulation time 10484018756 ps
CPU time 122.46 seconds
Started Aug 23 10:41:49 PM UTC 24
Finished Aug 23 10:43:53 PM UTC 24
Peak memory 276520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606643240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2606643240
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/43.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.4187894883
Short name T938
Test name
Test status
Simulation time 11905801992 ps
CPU time 77.63 seconds
Started Aug 23 10:41:49 PM UTC 24
Finished Aug 23 10:43:08 PM UTC 24
Peak memory 262156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187894883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4187894883
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.975693161
Short name T952
Test name
Test status
Simulation time 8995090004 ps
CPU time 90.12 seconds
Started Aug 23 10:41:50 PM UTC 24
Finished Aug 23 10:43:22 PM UTC 24
Peak memory 264196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975693161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.975693161
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.410080685
Short name T916
Test name
Test status
Simulation time 4376887723 ps
CPU time 40.96 seconds
Started Aug 23 10:41:46 PM UTC 24
Finished Aug 23 10:42:29 PM UTC 24
Peak memory 262092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410080685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.410080685
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/43.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.3548997563
Short name T898
Test name
Test status
Simulation time 922944493 ps
CPU time 9.47 seconds
Started Aug 23 10:41:46 PM UTC 24
Finished Aug 23 10:41:57 PM UTC 24
Peak memory 245516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548997563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.3548997563
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.1437807382
Short name T891
Test name
Test status
Simulation time 509349880 ps
CPU time 5.29 seconds
Started Aug 23 10:41:39 PM UTC 24
Finished Aug 23 10:41:46 PM UTC 24
Peak memory 235368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437807382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1437807382
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/43.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.541237382
Short name T914
Test name
Test status
Simulation time 4624198858 ps
CPU time 44.79 seconds
Started Aug 23 10:41:40 PM UTC 24
Finished Aug 23 10:42:27 PM UTC 24
Peak memory 251876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541237382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.541237382
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/43.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.265379921
Short name T890
Test name
Test status
Simulation time 115302366 ps
CPU time 2.32 seconds
Started Aug 23 10:41:37 PM UTC 24
Finished Aug 23 10:41:41 PM UTC 24
Peak memory 235340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265379921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.265379921
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/43.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.2837991423
Short name T894
Test name
Test status
Simulation time 2515369529 ps
CPU time 9.99 seconds
Started Aug 23 10:41:37 PM UTC 24
Finished Aug 23 10:41:48 PM UTC 24
Peak memory 245708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837991423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2837991423
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/43.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.31159191
Short name T902
Test name
Test status
Simulation time 5799543407 ps
CPU time 11.53 seconds
Started Aug 23 10:41:48 PM UTC 24
Finished Aug 23 10:42:00 PM UTC 24
Peak memory 231796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31159191 -assert nopostproc +UVM_TESTNAME=spi_device_bas
e_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.31159191
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/43.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.400737038
Short name T1022
Test name
Test status
Simulation time 115673373953 ps
CPU time 240.42 seconds
Started Aug 23 10:41:55 PM UTC 24
Finished Aug 23 10:45:58 PM UTC 24
Peak memory 268468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400737038 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.400737038
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/43.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.1574828032
Short name T888
Test name
Test status
Simulation time 5635808668 ps
CPU time 9.37 seconds
Started Aug 23 10:41:26 PM UTC 24
Finished Aug 23 10:41:37 PM UTC 24
Peak memory 228084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574828032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1574828032
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/43.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.655215223
Short name T893
Test name
Test status
Simulation time 33896246435 ps
CPU time 22.18 seconds
Started Aug 23 10:41:24 PM UTC 24
Finished Aug 23 10:41:47 PM UTC 24
Peak memory 229880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655215223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.655215223
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/43.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.974233721
Short name T889
Test name
Test status
Simulation time 43432696 ps
CPU time 1.24 seconds
Started Aug 23 10:41:36 PM UTC 24
Finished Aug 23 10:41:38 PM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974233721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.974233721
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/43.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.963276810
Short name T887
Test name
Test status
Simulation time 308895996 ps
CPU time 0.79 seconds
Started Aug 23 10:41:33 PM UTC 24
Finished Aug 23 10:41:35 PM UTC 24
Peak memory 215924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963276810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.963276810
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/43.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.2989652733
Short name T896
Test name
Test status
Simulation time 1067345429 ps
CPU time 11.5 seconds
Started Aug 23 10:41:41 PM UTC 24
Finished Aug 23 10:41:54 PM UTC 24
Peak memory 245580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989652733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2989652733
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/43.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.3345654317
Short name T917
Test name
Test status
Simulation time 39911558 ps
CPU time 0.59 seconds
Started Aug 23 10:42:28 PM UTC 24
Finished Aug 23 10:42:29 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345654317 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.3345654317
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/44.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.3717315625
Short name T911
Test name
Test status
Simulation time 256001739 ps
CPU time 1.71 seconds
Started Aug 23 10:42:11 PM UTC 24
Finished Aug 23 10:42:14 PM UTC 24
Peak memory 234724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717315625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3717315625
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/44.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.1117380299
Short name T901
Test name
Test status
Simulation time 15303787 ps
CPU time 0.68 seconds
Started Aug 23 10:41:58 PM UTC 24
Finished Aug 23 10:42:00 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117380299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1117380299
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/44.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.3088348988
Short name T935
Test name
Test status
Simulation time 11342599504 ps
CPU time 48.79 seconds
Started Aug 23 10:42:14 PM UTC 24
Finished Aug 23 10:43:05 PM UTC 24
Peak memory 262092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088348988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3088348988
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/44.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1578272507
Short name T933
Test name
Test status
Simulation time 8215472613 ps
CPU time 39.73 seconds
Started Aug 23 10:42:20 PM UTC 24
Finished Aug 23 10:43:01 PM UTC 24
Peak memory 262156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578272507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1578272507
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.1784552768
Short name T1015
Test name
Test status
Simulation time 44279558774 ps
CPU time 134.2 seconds
Started Aug 23 10:42:25 PM UTC 24
Finished Aug 23 10:44:41 PM UTC 24
Peak memory 262148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784552768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.1784552768
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.3645679931
Short name T924
Test name
Test status
Simulation time 2089397116 ps
CPU time 30.68 seconds
Started Aug 23 10:42:12 PM UTC 24
Finished Aug 23 10:42:44 PM UTC 24
Peak memory 245772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645679931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3645679931
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/44.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.498539768
Short name T939
Test name
Test status
Simulation time 15925776997 ps
CPU time 53.29 seconds
Started Aug 23 10:42:13 PM UTC 24
Finished Aug 23 10:43:08 PM UTC 24
Peak memory 251840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498539768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.498539768
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.2013620934
Short name T829
Test name
Test status
Simulation time 83967785 ps
CPU time 2.68 seconds
Started Aug 23 10:42:07 PM UTC 24
Finished Aug 23 10:42:11 PM UTC 24
Peak memory 245548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013620934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2013620934
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/44.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.3770731266
Short name T910
Test name
Test status
Simulation time 552915300 ps
CPU time 4.06 seconds
Started Aug 23 10:42:08 PM UTC 24
Finished Aug 23 10:42:13 PM UTC 24
Peak memory 245868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770731266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3770731266
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/44.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.3753019626
Short name T912
Test name
Test status
Simulation time 14532418936 ps
CPU time 13.27 seconds
Started Aug 23 10:42:04 PM UTC 24
Finished Aug 23 10:42:18 PM UTC 24
Peak memory 235464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753019626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.3753019626
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/44.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.1663474985
Short name T905
Test name
Test status
Simulation time 1353226427 ps
CPU time 3.67 seconds
Started Aug 23 10:42:02 PM UTC 24
Finished Aug 23 10:42:07 PM UTC 24
Peak memory 245800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663474985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1663474985
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/44.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.3276147665
Short name T915
Test name
Test status
Simulation time 1412234501 ps
CPU time 11.59 seconds
Started Aug 23 10:42:14 PM UTC 24
Finished Aug 23 10:42:27 PM UTC 24
Peak memory 231608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276147665 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.3276147665
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/44.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.3114323109
Short name T1017
Test name
Test status
Simulation time 12714778052 ps
CPU time 169.03 seconds
Started Aug 23 10:42:28 PM UTC 24
Finished Aug 23 10:45:19 PM UTC 24
Peak memory 278656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114323109 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.3114323109
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/44.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.4172685037
Short name T913
Test name
Test status
Simulation time 2804642639 ps
CPU time 22.66 seconds
Started Aug 23 10:42:00 PM UTC 24
Finished Aug 23 10:42:24 PM UTC 24
Peak memory 227952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172685037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.4172685037
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/44.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.530835534
Short name T906
Test name
Test status
Simulation time 3976794189 ps
CPU time 6.41 seconds
Started Aug 23 10:42:00 PM UTC 24
Finished Aug 23 10:42:07 PM UTC 24
Peak memory 227916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530835534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.530835534
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/44.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.1011216748
Short name T904
Test name
Test status
Simulation time 57011049 ps
CPU time 1.2 seconds
Started Aug 23 10:42:01 PM UTC 24
Finished Aug 23 10:42:03 PM UTC 24
Peak memory 228024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011216748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1011216748
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/44.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.685905137
Short name T903
Test name
Test status
Simulation time 397469157 ps
CPU time 0.79 seconds
Started Aug 23 10:42:00 PM UTC 24
Finished Aug 23 10:42:02 PM UTC 24
Peak memory 215924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685905137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.685905137
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/44.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.1987266493
Short name T909
Test name
Test status
Simulation time 351159241 ps
CPU time 1.69 seconds
Started Aug 23 10:42:09 PM UTC 24
Finished Aug 23 10:42:12 PM UTC 24
Peak memory 234596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987266493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1987266493
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/44.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.3075363717
Short name T934
Test name
Test status
Simulation time 12719484 ps
CPU time 0.64 seconds
Started Aug 23 10:43:02 PM UTC 24
Finished Aug 23 10:43:03 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075363717 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.3075363717
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/45.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.1304240808
Short name T929
Test name
Test status
Simulation time 764603106 ps
CPU time 3.53 seconds
Started Aug 23 10:42:47 PM UTC 24
Finished Aug 23 10:42:52 PM UTC 24
Peak memory 235340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304240808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1304240808
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/45.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.1089403774
Short name T918
Test name
Test status
Simulation time 26540357 ps
CPU time 0.65 seconds
Started Aug 23 10:42:30 PM UTC 24
Finished Aug 23 10:42:32 PM UTC 24
Peak memory 215688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089403774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1089403774
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/45.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.722287890
Short name T1025
Test name
Test status
Simulation time 51313737732 ps
CPU time 226.07 seconds
Started Aug 23 10:42:56 PM UTC 24
Finished Aug 23 10:46:46 PM UTC 24
Peak memory 262148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722287890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.722287890
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.3153773375
Short name T995
Test name
Test status
Simulation time 7761840351 ps
CPU time 75.38 seconds
Started Aug 23 10:42:58 PM UTC 24
Finished Aug 23 10:44:16 PM UTC 24
Peak memory 266528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153773375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.3153773375
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.776474980
Short name T349
Test name
Test status
Simulation time 22818145759 ps
CPU time 57.27 seconds
Started Aug 23 10:42:50 PM UTC 24
Finished Aug 23 10:43:49 PM UTC 24
Peak memory 245704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776474980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.776474980
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/45.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.2873033361
Short name T928
Test name
Test status
Simulation time 39032219 ps
CPU time 0.77 seconds
Started Aug 23 10:42:50 PM UTC 24
Finished Aug 23 10:42:52 PM UTC 24
Peak memory 225676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873033361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.2873033361
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.992188163
Short name T925
Test name
Test status
Simulation time 1322794341 ps
CPU time 3.89 seconds
Started Aug 23 10:42:41 PM UTC 24
Finished Aug 23 10:42:46 PM UTC 24
Peak memory 235272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992188163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.992188163
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/45.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.2409452371
Short name T931
Test name
Test status
Simulation time 18970820848 ps
CPU time 11.76 seconds
Started Aug 23 10:42:45 PM UTC 24
Finished Aug 23 10:42:58 PM UTC 24
Peak memory 245736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409452371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2409452371
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/45.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.4078149333
Short name T310
Test name
Test status
Simulation time 14662630877 ps
CPU time 10.86 seconds
Started Aug 23 10:42:38 PM UTC 24
Finished Aug 23 10:42:50 PM UTC 24
Peak memory 235468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078149333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.4078149333
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/45.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.1110055833
Short name T948
Test name
Test status
Simulation time 14606620028 ps
CPU time 38.84 seconds
Started Aug 23 10:42:37 PM UTC 24
Finished Aug 23 10:43:17 PM UTC 24
Peak memory 245708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110055833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1110055833
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/45.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.3144125216
Short name T932
Test name
Test status
Simulation time 916146587 ps
CPU time 4.16 seconds
Started Aug 23 10:42:52 PM UTC 24
Finished Aug 23 10:42:58 PM UTC 24
Peak memory 234160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144125216 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.3144125216
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/45.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.2113396988
Short name T332
Test name
Test status
Simulation time 156030817415 ps
CPU time 348.76 seconds
Started Aug 23 10:43:00 PM UTC 24
Finished Aug 23 10:48:53 PM UTC 24
Peak memory 284668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113396988 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.2113396988
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/45.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.2195237553
Short name T927
Test name
Test status
Simulation time 37049432543 ps
CPU time 14.98 seconds
Started Aug 23 10:42:33 PM UTC 24
Finished Aug 23 10:42:49 PM UTC 24
Peak memory 227900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195237553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2195237553
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/45.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.671667599
Short name T919
Test name
Test status
Simulation time 252365592 ps
CPU time 1.95 seconds
Started Aug 23 10:42:30 PM UTC 24
Finished Aug 23 10:42:33 PM UTC 24
Peak memory 226876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671667599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.671667599
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/45.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.2454281704
Short name T923
Test name
Test status
Simulation time 260604501 ps
CPU time 3.39 seconds
Started Aug 23 10:42:36 PM UTC 24
Finished Aug 23 10:42:40 PM UTC 24
Peak memory 227952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454281704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2454281704
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/45.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.789651900
Short name T920
Test name
Test status
Simulation time 28651403 ps
CPU time 0.58 seconds
Started Aug 23 10:42:34 PM UTC 24
Finished Aug 23 10:42:36 PM UTC 24
Peak memory 215800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789651900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.789651900
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/45.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.3090725609
Short name T930
Test name
Test status
Simulation time 442414620 ps
CPU time 7.03 seconds
Started Aug 23 10:42:47 PM UTC 24
Finished Aug 23 10:42:56 PM UTC 24
Peak memory 245580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090725609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3090725609
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/45.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.1726406493
Short name T953
Test name
Test status
Simulation time 12023428 ps
CPU time 0.62 seconds
Started Aug 23 10:43:21 PM UTC 24
Finished Aug 23 10:43:23 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726406493 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.1726406493
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/46.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.3291201988
Short name T955
Test name
Test status
Simulation time 2927125580 ps
CPU time 6.75 seconds
Started Aug 23 10:43:15 PM UTC 24
Finished Aug 23 10:43:23 PM UTC 24
Peak memory 235344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291201988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3291201988
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/46.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.80508070
Short name T936
Test name
Test status
Simulation time 13962016 ps
CPU time 0.65 seconds
Started Aug 23 10:43:04 PM UTC 24
Finished Aug 23 10:43:05 PM UTC 24
Peak memory 215800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80508070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.80508070
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/46.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.1034231158
Short name T1028
Test name
Test status
Simulation time 339774323157 ps
CPU time 364.17 seconds
Started Aug 23 10:43:17 PM UTC 24
Finished Aug 23 10:49:26 PM UTC 24
Peak memory 264328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034231158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1034231158
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/46.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.381801964
Short name T980
Test name
Test status
Simulation time 3763484734 ps
CPU time 37.07 seconds
Started Aug 23 10:43:18 PM UTC 24
Finished Aug 23 10:43:57 PM UTC 24
Peak memory 262348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381801964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.381801964
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/46.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.492922920
Short name T972
Test name
Test status
Simulation time 3012386554 ps
CPU time 29.37 seconds
Started Aug 23 10:43:18 PM UTC 24
Finished Aug 23 10:43:49 PM UTC 24
Peak memory 262180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492922920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.492922920
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.3875423512
Short name T983
Test name
Test status
Simulation time 3277376105 ps
CPU time 42.77 seconds
Started Aug 23 10:43:15 PM UTC 24
Finished Aug 23 10:44:00 PM UTC 24
Peak memory 261732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875423512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3875423512
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/46.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.666598978
Short name T974
Test name
Test status
Simulation time 6999560636 ps
CPU time 34.47 seconds
Started Aug 23 10:43:16 PM UTC 24
Finished Aug 23 10:43:52 PM UTC 24
Peak memory 262092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666598978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.666598978
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.2703302638
Short name T944
Test name
Test status
Simulation time 72266027 ps
CPU time 1.77 seconds
Started Aug 23 10:43:11 PM UTC 24
Finished Aug 23 10:43:14 PM UTC 24
Peak memory 234996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703302638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2703302638
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/46.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.2429381583
Short name T978
Test name
Test status
Simulation time 5000590463 ps
CPU time 40.9 seconds
Started Aug 23 10:43:12 PM UTC 24
Finished Aug 23 10:43:55 PM UTC 24
Peak memory 245772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429381583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2429381583
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/46.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.2589953235
Short name T947
Test name
Test status
Simulation time 1922574804 ps
CPU time 4.84 seconds
Started Aug 23 10:43:10 PM UTC 24
Finished Aug 23 10:43:16 PM UTC 24
Peak memory 235592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589953235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.2589953235
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/46.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.666236079
Short name T945
Test name
Test status
Simulation time 1400827974 ps
CPU time 5.25 seconds
Started Aug 23 10:43:09 PM UTC 24
Finished Aug 23 10:43:16 PM UTC 24
Peak memory 235288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666236079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.666236079
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/46.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.3704855869
Short name T957
Test name
Test status
Simulation time 1258309598 ps
CPU time 7.64 seconds
Started Aug 23 10:43:17 PM UTC 24
Finished Aug 23 10:43:26 PM UTC 24
Peak memory 234056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704855869 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.3704855869
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/46.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.3277639550
Short name T954
Test name
Test status
Simulation time 188821172 ps
CPU time 0.84 seconds
Started Aug 23 10:43:21 PM UTC 24
Finished Aug 23 10:43:23 PM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277639550 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.3277639550
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/46.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.557610849
Short name T937
Test name
Test status
Simulation time 22722885 ps
CPU time 0.66 seconds
Started Aug 23 10:43:06 PM UTC 24
Finished Aug 23 10:43:07 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557610849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.557610849
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/46.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.1259668726
Short name T940
Test name
Test status
Simulation time 1097333293 ps
CPU time 2.04 seconds
Started Aug 23 10:43:06 PM UTC 24
Finished Aug 23 10:43:09 PM UTC 24
Peak memory 227488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259668726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1259668726
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/46.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.3554766884
Short name T942
Test name
Test status
Simulation time 45917515 ps
CPU time 0.67 seconds
Started Aug 23 10:43:09 PM UTC 24
Finished Aug 23 10:43:11 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554766884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3554766884
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/46.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.4231654152
Short name T941
Test name
Test status
Simulation time 60554695 ps
CPU time 0.7 seconds
Started Aug 23 10:43:08 PM UTC 24
Finished Aug 23 10:43:10 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231654152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.4231654152
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/46.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.1212346184
Short name T960
Test name
Test status
Simulation time 6973922528 ps
CPU time 16.61 seconds
Started Aug 23 10:43:12 PM UTC 24
Finished Aug 23 10:43:30 PM UTC 24
Peak memory 245708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212346184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1212346184
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/46.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.3074224318
Short name T971
Test name
Test status
Simulation time 14112292 ps
CPU time 0.61 seconds
Started Aug 23 10:43:47 PM UTC 24
Finished Aug 23 10:43:49 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074224318 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.3074224318
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/47.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.46072450
Short name T968
Test name
Test status
Simulation time 14077830687 ps
CPU time 8.81 seconds
Started Aug 23 10:43:34 PM UTC 24
Finished Aug 23 10:43:44 PM UTC 24
Peak memory 235384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46072450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.46072450
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/47.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.895650184
Short name T956
Test name
Test status
Simulation time 53844785 ps
CPU time 0.65 seconds
Started Aug 23 10:43:23 PM UTC 24
Finished Aug 23 10:43:24 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895650184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.895650184
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/47.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.2706914553
Short name T1021
Test name
Test status
Simulation time 20250611874 ps
CPU time 133.22 seconds
Started Aug 23 10:43:39 PM UTC 24
Finished Aug 23 10:45:55 PM UTC 24
Peak memory 262284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706914553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2706914553
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/47.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3778142925
Short name T997
Test name
Test status
Simulation time 3857148162 ps
CPU time 31.51 seconds
Started Aug 23 10:43:44 PM UTC 24
Finished Aug 23 10:44:17 PM UTC 24
Peak memory 245796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778142925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3778142925
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.3239654104
Short name T76
Test name
Test status
Simulation time 7429088256 ps
CPU time 126.78 seconds
Started Aug 23 10:43:45 PM UTC 24
Finished Aug 23 10:45:54 PM UTC 24
Peak memory 284704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239654104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.3239654104
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.3558834865
Short name T969
Test name
Test status
Simulation time 553184901 ps
CPU time 7.9 seconds
Started Aug 23 10:43:35 PM UTC 24
Finished Aug 23 10:43:44 PM UTC 24
Peak memory 249680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558834865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3558834865
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/47.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.1806773721
Short name T998
Test name
Test status
Simulation time 64278456253 ps
CPU time 40.67 seconds
Started Aug 23 10:43:37 PM UTC 24
Finished Aug 23 10:44:19 PM UTC 24
Peak memory 262084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806773721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.1806773721
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.3541630999
Short name T964
Test name
Test status
Simulation time 1555579692 ps
CPU time 4.1 seconds
Started Aug 23 10:43:31 PM UTC 24
Finished Aug 23 10:43:36 PM UTC 24
Peak memory 235536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541630999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3541630999
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/47.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.1086444016
Short name T963
Test name
Test status
Simulation time 718554769 ps
CPU time 1.9 seconds
Started Aug 23 10:43:31 PM UTC 24
Finished Aug 23 10:43:34 PM UTC 24
Peak memory 234988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086444016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1086444016
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/47.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.1721038124
Short name T965
Test name
Test status
Simulation time 2835860400 ps
CPU time 8.35 seconds
Started Aug 23 10:43:27 PM UTC 24
Finished Aug 23 10:43:36 PM UTC 24
Peak memory 235404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721038124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.1721038124
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/47.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.4144356326
Short name T970
Test name
Test status
Simulation time 5882891017 ps
CPU time 18.62 seconds
Started Aug 23 10:43:27 PM UTC 24
Finished Aug 23 10:43:47 PM UTC 24
Peak memory 245712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144356326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.4144356326
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/47.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.519880814
Short name T967
Test name
Test status
Simulation time 973413428 ps
CPU time 4.98 seconds
Started Aug 23 10:43:37 PM UTC 24
Finished Aug 23 10:43:43 PM UTC 24
Peak memory 234192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519880814 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.519880814
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/47.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.1797034867
Short name T1016
Test name
Test status
Simulation time 5925132986 ps
CPU time 88.35 seconds
Started Aug 23 10:43:45 PM UTC 24
Finished Aug 23 10:45:15 PM UTC 24
Peak memory 278564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797034867 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.1797034867
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/47.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.1887974109
Short name T961
Test name
Test status
Simulation time 7351862108 ps
CPU time 7.8 seconds
Started Aug 23 10:43:24 PM UTC 24
Finished Aug 23 10:43:32 PM UTC 24
Peak memory 227896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887974109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1887974109
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/47.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.68173569
Short name T962
Test name
Test status
Simulation time 3216482755 ps
CPU time 8.65 seconds
Started Aug 23 10:43:24 PM UTC 24
Finished Aug 23 10:43:33 PM UTC 24
Peak memory 227888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68173569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.68173569
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/47.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.2448716213
Short name T959
Test name
Test status
Simulation time 177194012 ps
CPU time 3.84 seconds
Started Aug 23 10:43:25 PM UTC 24
Finished Aug 23 10:43:30 PM UTC 24
Peak memory 227824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448716213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2448716213
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/47.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.2252879963
Short name T958
Test name
Test status
Simulation time 54368874 ps
CPU time 0.8 seconds
Started Aug 23 10:43:25 PM UTC 24
Finished Aug 23 10:43:26 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252879963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2252879963
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/47.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.3994399502
Short name T966
Test name
Test status
Simulation time 589429063 ps
CPU time 4.68 seconds
Started Aug 23 10:43:33 PM UTC 24
Finished Aug 23 10:43:39 PM UTC 24
Peak memory 245548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994399502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3994399502
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/47.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.4079236355
Short name T991
Test name
Test status
Simulation time 13042619 ps
CPU time 0.62 seconds
Started Aug 23 10:44:10 PM UTC 24
Finished Aug 23 10:44:12 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079236355 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.4079236355
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/48.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.1414251199
Short name T984
Test name
Test status
Simulation time 137565343 ps
CPU time 2.3 seconds
Started Aug 23 10:43:58 PM UTC 24
Finished Aug 23 10:44:01 PM UTC 24
Peak memory 245580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414251199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1414251199
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/48.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.269543358
Short name T973
Test name
Test status
Simulation time 19894672 ps
CPU time 0.68 seconds
Started Aug 23 10:43:49 PM UTC 24
Finished Aug 23 10:43:51 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269543358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.269543358
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/48.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.2406743289
Short name T1000
Test name
Test status
Simulation time 2214824594 ps
CPU time 17.98 seconds
Started Aug 23 10:44:02 PM UTC 24
Finished Aug 23 10:44:21 PM UTC 24
Peak memory 251848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406743289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2406743289
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/48.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.2003067936
Short name T1019
Test name
Test status
Simulation time 5578481755 ps
CPU time 75.28 seconds
Started Aug 23 10:44:07 PM UTC 24
Finished Aug 23 10:45:24 PM UTC 24
Peak memory 262144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003067936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2003067936
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.493234693
Short name T1024
Test name
Test status
Simulation time 69400482302 ps
CPU time 149.97 seconds
Started Aug 23 10:44:08 PM UTC 24
Finished Aug 23 10:46:41 PM UTC 24
Peak memory 268320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493234693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.493234693
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.664446650
Short name T987
Test name
Test status
Simulation time 2260675055 ps
CPU time 9.34 seconds
Started Aug 23 10:43:59 PM UTC 24
Finished Aug 23 10:44:09 PM UTC 24
Peak memory 235404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664446650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.664446650
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/48.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.3250500665
Short name T1001
Test name
Test status
Simulation time 6739326600 ps
CPU time 19.32 seconds
Started Aug 23 10:44:01 PM UTC 24
Finished Aug 23 10:44:22 PM UTC 24
Peak memory 262152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250500665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.3250500665
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.2845035245
Short name T985
Test name
Test status
Simulation time 2426052260 ps
CPU time 11.25 seconds
Started Aug 23 10:43:55 PM UTC 24
Finished Aug 23 10:44:07 PM UTC 24
Peak memory 245900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845035245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2845035245
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/48.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.1520276038
Short name T1011
Test name
Test status
Simulation time 15670878974 ps
CPU time 38.28 seconds
Started Aug 23 10:43:56 PM UTC 24
Finished Aug 23 10:44:35 PM UTC 24
Peak memory 251820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520276038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1520276038
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/48.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.2233261976
Short name T981
Test name
Test status
Simulation time 1008923260 ps
CPU time 3.17 seconds
Started Aug 23 10:43:54 PM UTC 24
Finished Aug 23 10:43:58 PM UTC 24
Peak memory 235324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233261976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.2233261976
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/48.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2291027271
Short name T982
Test name
Test status
Simulation time 3180428718 ps
CPU time 5.06 seconds
Started Aug 23 10:43:54 PM UTC 24
Finished Aug 23 10:44:00 PM UTC 24
Peak memory 235404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291027271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2291027271
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/48.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.1970272472
Short name T989
Test name
Test status
Simulation time 7176147658 ps
CPU time 8.2 seconds
Started Aug 23 10:44:01 PM UTC 24
Finished Aug 23 10:44:10 PM UTC 24
Peak memory 233812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970272472 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.1970272472
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/48.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.524783020
Short name T988
Test name
Test status
Simulation time 33748328 ps
CPU time 0.78 seconds
Started Aug 23 10:44:08 PM UTC 24
Finished Aug 23 10:44:10 PM UTC 24
Peak memory 216268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524783020 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.524783020
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/48.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.689586754
Short name T990
Test name
Test status
Simulation time 3055652997 ps
CPU time 20.43 seconds
Started Aug 23 10:43:49 PM UTC 24
Finished Aug 23 10:44:11 PM UTC 24
Peak memory 232024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689586754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.689586754
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/48.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.4113517634
Short name T977
Test name
Test status
Simulation time 2362617366 ps
CPU time 3.82 seconds
Started Aug 23 10:43:49 PM UTC 24
Finished Aug 23 10:43:54 PM UTC 24
Peak memory 227828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113517634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.4113517634
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/48.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.1217740551
Short name T979
Test name
Test status
Simulation time 76894888 ps
CPU time 2.45 seconds
Started Aug 23 10:43:53 PM UTC 24
Finished Aug 23 10:43:56 PM UTC 24
Peak memory 227804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217740551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1217740551
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/48.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.2793306242
Short name T975
Test name
Test status
Simulation time 54886558 ps
CPU time 0.72 seconds
Started Aug 23 10:43:52 PM UTC 24
Finished Aug 23 10:43:53 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793306242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2793306242
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/48.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.1328135205
Short name T986
Test name
Test status
Simulation time 1197565144 ps
CPU time 9.22 seconds
Started Aug 23 10:43:57 PM UTC 24
Finished Aug 23 10:44:07 PM UTC 24
Peak memory 235340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328135205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1328135205
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/48.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.3446762329
Short name T1008
Test name
Test status
Simulation time 30480631 ps
CPU time 0.61 seconds
Started Aug 23 10:44:31 PM UTC 24
Finished Aug 23 10:44:33 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446762329 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.3446762329
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/49.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.733023318
Short name T1002
Test name
Test status
Simulation time 113489693 ps
CPU time 2.11 seconds
Started Aug 23 10:44:20 PM UTC 24
Finished Aug 23 10:44:23 PM UTC 24
Peak memory 245644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733023318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.733023318
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/49.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.2435167750
Short name T992
Test name
Test status
Simulation time 59904600 ps
CPU time 0.66 seconds
Started Aug 23 10:44:11 PM UTC 24
Finished Aug 23 10:44:13 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435167750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2435167750
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/49.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.221926114
Short name T324
Test name
Test status
Simulation time 54786780616 ps
CPU time 376.45 seconds
Started Aug 23 10:44:24 PM UTC 24
Finished Aug 23 10:50:45 PM UTC 24
Peak memory 282572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221926114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.221926114
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/49.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.3046251502
Short name T1013
Test name
Test status
Simulation time 5810528967 ps
CPU time 7.75 seconds
Started Aug 23 10:44:28 PM UTC 24
Finished Aug 23 10:44:37 PM UTC 24
Peak memory 235472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046251502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3046251502
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.501192552
Short name T1020
Test name
Test status
Simulation time 14989122320 ps
CPU time 68.02 seconds
Started Aug 23 10:44:28 PM UTC 24
Finished Aug 23 10:45:38 PM UTC 24
Peak memory 266508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501192552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.501192552
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.3525092601
Short name T1010
Test name
Test status
Simulation time 2518086891 ps
CPU time 12.14 seconds
Started Aug 23 10:44:21 PM UTC 24
Finished Aug 23 10:44:34 PM UTC 24
Peak memory 247752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525092601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3525092601
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/49.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.3542544351
Short name T1014
Test name
Test status
Simulation time 3281254888 ps
CPU time 17.1 seconds
Started Aug 23 10:44:22 PM UTC 24
Finished Aug 23 10:44:40 PM UTC 24
Peak memory 251876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542544351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.3542544351
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.1588721187
Short name T1004
Test name
Test status
Simulation time 2343970382 ps
CPU time 9.47 seconds
Started Aug 23 10:44:17 PM UTC 24
Finished Aug 23 10:44:27 PM UTC 24
Peak memory 235472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588721187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1588721187
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/49.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.1652942785
Short name T1005
Test name
Test status
Simulation time 674216859 ps
CPU time 11.29 seconds
Started Aug 23 10:44:17 PM UTC 24
Finished Aug 23 10:44:29 PM UTC 24
Peak memory 245520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652942785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1652942785
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/49.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.98043178
Short name T1003
Test name
Test status
Simulation time 2263922850 ps
CPU time 11.46 seconds
Started Aug 23 10:44:15 PM UTC 24
Finished Aug 23 10:44:27 PM UTC 24
Peak memory 251860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98043178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.98043178
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/49.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.2546114738
Short name T999
Test name
Test status
Simulation time 1668140473 ps
CPU time 4.04 seconds
Started Aug 23 10:44:15 PM UTC 24
Finished Aug 23 10:44:20 PM UTC 24
Peak memory 235344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546114738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2546114738
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/49.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.69103117
Short name T1007
Test name
Test status
Simulation time 3069868070 ps
CPU time 8.55 seconds
Started Aug 23 10:44:22 PM UTC 24
Finished Aug 23 10:44:31 PM UTC 24
Peak memory 231740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69103117 -assert nopostproc +UVM_TESTNAME=spi_device_bas
e_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.69103117
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/49.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.388168401
Short name T1027
Test name
Test status
Simulation time 28003062978 ps
CPU time 213.39 seconds
Started Aug 23 10:44:30 PM UTC 24
Finished Aug 23 10:48:07 PM UTC 24
Peak memory 264200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388168401 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.388168401
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/49.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.3009037842
Short name T1006
Test name
Test status
Simulation time 9454308693 ps
CPU time 16.8 seconds
Started Aug 23 10:44:12 PM UTC 24
Finished Aug 23 10:44:30 PM UTC 24
Peak memory 227980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009037842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3009037842
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/49.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.456276318
Short name T993
Test name
Test status
Simulation time 157379514 ps
CPU time 1.01 seconds
Started Aug 23 10:44:11 PM UTC 24
Finished Aug 23 10:44:13 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456276318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.456276318
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/49.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.755210385
Short name T996
Test name
Test status
Simulation time 94460897 ps
CPU time 1.44 seconds
Started Aug 23 10:44:13 PM UTC 24
Finished Aug 23 10:44:16 PM UTC 24
Peak memory 228084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755210385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.755210385
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/49.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.3750799577
Short name T994
Test name
Test status
Simulation time 39061125 ps
CPU time 0.68 seconds
Started Aug 23 10:44:12 PM UTC 24
Finished Aug 23 10:44:14 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750799577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3750799577
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/49.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.4127938545
Short name T1009
Test name
Test status
Simulation time 31774927776 ps
CPU time 14.54 seconds
Started Aug 23 10:44:18 PM UTC 24
Finished Aug 23 10:44:33 PM UTC 24
Peak memory 245728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127938545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.4127938545
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/49.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.416227207
Short name T382
Test name
Test status
Simulation time 39081460 ps
CPU time 0.65 seconds
Started Aug 23 10:23:35 PM UTC 24
Finished Aug 23 10:23:37 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416227207 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.416227207
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.1981348965
Short name T265
Test name
Test status
Simulation time 59731534 ps
CPU time 1.96 seconds
Started Aug 23 10:23:25 PM UTC 24
Finished Aug 23 10:23:28 PM UTC 24
Peak memory 244844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981348965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1981348965
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.3990173946
Short name T378
Test name
Test status
Simulation time 45725655 ps
CPU time 0.69 seconds
Started Aug 23 10:23:13 PM UTC 24
Finished Aug 23 10:23:15 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990173946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3990173946
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.1179440640
Short name T189
Test name
Test status
Simulation time 27224241964 ps
CPU time 169.6 seconds
Started Aug 23 10:23:29 PM UTC 24
Finished Aug 23 10:26:21 PM UTC 24
Peak memory 262352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179440640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1179440640
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.2898012368
Short name T89
Test name
Test status
Simulation time 8841848374 ps
CPU time 38.91 seconds
Started Aug 23 10:23:30 PM UTC 24
Finished Aug 23 10:24:10 PM UTC 24
Peak memory 245768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898012368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2898012368
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.1326185525
Short name T185
Test name
Test status
Simulation time 3843925918 ps
CPU time 55.22 seconds
Started Aug 23 10:23:33 PM UTC 24
Finished Aug 23 10:24:30 PM UTC 24
Peak memory 262152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326185525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.1326185525
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.2446855129
Short name T170
Test name
Test status
Simulation time 2745855582 ps
CPU time 14.97 seconds
Started Aug 23 10:23:25 PM UTC 24
Finished Aug 23 10:23:41 PM UTC 24
Peak memory 251876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446855129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2446855129
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.472681670
Short name T251
Test name
Test status
Simulation time 116613270060 ps
CPU time 358.63 seconds
Started Aug 23 10:23:26 PM UTC 24
Finished Aug 23 10:29:29 PM UTC 24
Peak memory 268232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472681670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.472681670
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.191945968
Short name T90
Test name
Test status
Simulation time 5938738335 ps
CPU time 12.27 seconds
Started Aug 23 10:23:21 PM UTC 24
Finished Aug 23 10:23:34 PM UTC 24
Peak memory 245732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191945968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.191945968
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.697830335
Short name T287
Test name
Test status
Simulation time 171660776 ps
CPU time 4.07 seconds
Started Aug 23 10:23:24 PM UTC 24
Finished Aug 23 10:23:29 PM UTC 24
Peak memory 249640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697830335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.697830335
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.1227298861
Short name T379
Test name
Test status
Simulation time 35270857 ps
CPU time 0.95 seconds
Started Aug 23 10:23:13 PM UTC 24
Finished Aug 23 10:23:15 PM UTC 24
Peak memory 229148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227298861 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mem_parity.1227298861
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.384791398
Short name T297
Test name
Test status
Simulation time 2892757546 ps
CPU time 15.13 seconds
Started Aug 23 10:23:21 PM UTC 24
Finished Aug 23 10:23:37 PM UTC 24
Peak memory 245652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384791398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.384791398
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.675243350
Short name T270
Test name
Test status
Simulation time 1856922515 ps
CPU time 2.97 seconds
Started Aug 23 10:23:20 PM UTC 24
Finished Aug 23 10:23:24 PM UTC 24
Peak memory 245612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675243350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.675243350
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.2221883132
Short name T169
Test name
Test status
Simulation time 1891736824 ps
CPU time 7.89 seconds
Started Aug 23 10:23:26 PM UTC 24
Finished Aug 23 10:23:35 PM UTC 24
Peak memory 233704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221883132 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.2221883132
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.411217649
Short name T70
Test name
Test status
Simulation time 1020738494 ps
CPU time 6.96 seconds
Started Aug 23 10:23:15 PM UTC 24
Finished Aug 23 10:23:23 PM UTC 24
Peak memory 227828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411217649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.411217649
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.1673795214
Short name T380
Test name
Test status
Simulation time 1530688564 ps
CPU time 2.51 seconds
Started Aug 23 10:23:15 PM UTC 24
Finished Aug 23 10:23:19 PM UTC 24
Peak memory 227700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673795214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1673795214
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.560735979
Short name T372
Test name
Test status
Simulation time 672689706 ps
CPU time 5.92 seconds
Started Aug 23 10:23:18 PM UTC 24
Finished Aug 23 10:23:24 PM UTC 24
Peak memory 227804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560735979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.560735979
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.80562119
Short name T381
Test name
Test status
Simulation time 153630925 ps
CPU time 0.96 seconds
Started Aug 23 10:23:17 PM UTC 24
Finished Aug 23 10:23:19 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80562119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.80562119
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.3525443971
Short name T87
Test name
Test status
Simulation time 5457208273 ps
CPU time 7.13 seconds
Started Aug 23 10:23:25 PM UTC 24
Finished Aug 23 10:23:33 PM UTC 24
Peak memory 235356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525443971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3525443971
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/5.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.3385678355
Short name T388
Test name
Test status
Simulation time 47409840 ps
CPU time 0.62 seconds
Started Aug 23 10:24:11 PM UTC 24
Finished Aug 23 10:24:13 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385678355 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3385678355
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.3762766522
Short name T112
Test name
Test status
Simulation time 397462747 ps
CPU time 4.97 seconds
Started Aug 23 10:23:49 PM UTC 24
Finished Aug 23 10:23:55 PM UTC 24
Peak memory 235280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762766522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3762766522
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.4284239590
Short name T383
Test name
Test status
Simulation time 53029882 ps
CPU time 0.66 seconds
Started Aug 23 10:23:35 PM UTC 24
Finished Aug 23 10:23:37 PM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284239590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.4284239590
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.2149338038
Short name T225
Test name
Test status
Simulation time 112115179057 ps
CPU time 185 seconds
Started Aug 23 10:23:56 PM UTC 24
Finished Aug 23 10:27:04 PM UTC 24
Peak memory 262288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149338038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2149338038
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.2660351000
Short name T353
Test name
Test status
Simulation time 1575993051 ps
CPU time 18.46 seconds
Started Aug 23 10:24:01 PM UTC 24
Finished Aug 23 10:24:21 PM UTC 24
Peak memory 229944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660351000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2660351000
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.12714873
Short name T208
Test name
Test status
Simulation time 24683680812 ps
CPU time 209.61 seconds
Started Aug 23 10:24:07 PM UTC 24
Finished Aug 23 10:27:40 PM UTC 24
Peak memory 278544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12714873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.12714873
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.713569335
Short name T207
Test name
Test status
Simulation time 3127627051 ps
CPU time 15.44 seconds
Started Aug 23 10:23:50 PM UTC 24
Finished Aug 23 10:24:07 PM UTC 24
Peak memory 235468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713569335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.713569335
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.1540839938
Short name T186
Test name
Test status
Simulation time 4517199070 ps
CPU time 55.68 seconds
Started Aug 23 10:23:54 PM UTC 24
Finished Aug 23 10:24:51 PM UTC 24
Peak memory 264332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540839938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.1540839938
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.1347319969
Short name T219
Test name
Test status
Simulation time 17573797442 ps
CPU time 27.04 seconds
Started Aug 23 10:23:41 PM UTC 24
Finished Aug 23 10:24:10 PM UTC 24
Peak memory 235500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347319969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1347319969
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.180969361
Short name T261
Test name
Test status
Simulation time 399202303 ps
CPU time 5.95 seconds
Started Aug 23 10:23:42 PM UTC 24
Finished Aug 23 10:23:49 PM UTC 24
Peak memory 245576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180969361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.180969361
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.1969477590
Short name T384
Test name
Test status
Simulation time 26709959 ps
CPU time 0.93 seconds
Started Aug 23 10:23:35 PM UTC 24
Finished Aug 23 10:23:37 PM UTC 24
Peak memory 229148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969477590 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mem_parity.1969477590
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.444224025
Short name T291
Test name
Test status
Simulation time 726830339 ps
CPU time 5.3 seconds
Started Aug 23 10:23:41 PM UTC 24
Finished Aug 23 10:23:48 PM UTC 24
Peak memory 235340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444224025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.444224025
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.4186148596
Short name T232
Test name
Test status
Simulation time 3841463422 ps
CPU time 6.66 seconds
Started Aug 23 10:23:40 PM UTC 24
Finished Aug 23 10:23:48 PM UTC 24
Peak memory 245736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186148596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.4186148596
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.531780696
Short name T387
Test name
Test status
Simulation time 303390294 ps
CPU time 3.03 seconds
Started Aug 23 10:23:56 PM UTC 24
Finished Aug 23 10:24:00 PM UTC 24
Peak memory 233748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531780696 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.531780696
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.2690867992
Short name T156
Test name
Test status
Simulation time 6550504210 ps
CPU time 69.35 seconds
Started Aug 23 10:24:09 PM UTC 24
Finished Aug 23 10:25:20 PM UTC 24
Peak memory 268384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690867992 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.2690867992
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.3481640900
Short name T386
Test name
Test status
Simulation time 325905855 ps
CPU time 2.37 seconds
Started Aug 23 10:23:37 PM UTC 24
Finished Aug 23 10:23:41 PM UTC 24
Peak memory 227536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481640900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3481640900
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.827368759
Short name T370
Test name
Test status
Simulation time 57136535 ps
CPU time 1.35 seconds
Started Aug 23 10:23:38 PM UTC 24
Finished Aug 23 10:23:41 PM UTC 24
Peak memory 226928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827368759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.827368759
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.1208550181
Short name T385
Test name
Test status
Simulation time 23686402 ps
CPU time 0.65 seconds
Started Aug 23 10:23:37 PM UTC 24
Finished Aug 23 10:23:39 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208550181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1208550181
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.2224173502
Short name T242
Test name
Test status
Simulation time 2025619977 ps
CPU time 5.37 seconds
Started Aug 23 10:23:49 PM UTC 24
Finished Aug 23 10:23:55 PM UTC 24
Peak memory 251748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224173502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2224173502
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/6.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.3704055572
Short name T394
Test name
Test status
Simulation time 15486118 ps
CPU time 0.64 seconds
Started Aug 23 10:24:43 PM UTC 24
Finished Aug 23 10:24:44 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704055572 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3704055572
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.2282489636
Short name T266
Test name
Test status
Simulation time 46805582 ps
CPU time 2.07 seconds
Started Aug 23 10:24:26 PM UTC 24
Finished Aug 23 10:24:30 PM UTC 24
Peak memory 235280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282489636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2282489636
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.1724609523
Short name T389
Test name
Test status
Simulation time 55631723 ps
CPU time 0.67 seconds
Started Aug 23 10:24:11 PM UTC 24
Finished Aug 23 10:24:13 PM UTC 24
Peak memory 215800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724609523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1724609523
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.1404358244
Short name T257
Test name
Test status
Simulation time 15709991712 ps
CPU time 111.01 seconds
Started Aug 23 10:24:34 PM UTC 24
Finished Aug 23 10:26:27 PM UTC 24
Peak memory 266192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404358244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1404358244
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.2393775254
Short name T241
Test name
Test status
Simulation time 8448310918 ps
CPU time 26.96 seconds
Started Aug 23 10:24:37 PM UTC 24
Finished Aug 23 10:25:05 PM UTC 24
Peak memory 245964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393775254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2393775254
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.2811284208
Short name T399
Test name
Test status
Simulation time 20090205366 ps
CPU time 29.95 seconds
Started Aug 23 10:24:29 PM UTC 24
Finished Aug 23 10:25:00 PM UTC 24
Peak memory 245828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811284208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2811284208
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.3595595807
Short name T48
Test name
Test status
Simulation time 1850213890 ps
CPU time 3.42 seconds
Started Aug 23 10:24:21 PM UTC 24
Finished Aug 23 10:24:26 PM UTC 24
Peak memory 245544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595595807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3595595807
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.2214925775
Short name T290
Test name
Test status
Simulation time 420264507 ps
CPU time 5.41 seconds
Started Aug 23 10:24:21 PM UTC 24
Finished Aug 23 10:24:28 PM UTC 24
Peak memory 235340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214925775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2214925775
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.717240555
Short name T390
Test name
Test status
Simulation time 62193078 ps
CPU time 0.84 seconds
Started Aug 23 10:24:13 PM UTC 24
Finished Aug 23 10:24:15 PM UTC 24
Peak memory 229204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717240555 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mem_parity.717240555
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3872646046
Short name T215
Test name
Test status
Simulation time 4066284907 ps
CPU time 14.5 seconds
Started Aug 23 10:24:20 PM UTC 24
Finished Aug 23 10:24:36 PM UTC 24
Peak memory 245736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872646046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.3872646046
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.1651830913
Short name T278
Test name
Test status
Simulation time 579356052 ps
CPU time 3.32 seconds
Started Aug 23 10:24:19 PM UTC 24
Finished Aug 23 10:24:24 PM UTC 24
Peak memory 245580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651830913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1651830913
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3562010863
Short name T393
Test name
Test status
Simulation time 601764589 ps
CPU time 3.76 seconds
Started Aug 23 10:24:31 PM UTC 24
Finished Aug 23 10:24:36 PM UTC 24
Peak memory 231604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562010863 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.3562010863
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.932196969
Short name T350
Test name
Test status
Simulation time 15222299370 ps
CPU time 39.76 seconds
Started Aug 23 10:24:16 PM UTC 24
Finished Aug 23 10:24:57 PM UTC 24
Peak memory 227896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932196969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.932196969
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1760776166
Short name T391
Test name
Test status
Simulation time 292289640 ps
CPU time 2.75 seconds
Started Aug 23 10:24:13 PM UTC 24
Finished Aug 23 10:24:17 PM UTC 24
Peak memory 227700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760776166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1760776166
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.3882320406
Short name T364
Test name
Test status
Simulation time 156381262 ps
CPU time 1.43 seconds
Started Aug 23 10:24:18 PM UTC 24
Finished Aug 23 10:24:21 PM UTC 24
Peak memory 226984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882320406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3882320406
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.2744826712
Short name T392
Test name
Test status
Simulation time 106862670 ps
CPU time 0.83 seconds
Started Aug 23 10:24:17 PM UTC 24
Finished Aug 23 10:24:19 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744826712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2744826712
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.2244410874
Short name T309
Test name
Test status
Simulation time 1670866647 ps
CPU time 7.08 seconds
Started Aug 23 10:24:24 PM UTC 24
Finished Aug 23 10:24:33 PM UTC 24
Peak memory 245512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244410874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2244410874
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/7.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.4202610504
Short name T400
Test name
Test status
Simulation time 25734500 ps
CPU time 0.61 seconds
Started Aug 23 10:25:13 PM UTC 24
Finished Aug 23 10:25:14 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202610504 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.4202610504
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.2192987729
Short name T271
Test name
Test status
Simulation time 274721376 ps
CPU time 4.1 seconds
Started Aug 23 10:25:02 PM UTC 24
Finished Aug 23 10:25:08 PM UTC 24
Peak memory 235280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192987729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2192987729
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.2483087563
Short name T395
Test name
Test status
Simulation time 55013709 ps
CPU time 0.64 seconds
Started Aug 23 10:24:45 PM UTC 24
Finished Aug 23 10:24:47 PM UTC 24
Peak memory 215800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483087563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2483087563
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.644959810
Short name T77
Test name
Test status
Simulation time 45811811190 ps
CPU time 86.62 seconds
Started Aug 23 10:25:10 PM UTC 24
Finished Aug 23 10:26:38 PM UTC 24
Peak memory 262116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644959810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.644959810
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.1066225055
Short name T240
Test name
Test status
Simulation time 41225232652 ps
CPU time 316.92 seconds
Started Aug 23 10:25:10 PM UTC 24
Finished Aug 23 10:30:30 PM UTC 24
Peak memory 274464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066225055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1066225055
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2590912800
Short name T411
Test name
Test status
Simulation time 7063751600 ps
CPU time 54.58 seconds
Started Aug 23 10:25:12 PM UTC 24
Finished Aug 23 10:26:08 PM UTC 24
Peak memory 252100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590912800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.2590912800
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.688236121
Short name T248
Test name
Test status
Simulation time 647726317 ps
CPU time 8.37 seconds
Started Aug 23 10:25:03 PM UTC 24
Finished Aug 23 10:25:13 PM UTC 24
Peak memory 247652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688236121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.688236121
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2040184624
Short name T80
Test name
Test status
Simulation time 8090955819 ps
CPU time 92.5 seconds
Started Aug 23 10:25:05 PM UTC 24
Finished Aug 23 10:26:40 PM UTC 24
Peak memory 266188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040184624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.2040184624
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.67676398
Short name T231
Test name
Test status
Simulation time 55186344 ps
CPU time 2.05 seconds
Started Aug 23 10:24:58 PM UTC 24
Finished Aug 23 10:25:01 PM UTC 24
Peak memory 245780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67676398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.67676398
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.2970823569
Short name T212
Test name
Test status
Simulation time 30478010846 ps
CPU time 90.59 seconds
Started Aug 23 10:25:00 PM UTC 24
Finished Aug 23 10:26:33 PM UTC 24
Peak memory 262092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970823569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2970823569
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.61726810
Short name T396
Test name
Test status
Simulation time 14529466 ps
CPU time 0.87 seconds
Started Aug 23 10:24:47 PM UTC 24
Finished Aug 23 10:24:49 PM UTC 24
Peak memory 229204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61726810 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mem_parity.61726810
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.2741323181
Short name T235
Test name
Test status
Simulation time 139628673 ps
CPU time 3.02 seconds
Started Aug 23 10:24:57 PM UTC 24
Finished Aug 23 10:25:01 PM UTC 24
Peak memory 235280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741323181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.2741323181
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.1603597447
Short name T243
Test name
Test status
Simulation time 3999915218 ps
CPU time 6.99 seconds
Started Aug 23 10:24:55 PM UTC 24
Finished Aug 23 10:25:03 PM UTC 24
Peak memory 245800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603597447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1603597447
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.424268696
Short name T162
Test name
Test status
Simulation time 1515081609 ps
CPU time 17.58 seconds
Started Aug 23 10:25:09 PM UTC 24
Finished Aug 23 10:25:28 PM UTC 24
Peak memory 231672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424268696 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.424268696
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.2627974463
Short name T159
Test name
Test status
Simulation time 25886788406 ps
CPU time 31.24 seconds
Started Aug 23 10:24:52 PM UTC 24
Finished Aug 23 10:25:24 PM UTC 24
Peak memory 228088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627974463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2627974463
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.2518655742
Short name T397
Test name
Test status
Simulation time 458713350 ps
CPU time 1.79 seconds
Started Aug 23 10:24:50 PM UTC 24
Finished Aug 23 10:24:53 PM UTC 24
Peak memory 226672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518655742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2518655742
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.3533411116
Short name T360
Test name
Test status
Simulation time 82669918 ps
CPU time 1.05 seconds
Started Aug 23 10:24:54 PM UTC 24
Finished Aug 23 10:24:56 PM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533411116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3533411116
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3836781300
Short name T398
Test name
Test status
Simulation time 130544496 ps
CPU time 0.67 seconds
Started Aug 23 10:24:53 PM UTC 24
Finished Aug 23 10:24:55 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836781300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3836781300
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.3680134443
Short name T160
Test name
Test status
Simulation time 6337835286 ps
CPU time 22.76 seconds
Started Aug 23 10:25:02 PM UTC 24
Finished Aug 23 10:25:26 PM UTC 24
Peak memory 252036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680134443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3680134443
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/8.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.3693699341
Short name T406
Test name
Test status
Simulation time 24091432 ps
CPU time 0.62 seconds
Started Aug 23 10:25:37 PM UTC 24
Finished Aug 23 10:25:38 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693699341 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3693699341
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1095175363
Short name T404
Test name
Test status
Simulation time 1957437497 ps
CPU time 5.03 seconds
Started Aug 23 10:25:27 PM UTC 24
Finished Aug 23 10:25:34 PM UTC 24
Peak memory 235464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095175363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1095175363
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.2039379808
Short name T401
Test name
Test status
Simulation time 24085130 ps
CPU time 0.64 seconds
Started Aug 23 10:25:14 PM UTC 24
Finished Aug 23 10:25:16 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039379808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2039379808
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.1052869602
Short name T457
Test name
Test status
Simulation time 93774853722 ps
CPU time 154.61 seconds
Started Aug 23 10:25:32 PM UTC 24
Finished Aug 23 10:28:10 PM UTC 24
Peak memory 262288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052869602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1052869602
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.426602627
Short name T41
Test name
Test status
Simulation time 107822126637 ps
CPU time 429.04 seconds
Started Aug 23 10:25:34 PM UTC 24
Finished Aug 23 10:32:47 PM UTC 24
Peak memory 266536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426602627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.426602627
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2477349314
Short name T362
Test name
Test status
Simulation time 12742978436 ps
CPU time 17.78 seconds
Started Aug 23 10:25:35 PM UTC 24
Finished Aug 23 10:25:54 PM UTC 24
Peak memory 235488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477349314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.2477349314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.902568117
Short name T238
Test name
Test status
Simulation time 522220348 ps
CPU time 3.46 seconds
Started Aug 23 10:25:28 PM UTC 24
Finished Aug 23 10:25:33 PM UTC 24
Peak memory 245608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902568117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.902568117
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.3667117012
Short name T403
Test name
Test status
Simulation time 50472285 ps
CPU time 0.63 seconds
Started Aug 23 10:25:31 PM UTC 24
Finished Aug 23 10:25:33 PM UTC 24
Peak memory 225680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667117012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.3667117012
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.879146722
Short name T289
Test name
Test status
Simulation time 9634744380 ps
CPU time 16.11 seconds
Started Aug 23 10:25:24 PM UTC 24
Finished Aug 23 10:25:42 PM UTC 24
Peak memory 235660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879146722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.879146722
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.1288499365
Short name T298
Test name
Test status
Simulation time 49542863249 ps
CPU time 50.77 seconds
Started Aug 23 10:25:25 PM UTC 24
Finished Aug 23 10:26:18 PM UTC 24
Peak memory 245708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288499365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1288499365
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.915186828
Short name T402
Test name
Test status
Simulation time 15608985 ps
CPU time 0.9 seconds
Started Aug 23 10:25:15 PM UTC 24
Finished Aug 23 10:25:17 PM UTC 24
Peak memory 229204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915186828 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mem_parity.915186828
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.3554104999
Short name T163
Test name
Test status
Simulation time 847132410 ps
CPU time 7.92 seconds
Started Aug 23 10:25:21 PM UTC 24
Finished Aug 23 10:25:30 PM UTC 24
Peak memory 251728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554104999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.3554104999
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.2267340859
Short name T161
Test name
Test status
Simulation time 272268369 ps
CPU time 4.64 seconds
Started Aug 23 10:25:21 PM UTC 24
Finished Aug 23 10:25:27 PM UTC 24
Peak memory 245608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267340859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2267340859
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.2565266921
Short name T405
Test name
Test status
Simulation time 195569489 ps
CPU time 3.37 seconds
Started Aug 23 10:25:31 PM UTC 24
Finished Aug 23 10:25:36 PM UTC 24
Peak memory 231604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565266921 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.2565266921
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.3015751790
Short name T164
Test name
Test status
Simulation time 197922704508 ps
CPU time 841.27 seconds
Started Aug 23 10:25:35 PM UTC 24
Finished Aug 23 10:39:45 PM UTC 24
Peak memory 268484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015751790 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.3015751790
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.1047883462
Short name T361
Test name
Test status
Simulation time 2203294918 ps
CPU time 12.95 seconds
Started Aug 23 10:25:18 PM UTC 24
Finished Aug 23 10:25:32 PM UTC 24
Peak memory 232080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047883462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1047883462
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.2776260281
Short name T155
Test name
Test status
Simulation time 295931536 ps
CPU time 2.23 seconds
Started Aug 23 10:25:16 PM UTC 24
Finished Aug 23 10:25:19 PM UTC 24
Peak memory 227680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776260281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2776260281
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.1558481798
Short name T158
Test name
Test status
Simulation time 461084847 ps
CPU time 2.32 seconds
Started Aug 23 10:25:20 PM UTC 24
Finished Aug 23 10:25:23 PM UTC 24
Peak memory 227824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558481798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1558481798
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.3134427036
Short name T157
Test name
Test status
Simulation time 53030962 ps
CPU time 0.74 seconds
Started Aug 23 10:25:19 PM UTC 24
Finished Aug 23 10:25:21 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134427036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3134427036
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.3856111792
Short name T305
Test name
Test status
Simulation time 131260576 ps
CPU time 1.96 seconds
Started Aug 23 10:25:27 PM UTC 24
Finished Aug 23 10:25:30 PM UTC 24
Peak memory 235112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856111792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3856111792
Directory /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/9.spi_device_upload/latest
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