| T485 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_rw.3542340106 |
|
|
Sep 04 08:27:31 AM UTC 24 |
Sep 04 08:27:34 AM UTC 24 |
45493975 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.1878479851 |
|
|
Sep 04 08:27:29 AM UTC 24 |
Sep 04 08:27:34 AM UTC 24 |
769442171 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.2257526270 |
|
|
Sep 04 08:25:32 AM UTC 24 |
Sep 04 08:27:37 AM UTC 24 |
39183875032 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.1031425729 |
|
|
Sep 04 08:27:09 AM UTC 24 |
Sep 04 08:27:38 AM UTC 24 |
10275541257 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.1868463804 |
|
|
Sep 04 08:27:33 AM UTC 24 |
Sep 04 08:27:38 AM UTC 24 |
129973452 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.321025801 |
|
|
Sep 04 08:27:10 AM UTC 24 |
Sep 04 08:27:40 AM UTC 24 |
4956814711 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_upload.129251518 |
|
|
Sep 04 08:27:36 AM UTC 24 |
Sep 04 08:27:41 AM UTC 24 |
511931438 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.3801176326 |
|
|
Sep 04 08:26:01 AM UTC 24 |
Sep 04 08:27:41 AM UTC 24 |
2653819807 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.4148749156 |
|
|
Sep 04 08:25:58 AM UTC 24 |
Sep 04 08:28:20 AM UTC 24 |
27688335020 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.3370399829 |
|
|
Sep 04 08:27:32 AM UTC 24 |
Sep 04 08:27:41 AM UTC 24 |
5315161249 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_cfg_cmd.481389176 |
|
|
Sep 04 08:27:38 AM UTC 24 |
Sep 04 08:27:42 AM UTC 24 |
130543949 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.4290474426 |
|
|
Sep 04 08:27:16 AM UTC 24 |
Sep 04 08:27:42 AM UTC 24 |
15155279223 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_intercept.1769318403 |
|
|
Sep 04 08:27:35 AM UTC 24 |
Sep 04 08:27:43 AM UTC 24 |
2279570075 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode.3505680034 |
|
|
Sep 04 08:27:16 AM UTC 24 |
Sep 04 08:27:44 AM UTC 24 |
2116977337 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode.760514270 |
|
|
Sep 04 08:27:39 AM UTC 24 |
Sep 04 08:27:44 AM UTC 24 |
1105109575 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_alert_test.4223388623 |
|
|
Sep 04 08:27:44 AM UTC 24 |
Sep 04 08:27:46 AM UTC 24 |
18472257 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_csb_read.4009952465 |
|
|
Sep 04 08:27:44 AM UTC 24 |
Sep 04 08:27:46 AM UTC 24 |
81501932 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mem_parity.496083353 |
|
|
Sep 04 08:27:44 AM UTC 24 |
Sep 04 08:27:47 AM UTC 24 |
27302425 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.3507323799 |
|
|
Sep 04 08:27:47 AM UTC 24 |
Sep 04 08:27:49 AM UTC 24 |
17442032 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.2202692157 |
|
|
Sep 04 08:27:41 AM UTC 24 |
Sep 04 08:27:49 AM UTC 24 |
1048631622 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_rw.1879472698 |
|
|
Sep 04 08:27:47 AM UTC 24 |
Sep 04 08:27:50 AM UTC 24 |
273217870 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.3424169466 |
|
|
Sep 04 08:27:45 AM UTC 24 |
Sep 04 08:27:51 AM UTC 24 |
1235378727 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_all.963341517 |
|
|
Sep 04 08:27:09 AM UTC 24 |
Sep 04 08:27:51 AM UTC 24 |
3922426464 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.3568353049 |
|
|
Sep 04 08:26:49 AM UTC 24 |
Sep 04 08:27:51 AM UTC 24 |
11366976659 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.4284184498 |
|
|
Sep 04 08:27:04 AM UTC 24 |
Sep 04 08:27:55 AM UTC 24 |
9403658319 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_cfg_cmd.2282513390 |
|
|
Sep 04 08:27:52 AM UTC 24 |
Sep 04 08:27:56 AM UTC 24 |
33813804 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.3580301811 |
|
|
Sep 04 08:27:23 AM UTC 24 |
Sep 04 08:27:56 AM UTC 24 |
3379686767 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.2840727652 |
|
|
Sep 04 08:26:49 AM UTC 24 |
Sep 04 08:27:57 AM UTC 24 |
9748655108 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_all.1876103135 |
|
|
Sep 04 08:27:45 AM UTC 24 |
Sep 04 08:27:58 AM UTC 24 |
1416384896 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.3062779890 |
|
|
Sep 04 08:25:45 AM UTC 24 |
Sep 04 08:27:59 AM UTC 24 |
4842491942 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.4240568060 |
|
|
Sep 04 08:27:01 AM UTC 24 |
Sep 04 08:28:00 AM UTC 24 |
7448268849 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_all.3091786457 |
|
|
Sep 04 08:27:31 AM UTC 24 |
Sep 04 08:28:00 AM UTC 24 |
9191834552 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode.4176745412 |
|
|
Sep 04 08:27:52 AM UTC 24 |
Sep 04 08:28:00 AM UTC 24 |
294738514 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.848250045 |
|
|
Sep 04 08:26:32 AM UTC 24 |
Sep 04 08:28:01 AM UTC 24 |
7470474152 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.739291144 |
|
|
Sep 04 08:27:48 AM UTC 24 |
Sep 04 08:28:01 AM UTC 24 |
3438806014 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_alert_test.4233354276 |
|
|
Sep 04 08:28:00 AM UTC 24 |
Sep 04 08:28:02 AM UTC 24 |
38980064 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_csb_read.3387518382 |
|
|
Sep 04 08:28:00 AM UTC 24 |
Sep 04 08:28:02 AM UTC 24 |
19399117 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.3379699106 |
|
|
Sep 04 08:27:57 AM UTC 24 |
Sep 04 08:28:03 AM UTC 24 |
165802204 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mem_parity.4294876491 |
|
|
Sep 04 08:28:01 AM UTC 24 |
Sep 04 08:28:03 AM UTC 24 |
14676036 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.2999424887 |
|
|
Sep 04 08:28:18 AM UTC 24 |
Sep 04 08:28:21 AM UTC 24 |
144960043 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.1351096568 |
|
|
Sep 04 08:27:04 AM UTC 24 |
Sep 04 08:28:04 AM UTC 24 |
5424760753 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_intercept.615741896 |
|
|
Sep 04 08:27:50 AM UTC 24 |
Sep 04 08:28:05 AM UTC 24 |
1285212251 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.1762551653 |
|
|
Sep 04 08:28:02 AM UTC 24 |
Sep 04 08:28:05 AM UTC 24 |
26005978 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.3870575859 |
|
|
Sep 04 08:27:19 AM UTC 24 |
Sep 04 08:28:06 AM UTC 24 |
3121613309 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_all.397223545 |
|
|
Sep 04 08:28:01 AM UTC 24 |
Sep 04 08:28:06 AM UTC 24 |
424481486 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_rw.1076320979 |
|
|
Sep 04 08:28:04 AM UTC 24 |
Sep 04 08:28:06 AM UTC 24 |
90250158 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_upload.3715842437 |
|
|
Sep 04 08:27:51 AM UTC 24 |
Sep 04 08:28:08 AM UTC 24 |
3670977347 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.393519201 |
|
|
Sep 04 08:26:17 AM UTC 24 |
Sep 04 08:28:09 AM UTC 24 |
87541619352 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.2788250210 |
|
|
Sep 04 08:28:04 AM UTC 24 |
Sep 04 08:28:10 AM UTC 24 |
735026674 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode.2341055684 |
|
|
Sep 04 08:28:07 AM UTC 24 |
Sep 04 08:28:12 AM UTC 24 |
160280729 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mailbox.4231725409 |
|
|
Sep 04 08:27:51 AM UTC 24 |
Sep 04 08:28:13 AM UTC 24 |
7415095582 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.1928128460 |
|
|
Sep 04 08:28:07 AM UTC 24 |
Sep 04 08:28:13 AM UTC 24 |
447576321 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.3023303970 |
|
|
Sep 04 08:28:12 AM UTC 24 |
Sep 04 08:28:15 AM UTC 24 |
142140227 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_intercept.426735870 |
|
|
Sep 04 08:28:05 AM UTC 24 |
Sep 04 08:28:16 AM UTC 24 |
321993215 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.379760498 |
|
|
Sep 04 08:27:19 AM UTC 24 |
Sep 04 08:28:16 AM UTC 24 |
56911265413 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_alert_test.2289141081 |
|
|
Sep 04 08:28:14 AM UTC 24 |
Sep 04 08:28:17 AM UTC 24 |
50040152 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_csb_read.1021126463 |
|
|
Sep 04 08:28:15 AM UTC 24 |
Sep 04 08:28:17 AM UTC 24 |
33311423 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mem_parity.4021341729 |
|
|
Sep 04 08:28:16 AM UTC 24 |
Sep 04 08:28:19 AM UTC 24 |
32495282 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_cfg_cmd.1644652934 |
|
|
Sep 04 08:28:06 AM UTC 24 |
Sep 04 08:28:19 AM UTC 24 |
3045740126 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_upload.300398433 |
|
|
Sep 04 08:28:06 AM UTC 24 |
Sep 04 08:28:19 AM UTC 24 |
5733159379 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_rw.3218759087 |
|
|
Sep 04 08:28:18 AM UTC 24 |
Sep 04 08:28:20 AM UTC 24 |
17747772 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.3176514483 |
|
|
Sep 04 08:27:50 AM UTC 24 |
Sep 04 08:28:25 AM UTC 24 |
91244290306 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_cfg_cmd.416115199 |
|
|
Sep 04 08:28:21 AM UTC 24 |
Sep 04 08:28:26 AM UTC 24 |
981048693 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_upload.1117719578 |
|
|
Sep 04 08:28:21 AM UTC 24 |
Sep 04 08:28:26 AM UTC 24 |
258382137 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.1432109102 |
|
|
Sep 04 08:28:20 AM UTC 24 |
Sep 04 08:28:27 AM UTC 24 |
2785234093 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mailbox.593544556 |
|
|
Sep 04 08:28:05 AM UTC 24 |
Sep 04 08:28:27 AM UTC 24 |
973539622 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.124921730 |
|
|
Sep 04 08:28:20 AM UTC 24 |
Sep 04 08:28:29 AM UTC 24 |
3567617958 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.500778287 |
|
|
Sep 04 08:28:17 AM UTC 24 |
Sep 04 08:28:30 AM UTC 24 |
1987756856 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.40260857 |
|
|
Sep 04 08:25:31 AM UTC 24 |
Sep 04 08:28:30 AM UTC 24 |
17508081445 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_all.1882539270 |
|
|
Sep 04 08:27:58 AM UTC 24 |
Sep 04 08:28:31 AM UTC 24 |
22430028660 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.709970821 |
|
|
Sep 04 08:28:26 AM UTC 24 |
Sep 04 08:28:32 AM UTC 24 |
229681108 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_alert_test.1935218892 |
|
|
Sep 04 08:28:30 AM UTC 24 |
Sep 04 08:28:32 AM UTC 24 |
38936354 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_csb_read.2395500513 |
|
|
Sep 04 08:28:31 AM UTC 24 |
Sep 04 08:28:34 AM UTC 24 |
63750141 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mem_parity.206829116 |
|
|
Sep 04 08:28:31 AM UTC 24 |
Sep 04 08:28:34 AM UTC 24 |
31407360 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.3223234987 |
|
|
Sep 04 08:28:04 AM UTC 24 |
Sep 04 08:28:35 AM UTC 24 |
9747783459 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.2955384620 |
|
|
Sep 04 08:28:01 AM UTC 24 |
Sep 04 08:28:35 AM UTC 24 |
37038737067 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.1316405969 |
|
|
Sep 04 08:28:33 AM UTC 24 |
Sep 04 08:28:36 AM UTC 24 |
169975310 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_all.831083702 |
|
|
Sep 04 08:28:32 AM UTC 24 |
Sep 04 08:28:36 AM UTC 24 |
741346768 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mailbox.1713986713 |
|
|
Sep 04 08:28:20 AM UTC 24 |
Sep 04 08:28:37 AM UTC 24 |
995604365 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_rw.3490802113 |
|
|
Sep 04 08:28:35 AM UTC 24 |
Sep 04 08:28:38 AM UTC 24 |
135422651 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_all.3534564215 |
|
|
Sep 04 08:26:59 AM UTC 24 |
Sep 04 08:28:39 AM UTC 24 |
59096554198 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.3991497362 |
|
|
Sep 04 08:26:58 AM UTC 24 |
Sep 04 08:28:40 AM UTC 24 |
9843855194 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.176534708 |
|
|
Sep 04 08:28:31 AM UTC 24 |
Sep 04 08:28:40 AM UTC 24 |
893987055 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.1643144463 |
|
|
Sep 04 08:27:39 AM UTC 24 |
Sep 04 08:28:40 AM UTC 24 |
2894931231 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_intercept.1286662917 |
|
|
Sep 04 08:28:20 AM UTC 24 |
Sep 04 08:28:41 AM UTC 24 |
6944412797 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.635076575 |
|
|
Sep 04 08:28:37 AM UTC 24 |
Sep 04 08:28:42 AM UTC 24 |
60232343 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.1478083002 |
|
|
Sep 04 08:28:35 AM UTC 24 |
Sep 04 08:28:42 AM UTC 24 |
846987830 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_cfg_cmd.3479190078 |
|
|
Sep 04 08:28:38 AM UTC 24 |
Sep 04 08:28:44 AM UTC 24 |
373422888 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_alert_test.2599736277 |
|
|
Sep 04 08:28:43 AM UTC 24 |
Sep 04 08:28:45 AM UTC 24 |
30848315 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_upload.1802569381 |
|
|
Sep 04 08:28:38 AM UTC 24 |
Sep 04 08:28:46 AM UTC 24 |
862798090 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_csb_read.1792751995 |
|
|
Sep 04 08:28:45 AM UTC 24 |
Sep 04 08:28:46 AM UTC 24 |
19599676 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.3536634773 |
|
|
Sep 04 08:28:41 AM UTC 24 |
Sep 04 08:28:47 AM UTC 24 |
452076949 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mem_parity.1677045401 |
|
|
Sep 04 08:28:46 AM UTC 24 |
Sep 04 08:28:48 AM UTC 24 |
66633404 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_all.3970830919 |
|
|
Sep 04 08:28:17 AM UTC 24 |
Sep 04 08:28:50 AM UTC 24 |
3590701678 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.2435370846 |
|
|
Sep 04 08:28:48 AM UTC 24 |
Sep 04 08:28:50 AM UTC 24 |
50745824 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.2440134236 |
|
|
Sep 04 08:28:07 AM UTC 24 |
Sep 04 08:28:50 AM UTC 24 |
3008287022 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_intercept.843942317 |
|
|
Sep 04 08:28:37 AM UTC 24 |
Sep 04 08:28:51 AM UTC 24 |
3216540325 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_rw.843232862 |
|
|
Sep 04 08:28:49 AM UTC 24 |
Sep 04 08:28:51 AM UTC 24 |
100865756 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mailbox.3128569532 |
|
|
Sep 04 08:27:35 AM UTC 24 |
Sep 04 08:28:53 AM UTC 24 |
38824721438 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.3611714649 |
|
|
Sep 04 08:28:50 AM UTC 24 |
Sep 04 08:28:54 AM UTC 24 |
64824016 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.1636566417 |
|
|
Sep 04 08:28:47 AM UTC 24 |
Sep 04 08:28:55 AM UTC 24 |
3903227406 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.1372955983 |
|
|
Sep 04 08:28:09 AM UTC 24 |
Sep 04 08:28:56 AM UTC 24 |
9296031858 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_upload.3106889795 |
|
|
Sep 04 08:28:52 AM UTC 24 |
Sep 04 08:28:56 AM UTC 24 |
372457419 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_all.1607677008 |
|
|
Sep 04 08:28:27 AM UTC 24 |
Sep 04 08:28:57 AM UTC 24 |
2696463673 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mailbox.276059681 |
|
|
Sep 04 08:28:37 AM UTC 24 |
Sep 04 08:28:57 AM UTC 24 |
3887076954 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mailbox.449867594 |
|
|
Sep 04 08:27:12 AM UTC 24 |
Sep 04 08:29:00 AM UTC 24 |
18788097416 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.3686586666 |
|
|
Sep 04 08:26:32 AM UTC 24 |
Sep 04 08:29:00 AM UTC 24 |
33764250981 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.13614944 |
|
|
Sep 04 08:28:57 AM UTC 24 |
Sep 04 08:29:01 AM UTC 24 |
632701447 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_alert_test.3126841865 |
|
|
Sep 04 08:29:01 AM UTC 24 |
Sep 04 08:29:03 AM UTC 24 |
47395895 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode.769493677 |
|
|
Sep 04 08:28:39 AM UTC 24 |
Sep 04 08:29:03 AM UTC 24 |
1338119951 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_csb_read.496317604 |
|
|
Sep 04 08:29:02 AM UTC 24 |
Sep 04 08:29:04 AM UTC 24 |
17678440 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.1513536237 |
|
|
Sep 04 08:29:05 AM UTC 24 |
Sep 04 08:29:07 AM UTC 24 |
38411065 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.500478006 |
|
|
Sep 04 08:29:04 AM UTC 24 |
Sep 04 08:29:08 AM UTC 24 |
1281739744 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode.1854572484 |
|
|
Sep 04 08:28:21 AM UTC 24 |
Sep 04 08:29:09 AM UTC 24 |
7329465124 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.690880113 |
|
|
Sep 04 08:28:27 AM UTC 24 |
Sep 04 08:29:09 AM UTC 24 |
28513079953 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_cfg_cmd.3741791437 |
|
|
Sep 04 08:28:53 AM UTC 24 |
Sep 04 08:29:10 AM UTC 24 |
939028856 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_all.3562235357 |
|
|
Sep 04 08:28:47 AM UTC 24 |
Sep 04 08:29:11 AM UTC 24 |
3674755807 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.1361250018 |
|
|
Sep 04 08:28:51 AM UTC 24 |
Sep 04 08:29:11 AM UTC 24 |
16413467626 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_rw.294192252 |
|
|
Sep 04 08:29:08 AM UTC 24 |
Sep 04 08:29:12 AM UTC 24 |
92368699 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.2769571310 |
|
|
Sep 04 08:26:31 AM UTC 24 |
Sep 04 08:29:12 AM UTC 24 |
54757659940 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.3383853559 |
|
|
Sep 04 08:29:09 AM UTC 24 |
Sep 04 08:29:15 AM UTC 24 |
765488904 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_intercept.2766695177 |
|
|
Sep 04 08:28:51 AM UTC 24 |
Sep 04 08:29:15 AM UTC 24 |
2430720834 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_mailbox.3295876974 |
|
|
Sep 04 08:29:11 AM UTC 24 |
Sep 04 08:29:16 AM UTC 24 |
786112254 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_cfg_cmd.3962580207 |
|
|
Sep 04 08:29:12 AM UTC 24 |
Sep 04 08:29:17 AM UTC 24 |
1171298591 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.1958393442 |
|
|
Sep 04 08:29:09 AM UTC 24 |
Sep 04 08:29:17 AM UTC 24 |
2162250298 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_upload.2158332465 |
|
|
Sep 04 08:29:12 AM UTC 24 |
Sep 04 08:29:18 AM UTC 24 |
483462494 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_alert_test.3975998489 |
|
|
Sep 04 08:29:18 AM UTC 24 |
Sep 04 08:29:20 AM UTC 24 |
49138361 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mailbox.1752595069 |
|
|
Sep 04 08:28:52 AM UTC 24 |
Sep 04 08:29:21 AM UTC 24 |
1426656507 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.972094791 |
|
|
Sep 04 08:27:41 AM UTC 24 |
Sep 04 08:29:23 AM UTC 24 |
18380901673 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_csb_read.597744448 |
|
|
Sep 04 08:29:21 AM UTC 24 |
Sep 04 08:29:23 AM UTC 24 |
28196037 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_all.181253214 |
|
|
Sep 04 08:29:04 AM UTC 24 |
Sep 04 08:29:24 AM UTC 24 |
27783159763 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_all.2404392049 |
|
|
Sep 04 08:27:41 AM UTC 24 |
Sep 04 08:29:25 AM UTC 24 |
11975678354 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.3672506058 |
|
|
Sep 04 08:27:58 AM UTC 24 |
Sep 04 08:29:26 AM UTC 24 |
37223664074 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.2618378808 |
|
|
Sep 04 08:23:58 AM UTC 24 |
Sep 04 08:29:27 AM UTC 24 |
176581033050 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.2359758784 |
|
|
Sep 04 08:29:25 AM UTC 24 |
Sep 04 08:29:27 AM UTC 24 |
312260628 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode.434204342 |
|
|
Sep 04 08:29:13 AM UTC 24 |
Sep 04 08:29:28 AM UTC 24 |
1087864826 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_rw.1882459540 |
|
|
Sep 04 08:29:26 AM UTC 24 |
Sep 04 08:29:28 AM UTC 24 |
457383525 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.1902440322 |
|
|
Sep 04 08:29:13 AM UTC 24 |
Sep 04 08:29:29 AM UTC 24 |
1224632203 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_cfg_cmd.3781066852 |
|
|
Sep 04 08:29:29 AM UTC 24 |
Sep 04 08:29:34 AM UTC 24 |
280211144 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode.3386301531 |
|
|
Sep 04 08:29:29 AM UTC 24 |
Sep 04 08:29:34 AM UTC 24 |
2004892660 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.336124742 |
|
|
Sep 04 08:29:16 AM UTC 24 |
Sep 04 08:29:38 AM UTC 24 |
1512201681 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.2290382511 |
|
|
Sep 04 08:29:26 AM UTC 24 |
Sep 04 08:29:38 AM UTC 24 |
391212590 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.3632017653 |
|
|
Sep 04 08:29:27 AM UTC 24 |
Sep 04 08:29:39 AM UTC 24 |
4793025414 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.1894476068 |
|
|
Sep 04 08:27:57 AM UTC 24 |
Sep 04 08:29:39 AM UTC 24 |
30213982724 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_mailbox.63563599 |
|
|
Sep 04 08:29:28 AM UTC 24 |
Sep 04 08:29:41 AM UTC 24 |
545606524 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.3745943339 |
|
|
Sep 04 08:25:43 AM UTC 24 |
Sep 04 08:29:41 AM UTC 24 |
106218628336 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.155379543 |
|
|
Sep 04 08:29:35 AM UTC 24 |
Sep 04 08:29:41 AM UTC 24 |
246957656 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_alert_test.2326086327 |
|
|
Sep 04 08:29:40 AM UTC 24 |
Sep 04 08:29:42 AM UTC 24 |
41925866 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.4281381684 |
|
|
Sep 04 08:29:21 AM UTC 24 |
Sep 04 08:29:43 AM UTC 24 |
10157582892 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_csb_read.2816557804 |
|
|
Sep 04 08:29:42 AM UTC 24 |
Sep 04 08:29:46 AM UTC 24 |
82338932 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.2925797319 |
|
|
Sep 04 08:29:43 AM UTC 24 |
Sep 04 08:29:46 AM UTC 24 |
232825536 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_intercept.1300852060 |
|
|
Sep 04 08:29:11 AM UTC 24 |
Sep 04 08:29:48 AM UTC 24 |
3503259450 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_rw.2810847710 |
|
|
Sep 04 08:29:44 AM UTC 24 |
Sep 04 08:29:48 AM UTC 24 |
241600866 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.957196430 |
|
|
Sep 04 08:28:28 AM UTC 24 |
Sep 04 08:29:49 AM UTC 24 |
3208823867 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.3128287108 |
|
|
Sep 04 08:28:58 AM UTC 24 |
Sep 04 08:29:50 AM UTC 24 |
4354983683 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_intercept.2204430722 |
|
|
Sep 04 08:29:27 AM UTC 24 |
Sep 04 08:29:50 AM UTC 24 |
5121846766 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.183959191 |
|
|
Sep 04 08:29:46 AM UTC 24 |
Sep 04 08:29:51 AM UTC 24 |
611339045 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.3274252408 |
|
|
Sep 04 08:29:46 AM UTC 24 |
Sep 04 08:29:51 AM UTC 24 |
253687204 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_all.3357896091 |
|
|
Sep 04 08:29:16 AM UTC 24 |
Sep 04 08:29:52 AM UTC 24 |
1120878322 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_intercept.107990546 |
|
|
Sep 04 08:29:48 AM UTC 24 |
Sep 04 08:29:53 AM UTC 24 |
135323157 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.2770409086 |
|
|
Sep 04 08:28:40 AM UTC 24 |
Sep 04 08:29:55 AM UTC 24 |
14229721599 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.4240773348 |
|
|
Sep 04 08:29:52 AM UTC 24 |
Sep 04 08:29:56 AM UTC 24 |
476339539 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.2924949334 |
|
|
Sep 04 08:29:42 AM UTC 24 |
Sep 04 08:29:57 AM UTC 24 |
2377726858 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_all.4047451936 |
|
|
Sep 04 08:29:25 AM UTC 24 |
Sep 04 08:29:59 AM UTC 24 |
5254067325 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_upload.317653191 |
|
|
Sep 04 08:29:51 AM UTC 24 |
Sep 04 08:29:59 AM UTC 24 |
209909831 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_all.3853378105 |
|
|
Sep 04 08:29:42 AM UTC 24 |
Sep 04 08:30:00 AM UTC 24 |
2639407918 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.2639470498 |
|
|
Sep 04 08:29:17 AM UTC 24 |
Sep 04 08:30:00 AM UTC 24 |
3680525600 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_all.926043945 |
|
|
Sep 04 08:28:58 AM UTC 24 |
Sep 04 08:30:00 AM UTC 24 |
3884982414 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_alert_test.2513019825 |
|
|
Sep 04 08:29:58 AM UTC 24 |
Sep 04 08:30:00 AM UTC 24 |
12582072 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_upload.3586274055 |
|
|
Sep 04 08:29:28 AM UTC 24 |
Sep 04 08:30:01 AM UTC 24 |
15071233557 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode.1658954562 |
|
|
Sep 04 08:29:51 AM UTC 24 |
Sep 04 08:30:01 AM UTC 24 |
6639634784 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_csb_read.1549757810 |
|
|
Sep 04 08:29:59 AM UTC 24 |
Sep 04 08:30:02 AM UTC 24 |
15714675 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode.2070904380 |
|
|
Sep 04 08:28:55 AM UTC 24 |
Sep 04 08:30:02 AM UTC 24 |
8335495375 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.3390914340 |
|
|
Sep 04 08:30:01 AM UTC 24 |
Sep 04 08:30:03 AM UTC 24 |
852452290 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_all.64801923 |
|
|
Sep 04 08:28:41 AM UTC 24 |
Sep 04 08:30:04 AM UTC 24 |
79243046027 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_stress_all.641384018 |
|
|
Sep 04 08:28:28 AM UTC 24 |
Sep 04 08:30:04 AM UTC 24 |
52873639319 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_mailbox.2722921632 |
|
|
Sep 04 08:29:49 AM UTC 24 |
Sep 04 08:30:06 AM UTC 24 |
4880742328 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_rw.1857818846 |
|
|
Sep 04 08:30:02 AM UTC 24 |
Sep 04 08:30:08 AM UTC 24 |
549235576 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_cfg_cmd.3132608643 |
|
|
Sep 04 08:30:04 AM UTC 24 |
Sep 04 08:30:08 AM UTC 24 |
632089631 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.3354435036 |
|
|
Sep 04 08:24:46 AM UTC 24 |
Sep 04 08:30:08 AM UTC 24 |
150968719596 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_upload.3961835802 |
|
|
Sep 04 08:30:03 AM UTC 24 |
Sep 04 08:30:09 AM UTC 24 |
249697699 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_intercept.3754812037 |
|
|
Sep 04 08:30:03 AM UTC 24 |
Sep 04 08:30:10 AM UTC 24 |
1063761966 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.139557568 |
|
|
Sep 04 08:30:02 AM UTC 24 |
Sep 04 08:30:11 AM UTC 24 |
514815740 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.382384411 |
|
|
Sep 04 08:30:00 AM UTC 24 |
Sep 04 08:30:11 AM UTC 24 |
2504513301 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_mailbox.2177226627 |
|
|
Sep 04 08:30:03 AM UTC 24 |
Sep 04 08:30:12 AM UTC 24 |
1909968296 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_alert_test.1604576239 |
|
|
Sep 04 08:30:11 AM UTC 24 |
Sep 04 08:30:13 AM UTC 24 |
11269867 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.108879437 |
|
|
Sep 04 08:30:02 AM UTC 24 |
Sep 04 08:30:13 AM UTC 24 |
667182639 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_csb_read.3720692006 |
|
|
Sep 04 08:30:12 AM UTC 24 |
Sep 04 08:30:14 AM UTC 24 |
23393628 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.3330388281 |
|
|
Sep 04 08:30:13 AM UTC 24 |
Sep 04 08:30:15 AM UTC 24 |
40244351 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_cfg_cmd.1762537197 |
|
|
Sep 04 08:29:51 AM UTC 24 |
Sep 04 08:30:16 AM UTC 24 |
2141187231 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.3373315433 |
|
|
Sep 04 08:30:14 AM UTC 24 |
Sep 04 08:30:16 AM UTC 24 |
40635200 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_rw.1991681499 |
|
|
Sep 04 08:30:14 AM UTC 24 |
Sep 04 08:30:17 AM UTC 24 |
104060617 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.4277770853 |
|
|
Sep 04 08:30:07 AM UTC 24 |
Sep 04 08:30:19 AM UTC 24 |
617063437 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.3892749742 |
|
|
Sep 04 08:30:15 AM UTC 24 |
Sep 04 08:30:19 AM UTC 24 |
92049144 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.810876120 |
|
|
Sep 04 08:29:30 AM UTC 24 |
Sep 04 08:30:20 AM UTC 24 |
10563397742 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_all.124220684 |
|
|
Sep 04 08:30:14 AM UTC 24 |
Sep 04 08:30:25 AM UTC 24 |
1187541121 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode.1066396383 |
|
|
Sep 04 08:30:04 AM UTC 24 |
Sep 04 08:30:27 AM UTC 24 |
6420738294 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.1261384374 |
|
|
Sep 04 08:30:15 AM UTC 24 |
Sep 04 08:30:28 AM UTC 24 |
2280783090 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.3205296698 |
|
|
Sep 04 08:30:19 AM UTC 24 |
Sep 04 08:30:28 AM UTC 24 |
212804772 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_upload.1309249055 |
|
|
Sep 04 08:30:17 AM UTC 24 |
Sep 04 08:30:28 AM UTC 24 |
2202425855 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.2191910389 |
|
|
Sep 04 08:28:41 AM UTC 24 |
Sep 04 08:30:34 AM UTC 24 |
4220325526 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_all.697365277 |
|
|
Sep 04 08:29:35 AM UTC 24 |
Sep 04 08:30:34 AM UTC 24 |
5962866946 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_alert_test.1035357363 |
|
|
Sep 04 08:30:35 AM UTC 24 |
Sep 04 08:30:37 AM UTC 24 |
37315760 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_csb_read.3516703283 |
|
|
Sep 04 08:30:35 AM UTC 24 |
Sep 04 08:30:37 AM UTC 24 |
19692328 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_all.3520022860 |
|
|
Sep 04 08:30:00 AM UTC 24 |
Sep 04 08:30:38 AM UTC 24 |
9525619845 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.1135913838 |
|
|
Sep 04 08:30:27 AM UTC 24 |
Sep 04 08:30:39 AM UTC 24 |
590369135 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.3311496359 |
|
|
Sep 04 08:30:38 AM UTC 24 |
Sep 04 08:30:41 AM UTC 24 |
73540356 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_rw.2181579173 |
|
|
Sep 04 08:30:39 AM UTC 24 |
Sep 04 08:30:42 AM UTC 24 |
45530154 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_intercept.3359348906 |
|
|
Sep 04 08:30:17 AM UTC 24 |
Sep 04 08:30:42 AM UTC 24 |
10024619446 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_all.112324965 |
|
|
Sep 04 08:28:09 AM UTC 24 |
Sep 04 08:30:46 AM UTC 24 |
11191973688 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.808415670 |
|
|
Sep 04 08:30:42 AM UTC 24 |
Sep 04 08:30:46 AM UTC 24 |
33044310 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.306331535 |
|
|
Sep 04 08:24:25 AM UTC 24 |
Sep 04 08:30:47 AM UTC 24 |
48814359306 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.393236707 |
|
|
Sep 04 08:29:39 AM UTC 24 |
Sep 04 08:30:48 AM UTC 24 |
28184782402 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_cfg_cmd.1666702339 |
|
|
Sep 04 08:30:19 AM UTC 24 |
Sep 04 08:30:49 AM UTC 24 |
4110312042 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_mailbox.3104144574 |
|
|
Sep 04 08:30:47 AM UTC 24 |
Sep 04 08:30:50 AM UTC 24 |
32450671 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.1412193975 |
|
|
Sep 04 08:28:25 AM UTC 24 |
Sep 04 08:30:51 AM UTC 24 |
36465652356 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.2174059066 |
|
|
Sep 04 08:30:41 AM UTC 24 |
Sep 04 08:30:51 AM UTC 24 |
637767810 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_upload.3835430155 |
|
|
Sep 04 08:30:48 AM UTC 24 |
Sep 04 08:30:52 AM UTC 24 |
456924515 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_all.3459051220 |
|
|
Sep 04 08:29:53 AM UTC 24 |
Sep 04 08:30:53 AM UTC 24 |
4937660576 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_cfg_cmd.3198683325 |
|
|
Sep 04 08:30:48 AM UTC 24 |
Sep 04 08:30:54 AM UTC 24 |
259326295 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode.633300423 |
|
|
Sep 04 08:30:49 AM UTC 24 |
Sep 04 08:30:54 AM UTC 24 |
87151896 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.1980626342 |
|
|
Sep 04 08:30:20 AM UTC 24 |
Sep 04 08:30:54 AM UTC 24 |
15047029635 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.2956973424 |
|
|
Sep 04 08:30:38 AM UTC 24 |
Sep 04 08:30:54 AM UTC 24 |
20092471219 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.460709519 |
|
|
Sep 04 08:30:51 AM UTC 24 |
Sep 04 08:30:56 AM UTC 24 |
110072782 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.3956674655 |
|
|
Sep 04 08:30:05 AM UTC 24 |
Sep 04 08:30:56 AM UTC 24 |
15203335702 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_alert_test.1042797091 |
|
|
Sep 04 08:30:54 AM UTC 24 |
Sep 04 08:30:56 AM UTC 24 |
24070377 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_intercept.2561106019 |
|
|
Sep 04 08:30:43 AM UTC 24 |
Sep 04 08:30:56 AM UTC 24 |
1184192868 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_csb_read.1893026841 |
|
|
Sep 04 08:30:55 AM UTC 24 |
Sep 04 08:30:58 AM UTC 24 |
85586873 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2483682697 |
|
|
Sep 04 08:28:11 AM UTC 24 |
Sep 04 08:30:58 AM UTC 24 |
101730659958 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.941962896 |
|
|
Sep 04 08:29:17 AM UTC 24 |
Sep 04 08:30:59 AM UTC 24 |
4194031186 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_rw.3315430233 |
|
|
Sep 04 08:30:57 AM UTC 24 |
Sep 04 08:30:59 AM UTC 24 |
36092828 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.2744898211 |
|
|
Sep 04 08:30:57 AM UTC 24 |
Sep 04 08:30:59 AM UTC 24 |
37719432 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_mailbox.1756061981 |
|
|
Sep 04 08:30:17 AM UTC 24 |
Sep 04 08:31:01 AM UTC 24 |
21645464642 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.27015398 |
|
|
Sep 04 08:30:58 AM UTC 24 |
Sep 04 08:31:02 AM UTC 24 |
2314482047 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_cfg_cmd.1940342237 |
|
|
Sep 04 08:31:00 AM UTC 24 |
Sep 04 08:31:03 AM UTC 24 |
563480780 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.543552281 |
|
|
Sep 04 08:30:55 AM UTC 24 |
Sep 04 08:31:07 AM UTC 24 |
14726354636 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_upload.4014852317 |
|
|
Sep 04 08:31:00 AM UTC 24 |
Sep 04 08:31:08 AM UTC 24 |
1495953533 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_intercept.1247081971 |
|
|
Sep 04 08:30:59 AM UTC 24 |
Sep 04 08:31:10 AM UTC 24 |
2091542465 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.1398113033 |
|
|
Sep 04 08:31:11 AM UTC 24 |
Sep 04 08:31:14 AM UTC 24 |
100393926 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.60750859 |
|
|
Sep 04 08:30:09 AM UTC 24 |
Sep 04 08:31:14 AM UTC 24 |
9727430801 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.2875462208 |
|
|
Sep 04 08:27:20 AM UTC 24 |
Sep 04 08:31:15 AM UTC 24 |
164908212180 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_all.4206360328 |
|
|
Sep 04 08:30:56 AM UTC 24 |
Sep 04 08:31:16 AM UTC 24 |
3094969847 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.2802405327 |
|
|
Sep 04 08:31:03 AM UTC 24 |
Sep 04 08:31:16 AM UTC 24 |
1156838047 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_alert_test.3190596996 |
|
|
Sep 04 08:31:15 AM UTC 24 |
Sep 04 08:31:17 AM UTC 24 |
23630196 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_csb_read.4074116433 |
|
|
Sep 04 08:31:15 AM UTC 24 |
Sep 04 08:31:17 AM UTC 24 |
12979129 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.902119737 |
|
|
Sep 04 08:30:58 AM UTC 24 |
Sep 04 08:31:18 AM UTC 24 |
9227793892 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_all.1105228802 |
|
|
Sep 04 08:30:38 AM UTC 24 |
Sep 04 08:31:18 AM UTC 24 |
1749441227 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.600281019 |
|
|
Sep 04 08:31:16 AM UTC 24 |
Sep 04 08:31:19 AM UTC 24 |
278605054 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.3149936406 |
|
|
Sep 04 08:31:17 AM UTC 24 |
Sep 04 08:31:20 AM UTC 24 |
72460570 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_rw.3040698132 |
|
|
Sep 04 08:31:17 AM UTC 24 |
Sep 04 08:31:21 AM UTC 24 |
336378328 ps |