| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.07 | 98.44 | 94.08 | 98.62 | 89.36 | 97.28 | 95.43 | 99.26 |
| T106 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3330155692 | Sep 04 12:41:22 PM UTC 24 | Sep 04 12:41:31 PM UTC 24 | 69185804 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.1252021769 | Sep 04 12:41:22 PM UTC 24 | Sep 04 12:41:31 PM UTC 24 | 224367087 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.2550117536 | Sep 04 12:41:30 PM UTC 24 | Sep 04 12:41:31 PM UTC 24 | 121357955 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.1932875489 | Sep 04 12:41:30 PM UTC 24 | Sep 04 12:41:32 PM UTC 24 | 22762691 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.2912961178 | Sep 04 12:41:22 PM UTC 24 | Sep 04 12:41:32 PM UTC 24 | 47031123 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.4168076952 | Sep 04 12:41:19 PM UTC 24 | Sep 04 12:41:32 PM UTC 24 | 22775138 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2879674654 | Sep 04 12:41:16 PM UTC 24 | Sep 04 12:41:32 PM UTC 24 | 1520005577 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3920727152 | Sep 04 12:41:29 PM UTC 24 | Sep 04 12:41:32 PM UTC 24 | 28257348 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.247238274 | Sep 04 12:41:20 PM UTC 24 | Sep 04 12:41:32 PM UTC 24 | 158970527 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.555440526 | Sep 04 12:41:31 PM UTC 24 | Sep 04 12:41:33 PM UTC 24 | 65889340 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2565302348 | Sep 04 12:41:29 PM UTC 24 | Sep 04 12:41:33 PM UTC 24 | 209113940 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.2866062773 | Sep 04 12:41:31 PM UTC 24 | Sep 04 12:41:33 PM UTC 24 | 34718185 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.2357752277 | Sep 04 12:41:25 PM UTC 24 | Sep 04 12:41:33 PM UTC 24 | 711136609 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.4154259079 | Sep 04 12:41:29 PM UTC 24 | Sep 04 12:41:34 PM UTC 24 | 89664465 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2778187941 | Sep 04 12:41:32 PM UTC 24 | Sep 04 12:41:45 PM UTC 24 | 2523617584 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3683858227 | Sep 04 12:41:20 PM UTC 24 | Sep 04 12:41:34 PM UTC 24 | 212896301 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.1992574207 | Sep 04 12:41:32 PM UTC 24 | Sep 04 12:41:34 PM UTC 24 | 46206246 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.2034624477 | Sep 04 12:41:31 PM UTC 24 | Sep 04 12:41:34 PM UTC 24 | 93185240 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3819148204 | Sep 04 12:41:16 PM UTC 24 | Sep 04 12:41:34 PM UTC 24 | 2985254639 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.4028367507 | Sep 04 12:41:32 PM UTC 24 | Sep 04 12:41:35 PM UTC 24 | 51216833 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.300589090 | Sep 04 12:41:32 PM UTC 24 | Sep 04 12:41:35 PM UTC 24 | 54045458 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4018382960 | Sep 04 12:41:32 PM UTC 24 | Sep 04 12:41:35 PM UTC 24 | 63593098 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1268006438 | Sep 04 12:41:25 PM UTC 24 | Sep 04 12:41:36 PM UTC 24 | 281319125 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.3954828343 | Sep 04 12:41:28 PM UTC 24 | Sep 04 12:41:36 PM UTC 24 | 115817544 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1166744323 | Sep 04 12:41:32 PM UTC 24 | Sep 04 12:41:36 PM UTC 24 | 610348019 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.3111380059 | Sep 04 12:41:32 PM UTC 24 | Sep 04 12:41:37 PM UTC 24 | 296607752 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3877078118 | Sep 04 12:41:32 PM UTC 24 | Sep 04 12:41:37 PM UTC 24 | 114402433 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2550400036 | Sep 04 12:41:32 PM UTC 24 | Sep 04 12:41:37 PM UTC 24 | 161782388 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.4137659234 | Sep 04 12:41:35 PM UTC 24 | Sep 04 12:41:38 PM UTC 24 | 28302693 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.3255523723 | Sep 04 12:41:34 PM UTC 24 | Sep 04 12:41:39 PM UTC 24 | 170157823 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.3130655677 | Sep 04 12:41:36 PM UTC 24 | Sep 04 12:41:39 PM UTC 24 | 156802127 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.402810083 | Sep 04 12:41:34 PM UTC 24 | Sep 04 12:41:39 PM UTC 24 | 38928387 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2306591136 | Sep 04 12:41:35 PM UTC 24 | Sep 04 12:41:39 PM UTC 24 | 175634332 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.718624867 | Sep 04 12:41:35 PM UTC 24 | Sep 04 12:41:39 PM UTC 24 | 102513879 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.4182563650 | Sep 04 12:41:37 PM UTC 24 | Sep 04 12:41:39 PM UTC 24 | 97481438 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4289803653 | Sep 04 12:41:34 PM UTC 24 | Sep 04 12:41:40 PM UTC 24 | 87737601 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.4229683011 | Sep 04 12:41:35 PM UTC 24 | Sep 04 12:41:40 PM UTC 24 | 207938050 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3291634061 | Sep 04 12:41:16 PM UTC 24 | Sep 04 12:41:40 PM UTC 24 | 3565777655 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.477652732 | Sep 04 12:41:34 PM UTC 24 | Sep 04 12:41:40 PM UTC 24 | 43549790 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2952832112 | Sep 04 12:41:35 PM UTC 24 | Sep 04 12:41:41 PM UTC 24 | 278164278 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.376046230 | Sep 04 12:41:34 PM UTC 24 | Sep 04 12:41:41 PM UTC 24 | 199609856 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1109636824 | Sep 04 12:41:34 PM UTC 24 | Sep 04 12:41:41 PM UTC 24 | 97731143 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.4287881941 | Sep 04 12:41:34 PM UTC 24 | Sep 04 12:41:41 PM UTC 24 | 448701019 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2448889333 | Sep 04 12:41:37 PM UTC 24 | Sep 04 12:41:41 PM UTC 24 | 749448712 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2558291911 | Sep 04 12:41:20 PM UTC 24 | Sep 04 12:41:42 PM UTC 24 | 2189822993 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.2680029740 | Sep 04 12:41:34 PM UTC 24 | Sep 04 12:41:42 PM UTC 24 | 12474219 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1042853555 | Sep 04 12:41:37 PM UTC 24 | Sep 04 12:41:42 PM UTC 24 | 229007568 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.2108568482 | Sep 04 12:41:20 PM UTC 24 | Sep 04 12:41:42 PM UTC 24 | 1134575774 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1280809039 | Sep 04 12:41:34 PM UTC 24 | Sep 04 12:41:43 PM UTC 24 | 26830811 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.1669626755 | Sep 04 12:41:40 PM UTC 24 | Sep 04 12:41:43 PM UTC 24 | 96494336 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.2549200055 | Sep 04 12:41:39 PM UTC 24 | Sep 04 12:41:44 PM UTC 24 | 55435745 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.3564941773 | Sep 04 12:41:40 PM UTC 24 | Sep 04 12:41:45 PM UTC 24 | 585112424 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1558879974 | Sep 04 12:41:40 PM UTC 24 | Sep 04 12:41:44 PM UTC 24 | 57821611 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.1273185997 | Sep 04 12:41:39 PM UTC 24 | Sep 04 12:41:45 PM UTC 24 | 116333512 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3461869389 | Sep 04 12:41:40 PM UTC 24 | Sep 04 12:41:46 PM UTC 24 | 435911865 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.3644130124 | Sep 04 12:41:41 PM UTC 24 | Sep 04 12:41:46 PM UTC 24 | 293597366 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1093991330 | Sep 04 12:41:40 PM UTC 24 | Sep 04 12:41:46 PM UTC 24 | 256292906 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2761973327 | Sep 04 12:41:40 PM UTC 24 | Sep 04 12:41:46 PM UTC 24 | 207370649 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.4147615364 | Sep 04 12:41:19 PM UTC 24 | Sep 04 12:41:46 PM UTC 24 | 798839001 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.3771806334 | Sep 04 12:41:34 PM UTC 24 | Sep 04 12:41:46 PM UTC 24 | 272261232 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3141989273 | Sep 04 12:41:39 PM UTC 24 | Sep 04 12:41:47 PM UTC 24 | 160744254 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.622248093 | Sep 04 12:41:24 PM UTC 24 | Sep 04 12:41:47 PM UTC 24 | 293704209 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.956721959 | Sep 04 12:41:43 PM UTC 24 | Sep 04 12:41:48 PM UTC 24 | 63560900 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.1348374775 | Sep 04 12:41:58 PM UTC 24 | Sep 04 12:42:03 PM UTC 24 | 27755406 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.3533939785 | Sep 04 12:41:43 PM UTC 24 | Sep 04 12:41:48 PM UTC 24 | 20284820 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.924272498 | Sep 04 12:41:29 PM UTC 24 | Sep 04 12:41:48 PM UTC 24 | 305184119 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.2712481577 | Sep 04 12:41:45 PM UTC 24 | Sep 04 12:41:48 PM UTC 24 | 25244191 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.298895747 | Sep 04 12:41:43 PM UTC 24 | Sep 04 12:41:49 PM UTC 24 | 168967112 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.3159737208 | Sep 04 12:41:43 PM UTC 24 | Sep 04 12:41:49 PM UTC 24 | 99569374 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.413176800 | Sep 04 12:41:43 PM UTC 24 | Sep 04 12:41:49 PM UTC 24 | 27475953 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.338944820 | Sep 04 12:41:45 PM UTC 24 | Sep 04 12:41:49 PM UTC 24 | 20359095 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4214396803 | Sep 04 12:41:43 PM UTC 24 | Sep 04 12:41:49 PM UTC 24 | 160781056 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2453241123 | Sep 04 12:41:43 PM UTC 24 | Sep 04 12:41:49 PM UTC 24 | 119119953 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.42773364 | Sep 04 12:41:39 PM UTC 24 | Sep 04 12:41:49 PM UTC 24 | 422550421 ps | ||
| T1081 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2132602170 | Sep 04 12:41:48 PM UTC 24 | Sep 04 12:41:49 PM UTC 24 | 37035636 ps | ||
| T1082 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1127149754 | Sep 04 12:41:43 PM UTC 24 | Sep 04 12:41:50 PM UTC 24 | 235790768 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.955603461 | Sep 04 12:41:32 PM UTC 24 | Sep 04 12:41:50 PM UTC 24 | 614964136 ps | ||
| T1083 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1766510664 | Sep 04 12:41:45 PM UTC 24 | Sep 04 12:41:50 PM UTC 24 | 89064633 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.3099490288 | Sep 04 12:41:45 PM UTC 24 | Sep 04 12:41:50 PM UTC 24 | 82705753 ps | ||
| T1084 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2959657017 | Sep 04 12:41:43 PM UTC 24 | Sep 04 12:41:51 PM UTC 24 | 243833727 ps | ||
| T1085 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2192812536 | Sep 04 12:41:45 PM UTC 24 | Sep 04 12:41:51 PM UTC 24 | 146925101 ps | ||
| T1086 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.3560358429 | Sep 04 12:41:32 PM UTC 24 | Sep 04 12:41:51 PM UTC 24 | 2311968550 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.3933060542 | Sep 04 12:41:43 PM UTC 24 | Sep 04 12:41:52 PM UTC 24 | 84636073 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.3962551873 | Sep 04 12:41:43 PM UTC 24 | Sep 04 12:41:53 PM UTC 24 | 103438140 ps | ||
| T1087 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.683896523 | Sep 04 12:41:48 PM UTC 24 | Sep 04 12:41:53 PM UTC 24 | 28960614 ps | ||
| T1088 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.3221801047 | Sep 04 12:41:51 PM UTC 24 | Sep 04 12:41:53 PM UTC 24 | 95068519 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.3524318301 | Sep 04 12:41:34 PM UTC 24 | Sep 04 12:41:54 PM UTC 24 | 200829159 ps | ||
| T1089 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.2460409985 | Sep 04 12:41:48 PM UTC 24 | Sep 04 12:41:54 PM UTC 24 | 72675522 ps | ||
| T1090 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.200268087 | Sep 04 12:41:48 PM UTC 24 | Sep 04 12:41:54 PM UTC 24 | 173513565 ps | ||
| T1091 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.1988993392 | Sep 04 12:41:51 PM UTC 24 | Sep 04 12:41:54 PM UTC 24 | 33788485 ps | ||
| T1092 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.4260693688 | Sep 04 12:41:35 PM UTC 24 | Sep 04 12:41:54 PM UTC 24 | 578829878 ps | ||
| T1093 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3025389396 | Sep 04 12:41:48 PM UTC 24 | Sep 04 12:41:54 PM UTC 24 | 58539005 ps | ||
| T1094 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3315200975 | Sep 04 12:41:28 PM UTC 24 | Sep 04 12:41:54 PM UTC 24 | 7511818245 ps | ||
| T1095 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.1727347905 | Sep 04 12:41:48 PM UTC 24 | Sep 04 12:41:54 PM UTC 24 | 219530193 ps | ||
| T1096 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1316672990 | Sep 04 12:41:48 PM UTC 24 | Sep 04 12:41:54 PM UTC 24 | 419294282 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.2189074599 | Sep 04 12:41:41 PM UTC 24 | Sep 04 12:41:54 PM UTC 24 | 935081126 ps | ||
| T1097 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4007421121 | Sep 04 12:41:51 PM UTC 24 | Sep 04 12:41:54 PM UTC 24 | 54943844 ps | ||
| T1098 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1172781489 | Sep 04 12:41:50 PM UTC 24 | Sep 04 12:41:55 PM UTC 24 | 94139448 ps | ||
| T1099 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.945990566 | Sep 04 12:41:51 PM UTC 24 | Sep 04 12:41:55 PM UTC 24 | 102799250 ps | ||
| T1100 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.3953481195 | Sep 04 12:41:51 PM UTC 24 | Sep 04 12:41:55 PM UTC 24 | 29688561 ps | ||
| T1101 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.2336268637 | Sep 04 12:41:32 PM UTC 24 | Sep 04 12:41:55 PM UTC 24 | 4575026374 ps | ||
| T1102 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1040745368 | Sep 04 12:41:51 PM UTC 24 | Sep 04 12:41:55 PM UTC 24 | 60760323 ps | ||
| T1103 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4257369546 | Sep 04 12:41:51 PM UTC 24 | Sep 04 12:41:55 PM UTC 24 | 43825233 ps | ||
| T1104 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.347127798 | Sep 04 12:41:51 PM UTC 24 | Sep 04 12:41:55 PM UTC 24 | 350427162 ps | ||
| T1105 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.1224576255 | Sep 04 12:41:52 PM UTC 24 | Sep 04 12:41:55 PM UTC 24 | 323555663 ps | ||
| T1106 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.3184879295 | Sep 04 12:41:53 PM UTC 24 | Sep 04 12:41:55 PM UTC 24 | 44092475 ps | ||
| T1107 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.4041296008 | Sep 04 12:41:34 PM UTC 24 | Sep 04 12:41:56 PM UTC 24 | 572621003 ps | ||
| T1108 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.62530351 | Sep 04 12:41:48 PM UTC 24 | Sep 04 12:41:56 PM UTC 24 | 525712933 ps | ||
| T1109 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3637981938 | Sep 04 12:41:51 PM UTC 24 | Sep 04 12:41:56 PM UTC 24 | 150680542 ps | ||
| T1110 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.3676298456 | Sep 04 12:41:50 PM UTC 24 | Sep 04 12:41:56 PM UTC 24 | 652306413 ps | ||
| T1111 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.570682721 | Sep 04 12:41:55 PM UTC 24 | Sep 04 12:41:58 PM UTC 24 | 14069722 ps | ||
| T1112 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.3891568611 | Sep 04 12:41:55 PM UTC 24 | Sep 04 12:41:58 PM UTC 24 | 11772531 ps | ||
| T1113 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.4081756153 | Sep 04 12:41:55 PM UTC 24 | Sep 04 12:41:58 PM UTC 24 | 59373695 ps | ||
| T1114 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.4096517355 | Sep 04 12:41:55 PM UTC 24 | Sep 04 12:41:58 PM UTC 24 | 17792996 ps | ||
| T1115 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.1710826218 | Sep 04 12:41:55 PM UTC 24 | Sep 04 12:41:58 PM UTC 24 | 26549622 ps | ||
| T1116 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.85360453 | Sep 04 12:41:56 PM UTC 24 | Sep 04 12:41:58 PM UTC 24 | 32925606 ps | ||
| T1117 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.4122313042 | Sep 04 12:41:53 PM UTC 24 | Sep 04 12:41:58 PM UTC 24 | 15128689 ps | ||
| T1118 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.1465118700 | Sep 04 12:41:56 PM UTC 24 | Sep 04 12:41:58 PM UTC 24 | 85721783 ps | ||
| T1119 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.3134490692 | Sep 04 12:41:56 PM UTC 24 | Sep 04 12:41:58 PM UTC 24 | 19880079 ps | ||
| T1120 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.1633831693 | Sep 04 12:41:56 PM UTC 24 | Sep 04 12:41:58 PM UTC 24 | 14599549 ps | ||
| T1121 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.3485634817 | Sep 04 12:41:40 PM UTC 24 | Sep 04 12:41:59 PM UTC 24 | 286723447 ps | ||
| T1122 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.3951713247 | Sep 04 12:41:48 PM UTC 24 | Sep 04 12:41:59 PM UTC 24 | 3336677990 ps | ||
| T1123 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.196327093 | Sep 04 12:41:53 PM UTC 24 | Sep 04 12:41:59 PM UTC 24 | 57766486 ps | ||
| T1124 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2901503288 | Sep 04 12:41:22 PM UTC 24 | Sep 04 12:42:00 PM UTC 24 | 527970447 ps | ||
| T1125 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3077690043 | Sep 04 12:41:53 PM UTC 24 | Sep 04 12:42:01 PM UTC 24 | 521195688 ps | ||
| T1126 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.2197677430 | Sep 04 12:41:50 PM UTC 24 | Sep 04 12:42:01 PM UTC 24 | 1604433056 ps | ||
| T1127 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.2350037381 | Sep 04 12:41:58 PM UTC 24 | Sep 04 12:42:03 PM UTC 24 | 18643471 ps | ||
| T1128 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.2059556892 | Sep 04 12:41:58 PM UTC 24 | Sep 04 12:42:03 PM UTC 24 | 17183566 ps | ||
| T1129 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.3416238707 | Sep 04 12:41:45 PM UTC 24 | Sep 04 12:42:03 PM UTC 24 | 1316725566 ps | ||
| T1130 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.628841792 | Sep 04 12:41:53 PM UTC 24 | Sep 04 12:42:03 PM UTC 24 | 191964973 ps | ||
| T1131 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.130315781 | Sep 04 12:41:55 PM UTC 24 | Sep 04 12:42:03 PM UTC 24 | 44575271 ps | ||
| T1132 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.1036205808 | Sep 04 12:41:55 PM UTC 24 | Sep 04 12:42:03 PM UTC 24 | 21959240 ps | ||
| T1133 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.814892465 | Sep 04 12:41:55 PM UTC 24 | Sep 04 12:42:04 PM UTC 24 | 76519253 ps | ||
| T1134 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.2197350371 | Sep 04 12:41:55 PM UTC 24 | Sep 04 12:42:04 PM UTC 24 | 79553379 ps | ||
| T1135 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.1168938970 | Sep 04 12:41:55 PM UTC 24 | Sep 04 12:42:04 PM UTC 24 | 11801547 ps | ||
| T1136 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.4209643996 | Sep 04 12:41:55 PM UTC 24 | Sep 04 12:42:04 PM UTC 24 | 42492410 ps | ||
| T1137 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.918865401 | Sep 04 12:41:56 PM UTC 24 | Sep 04 12:42:05 PM UTC 24 | 29229943 ps | ||
| T1138 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.1598531306 | Sep 04 12:41:56 PM UTC 24 | Sep 04 12:42:05 PM UTC 24 | 29229320 ps | ||
| T1139 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.1231454165 | Sep 04 12:41:56 PM UTC 24 | Sep 04 12:42:05 PM UTC 24 | 41166806 ps | ||
| T1140 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.2308730299 | Sep 04 12:41:56 PM UTC 24 | Sep 04 12:42:05 PM UTC 24 | 41161932 ps | ||
| T1141 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.4216318796 | Sep 04 12:41:57 PM UTC 24 | Sep 04 12:42:06 PM UTC 24 | 21715671 ps | ||
| T1142 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.1458666412 | Sep 04 12:41:57 PM UTC 24 | Sep 04 12:42:06 PM UTC 24 | 57229766 ps | ||
| T1143 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.199934723 | Sep 04 12:41:57 PM UTC 24 | Sep 04 12:42:06 PM UTC 24 | 36537151 ps | ||
| T1144 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.555696194 | Sep 04 12:41:57 PM UTC 24 | Sep 04 12:42:06 PM UTC 24 | 29701360 ps | ||
| T1145 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.3742679937 | Sep 04 12:41:57 PM UTC 24 | Sep 04 12:42:06 PM UTC 24 | 17753231 ps | ||
| T1146 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.2689556108 | Sep 04 12:41:57 PM UTC 24 | Sep 04 12:42:06 PM UTC 24 | 21089059 ps | ||
| T1147 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.2437617137 | Sep 04 12:41:57 PM UTC 24 | Sep 04 12:42:06 PM UTC 24 | 29624418 ps | ||
| T1148 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.2445740597 | Sep 04 12:41:57 PM UTC 24 | Sep 04 12:42:06 PM UTC 24 | 25509741 ps | ||
| T1149 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.2563409603 | Sep 04 12:41:43 PM UTC 24 | Sep 04 12:42:08 PM UTC 24 | 1972232136 ps | ||
| T1150 | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.3674948067 | Sep 04 12:41:51 PM UTC 24 | Sep 04 12:42:12 PM UTC 24 | 966646547 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.900575929 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 370064424 ps |
| CPU time | 3.53 seconds |
| Started | Sep 04 08:23:08 AM UTC 24 |
| Finished | Sep 04 08:23:13 AM UTC 24 |
| Peak memory | 235224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900575929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.900575929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2521432417 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 2254761407 ps |
| CPU time | 51.13 seconds |
| Started | Sep 04 08:24:04 AM UTC 24 |
| Finished | Sep 04 08:24:57 AM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521432417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.2521432417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.3891022778 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2141954406 ps |
| CPU time | 8.71 seconds |
| Started | Sep 04 08:23:23 AM UTC 24 |
| Finished | Sep 04 08:23:33 AM UTC 24 |
| Peak memory | 231860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891022778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3891022778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.3656280550 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 7539132104 ps |
| CPU time | 128.36 seconds |
| Started | Sep 04 08:23:15 AM UTC 24 |
| Finished | Sep 04 08:25:26 AM UTC 24 |
| Peak memory | 278752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656280550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3656280550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.45805882 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 4711042227 ps |
| CPU time | 38.15 seconds |
| Started | Sep 04 08:24:25 AM UTC 24 |
| Finished | Sep 04 08:25:05 AM UTC 24 |
| Peak memory | 262180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45805882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.45805882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.2203783089 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2399017937 ps |
| CPU time | 22.77 seconds |
| Started | Sep 04 08:25:17 AM UTC 24 |
| Finished | Sep 04 08:25:41 AM UTC 24 |
| Peak memory | 245908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203783089 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.2203783089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2565302348 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 209113940 ps |
| CPU time | 2.41 seconds |
| Started | Sep 04 12:41:29 PM UTC 24 |
| Finished | Sep 04 12:41:33 PM UTC 24 |
| Peak memory | 226240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2565302348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2565302348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.3215344951 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9842705379 ps |
| CPU time | 148.19 seconds |
| Started | Sep 04 08:23:34 AM UTC 24 |
| Finished | Sep 04 08:26:05 AM UTC 24 |
| Peak memory | 268440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215344951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3215344951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.1245615084 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 3417065523 ps |
| CPU time | 21.87 seconds |
| Started | Sep 04 08:23:30 AM UTC 24 |
| Finished | Sep 04 08:23:53 AM UTC 24 |
| Peak memory | 262028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245615084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1245615084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.3505066791 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 42054905 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 08:23:02 AM UTC 24 |
| Finished | Sep 04 08:23:05 AM UTC 24 |
| Peak memory | 225668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505066791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3505066791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.1463062160 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 27549310069 ps |
| CPU time | 172.9 seconds |
| Started | Sep 04 08:23:36 AM UTC 24 |
| Finished | Sep 04 08:26:32 AM UTC 24 |
| Peak memory | 264200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463062160 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.1463062160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.3062779890 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 4842491942 ps |
| CPU time | 130.87 seconds |
| Started | Sep 04 08:25:45 AM UTC 24 |
| Finished | Sep 04 08:27:59 AM UTC 24 |
| Peak memory | 282856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062779890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.3062779890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.3686586666 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 33764250981 ps |
| CPU time | 145.77 seconds |
| Started | Sep 04 08:26:32 AM UTC 24 |
| Finished | Sep 04 08:29:00 AM UTC 24 |
| Peak memory | 278724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686586666 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.3686586666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.3383737834 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 372535692 ps |
| CPU time | 1.83 seconds |
| Started | Sep 04 08:23:17 AM UTC 24 |
| Finished | Sep 04 08:23:19 AM UTC 24 |
| Peak memory | 257740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383737834 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3383737834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.1054844158 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 8286291239 ps |
| CPU time | 23.6 seconds |
| Started | Sep 04 08:23:30 AM UTC 24 |
| Finished | Sep 04 08:23:55 AM UTC 24 |
| Peak memory | 235492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054844158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1054844158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.3537090356 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 123056896771 ps |
| CPU time | 309.25 seconds |
| Started | Sep 04 08:26:14 AM UTC 24 |
| Finished | Sep 04 08:31:28 AM UTC 24 |
| Peak memory | 278668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537090356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.3537090356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.3354435036 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 150968719596 ps |
| CPU time | 317.86 seconds |
| Started | Sep 04 08:24:46 AM UTC 24 |
| Finished | Sep 04 08:30:08 AM UTC 24 |
| Peak memory | 278468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354435036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3354435036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.3640094670 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 6563479913 ps |
| CPU time | 18.27 seconds |
| Started | Sep 04 08:23:47 AM UTC 24 |
| Finished | Sep 04 08:24:06 AM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640094670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3640094670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.4148749156 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27688335020 ps |
| CPU time | 139.66 seconds |
| Started | Sep 04 08:25:58 AM UTC 24 |
| Finished | Sep 04 08:28:20 AM UTC 24 |
| Peak memory | 264168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148749156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.4148749156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.4275134425 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 17845823301 ps |
| CPU time | 232 seconds |
| Started | Sep 04 08:29:57 AM UTC 24 |
| Finished | Sep 04 08:33:53 AM UTC 24 |
| Peak memory | 295172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275134425 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.4275134425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/22.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3819148204 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 2985254639 ps |
| CPU time | 17.18 seconds |
| Started | Sep 04 12:41:16 PM UTC 24 |
| Finished | Sep 04 12:41:34 PM UTC 24 |
| Peak memory | 224200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819148204 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.3819148204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3031428542 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 20225399 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 12:41:16 PM UTC 24 |
| Finished | Sep 04 12:41:18 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031428542 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3031428542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.3801176326 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 2653819807 ps |
| CPU time | 97.83 seconds |
| Started | Sep 04 08:26:01 AM UTC 24 |
| Finished | Sep 04 08:27:41 AM UTC 24 |
| Peak memory | 262336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801176326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.3801176326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_stress_all.1166953981 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 11318111863 ps |
| CPU time | 178.8 seconds |
| Started | Sep 04 08:30:30 AM UTC 24 |
| Finished | Sep 04 08:33:32 AM UTC 24 |
| Peak memory | 278728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166953981 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.1166953981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/24.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3683858227 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 212896301 ps |
| CPU time | 4.29 seconds |
| Started | Sep 04 12:41:20 PM UTC 24 |
| Finished | Sep 04 12:41:34 PM UTC 24 |
| Peak memory | 224468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683858227 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3683858227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.371657099 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 26230815 ps |
| CPU time | 1.55 seconds |
| Started | Sep 04 08:23:44 AM UTC 24 |
| Finished | Sep 04 08:23:46 AM UTC 24 |
| Peak memory | 229200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371657099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_parity.371657099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.1002131028 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 9662980066 ps |
| CPU time | 9.76 seconds |
| Started | Sep 04 08:23:04 AM UTC 24 |
| Finished | Sep 04 08:23:15 AM UTC 24 |
| Peak memory | 228088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002131028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1002131028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.113809247 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 65827638882 ps |
| CPU time | 577.57 seconds |
| Started | Sep 04 08:24:50 AM UTC 24 |
| Finished | Sep 04 08:34:34 AM UTC 24 |
| Peak memory | 268516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113809247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.113809247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.2229900959 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 16837497249 ps |
| CPU time | 28.8 seconds |
| Started | Sep 04 08:23:12 AM UTC 24 |
| Finished | Sep 04 08:23:42 AM UTC 24 |
| Peak memory | 235412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229900959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.2229900959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.2875462208 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 164908212180 ps |
| CPU time | 232.04 seconds |
| Started | Sep 04 08:27:20 AM UTC 24 |
| Finished | Sep 04 08:31:15 AM UTC 24 |
| Peak memory | 278724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875462208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.2875462208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.4190850603 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 357015474548 ps |
| CPU time | 226.57 seconds |
| Started | Sep 04 08:23:15 AM UTC 24 |
| Finished | Sep 04 08:27:05 AM UTC 24 |
| Peak memory | 266440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190850603 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.4190850603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.1373971567 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 6072567522 ps |
| CPU time | 144.1 seconds |
| Started | Sep 04 08:31:27 AM UTC 24 |
| Finished | Sep 04 08:33:54 AM UTC 24 |
| Peak memory | 278536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373971567 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.1373971567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/27.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.2382400560 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 5019442494 ps |
| CPU time | 145.05 seconds |
| Started | Sep 04 08:30:29 AM UTC 24 |
| Finished | Sep 04 08:32:56 AM UTC 24 |
| Peak memory | 278424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382400560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.2382400560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.4240568060 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 7448268849 ps |
| CPU time | 56.85 seconds |
| Started | Sep 04 08:27:01 AM UTC 24 |
| Finished | Sep 04 08:28:00 AM UTC 24 |
| Peak memory | 268296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240568060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.4240568060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.3920094789 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 25012726 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 08:23:20 AM UTC 24 |
| Finished | Sep 04 08:23:22 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920094789 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3920094789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.3771806334 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 272261232 ps |
| CPU time | 4.69 seconds |
| Started | Sep 04 12:41:34 PM UTC 24 |
| Finished | Sep 04 12:41:46 PM UTC 24 |
| Peak memory | 224288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771806334 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3771806334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.1315152119 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 5559315060 ps |
| CPU time | 33.14 seconds |
| Started | Sep 04 08:24:47 AM UTC 24 |
| Finished | Sep 04 08:25:22 AM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315152119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1315152119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2585973903 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 6015759551 ps |
| CPU time | 20.36 seconds |
| Started | Sep 04 08:23:07 AM UTC 24 |
| Finished | Sep 04 08:23:29 AM UTC 24 |
| Peak memory | 245652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585973903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.2585973903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.2653564111 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 183008352564 ps |
| CPU time | 532.21 seconds |
| Started | Sep 04 08:26:49 AM UTC 24 |
| Finished | Sep 04 08:35:48 AM UTC 24 |
| Peak memory | 265960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653564111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.2653564111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.3870575859 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 3121613309 ps |
| CPU time | 45.94 seconds |
| Started | Sep 04 08:27:19 AM UTC 24 |
| Finished | Sep 04 08:28:06 AM UTC 24 |
| Peak memory | 264028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870575859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3870575859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.2683610794 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 25914289831 ps |
| CPU time | 222.79 seconds |
| Started | Sep 04 08:31:42 AM UTC 24 |
| Finished | Sep 04 08:35:28 AM UTC 24 |
| Peak memory | 280580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683610794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.2683610794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.945286151 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 62294716080 ps |
| CPU time | 52.51 seconds |
| Started | Sep 04 08:26:01 AM UTC 24 |
| Finished | Sep 04 08:26:55 AM UTC 24 |
| Peak memory | 262140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945286151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.945286151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.4172433616 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 27808879413 ps |
| CPU time | 250.53 seconds |
| Started | Sep 04 08:28:56 AM UTC 24 |
| Finished | Sep 04 08:33:10 AM UTC 24 |
| Peak memory | 276424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172433616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.4172433616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.2551457064 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 29869235432 ps |
| CPU time | 122.05 seconds |
| Started | Sep 04 08:23:58 AM UTC 24 |
| Finished | Sep 04 08:26:02 AM UTC 24 |
| Peak memory | 264360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551457064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2551457064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_all.3405572050 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 39712349364 ps |
| CPU time | 142.7 seconds |
| Started | Sep 04 08:31:41 AM UTC 24 |
| Finished | Sep 04 08:34:06 AM UTC 24 |
| Peak memory | 284872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405572050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3405572050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/28.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode.1842222081 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 383059304 ps |
| CPU time | 10.18 seconds |
| Started | Sep 04 08:32:20 AM UTC 24 |
| Finished | Sep 04 08:32:32 AM UTC 24 |
| Peak memory | 249868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842222081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1842222081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/30.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.687479228 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 38480625569 ps |
| CPU time | 211.47 seconds |
| Started | Sep 04 08:33:19 AM UTC 24 |
| Finished | Sep 04 08:36:54 AM UTC 24 |
| Peak memory | 262372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687479228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.687479228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.2859912632 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 13340195824 ps |
| CPU time | 191.21 seconds |
| Started | Sep 04 08:36:40 AM UTC 24 |
| Finished | Sep 04 08:39:54 AM UTC 24 |
| Peak memory | 282564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859912632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.2859912632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.393519201 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 87541619352 ps |
| CPU time | 109.98 seconds |
| Started | Sep 04 08:26:17 AM UTC 24 |
| Finished | Sep 04 08:28:09 AM UTC 24 |
| Peak memory | 264424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393519201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.393519201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.480960348 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 646282564 ps |
| CPU time | 7.27 seconds |
| Started | Sep 04 08:24:12 AM UTC 24 |
| Finished | Sep 04 08:24:21 AM UTC 24 |
| Peak memory | 245588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480960348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.480960348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.4154259079 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 89664465 ps |
| CPU time | 2.97 seconds |
| Started | Sep 04 12:41:29 PM UTC 24 |
| Finished | Sep 04 12:41:34 PM UTC 24 |
| Peak memory | 224268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154259079 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.4154259079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.42773364 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 422550421 ps |
| CPU time | 6.08 seconds |
| Started | Sep 04 12:41:39 PM UTC 24 |
| Finished | Sep 04 12:41:49 PM UTC 24 |
| Peak memory | 226180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42773364 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.42773364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1268006438 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 281319125 ps |
| CPU time | 6.98 seconds |
| Started | Sep 04 12:41:25 PM UTC 24 |
| Finished | Sep 04 12:41:36 PM UTC 24 |
| Peak memory | 226192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268006438 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.1268006438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.4290474426 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 15155279223 ps |
| CPU time | 24.58 seconds |
| Started | Sep 04 08:27:16 AM UTC 24 |
| Finished | Sep 04 08:27:42 AM UTC 24 |
| Peak memory | 262088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290474426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.4290474426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.4279347940 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 3923123522 ps |
| CPU time | 89.84 seconds |
| Started | Sep 04 08:30:28 AM UTC 24 |
| Finished | Sep 04 08:31:59 AM UTC 24 |
| Peak memory | 284644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279347940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.4279347940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/24.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.3958234793 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 125339670027 ps |
| CPU time | 272.05 seconds |
| Started | Sep 04 08:32:04 AM UTC 24 |
| Finished | Sep 04 08:36:40 AM UTC 24 |
| Peak memory | 268452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958234793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3958234793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/29.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.2178876672 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 10221400082 ps |
| CPU time | 28.62 seconds |
| Started | Sep 04 08:34:51 AM UTC 24 |
| Finished | Sep 04 08:35:21 AM UTC 24 |
| Peak memory | 249808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178876672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2178876672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/39.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.2672385824 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 20489150715 ps |
| CPU time | 14.73 seconds |
| Started | Sep 04 08:26:30 AM UTC 24 |
| Finished | Sep 04 08:26:46 AM UTC 24 |
| Peak memory | 233972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672385824 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.2672385824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3445642915 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 129871283 ps |
| CPU time | 1.29 seconds |
| Started | Sep 04 12:41:16 PM UTC 24 |
| Finished | Sep 04 12:41:18 PM UTC 24 |
| Peak memory | 225284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445642915 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.3445642915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.3485102652 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 31034511 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 08:23:01 AM UTC 24 |
| Finished | Sep 04 08:23:03 AM UTC 24 |
| Peak memory | 215608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485102652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3485102652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.3955965965 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 22139555978 ps |
| CPU time | 154.57 seconds |
| Started | Sep 04 08:32:48 AM UTC 24 |
| Finished | Sep 04 08:35:26 AM UTC 24 |
| Peak memory | 262216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955965965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3955965965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2879674654 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1520005577 ps |
| CPU time | 14.18 seconds |
| Started | Sep 04 12:41:16 PM UTC 24 |
| Finished | Sep 04 12:41:32 PM UTC 24 |
| Peak memory | 224076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879674654 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.2879674654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3291634061 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 3565777655 ps |
| CPU time | 22.48 seconds |
| Started | Sep 04 12:41:16 PM UTC 24 |
| Finished | Sep 04 12:41:40 PM UTC 24 |
| Peak memory | 224172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291634061 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.3291634061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2104371719 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 45781797 ps |
| CPU time | 2.92 seconds |
| Started | Sep 04 12:41:16 PM UTC 24 |
| Finished | Sep 04 12:41:20 PM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2104371719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2104371719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.1991795799 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 14462661 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 12:41:16 PM UTC 24 |
| Finished | Sep 04 12:41:18 PM UTC 24 |
| Peak memory | 211784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991795799 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1991795799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.3179200655 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 171522899 ps |
| CPU time | 1.3 seconds |
| Started | Sep 04 12:41:16 PM UTC 24 |
| Finished | Sep 04 12:41:18 PM UTC 24 |
| Peak memory | 222928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179200655 -assert nopostp roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.3179200655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.3796973177 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 31430836 ps |
| CPU time | 0.6 seconds |
| Started | Sep 04 12:41:16 PM UTC 24 |
| Finished | Sep 04 12:41:18 PM UTC 24 |
| Peak memory | 211384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796973177 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.3796973177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1928501289 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 422089524 ps |
| CPU time | 2.62 seconds |
| Started | Sep 04 12:41:16 PM UTC 24 |
| Finished | Sep 04 12:41:20 PM UTC 24 |
| Peak memory | 226180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928501289 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstanding.1928501289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.3108590477 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 442721847 ps |
| CPU time | 3.14 seconds |
| Started | Sep 04 12:41:14 PM UTC 24 |
| Finished | Sep 04 12:41:25 PM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108590477 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3108590477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3562485868 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 224468614 ps |
| CPU time | 6.69 seconds |
| Started | Sep 04 12:41:20 PM UTC 24 |
| Finished | Sep 04 12:41:29 PM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562485868 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.3562485868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2558291911 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 2189822993 ps |
| CPU time | 19.2 seconds |
| Started | Sep 04 12:41:20 PM UTC 24 |
| Finished | Sep 04 12:41:42 PM UTC 24 |
| Peak memory | 223344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558291911 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.2558291911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1360621730 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 47198395 ps |
| CPU time | 0.92 seconds |
| Started | Sep 04 12:41:19 PM UTC 24 |
| Finished | Sep 04 12:41:28 PM UTC 24 |
| Peak memory | 213416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360621730 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.1360621730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.247238274 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 158970527 ps |
| CPU time | 2.69 seconds |
| Started | Sep 04 12:41:20 PM UTC 24 |
| Finished | Sep 04 12:41:32 PM UTC 24 |
| Peak memory | 226444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=247238274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.247238274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.1580593231 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 29442182 ps |
| CPU time | 1.62 seconds |
| Started | Sep 04 12:41:19 PM UTC 24 |
| Finished | Sep 04 12:41:29 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580593231 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1580593231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.701510721 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 51301448 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 12:41:19 PM UTC 24 |
| Finished | Sep 04 12:41:31 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701510721 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.701510721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.4168076952 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 22775138 ps |
| CPU time | 1.6 seconds |
| Started | Sep 04 12:41:19 PM UTC 24 |
| Finished | Sep 04 12:41:32 PM UTC 24 |
| Peak memory | 222928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168076952 -assert nopostp roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.4168076952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2647555932 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 14619519 ps |
| CPU time | 0.62 seconds |
| Started | Sep 04 12:41:19 PM UTC 24 |
| Finished | Sep 04 12:41:31 PM UTC 24 |
| Peak memory | 211192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647555932 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.2647555932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1761173665 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 67482849 ps |
| CPU time | 1.7 seconds |
| Started | Sep 04 12:41:20 PM UTC 24 |
| Finished | Sep 04 12:41:24 PM UTC 24 |
| Peak memory | 223528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761173665 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstanding.1761173665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1606253793 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 284937814 ps |
| CPU time | 2.87 seconds |
| Started | Sep 04 12:41:16 PM UTC 24 |
| Finished | Sep 04 12:41:20 PM UTC 24 |
| Peak memory | 224272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606253793 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1606253793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.4147615364 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 798839001 ps |
| CPU time | 15.73 seconds |
| Started | Sep 04 12:41:19 PM UTC 24 |
| Finished | Sep 04 12:41:46 PM UTC 24 |
| Peak memory | 224080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147615364 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.4147615364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1093991330 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 256292906 ps |
| CPU time | 3.52 seconds |
| Started | Sep 04 12:41:40 PM UTC 24 |
| Finished | Sep 04 12:41:46 PM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1093991330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1093991330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.1273185997 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 116333512 ps |
| CPU time | 1.76 seconds |
| Started | Sep 04 12:41:39 PM UTC 24 |
| Finished | Sep 04 12:41:45 PM UTC 24 |
| Peak memory | 212668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273185997 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.1273185997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.2549200055 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 55435745 ps |
| CPU time | 0.9 seconds |
| Started | Sep 04 12:41:39 PM UTC 24 |
| Finished | Sep 04 12:41:44 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549200055 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.2549200055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3141989273 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 160744254 ps |
| CPU time | 3.58 seconds |
| Started | Sep 04 12:41:39 PM UTC 24 |
| Finished | Sep 04 12:41:47 PM UTC 24 |
| Peak memory | 224080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141989273 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstanding.3141989273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.4182563650 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 97481438 ps |
| CPU time | 1.57 seconds |
| Started | Sep 04 12:41:37 PM UTC 24 |
| Finished | Sep 04 12:41:39 PM UTC 24 |
| Peak memory | 223260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182563650 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.4182563650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2761973327 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 207370649 ps |
| CPU time | 3.31 seconds |
| Started | Sep 04 12:41:40 PM UTC 24 |
| Finished | Sep 04 12:41:46 PM UTC 24 |
| Peak memory | 228312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2761973327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2761973327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.3564941773 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 585112424 ps |
| CPU time | 2.39 seconds |
| Started | Sep 04 12:41:40 PM UTC 24 |
| Finished | Sep 04 12:41:45 PM UTC 24 |
| Peak memory | 224156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564941773 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.3564941773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.1669626755 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 96494336 ps |
| CPU time | 0.96 seconds |
| Started | Sep 04 12:41:40 PM UTC 24 |
| Finished | Sep 04 12:41:43 PM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669626755 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.1669626755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1558879974 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 57821611 ps |
| CPU time | 1.8 seconds |
| Started | Sep 04 12:41:40 PM UTC 24 |
| Finished | Sep 04 12:41:44 PM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558879974 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstanding.1558879974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3461869389 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 435911865 ps |
| CPU time | 3.39 seconds |
| Started | Sep 04 12:41:40 PM UTC 24 |
| Finished | Sep 04 12:41:46 PM UTC 24 |
| Peak memory | 226516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461869389 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.3461869389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.3485634817 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 286723447 ps |
| CPU time | 15.93 seconds |
| Started | Sep 04 12:41:40 PM UTC 24 |
| Finished | Sep 04 12:41:59 PM UTC 24 |
| Peak memory | 224156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485634817 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.3485634817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2959657017 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 243833727 ps |
| CPU time | 3.59 seconds |
| Started | Sep 04 12:41:43 PM UTC 24 |
| Finished | Sep 04 12:41:51 PM UTC 24 |
| Peak memory | 228324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2959657017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2959657017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.3159737208 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 99569374 ps |
| CPU time | 1.78 seconds |
| Started | Sep 04 12:41:43 PM UTC 24 |
| Finished | Sep 04 12:41:49 PM UTC 24 |
| Peak memory | 212668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159737208 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.3159737208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.956721959 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 63560900 ps |
| CPU time | 0.85 seconds |
| Started | Sep 04 12:41:43 PM UTC 24 |
| Finished | Sep 04 12:41:48 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956721959 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.956721959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1127149754 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 235790768 ps |
| CPU time | 2.89 seconds |
| Started | Sep 04 12:41:43 PM UTC 24 |
| Finished | Sep 04 12:41:50 PM UTC 24 |
| Peak memory | 224140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127149754 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstanding.1127149754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.3644130124 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 293597366 ps |
| CPU time | 3.04 seconds |
| Started | Sep 04 12:41:41 PM UTC 24 |
| Finished | Sep 04 12:41:46 PM UTC 24 |
| Peak memory | 226064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644130124 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.3644130124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.2189074599 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 935081126 ps |
| CPU time | 11.6 seconds |
| Started | Sep 04 12:41:41 PM UTC 24 |
| Finished | Sep 04 12:41:54 PM UTC 24 |
| Peak memory | 226448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189074599 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.2189074599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2453241123 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 119119953 ps |
| CPU time | 2.05 seconds |
| Started | Sep 04 12:41:43 PM UTC 24 |
| Finished | Sep 04 12:41:49 PM UTC 24 |
| Peak memory | 226448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2453241123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2453241123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.298895747 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 168967112 ps |
| CPU time | 1.53 seconds |
| Started | Sep 04 12:41:43 PM UTC 24 |
| Finished | Sep 04 12:41:49 PM UTC 24 |
| Peak memory | 222864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298895747 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.298895747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.3533939785 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 20284820 ps |
| CPU time | 0.87 seconds |
| Started | Sep 04 12:41:43 PM UTC 24 |
| Finished | Sep 04 12:41:48 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533939785 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.3533939785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4214396803 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 160781056 ps |
| CPU time | 1.93 seconds |
| Started | Sep 04 12:41:43 PM UTC 24 |
| Finished | Sep 04 12:41:49 PM UTC 24 |
| Peak memory | 223200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214396803 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstanding.4214396803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.3933060542 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 84636073 ps |
| CPU time | 4.85 seconds |
| Started | Sep 04 12:41:43 PM UTC 24 |
| Finished | Sep 04 12:41:52 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933060542 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.3933060542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.3962551873 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 103438140 ps |
| CPU time | 5.76 seconds |
| Started | Sep 04 12:41:43 PM UTC 24 |
| Finished | Sep 04 12:41:53 PM UTC 24 |
| Peak memory | 226184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962551873 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.3962551873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1766510664 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 89064633 ps |
| CPU time | 2.82 seconds |
| Started | Sep 04 12:41:45 PM UTC 24 |
| Finished | Sep 04 12:41:50 PM UTC 24 |
| Peak memory | 226248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1766510664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1766510664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.338944820 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 20359095 ps |
| CPU time | 1.53 seconds |
| Started | Sep 04 12:41:45 PM UTC 24 |
| Finished | Sep 04 12:41:49 PM UTC 24 |
| Peak memory | 222884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338944820 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.338944820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.2712481577 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 25244191 ps |
| CPU time | 0.85 seconds |
| Started | Sep 04 12:41:45 PM UTC 24 |
| Finished | Sep 04 12:41:48 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712481577 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.2712481577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2192812536 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 146925101 ps |
| CPU time | 3.43 seconds |
| Started | Sep 04 12:41:45 PM UTC 24 |
| Finished | Sep 04 12:41:51 PM UTC 24 |
| Peak memory | 224244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192812536 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstanding.2192812536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.413176800 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 27475953 ps |
| CPU time | 1.61 seconds |
| Started | Sep 04 12:41:43 PM UTC 24 |
| Finished | Sep 04 12:41:49 PM UTC 24 |
| Peak memory | 223240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413176800 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.413176800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.2563409603 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 1972232136 ps |
| CPU time | 20.2 seconds |
| Started | Sep 04 12:41:43 PM UTC 24 |
| Finished | Sep 04 12:42:08 PM UTC 24 |
| Peak memory | 226192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563409603 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.2563409603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.200268087 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 173513565 ps |
| CPU time | 1.73 seconds |
| Started | Sep 04 12:41:48 PM UTC 24 |
| Finished | Sep 04 12:41:54 PM UTC 24 |
| Peak memory | 225044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=200268087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.200268087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.1727347905 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 219530193 ps |
| CPU time | 2.16 seconds |
| Started | Sep 04 12:41:48 PM UTC 24 |
| Finished | Sep 04 12:41:54 PM UTC 24 |
| Peak memory | 213836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727347905 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.1727347905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2132602170 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 37035636 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 12:41:48 PM UTC 24 |
| Finished | Sep 04 12:41:49 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132602170 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.2132602170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3025389396 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 58539005 ps |
| CPU time | 1.91 seconds |
| Started | Sep 04 12:41:48 PM UTC 24 |
| Finished | Sep 04 12:41:54 PM UTC 24 |
| Peak memory | 213312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025389396 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstanding.3025389396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.3099490288 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 82705753 ps |
| CPU time | 2.81 seconds |
| Started | Sep 04 12:41:45 PM UTC 24 |
| Finished | Sep 04 12:41:50 PM UTC 24 |
| Peak memory | 224280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099490288 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.3099490288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.3416238707 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 1316725566 ps |
| CPU time | 15.27 seconds |
| Started | Sep 04 12:41:45 PM UTC 24 |
| Finished | Sep 04 12:42:03 PM UTC 24 |
| Peak memory | 226388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416238707 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.3416238707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1172781489 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 94139448 ps |
| CPU time | 2.11 seconds |
| Started | Sep 04 12:41:50 PM UTC 24 |
| Finished | Sep 04 12:41:55 PM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1172781489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1172781489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.2460409985 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 72675522 ps |
| CPU time | 1.4 seconds |
| Started | Sep 04 12:41:48 PM UTC 24 |
| Finished | Sep 04 12:41:54 PM UTC 24 |
| Peak memory | 212712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460409985 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.2460409985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.683896523 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 28960614 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 12:41:48 PM UTC 24 |
| Finished | Sep 04 12:41:53 PM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683896523 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.683896523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1316672990 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 419294282 ps |
| CPU time | 1.98 seconds |
| Started | Sep 04 12:41:48 PM UTC 24 |
| Finished | Sep 04 12:41:54 PM UTC 24 |
| Peak memory | 223576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316672990 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstanding.1316672990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.62530351 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 525712933 ps |
| CPU time | 3.62 seconds |
| Started | Sep 04 12:41:48 PM UTC 24 |
| Finished | Sep 04 12:41:56 PM UTC 24 |
| Peak memory | 224236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62530351 -assert nopostproc +UVM_TESTNAME=spi _device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.62530351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.3951713247 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 3336677990 ps |
| CPU time | 6.9 seconds |
| Started | Sep 04 12:41:48 PM UTC 24 |
| Finished | Sep 04 12:41:59 PM UTC 24 |
| Peak memory | 224208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951713247 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.3951713247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4257369546 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 43825233 ps |
| CPU time | 2.6 seconds |
| Started | Sep 04 12:41:51 PM UTC 24 |
| Finished | Sep 04 12:41:55 PM UTC 24 |
| Peak memory | 228432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4257369546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.4257369546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.347127798 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 350427162 ps |
| CPU time | 2.72 seconds |
| Started | Sep 04 12:41:51 PM UTC 24 |
| Finished | Sep 04 12:41:55 PM UTC 24 |
| Peak memory | 224136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347127798 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.347127798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.3221801047 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 95068519 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 12:41:51 PM UTC 24 |
| Finished | Sep 04 12:41:53 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221801047 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.3221801047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3637981938 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 150680542 ps |
| CPU time | 3.63 seconds |
| Started | Sep 04 12:41:51 PM UTC 24 |
| Finished | Sep 04 12:41:56 PM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637981938 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstanding.3637981938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.3676298456 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 652306413 ps |
| CPU time | 3.87 seconds |
| Started | Sep 04 12:41:50 PM UTC 24 |
| Finished | Sep 04 12:41:56 PM UTC 24 |
| Peak memory | 226304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676298456 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.3676298456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.2197677430 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 1604433056 ps |
| CPU time | 8.2 seconds |
| Started | Sep 04 12:41:50 PM UTC 24 |
| Finished | Sep 04 12:42:01 PM UTC 24 |
| Peak memory | 226192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197677430 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.2197677430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4007421121 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 54943844 ps |
| CPU time | 1.59 seconds |
| Started | Sep 04 12:41:51 PM UTC 24 |
| Finished | Sep 04 12:41:54 PM UTC 24 |
| Peak memory | 222992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4007421121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.4007421121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.945990566 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 102799250 ps |
| CPU time | 1.89 seconds |
| Started | Sep 04 12:41:51 PM UTC 24 |
| Finished | Sep 04 12:41:55 PM UTC 24 |
| Peak memory | 222884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945990566 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.945990566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.1988993392 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 33788485 ps |
| CPU time | 0.9 seconds |
| Started | Sep 04 12:41:51 PM UTC 24 |
| Finished | Sep 04 12:41:54 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988993392 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.1988993392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1040745368 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 60760323 ps |
| CPU time | 3.36 seconds |
| Started | Sep 04 12:41:51 PM UTC 24 |
| Finished | Sep 04 12:41:55 PM UTC 24 |
| Peak memory | 224440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040745368 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstanding.1040745368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.3953481195 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 29688561 ps |
| CPU time | 2.03 seconds |
| Started | Sep 04 12:41:51 PM UTC 24 |
| Finished | Sep 04 12:41:55 PM UTC 24 |
| Peak memory | 224468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953481195 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.3953481195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.3674948067 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 966646547 ps |
| CPU time | 18.52 seconds |
| Started | Sep 04 12:41:51 PM UTC 24 |
| Finished | Sep 04 12:42:12 PM UTC 24 |
| Peak memory | 226212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674948067 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.3674948067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3077690043 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 521195688 ps |
| CPU time | 3.31 seconds |
| Started | Sep 04 12:41:53 PM UTC 24 |
| Finished | Sep 04 12:42:01 PM UTC 24 |
| Peak memory | 226272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3077690043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3077690043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.3184879295 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 44092475 ps |
| CPU time | 1.39 seconds |
| Started | Sep 04 12:41:53 PM UTC 24 |
| Finished | Sep 04 12:41:55 PM UTC 24 |
| Peak memory | 222888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184879295 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.3184879295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.4122313042 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 15128689 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 12:41:53 PM UTC 24 |
| Finished | Sep 04 12:41:58 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122313042 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.4122313042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.196327093 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 57766486 ps |
| CPU time | 1.72 seconds |
| Started | Sep 04 12:41:53 PM UTC 24 |
| Finished | Sep 04 12:41:59 PM UTC 24 |
| Peak memory | 223532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196327093 -assert nopost proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstanding.196327093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.1224576255 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 323555663 ps |
| CPU time | 2.4 seconds |
| Started | Sep 04 12:41:52 PM UTC 24 |
| Finished | Sep 04 12:41:55 PM UTC 24 |
| Peak memory | 226324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224576255 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.1224576255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.628841792 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 191964973 ps |
| CPU time | 5.87 seconds |
| Started | Sep 04 12:41:53 PM UTC 24 |
| Finished | Sep 04 12:42:03 PM UTC 24 |
| Peak memory | 224064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628841792 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.628841792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.622248093 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 293704209 ps |
| CPU time | 18.32 seconds |
| Started | Sep 04 12:41:24 PM UTC 24 |
| Finished | Sep 04 12:41:47 PM UTC 24 |
| Peak memory | 224140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622248093 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.622248093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2901503288 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 527970447 ps |
| CPU time | 29.33 seconds |
| Started | Sep 04 12:41:22 PM UTC 24 |
| Finished | Sep 04 12:42:00 PM UTC 24 |
| Peak memory | 216160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901503288 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.2901503288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3330155692 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 69185804 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 12:41:22 PM UTC 24 |
| Finished | Sep 04 12:41:31 PM UTC 24 |
| Peak memory | 225164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330155692 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.3330155692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2669527791 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 466681099 ps |
| CPU time | 1.97 seconds |
| Started | Sep 04 12:41:25 PM UTC 24 |
| Finished | Sep 04 12:41:31 PM UTC 24 |
| Peak memory | 225040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2669527791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2669527791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.1252021769 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 224367087 ps |
| CPU time | 1.58 seconds |
| Started | Sep 04 12:41:22 PM UTC 24 |
| Finished | Sep 04 12:41:31 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252021769 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1252021769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.398553370 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 11437150 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 12:41:20 PM UTC 24 |
| Finished | Sep 04 12:41:30 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398553370 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.398553370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.2912961178 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 47031123 ps |
| CPU time | 1.72 seconds |
| Started | Sep 04 12:41:22 PM UTC 24 |
| Finished | Sep 04 12:41:32 PM UTC 24 |
| Peak memory | 222392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912961178 -assert nopostp roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.2912961178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.3554762300 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 39211649 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 12:41:22 PM UTC 24 |
| Finished | Sep 04 12:41:31 PM UTC 24 |
| Peak memory | 210848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554762300 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.3554762300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3612862891 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 475932700 ps |
| CPU time | 2.61 seconds |
| Started | Sep 04 12:41:24 PM UTC 24 |
| Finished | Sep 04 12:41:31 PM UTC 24 |
| Peak memory | 224332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612862891 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstanding.3612862891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.2108568482 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1134575774 ps |
| CPU time | 12.57 seconds |
| Started | Sep 04 12:41:20 PM UTC 24 |
| Finished | Sep 04 12:41:42 PM UTC 24 |
| Peak memory | 224400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108568482 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.2108568482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.130315781 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 44575271 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 12:41:55 PM UTC 24 |
| Finished | Sep 04 12:42:03 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130315781 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.130315781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/20.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.1036205808 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 21959240 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 12:41:55 PM UTC 24 |
| Finished | Sep 04 12:42:03 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036205808 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.1036205808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/21.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.2197350371 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 79553379 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 12:41:55 PM UTC 24 |
| Finished | Sep 04 12:42:04 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197350371 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.2197350371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/22.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.814892465 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 76519253 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 12:41:55 PM UTC 24 |
| Finished | Sep 04 12:42:04 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814892465 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.814892465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/23.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.4209643996 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 42492410 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 12:41:55 PM UTC 24 |
| Finished | Sep 04 12:42:04 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209643996 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.4209643996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/24.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.570682721 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 14069722 ps |
| CPU time | 0.8 seconds |
| Started | Sep 04 12:41:55 PM UTC 24 |
| Finished | Sep 04 12:41:58 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570682721 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.570682721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/25.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.1168938970 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 11801547 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 12:41:55 PM UTC 24 |
| Finished | Sep 04 12:42:04 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168938970 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.1168938970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/26.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.3891568611 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 11772531 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 12:41:55 PM UTC 24 |
| Finished | Sep 04 12:41:58 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891568611 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.3891568611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/27.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.4096517355 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 17792996 ps |
| CPU time | 0.83 seconds |
| Started | Sep 04 12:41:55 PM UTC 24 |
| Finished | Sep 04 12:41:58 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096517355 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.4096517355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/28.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.1710826218 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 26549622 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 12:41:55 PM UTC 24 |
| Finished | Sep 04 12:41:58 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710826218 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.1710826218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/29.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.3954828343 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 115817544 ps |
| CPU time | 6.92 seconds |
| Started | Sep 04 12:41:28 PM UTC 24 |
| Finished | Sep 04 12:41:36 PM UTC 24 |
| Peak memory | 215876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954828343 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.3954828343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3315200975 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 7511818245 ps |
| CPU time | 24.59 seconds |
| Started | Sep 04 12:41:28 PM UTC 24 |
| Finished | Sep 04 12:41:54 PM UTC 24 |
| Peak memory | 214220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315200975 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.3315200975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3688852930 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 22792216 ps |
| CPU time | 1.23 seconds |
| Started | Sep 04 12:41:26 PM UTC 24 |
| Finished | Sep 04 12:41:28 PM UTC 24 |
| Peak memory | 212784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688852930 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.3688852930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.1771868100 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 525542827 ps |
| CPU time | 1.88 seconds |
| Started | Sep 04 12:41:26 PM UTC 24 |
| Finished | Sep 04 12:41:29 PM UTC 24 |
| Peak memory | 222864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771868100 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1771868100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.1299459667 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 14868103 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 12:41:25 PM UTC 24 |
| Finished | Sep 04 12:41:29 PM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299459667 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1299459667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.3078386173 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 72877894 ps |
| CPU time | 1.28 seconds |
| Started | Sep 04 12:41:26 PM UTC 24 |
| Finished | Sep 04 12:41:28 PM UTC 24 |
| Peak memory | 222928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078386173 -assert nopostp roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.3078386173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.183170826 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 33535268 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 12:41:25 PM UTC 24 |
| Finished | Sep 04 12:41:29 PM UTC 24 |
| Peak memory | 211388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183170826 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.183170826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3920727152 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 28257348 ps |
| CPU time | 1.49 seconds |
| Started | Sep 04 12:41:29 PM UTC 24 |
| Finished | Sep 04 12:41:32 PM UTC 24 |
| Peak memory | 223468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920727152 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstanding.3920727152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.2357752277 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 711136609 ps |
| CPU time | 4.58 seconds |
| Started | Sep 04 12:41:25 PM UTC 24 |
| Finished | Sep 04 12:41:33 PM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357752277 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2357752277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.4081756153 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 59373695 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 12:41:55 PM UTC 24 |
| Finished | Sep 04 12:41:58 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081756153 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.4081756153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/30.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.1465118700 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 85721783 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 12:41:56 PM UTC 24 |
| Finished | Sep 04 12:41:58 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465118700 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.1465118700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/31.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.85360453 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 32925606 ps |
| CPU time | 0.66 seconds |
| Started | Sep 04 12:41:56 PM UTC 24 |
| Finished | Sep 04 12:41:58 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85360453 -assert nopostproc +UVM_TESTNAME=spi _device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.85360453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/32.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.3134490692 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 19880079 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 12:41:56 PM UTC 24 |
| Finished | Sep 04 12:41:58 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134490692 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.3134490692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/33.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.1633831693 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 14599549 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 12:41:56 PM UTC 24 |
| Finished | Sep 04 12:41:58 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633831693 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.1633831693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/34.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.918865401 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 29229943 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 12:41:56 PM UTC 24 |
| Finished | Sep 04 12:42:05 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918865401 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.918865401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/35.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.1231454165 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 41166806 ps |
| CPU time | 0.83 seconds |
| Started | Sep 04 12:41:56 PM UTC 24 |
| Finished | Sep 04 12:42:05 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231454165 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.1231454165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/36.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.1598531306 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 29229320 ps |
| CPU time | 0.85 seconds |
| Started | Sep 04 12:41:56 PM UTC 24 |
| Finished | Sep 04 12:42:05 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598531306 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.1598531306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/37.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.2308730299 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 41161932 ps |
| CPU time | 0.83 seconds |
| Started | Sep 04 12:41:56 PM UTC 24 |
| Finished | Sep 04 12:42:05 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308730299 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.2308730299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/38.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.4216318796 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 21715671 ps |
| CPU time | 0.87 seconds |
| Started | Sep 04 12:41:57 PM UTC 24 |
| Finished | Sep 04 12:42:06 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216318796 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.4216318796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/39.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.3560358429 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 2311968550 ps |
| CPU time | 18.19 seconds |
| Started | Sep 04 12:41:32 PM UTC 24 |
| Finished | Sep 04 12:41:51 PM UTC 24 |
| Peak memory | 224396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560358429 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.3560358429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2778187941 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 2523617584 ps |
| CPU time | 11.42 seconds |
| Started | Sep 04 12:41:32 PM UTC 24 |
| Finished | Sep 04 12:41:45 PM UTC 24 |
| Peak memory | 213928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778187941 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.2778187941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.555440526 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 65889340 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 12:41:31 PM UTC 24 |
| Finished | Sep 04 12:41:33 PM UTC 24 |
| Peak memory | 213008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555440526 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.555440526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1166744323 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 610348019 ps |
| CPU time | 3.41 seconds |
| Started | Sep 04 12:41:32 PM UTC 24 |
| Finished | Sep 04 12:41:36 PM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1166744323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1166744323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.2034624477 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 93185240 ps |
| CPU time | 2.59 seconds |
| Started | Sep 04 12:41:31 PM UTC 24 |
| Finished | Sep 04 12:41:34 PM UTC 24 |
| Peak memory | 224132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034624477 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2034624477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.1932875489 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 22762691 ps |
| CPU time | 0.95 seconds |
| Started | Sep 04 12:41:30 PM UTC 24 |
| Finished | Sep 04 12:41:32 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932875489 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1932875489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.2866062773 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 34718185 ps |
| CPU time | 1.34 seconds |
| Started | Sep 04 12:41:31 PM UTC 24 |
| Finished | Sep 04 12:41:33 PM UTC 24 |
| Peak memory | 222856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866062773 -assert nopostp roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.2866062773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.2550117536 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 121357955 ps |
| CPU time | 0.83 seconds |
| Started | Sep 04 12:41:30 PM UTC 24 |
| Finished | Sep 04 12:41:31 PM UTC 24 |
| Peak memory | 211384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550117536 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.2550117536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3877078118 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 114402433 ps |
| CPU time | 3.45 seconds |
| Started | Sep 04 12:41:32 PM UTC 24 |
| Finished | Sep 04 12:41:37 PM UTC 24 |
| Peak memory | 224312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877078118 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstanding.3877078118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.924272498 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 305184119 ps |
| CPU time | 17.47 seconds |
| Started | Sep 04 12:41:29 PM UTC 24 |
| Finished | Sep 04 12:41:48 PM UTC 24 |
| Peak memory | 224132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924272498 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.924272498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.199934723 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 36537151 ps |
| CPU time | 0.85 seconds |
| Started | Sep 04 12:41:57 PM UTC 24 |
| Finished | Sep 04 12:42:06 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199934723 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.199934723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/40.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.2689556108 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 21089059 ps |
| CPU time | 0.92 seconds |
| Started | Sep 04 12:41:57 PM UTC 24 |
| Finished | Sep 04 12:42:06 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689556108 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.2689556108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/41.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.555696194 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 29701360 ps |
| CPU time | 0.97 seconds |
| Started | Sep 04 12:41:57 PM UTC 24 |
| Finished | Sep 04 12:42:06 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555696194 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.555696194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/42.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.1458666412 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 57229766 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 12:41:57 PM UTC 24 |
| Finished | Sep 04 12:42:06 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458666412 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.1458666412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/43.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.3742679937 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 17753231 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 12:41:57 PM UTC 24 |
| Finished | Sep 04 12:42:06 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742679937 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.3742679937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/44.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.2437617137 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 29624418 ps |
| CPU time | 0.91 seconds |
| Started | Sep 04 12:41:57 PM UTC 24 |
| Finished | Sep 04 12:42:06 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437617137 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.2437617137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/45.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.2445740597 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 25509741 ps |
| CPU time | 0.99 seconds |
| Started | Sep 04 12:41:57 PM UTC 24 |
| Finished | Sep 04 12:42:06 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445740597 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.2445740597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/46.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.2350037381 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 18643471 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 12:41:58 PM UTC 24 |
| Finished | Sep 04 12:42:03 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350037381 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.2350037381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/47.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.2059556892 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 17183566 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 12:41:58 PM UTC 24 |
| Finished | Sep 04 12:42:03 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059556892 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.2059556892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/48.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.1348374775 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 27755406 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 12:41:58 PM UTC 24 |
| Finished | Sep 04 12:42:03 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348374775 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.1348374775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/49.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4018382960 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 63593098 ps |
| CPU time | 2.13 seconds |
| Started | Sep 04 12:41:32 PM UTC 24 |
| Finished | Sep 04 12:41:35 PM UTC 24 |
| Peak memory | 224396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4018382960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.4018382960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.4028367507 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 51216833 ps |
| CPU time | 1.36 seconds |
| Started | Sep 04 12:41:32 PM UTC 24 |
| Finished | Sep 04 12:41:35 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028367507 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.4028367507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.1992574207 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 46206246 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 12:41:32 PM UTC 24 |
| Finished | Sep 04 12:41:34 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992574207 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1992574207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2550400036 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 161782388 ps |
| CPU time | 3.94 seconds |
| Started | Sep 04 12:41:32 PM UTC 24 |
| Finished | Sep 04 12:41:37 PM UTC 24 |
| Peak memory | 213896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550400036 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstanding.2550400036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.3111380059 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 296607752 ps |
| CPU time | 3.47 seconds |
| Started | Sep 04 12:41:32 PM UTC 24 |
| Finished | Sep 04 12:41:37 PM UTC 24 |
| Peak memory | 224468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111380059 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3111380059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.2336268637 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 4575026374 ps |
| CPU time | 21.64 seconds |
| Started | Sep 04 12:41:32 PM UTC 24 |
| Finished | Sep 04 12:41:55 PM UTC 24 |
| Peak memory | 232392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336268637 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.2336268637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1109636824 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 97731143 ps |
| CPU time | 2.92 seconds |
| Started | Sep 04 12:41:34 PM UTC 24 |
| Finished | Sep 04 12:41:41 PM UTC 24 |
| Peak memory | 226184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1109636824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1109636824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.477652732 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 43549790 ps |
| CPU time | 2.33 seconds |
| Started | Sep 04 12:41:34 PM UTC 24 |
| Finished | Sep 04 12:41:40 PM UTC 24 |
| Peak memory | 224064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477652732 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.477652732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.3255523723 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 170157823 ps |
| CPU time | 0.99 seconds |
| Started | Sep 04 12:41:34 PM UTC 24 |
| Finished | Sep 04 12:41:39 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255523723 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3255523723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4289803653 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 87737601 ps |
| CPU time | 1.86 seconds |
| Started | Sep 04 12:41:34 PM UTC 24 |
| Finished | Sep 04 12:41:40 PM UTC 24 |
| Peak memory | 223588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289803653 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstanding.4289803653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.300589090 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 54045458 ps |
| CPU time | 1.71 seconds |
| Started | Sep 04 12:41:32 PM UTC 24 |
| Finished | Sep 04 12:41:35 PM UTC 24 |
| Peak memory | 225068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300589090 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.300589090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.955603461 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 614964136 ps |
| CPU time | 16.45 seconds |
| Started | Sep 04 12:41:32 PM UTC 24 |
| Finished | Sep 04 12:41:50 PM UTC 24 |
| Peak memory | 226116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955603461 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.955603461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.376046230 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 199609856 ps |
| CPU time | 2.49 seconds |
| Started | Sep 04 12:41:34 PM UTC 24 |
| Finished | Sep 04 12:41:41 PM UTC 24 |
| Peak memory | 228224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=376046230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.376046230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.4287881941 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 448701019 ps |
| CPU time | 2.82 seconds |
| Started | Sep 04 12:41:34 PM UTC 24 |
| Finished | Sep 04 12:41:41 PM UTC 24 |
| Peak memory | 224144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287881941 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.4287881941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.402810083 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 38928387 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 12:41:34 PM UTC 24 |
| Finished | Sep 04 12:41:39 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402810083 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.402810083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1280809039 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 26830811 ps |
| CPU time | 1.71 seconds |
| Started | Sep 04 12:41:34 PM UTC 24 |
| Finished | Sep 04 12:41:43 PM UTC 24 |
| Peak memory | 223176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280809039 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstanding.1280809039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.3758428692 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 98735721 ps |
| CPU time | 2.63 seconds |
| Started | Sep 04 12:41:34 PM UTC 24 |
| Finished | Sep 04 12:41:41 PM UTC 24 |
| Peak memory | 224516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758428692 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3758428692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.4041296008 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 572621003 ps |
| CPU time | 14.2 seconds |
| Started | Sep 04 12:41:34 PM UTC 24 |
| Finished | Sep 04 12:41:56 PM UTC 24 |
| Peak memory | 224316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041296008 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.4041296008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2306591136 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 175634332 ps |
| CPU time | 1.73 seconds |
| Started | Sep 04 12:41:35 PM UTC 24 |
| Finished | Sep 04 12:41:39 PM UTC 24 |
| Peak memory | 224584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2306591136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2306591136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.4229683011 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 207938050 ps |
| CPU time | 2.56 seconds |
| Started | Sep 04 12:41:35 PM UTC 24 |
| Finished | Sep 04 12:41:40 PM UTC 24 |
| Peak memory | 224336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229683011 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.4229683011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.2680029740 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 12474219 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 12:41:34 PM UTC 24 |
| Finished | Sep 04 12:41:42 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680029740 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2680029740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2952832112 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 278164278 ps |
| CPU time | 3.12 seconds |
| Started | Sep 04 12:41:35 PM UTC 24 |
| Finished | Sep 04 12:41:41 PM UTC 24 |
| Peak memory | 226312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952832112 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstanding.2952832112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.3524318301 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 200829159 ps |
| CPU time | 11.92 seconds |
| Started | Sep 04 12:41:34 PM UTC 24 |
| Finished | Sep 04 12:41:54 PM UTC 24 |
| Peak memory | 224052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524318301 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.3524318301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2448889333 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 749448712 ps |
| CPU time | 3.53 seconds |
| Started | Sep 04 12:41:37 PM UTC 24 |
| Finished | Sep 04 12:41:41 PM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2448889333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2448889333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.3130655677 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 156802127 ps |
| CPU time | 1.41 seconds |
| Started | Sep 04 12:41:36 PM UTC 24 |
| Finished | Sep 04 12:41:39 PM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130655677 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3130655677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.4137659234 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 28302693 ps |
| CPU time | 0.8 seconds |
| Started | Sep 04 12:41:35 PM UTC 24 |
| Finished | Sep 04 12:41:38 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137659234 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.4137659234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1042853555 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 229007568 ps |
| CPU time | 4.43 seconds |
| Started | Sep 04 12:41:37 PM UTC 24 |
| Finished | Sep 04 12:41:42 PM UTC 24 |
| Peak memory | 224068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042853555 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstanding.1042853555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.718624867 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 102513879 ps |
| CPU time | 1.88 seconds |
| Started | Sep 04 12:41:35 PM UTC 24 |
| Finished | Sep 04 12:41:39 PM UTC 24 |
| Peak memory | 222992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718624867 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.718624867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.4260693688 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 578829878 ps |
| CPU time | 16.01 seconds |
| Started | Sep 04 12:41:35 PM UTC 24 |
| Finished | Sep 04 12:41:54 PM UTC 24 |
| Peak memory | 232040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260693688 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.4260693688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.3830652505 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2231206126 ps |
| CPU time | 18.54 seconds |
| Started | Sep 04 08:23:10 AM UTC 24 |
| Finished | Sep 04 08:23:29 AM UTC 24 |
| Peak memory | 245632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830652505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3830652505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.706626612 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 17651375506 ps |
| CPU time | 87.86 seconds |
| Started | Sep 04 08:23:14 AM UTC 24 |
| Finished | Sep 04 08:24:44 AM UTC 24 |
| Peak memory | 249988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706626612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.706626612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.878920937 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 12647526664 ps |
| CPU time | 31.87 seconds |
| Started | Sep 04 08:23:15 AM UTC 24 |
| Finished | Sep 04 08:23:49 AM UTC 24 |
| Peak memory | 245896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878920937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.878920937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.3340253750 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 2649727420 ps |
| CPU time | 16.5 seconds |
| Started | Sep 04 08:23:11 AM UTC 24 |
| Finished | Sep 04 08:23:29 AM UTC 24 |
| Peak memory | 251876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340253750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3340253750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.521921274 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 281126457 ps |
| CPU time | 3.3 seconds |
| Started | Sep 04 08:23:09 AM UTC 24 |
| Finished | Sep 04 08:23:14 AM UTC 24 |
| Peak memory | 245732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521921274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.521921274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.4213243256 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 236848613 ps |
| CPU time | 1.5 seconds |
| Started | Sep 04 08:23:02 AM UTC 24 |
| Finished | Sep 04 08:23:05 AM UTC 24 |
| Peak memory | 229140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213243256 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_parity.4213243256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.3295601724 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 102588820 ps |
| CPU time | 3.41 seconds |
| Started | Sep 04 08:23:06 AM UTC 24 |
| Finished | Sep 04 08:23:11 AM UTC 24 |
| Peak memory | 245840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295601724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3295601724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.3041449594 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 452312140 ps |
| CPU time | 5.4 seconds |
| Started | Sep 04 08:23:13 AM UTC 24 |
| Finished | Sep 04 08:23:20 AM UTC 24 |
| Peak memory | 231604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041449594 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.3041449594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.434829788 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 5964976891 ps |
| CPU time | 22.61 seconds |
| Started | Sep 04 08:23:04 AM UTC 24 |
| Finished | Sep 04 08:23:28 AM UTC 24 |
| Peak memory | 232044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434829788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.434829788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.3008163811 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 142970876 ps |
| CPU time | 1.86 seconds |
| Started | Sep 04 08:23:06 AM UTC 24 |
| Finished | Sep 04 08:23:09 AM UTC 24 |
| Peak memory | 228020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008163811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3008163811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.1768591555 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 24679873 ps |
| CPU time | 1.26 seconds |
| Started | Sep 04 08:23:06 AM UTC 24 |
| Finished | Sep 04 08:23:08 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768591555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1768591555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.1283179804 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2765617044 ps |
| CPU time | 15.94 seconds |
| Started | Sep 04 08:23:10 AM UTC 24 |
| Finished | Sep 04 08:23:27 AM UTC 24 |
| Peak memory | 245828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283179804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1283179804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/0.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.2475689485 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 13419215 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 08:23:41 AM UTC 24 |
| Finished | Sep 04 08:23:43 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475689485 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2475689485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1659047971 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 194945992 ps |
| CPU time | 5.17 seconds |
| Started | Sep 04 08:23:30 AM UTC 24 |
| Finished | Sep 04 08:23:36 AM UTC 24 |
| Peak memory | 245592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659047971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1659047971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.3902241462 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 15337917 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 08:23:20 AM UTC 24 |
| Finished | Sep 04 08:23:22 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902241462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3902241462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.2924695032 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5863617020 ps |
| CPU time | 30.52 seconds |
| Started | Sep 04 08:23:32 AM UTC 24 |
| Finished | Sep 04 08:24:04 AM UTC 24 |
| Peak memory | 251868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924695032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2924695032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.691719736 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 90514884105 ps |
| CPU time | 209.11 seconds |
| Started | Sep 04 08:23:36 AM UTC 24 |
| Finished | Sep 04 08:27:09 AM UTC 24 |
| Peak memory | 262184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691719736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.691719736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.238512296 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 24120178225 ps |
| CPU time | 221.68 seconds |
| Started | Sep 04 08:23:31 AM UTC 24 |
| Finished | Sep 04 08:27:16 AM UTC 24 |
| Peak memory | 268460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238512296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.238512296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.3106769963 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 118054003 ps |
| CPU time | 3.04 seconds |
| Started | Sep 04 08:23:28 AM UTC 24 |
| Finished | Sep 04 08:23:32 AM UTC 24 |
| Peak memory | 245484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106769963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3106769963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.2429779389 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 5844939867 ps |
| CPU time | 59.78 seconds |
| Started | Sep 04 08:23:29 AM UTC 24 |
| Finished | Sep 04 08:24:30 AM UTC 24 |
| Peak memory | 251872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429779389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2429779389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.3905211713 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 124057146 ps |
| CPU time | 1.55 seconds |
| Started | Sep 04 08:23:20 AM UTC 24 |
| Finished | Sep 04 08:23:23 AM UTC 24 |
| Peak memory | 229204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905211713 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_parity.3905211713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.363424290 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 2495536188 ps |
| CPU time | 7.13 seconds |
| Started | Sep 04 08:23:27 AM UTC 24 |
| Finished | Sep 04 08:23:36 AM UTC 24 |
| Peak memory | 235476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363424290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.363424290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.1725142567 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13337467037 ps |
| CPU time | 19.77 seconds |
| Started | Sep 04 08:23:26 AM UTC 24 |
| Finished | Sep 04 08:23:47 AM UTC 24 |
| Peak memory | 235592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725142567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1725142567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.1445724543 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1562114110 ps |
| CPU time | 13.31 seconds |
| Started | Sep 04 08:23:32 AM UTC 24 |
| Finished | Sep 04 08:23:47 AM UTC 24 |
| Peak memory | 231664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445724543 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.1445724543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.1049284763 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 128651523 ps |
| CPU time | 1.66 seconds |
| Started | Sep 04 08:23:38 AM UTC 24 |
| Finished | Sep 04 08:23:40 AM UTC 24 |
| Peak memory | 257740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049284763 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1049284763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.3998004773 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 771472983 ps |
| CPU time | 7.04 seconds |
| Started | Sep 04 08:23:21 AM UTC 24 |
| Finished | Sep 04 08:23:29 AM UTC 24 |
| Peak memory | 227764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998004773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3998004773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.2854373853 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 47225120 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 08:23:23 AM UTC 24 |
| Finished | Sep 04 08:23:25 AM UTC 24 |
| Peak memory | 215980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854373853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2854373853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.2261296798 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 224653917 ps |
| CPU time | 1.95 seconds |
| Started | Sep 04 08:23:23 AM UTC 24 |
| Finished | Sep 04 08:23:26 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261296798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2261296798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/1.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.4020607877 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 40470551 ps |
| CPU time | 1.09 seconds |
| Started | Sep 04 08:26:33 AM UTC 24 |
| Finished | Sep 04 08:26:35 AM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020607877 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.4020607877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.2711287558 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 764688678 ps |
| CPU time | 7.71 seconds |
| Started | Sep 04 08:26:27 AM UTC 24 |
| Finished | Sep 04 08:26:35 AM UTC 24 |
| Peak memory | 245540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711287558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2711287558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.3811342103 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 38990912 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 08:26:20 AM UTC 24 |
| Finished | Sep 04 08:26:22 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811342103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3811342103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.2769571310 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 54757659940 ps |
| CPU time | 158.7 seconds |
| Started | Sep 04 08:26:31 AM UTC 24 |
| Finished | Sep 04 08:29:12 AM UTC 24 |
| Peak memory | 262084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769571310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2769571310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.3816254708 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 90546477634 ps |
| CPU time | 436.27 seconds |
| Started | Sep 04 08:26:31 AM UTC 24 |
| Finished | Sep 04 08:33:53 AM UTC 24 |
| Peak memory | 266412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816254708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3816254708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.848250045 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 7470474152 ps |
| CPU time | 86.72 seconds |
| Started | Sep 04 08:26:32 AM UTC 24 |
| Finished | Sep 04 08:28:01 AM UTC 24 |
| Peak memory | 250048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848250045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.848250045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.807675484 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 818417140 ps |
| CPU time | 19.8 seconds |
| Started | Sep 04 08:26:27 AM UTC 24 |
| Finished | Sep 04 08:26:48 AM UTC 24 |
| Peak memory | 235496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807675484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.807675484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.3225079034 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 4301086082 ps |
| CPU time | 61.8 seconds |
| Started | Sep 04 08:26:28 AM UTC 24 |
| Finished | Sep 04 08:27:31 AM UTC 24 |
| Peak memory | 262112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225079034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.3225079034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.1111629069 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 126834430 ps |
| CPU time | 4.16 seconds |
| Started | Sep 04 08:26:24 AM UTC 24 |
| Finished | Sep 04 08:26:30 AM UTC 24 |
| Peak memory | 245672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111629069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1111629069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.3069333242 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 2845913149 ps |
| CPU time | 28.14 seconds |
| Started | Sep 04 08:26:25 AM UTC 24 |
| Finished | Sep 04 08:26:55 AM UTC 24 |
| Peak memory | 252072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069333242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3069333242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.3936649919 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 119578148 ps |
| CPU time | 1.5 seconds |
| Started | Sep 04 08:26:21 AM UTC 24 |
| Finished | Sep 04 08:26:23 AM UTC 24 |
| Peak memory | 229204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936649919 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mem_parity.3936649919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.2479263605 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 64619620545 ps |
| CPU time | 22.27 seconds |
| Started | Sep 04 08:26:24 AM UTC 24 |
| Finished | Sep 04 08:26:48 AM UTC 24 |
| Peak memory | 245460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479263605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.2479263605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.3734522714 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 23445002392 ps |
| CPU time | 20.96 seconds |
| Started | Sep 04 08:26:24 AM UTC 24 |
| Finished | Sep 04 08:26:46 AM UTC 24 |
| Peak memory | 235236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734522714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3734522714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.1571142701 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 1028577864 ps |
| CPU time | 4.47 seconds |
| Started | Sep 04 08:26:22 AM UTC 24 |
| Finished | Sep 04 08:26:27 AM UTC 24 |
| Peak memory | 228016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571142701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1571142701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.3916747448 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1257404769 ps |
| CPU time | 13.69 seconds |
| Started | Sep 04 08:26:22 AM UTC 24 |
| Finished | Sep 04 08:26:37 AM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916747448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3916747448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.2911568556 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 30148875 ps |
| CPU time | 1.2 seconds |
| Started | Sep 04 08:26:23 AM UTC 24 |
| Finished | Sep 04 08:26:25 AM UTC 24 |
| Peak memory | 215984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911568556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2911568556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.1394996851 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 71821316 ps |
| CPU time | 1 seconds |
| Started | Sep 04 08:26:23 AM UTC 24 |
| Finished | Sep 04 08:26:25 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394996851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1394996851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.2117848545 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 6489743238 ps |
| CPU time | 15.88 seconds |
| Started | Sep 04 08:26:25 AM UTC 24 |
| Finished | Sep 04 08:26:43 AM UTC 24 |
| Peak memory | 252004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117848545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2117848545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/10.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.1164493706 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 45630917 ps |
| CPU time | 1.05 seconds |
| Started | Sep 04 08:26:51 AM UTC 24 |
| Finished | Sep 04 08:26:53 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164493706 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.1164493706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.4268281252 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 191763723 ps |
| CPU time | 4.39 seconds |
| Started | Sep 04 08:26:45 AM UTC 24 |
| Finished | Sep 04 08:26:51 AM UTC 24 |
| Peak memory | 245604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268281252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4268281252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.2804765666 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 105321158 ps |
| CPU time | 1.18 seconds |
| Started | Sep 04 08:26:36 AM UTC 24 |
| Finished | Sep 04 08:26:38 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804765666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2804765666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.3568353049 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 11366976659 ps |
| CPU time | 61.1 seconds |
| Started | Sep 04 08:26:49 AM UTC 24 |
| Finished | Sep 04 08:27:51 AM UTC 24 |
| Peak memory | 268268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568353049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3568353049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.2840727652 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 9748655108 ps |
| CPU time | 66.41 seconds |
| Started | Sep 04 08:26:49 AM UTC 24 |
| Finished | Sep 04 08:27:57 AM UTC 24 |
| Peak memory | 266276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840727652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2840727652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.2837058882 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 195642661 ps |
| CPU time | 3.32 seconds |
| Started | Sep 04 08:26:46 AM UTC 24 |
| Finished | Sep 04 08:26:51 AM UTC 24 |
| Peak memory | 245548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837058882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2837058882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.2770137497 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1640299459 ps |
| CPU time | 36.37 seconds |
| Started | Sep 04 08:26:46 AM UTC 24 |
| Finished | Sep 04 08:27:24 AM UTC 24 |
| Peak memory | 266056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770137497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.2770137497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.2890335600 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 159840698 ps |
| CPU time | 5.84 seconds |
| Started | Sep 04 08:26:43 AM UTC 24 |
| Finished | Sep 04 08:26:50 AM UTC 24 |
| Peak memory | 235276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890335600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2890335600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.3238538735 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 16311268124 ps |
| CPU time | 34.31 seconds |
| Started | Sep 04 08:26:43 AM UTC 24 |
| Finished | Sep 04 08:27:19 AM UTC 24 |
| Peak memory | 235652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238538735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3238538735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.2703378138 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 121454524 ps |
| CPU time | 1.57 seconds |
| Started | Sep 04 08:26:36 AM UTC 24 |
| Finished | Sep 04 08:26:39 AM UTC 24 |
| Peak memory | 229264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703378138 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mem_parity.2703378138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.2779950290 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 28790310834 ps |
| CPU time | 24.97 seconds |
| Started | Sep 04 08:26:43 AM UTC 24 |
| Finished | Sep 04 08:27:09 AM UTC 24 |
| Peak memory | 235432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779950290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.2779950290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.1718106893 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 169222954 ps |
| CPU time | 4.52 seconds |
| Started | Sep 04 08:26:40 AM UTC 24 |
| Finished | Sep 04 08:26:45 AM UTC 24 |
| Peak memory | 235344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718106893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1718106893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.3778535978 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2650279490 ps |
| CPU time | 9.52 seconds |
| Started | Sep 04 08:26:47 AM UTC 24 |
| Finished | Sep 04 08:26:58 AM UTC 24 |
| Peak memory | 234076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778535978 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.3778535978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.1660429981 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 34992989 ps |
| CPU time | 1.29 seconds |
| Started | Sep 04 08:26:49 AM UTC 24 |
| Finished | Sep 04 08:26:51 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660429981 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.1660429981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.4148467960 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 1304411699 ps |
| CPU time | 16.76 seconds |
| Started | Sep 04 08:26:40 AM UTC 24 |
| Finished | Sep 04 08:26:58 AM UTC 24 |
| Peak memory | 231888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148467960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.4148467960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.633443543 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 376876868 ps |
| CPU time | 3.61 seconds |
| Started | Sep 04 08:26:38 AM UTC 24 |
| Finished | Sep 04 08:26:42 AM UTC 24 |
| Peak memory | 227696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633443543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.633443543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.1293587524 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 49216282 ps |
| CPU time | 1.88 seconds |
| Started | Sep 04 08:26:40 AM UTC 24 |
| Finished | Sep 04 08:26:43 AM UTC 24 |
| Peak memory | 228020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293587524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1293587524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.1992945641 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 189072884 ps |
| CPU time | 1.21 seconds |
| Started | Sep 04 08:26:40 AM UTC 24 |
| Finished | Sep 04 08:26:42 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992945641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1992945641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.2946320275 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 21094791305 ps |
| CPU time | 42.11 seconds |
| Started | Sep 04 08:26:43 AM UTC 24 |
| Finished | Sep 04 08:27:26 AM UTC 24 |
| Peak memory | 245700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946320275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2946320275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/11.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.1212835151 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 30780047 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 08:27:05 AM UTC 24 |
| Finished | Sep 04 08:27:08 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212835151 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.1212835151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.319048138 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 433648949 ps |
| CPU time | 5.2 seconds |
| Started | Sep 04 08:26:58 AM UTC 24 |
| Finished | Sep 04 08:27:04 AM UTC 24 |
| Peak memory | 235368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319048138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.319048138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.396934245 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 26297757 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 08:26:52 AM UTC 24 |
| Finished | Sep 04 08:26:54 AM UTC 24 |
| Peak memory | 215636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396934245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.396934245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_all.3534564215 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 59096554198 ps |
| CPU time | 98.03 seconds |
| Started | Sep 04 08:26:59 AM UTC 24 |
| Finished | Sep 04 08:28:39 AM UTC 24 |
| Peak memory | 268488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534564215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3534564215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.1351096568 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 5424760753 ps |
| CPU time | 58.35 seconds |
| Started | Sep 04 08:27:04 AM UTC 24 |
| Finished | Sep 04 08:28:04 AM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351096568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.1351096568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.143645910 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 202189333 ps |
| CPU time | 8.31 seconds |
| Started | Sep 04 08:26:58 AM UTC 24 |
| Finished | Sep 04 08:27:07 AM UTC 24 |
| Peak memory | 251656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143645910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.143645910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.3991497362 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 9843855194 ps |
| CPU time | 99.86 seconds |
| Started | Sep 04 08:26:58 AM UTC 24 |
| Finished | Sep 04 08:28:40 AM UTC 24 |
| Peak memory | 282760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991497362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.3991497362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.2842650615 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 492657154 ps |
| CPU time | 4.28 seconds |
| Started | Sep 04 08:26:55 AM UTC 24 |
| Finished | Sep 04 08:27:01 AM UTC 24 |
| Peak memory | 235408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842650615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2842650615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.2004840036 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 1423862706 ps |
| CPU time | 11.6 seconds |
| Started | Sep 04 08:26:57 AM UTC 24 |
| Finished | Sep 04 08:27:09 AM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004840036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2004840036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.2797940765 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 15785512 ps |
| CPU time | 1.48 seconds |
| Started | Sep 04 08:26:52 AM UTC 24 |
| Finished | Sep 04 08:26:54 AM UTC 24 |
| Peak memory | 229204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797940765 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mem_parity.2797940765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.3381318148 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 1660561772 ps |
| CPU time | 15.12 seconds |
| Started | Sep 04 08:26:55 AM UTC 24 |
| Finished | Sep 04 08:27:12 AM UTC 24 |
| Peak memory | 251724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381318148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.3381318148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.2519933660 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 12257908082 ps |
| CPU time | 18.66 seconds |
| Started | Sep 04 08:26:55 AM UTC 24 |
| Finished | Sep 04 08:27:15 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519933660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2519933660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.688012146 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 1769592392 ps |
| CPU time | 21.32 seconds |
| Started | Sep 04 08:26:59 AM UTC 24 |
| Finished | Sep 04 08:27:22 AM UTC 24 |
| Peak memory | 231600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688012146 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.688012146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.4284184498 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 9403658319 ps |
| CPU time | 49.21 seconds |
| Started | Sep 04 08:27:04 AM UTC 24 |
| Finished | Sep 04 08:27:55 AM UTC 24 |
| Peak memory | 262440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284184498 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.4284184498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.3279716177 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1712669952 ps |
| CPU time | 3.66 seconds |
| Started | Sep 04 08:26:52 AM UTC 24 |
| Finished | Sep 04 08:26:57 AM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279716177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3279716177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.398021892 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 5643856364 ps |
| CPU time | 10.42 seconds |
| Started | Sep 04 08:26:52 AM UTC 24 |
| Finished | Sep 04 08:27:04 AM UTC 24 |
| Peak memory | 227836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398021892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.398021892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.1293232488 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 28885387 ps |
| CPU time | 1.64 seconds |
| Started | Sep 04 08:26:55 AM UTC 24 |
| Finished | Sep 04 08:26:58 AM UTC 24 |
| Peak memory | 216504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293232488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1293232488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.273627808 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 378253573 ps |
| CPU time | 1.45 seconds |
| Started | Sep 04 08:26:54 AM UTC 24 |
| Finished | Sep 04 08:26:57 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273627808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.273627808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.1261450171 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 1978897992 ps |
| CPU time | 10.03 seconds |
| Started | Sep 04 08:26:57 AM UTC 24 |
| Finished | Sep 04 08:27:08 AM UTC 24 |
| Peak memory | 251648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261450171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1261450171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/12.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_alert_test.2036643113 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 16680141 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 08:27:25 AM UTC 24 |
| Finished | Sep 04 08:27:28 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036643113 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.2036643113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_cfg_cmd.1598521495 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 78427140 ps |
| CPU time | 2.87 seconds |
| Started | Sep 04 08:27:13 AM UTC 24 |
| Finished | Sep 04 08:27:17 AM UTC 24 |
| Peak memory | 245224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598521495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1598521495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.779539904 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 46311559 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 08:27:07 AM UTC 24 |
| Finished | Sep 04 08:27:09 AM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779539904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.779539904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.379760498 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 56911265413 ps |
| CPU time | 55.62 seconds |
| Started | Sep 04 08:27:19 AM UTC 24 |
| Finished | Sep 04 08:28:16 AM UTC 24 |
| Peak memory | 235384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379760498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.379760498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode.3505680034 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 2116977337 ps |
| CPU time | 25.93 seconds |
| Started | Sep 04 08:27:16 AM UTC 24 |
| Finished | Sep 04 08:27:44 AM UTC 24 |
| Peak memory | 245560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505680034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3505680034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_intercept.455675136 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 135895573 ps |
| CPU time | 4.56 seconds |
| Started | Sep 04 08:27:12 AM UTC 24 |
| Finished | Sep 04 08:27:18 AM UTC 24 |
| Peak memory | 245576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455675136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.455675136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mailbox.449867594 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 18788097416 ps |
| CPU time | 105.51 seconds |
| Started | Sep 04 08:27:12 AM UTC 24 |
| Finished | Sep 04 08:29:00 AM UTC 24 |
| Peak memory | 262056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449867594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.449867594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.280977364 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 51824579 ps |
| CPU time | 1.42 seconds |
| Started | Sep 04 08:27:09 AM UTC 24 |
| Finished | Sep 04 08:27:11 AM UTC 24 |
| Peak memory | 229200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280977364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mem_parity.280977364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.321025801 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 4956814711 ps |
| CPU time | 29.04 seconds |
| Started | Sep 04 08:27:10 AM UTC 24 |
| Finished | Sep 04 08:27:40 AM UTC 24 |
| Peak memory | 252068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321025801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.321025801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.1835788727 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 1802166641 ps |
| CPU time | 14.95 seconds |
| Started | Sep 04 08:27:10 AM UTC 24 |
| Finished | Sep 04 08:27:26 AM UTC 24 |
| Peak memory | 245772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835788727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1835788727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.3388767572 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 1168735994 ps |
| CPU time | 11.79 seconds |
| Started | Sep 04 08:27:18 AM UTC 24 |
| Finished | Sep 04 08:27:30 AM UTC 24 |
| Peak memory | 231668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388767572 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.3388767572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.3580301811 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 3379686767 ps |
| CPU time | 32.17 seconds |
| Started | Sep 04 08:27:23 AM UTC 24 |
| Finished | Sep 04 08:27:56 AM UTC 24 |
| Peak memory | 248008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580301811 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.3580301811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_all.963341517 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 3922426464 ps |
| CPU time | 41.11 seconds |
| Started | Sep 04 08:27:09 AM UTC 24 |
| Finished | Sep 04 08:27:51 AM UTC 24 |
| Peak memory | 228148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963341517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.963341517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.1031425729 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 10275541257 ps |
| CPU time | 28.31 seconds |
| Started | Sep 04 08:27:09 AM UTC 24 |
| Finished | Sep 04 08:27:38 AM UTC 24 |
| Peak memory | 228124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031425729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1031425729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.3252839130 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 19804985 ps |
| CPU time | 1.27 seconds |
| Started | Sep 04 08:27:10 AM UTC 24 |
| Finished | Sep 04 08:27:12 AM UTC 24 |
| Peak memory | 215984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252839130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3252839130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.2276542658 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 100707838 ps |
| CPU time | 1.62 seconds |
| Started | Sep 04 08:27:10 AM UTC 24 |
| Finished | Sep 04 08:27:13 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276542658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2276542658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_upload.2626060227 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 40908089 ps |
| CPU time | 3.01 seconds |
| Started | Sep 04 08:27:13 AM UTC 24 |
| Finished | Sep 04 08:27:17 AM UTC 24 |
| Peak memory | 245316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626060227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2626060227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/13.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_alert_test.4223388623 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 18472257 ps |
| CPU time | 1.07 seconds |
| Started | Sep 04 08:27:44 AM UTC 24 |
| Finished | Sep 04 08:27:46 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223388623 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.4223388623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_cfg_cmd.481389176 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 130543949 ps |
| CPU time | 3.12 seconds |
| Started | Sep 04 08:27:38 AM UTC 24 |
| Finished | Sep 04 08:27:42 AM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481389176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.481389176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_csb_read.3661789548 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 15138442 ps |
| CPU time | 1.15 seconds |
| Started | Sep 04 08:27:28 AM UTC 24 |
| Finished | Sep 04 08:27:30 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661789548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3661789548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_all.2404392049 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 11975678354 ps |
| CPU time | 101.25 seconds |
| Started | Sep 04 08:27:41 AM UTC 24 |
| Finished | Sep 04 08:29:25 AM UTC 24 |
| Peak memory | 266184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404392049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2404392049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.972094791 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 18380901673 ps |
| CPU time | 99.42 seconds |
| Started | Sep 04 08:27:41 AM UTC 24 |
| Finished | Sep 04 08:29:23 AM UTC 24 |
| Peak memory | 262184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972094791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.972094791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.120064670 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 170936851505 ps |
| CPU time | 753.45 seconds |
| Started | Sep 04 08:27:42 AM UTC 24 |
| Finished | Sep 04 08:40:25 AM UTC 24 |
| Peak memory | 278532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120064670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.120064670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode.760514270 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 1105109575 ps |
| CPU time | 3.7 seconds |
| Started | Sep 04 08:27:39 AM UTC 24 |
| Finished | Sep 04 08:27:44 AM UTC 24 |
| Peak memory | 235516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760514270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.760514270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.1643144463 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 2894931231 ps |
| CPU time | 59.05 seconds |
| Started | Sep 04 08:27:39 AM UTC 24 |
| Finished | Sep 04 08:28:40 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643144463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.1643144463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_intercept.1769318403 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 2279570075 ps |
| CPU time | 7.27 seconds |
| Started | Sep 04 08:27:35 AM UTC 24 |
| Finished | Sep 04 08:27:43 AM UTC 24 |
| Peak memory | 235300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769318403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1769318403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mailbox.3128569532 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 38824721438 ps |
| CPU time | 75.91 seconds |
| Started | Sep 04 08:27:35 AM UTC 24 |
| Finished | Sep 04 08:28:53 AM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128569532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3128569532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mem_parity.460498632 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 85244170 ps |
| CPU time | 1.48 seconds |
| Started | Sep 04 08:27:28 AM UTC 24 |
| Finished | Sep 04 08:27:31 AM UTC 24 |
| Peak memory | 229260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460498632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mem_parity.460498632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.1868463804 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 129973452 ps |
| CPU time | 3.19 seconds |
| Started | Sep 04 08:27:33 AM UTC 24 |
| Finished | Sep 04 08:27:38 AM UTC 24 |
| Peak memory | 245836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868463804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.1868463804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.3370399829 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 5315161249 ps |
| CPU time | 7.79 seconds |
| Started | Sep 04 08:27:32 AM UTC 24 |
| Finished | Sep 04 08:27:41 AM UTC 24 |
| Peak memory | 245900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370399829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3370399829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.2202692157 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1048631622 ps |
| CPU time | 6.33 seconds |
| Started | Sep 04 08:27:41 AM UTC 24 |
| Finished | Sep 04 08:27:49 AM UTC 24 |
| Peak memory | 231608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202692157 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.2202692157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.1281616358 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 45578148673 ps |
| CPU time | 252.1 seconds |
| Started | Sep 04 08:27:43 AM UTC 24 |
| Finished | Sep 04 08:31:58 AM UTC 24 |
| Peak memory | 262148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281616358 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.1281616358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_all.3091786457 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 9191834552 ps |
| CPU time | 27.16 seconds |
| Started | Sep 04 08:27:31 AM UTC 24 |
| Finished | Sep 04 08:28:00 AM UTC 24 |
| Peak memory | 227892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091786457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3091786457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.1878479851 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 769442171 ps |
| CPU time | 4.18 seconds |
| Started | Sep 04 08:27:29 AM UTC 24 |
| Finished | Sep 04 08:27:34 AM UTC 24 |
| Peak memory | 217436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878479851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1878479851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_rw.3542340106 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 45493975 ps |
| CPU time | 1.71 seconds |
| Started | Sep 04 08:27:31 AM UTC 24 |
| Finished | Sep 04 08:27:34 AM UTC 24 |
| Peak memory | 216704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542340106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3542340106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.402062384 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 243653305 ps |
| CPU time | 1.4 seconds |
| Started | Sep 04 08:27:31 AM UTC 24 |
| Finished | Sep 04 08:27:34 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402062384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.402062384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_upload.129251518 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 511931438 ps |
| CPU time | 3.57 seconds |
| Started | Sep 04 08:27:36 AM UTC 24 |
| Finished | Sep 04 08:27:41 AM UTC 24 |
| Peak memory | 245664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129251518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.129251518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/14.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_alert_test.4233354276 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 38980064 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 08:28:00 AM UTC 24 |
| Finished | Sep 04 08:28:02 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233354276 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.4233354276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_cfg_cmd.2282513390 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 33813804 ps |
| CPU time | 2.1 seconds |
| Started | Sep 04 08:27:52 AM UTC 24 |
| Finished | Sep 04 08:27:56 AM UTC 24 |
| Peak memory | 235252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282513390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2282513390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_csb_read.4009952465 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 81501932 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 08:27:44 AM UTC 24 |
| Finished | Sep 04 08:27:46 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009952465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.4009952465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_all.1882539270 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 22430028660 ps |
| CPU time | 31.4 seconds |
| Started | Sep 04 08:27:58 AM UTC 24 |
| Finished | Sep 04 08:28:31 AM UTC 24 |
| Peak memory | 251872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882539270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1882539270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.3672506058 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 37223664074 ps |
| CPU time | 86.42 seconds |
| Started | Sep 04 08:27:58 AM UTC 24 |
| Finished | Sep 04 08:29:26 AM UTC 24 |
| Peak memory | 278536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672506058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3672506058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.1167144196 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 86272165647 ps |
| CPU time | 206.95 seconds |
| Started | Sep 04 08:27:58 AM UTC 24 |
| Finished | Sep 04 08:31:28 AM UTC 24 |
| Peak memory | 262164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167144196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.1167144196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode.4176745412 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 294738514 ps |
| CPU time | 6.81 seconds |
| Started | Sep 04 08:27:52 AM UTC 24 |
| Finished | Sep 04 08:28:00 AM UTC 24 |
| Peak memory | 245612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176745412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.4176745412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.1894476068 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 30213982724 ps |
| CPU time | 100.69 seconds |
| Started | Sep 04 08:27:57 AM UTC 24 |
| Finished | Sep 04 08:29:39 AM UTC 24 |
| Peak memory | 262116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894476068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.1894476068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_intercept.615741896 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 1285212251 ps |
| CPU time | 13.27 seconds |
| Started | Sep 04 08:27:50 AM UTC 24 |
| Finished | Sep 04 08:28:05 AM UTC 24 |
| Peak memory | 245772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615741896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.615741896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mailbox.4231725409 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 7415095582 ps |
| CPU time | 20.47 seconds |
| Started | Sep 04 08:27:51 AM UTC 24 |
| Finished | Sep 04 08:28:13 AM UTC 24 |
| Peak memory | 235488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231725409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.4231725409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mem_parity.496083353 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 27302425 ps |
| CPU time | 1.56 seconds |
| Started | Sep 04 08:27:44 AM UTC 24 |
| Finished | Sep 04 08:27:47 AM UTC 24 |
| Peak memory | 229200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496083353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mem_parity.496083353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.3176514483 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 91244290306 ps |
| CPU time | 33.12 seconds |
| Started | Sep 04 08:27:50 AM UTC 24 |
| Finished | Sep 04 08:28:25 AM UTC 24 |
| Peak memory | 245708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176514483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.3176514483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.739291144 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 3438806014 ps |
| CPU time | 11.9 seconds |
| Started | Sep 04 08:27:48 AM UTC 24 |
| Finished | Sep 04 08:28:01 AM UTC 24 |
| Peak memory | 245712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739291144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.739291144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.3379699106 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 165802204 ps |
| CPU time | 5.27 seconds |
| Started | Sep 04 08:27:57 AM UTC 24 |
| Finished | Sep 04 08:28:03 AM UTC 24 |
| Peak memory | 233932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379699106 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.3379699106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_stress_all.1999606273 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 159248301435 ps |
| CPU time | 412.23 seconds |
| Started | Sep 04 08:27:59 AM UTC 24 |
| Finished | Sep 04 08:34:57 AM UTC 24 |
| Peak memory | 284896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999606273 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.1999606273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_all.1876103135 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1416384896 ps |
| CPU time | 12.23 seconds |
| Started | Sep 04 08:27:45 AM UTC 24 |
| Finished | Sep 04 08:27:58 AM UTC 24 |
| Peak memory | 227956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876103135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1876103135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.3424169466 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1235378727 ps |
| CPU time | 4.95 seconds |
| Started | Sep 04 08:27:45 AM UTC 24 |
| Finished | Sep 04 08:27:51 AM UTC 24 |
| Peak memory | 227936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424169466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3424169466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_rw.1879472698 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 273217870 ps |
| CPU time | 2.24 seconds |
| Started | Sep 04 08:27:47 AM UTC 24 |
| Finished | Sep 04 08:27:50 AM UTC 24 |
| Peak memory | 227760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879472698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1879472698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.3507323799 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 17442032 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 08:27:47 AM UTC 24 |
| Finished | Sep 04 08:27:49 AM UTC 24 |
| Peak memory | 215924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507323799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3507323799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/15.spi_device_upload.3715842437 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 3670977347 ps |
| CPU time | 15.28 seconds |
| Started | Sep 04 08:27:51 AM UTC 24 |
| Finished | Sep 04 08:28:08 AM UTC 24 |
| Peak memory | 235404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715842437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3715842437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/15.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_alert_test.2289141081 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 50040152 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 08:28:14 AM UTC 24 |
| Finished | Sep 04 08:28:17 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289141081 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.2289141081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_cfg_cmd.1644652934 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 3045740126 ps |
| CPU time | 11.96 seconds |
| Started | Sep 04 08:28:06 AM UTC 24 |
| Finished | Sep 04 08:28:19 AM UTC 24 |
| Peak memory | 245924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644652934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1644652934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_csb_read.3387518382 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 19399117 ps |
| CPU time | 1.17 seconds |
| Started | Sep 04 08:28:00 AM UTC 24 |
| Finished | Sep 04 08:28:02 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387518382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3387518382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_all.112324965 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 11191973688 ps |
| CPU time | 153.52 seconds |
| Started | Sep 04 08:28:09 AM UTC 24 |
| Finished | Sep 04 08:30:46 AM UTC 24 |
| Peak memory | 278692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112324965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.112324965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.1372955983 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 9296031858 ps |
| CPU time | 45.15 seconds |
| Started | Sep 04 08:28:09 AM UTC 24 |
| Finished | Sep 04 08:28:56 AM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372955983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1372955983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2483682697 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 101730659958 ps |
| CPU time | 163.96 seconds |
| Started | Sep 04 08:28:11 AM UTC 24 |
| Finished | Sep 04 08:30:58 AM UTC 24 |
| Peak memory | 262148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483682697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.2483682697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode.2341055684 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 160280729 ps |
| CPU time | 3.87 seconds |
| Started | Sep 04 08:28:07 AM UTC 24 |
| Finished | Sep 04 08:28:12 AM UTC 24 |
| Peak memory | 235472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341055684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2341055684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.2440134236 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 3008287022 ps |
| CPU time | 41.63 seconds |
| Started | Sep 04 08:28:07 AM UTC 24 |
| Finished | Sep 04 08:28:50 AM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440134236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.2440134236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_intercept.426735870 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 321993215 ps |
| CPU time | 9.71 seconds |
| Started | Sep 04 08:28:05 AM UTC 24 |
| Finished | Sep 04 08:28:16 AM UTC 24 |
| Peak memory | 235472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426735870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.426735870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mailbox.593544556 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 973539622 ps |
| CPU time | 20.94 seconds |
| Started | Sep 04 08:28:05 AM UTC 24 |
| Finished | Sep 04 08:28:27 AM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593544556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.593544556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mem_parity.4294876491 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 14676036 ps |
| CPU time | 1.21 seconds |
| Started | Sep 04 08:28:01 AM UTC 24 |
| Finished | Sep 04 08:28:03 AM UTC 24 |
| Peak memory | 229204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294876491 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mem_parity.4294876491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.3223234987 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 9747783459 ps |
| CPU time | 30.55 seconds |
| Started | Sep 04 08:28:04 AM UTC 24 |
| Finished | Sep 04 08:28:35 AM UTC 24 |
| Peak memory | 262348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223234987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.3223234987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.2788250210 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 735026674 ps |
| CPU time | 5.44 seconds |
| Started | Sep 04 08:28:04 AM UTC 24 |
| Finished | Sep 04 08:28:10 AM UTC 24 |
| Peak memory | 235472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788250210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2788250210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.1928128460 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 447576321 ps |
| CPU time | 5.25 seconds |
| Started | Sep 04 08:28:07 AM UTC 24 |
| Finished | Sep 04 08:28:13 AM UTC 24 |
| Peak memory | 234100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928128460 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.1928128460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.3023303970 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 142140227 ps |
| CPU time | 1.43 seconds |
| Started | Sep 04 08:28:12 AM UTC 24 |
| Finished | Sep 04 08:28:15 AM UTC 24 |
| Peak memory | 216408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023303970 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.3023303970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_all.397223545 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 424481486 ps |
| CPU time | 4.07 seconds |
| Started | Sep 04 08:28:01 AM UTC 24 |
| Finished | Sep 04 08:28:06 AM UTC 24 |
| Peak memory | 228020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397223545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.397223545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.2955384620 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 37038737067 ps |
| CPU time | 32.85 seconds |
| Started | Sep 04 08:28:01 AM UTC 24 |
| Finished | Sep 04 08:28:35 AM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955384620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2955384620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_rw.1076320979 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 90250158 ps |
| CPU time | 1.86 seconds |
| Started | Sep 04 08:28:04 AM UTC 24 |
| Finished | Sep 04 08:28:06 AM UTC 24 |
| Peak memory | 216504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076320979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1076320979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.1762551653 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 26005978 ps |
| CPU time | 1.23 seconds |
| Started | Sep 04 08:28:02 AM UTC 24 |
| Finished | Sep 04 08:28:05 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762551653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1762551653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/16.spi_device_upload.300398433 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 5733159379 ps |
| CPU time | 11.95 seconds |
| Started | Sep 04 08:28:06 AM UTC 24 |
| Finished | Sep 04 08:28:19 AM UTC 24 |
| Peak memory | 245640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300398433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.300398433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/16.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_alert_test.1935218892 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 38936354 ps |
| CPU time | 1.09 seconds |
| Started | Sep 04 08:28:30 AM UTC 24 |
| Finished | Sep 04 08:28:32 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935218892 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.1935218892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_cfg_cmd.416115199 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 981048693 ps |
| CPU time | 3.09 seconds |
| Started | Sep 04 08:28:21 AM UTC 24 |
| Finished | Sep 04 08:28:26 AM UTC 24 |
| Peak memory | 234660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416115199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.416115199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_csb_read.1021126463 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 33311423 ps |
| CPU time | 1.18 seconds |
| Started | Sep 04 08:28:15 AM UTC 24 |
| Finished | Sep 04 08:28:17 AM UTC 24 |
| Peak memory | 214960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021126463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1021126463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_all.1607677008 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 2696463673 ps |
| CPU time | 28.92 seconds |
| Started | Sep 04 08:28:27 AM UTC 24 |
| Finished | Sep 04 08:28:57 AM UTC 24 |
| Peak memory | 245660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607677008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1607677008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.690880113 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 28513079953 ps |
| CPU time | 41.13 seconds |
| Started | Sep 04 08:28:27 AM UTC 24 |
| Finished | Sep 04 08:29:09 AM UTC 24 |
| Peak memory | 230176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690880113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.690880113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.957196430 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 3208823867 ps |
| CPU time | 79.26 seconds |
| Started | Sep 04 08:28:28 AM UTC 24 |
| Finished | Sep 04 08:29:49 AM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957196430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.957196430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode.1854572484 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 7329465124 ps |
| CPU time | 45.49 seconds |
| Started | Sep 04 08:28:21 AM UTC 24 |
| Finished | Sep 04 08:29:09 AM UTC 24 |
| Peak memory | 245772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854572484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1854572484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.1412193975 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 36465652356 ps |
| CPU time | 143.45 seconds |
| Started | Sep 04 08:28:25 AM UTC 24 |
| Finished | Sep 04 08:30:51 AM UTC 24 |
| Peak memory | 251876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412193975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.1412193975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_intercept.1286662917 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 6944412797 ps |
| CPU time | 19.4 seconds |
| Started | Sep 04 08:28:20 AM UTC 24 |
| Finished | Sep 04 08:28:41 AM UTC 24 |
| Peak memory | 245704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286662917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1286662917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mailbox.1713986713 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 995604365 ps |
| CPU time | 14.99 seconds |
| Started | Sep 04 08:28:20 AM UTC 24 |
| Finished | Sep 04 08:28:37 AM UTC 24 |
| Peak memory | 244308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713986713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1713986713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mem_parity.4021341729 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 32495282 ps |
| CPU time | 1.56 seconds |
| Started | Sep 04 08:28:16 AM UTC 24 |
| Finished | Sep 04 08:28:19 AM UTC 24 |
| Peak memory | 229204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021341729 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mem_parity.4021341729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.1432109102 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 2785234093 ps |
| CPU time | 5.26 seconds |
| Started | Sep 04 08:28:20 AM UTC 24 |
| Finished | Sep 04 08:28:27 AM UTC 24 |
| Peak memory | 235408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432109102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.1432109102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.124921730 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 3567617958 ps |
| CPU time | 7.64 seconds |
| Started | Sep 04 08:28:20 AM UTC 24 |
| Finished | Sep 04 08:28:29 AM UTC 24 |
| Peak memory | 245904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124921730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.124921730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.709970821 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 229681108 ps |
| CPU time | 5.16 seconds |
| Started | Sep 04 08:28:26 AM UTC 24 |
| Finished | Sep 04 08:28:32 AM UTC 24 |
| Peak memory | 231664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709970821 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.709970821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_stress_all.641384018 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 52873639319 ps |
| CPU time | 94.08 seconds |
| Started | Sep 04 08:28:28 AM UTC 24 |
| Finished | Sep 04 08:30:04 AM UTC 24 |
| Peak memory | 235144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641384018 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.641384018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_all.3970830919 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 3590701678 ps |
| CPU time | 31.67 seconds |
| Started | Sep 04 08:28:17 AM UTC 24 |
| Finished | Sep 04 08:28:50 AM UTC 24 |
| Peak memory | 227892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970830919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3970830919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.500778287 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1987756856 ps |
| CPU time | 12.31 seconds |
| Started | Sep 04 08:28:17 AM UTC 24 |
| Finished | Sep 04 08:28:30 AM UTC 24 |
| Peak memory | 227828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500778287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.500778287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_rw.3218759087 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 17747772 ps |
| CPU time | 1.15 seconds |
| Started | Sep 04 08:28:18 AM UTC 24 |
| Finished | Sep 04 08:28:20 AM UTC 24 |
| Peak memory | 215984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218759087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3218759087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.2999424887 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 144960043 ps |
| CPU time | 1.24 seconds |
| Started | Sep 04 08:28:18 AM UTC 24 |
| Finished | Sep 04 08:28:21 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999424887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2999424887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/17.spi_device_upload.1117719578 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 258382137 ps |
| CPU time | 3.58 seconds |
| Started | Sep 04 08:28:21 AM UTC 24 |
| Finished | Sep 04 08:28:26 AM UTC 24 |
| Peak memory | 235156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117719578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1117719578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/17.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_alert_test.2599736277 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 30848315 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 08:28:43 AM UTC 24 |
| Finished | Sep 04 08:28:45 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599736277 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.2599736277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_cfg_cmd.3479190078 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 373422888 ps |
| CPU time | 4.51 seconds |
| Started | Sep 04 08:28:38 AM UTC 24 |
| Finished | Sep 04 08:28:44 AM UTC 24 |
| Peak memory | 245596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479190078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3479190078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_csb_read.2395500513 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 63750141 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 08:28:31 AM UTC 24 |
| Finished | Sep 04 08:28:34 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395500513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2395500513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_all.64801923 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 79243046027 ps |
| CPU time | 80.47 seconds |
| Started | Sep 04 08:28:41 AM UTC 24 |
| Finished | Sep 04 08:30:04 AM UTC 24 |
| Peak memory | 262300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64801923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.64801923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.2191910389 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 4220325526 ps |
| CPU time | 110.14 seconds |
| Started | Sep 04 08:28:41 AM UTC 24 |
| Finished | Sep 04 08:30:34 AM UTC 24 |
| Peak memory | 278732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191910389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2191910389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.3580036785 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 123716237092 ps |
| CPU time | 197.69 seconds |
| Started | Sep 04 08:28:42 AM UTC 24 |
| Finished | Sep 04 08:32:03 AM UTC 24 |
| Peak memory | 262144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580036785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.3580036785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode.769493677 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1338119951 ps |
| CPU time | 23.23 seconds |
| Started | Sep 04 08:28:39 AM UTC 24 |
| Finished | Sep 04 08:29:03 AM UTC 24 |
| Peak memory | 235340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769493677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.769493677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.2770409086 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 14229721599 ps |
| CPU time | 73.25 seconds |
| Started | Sep 04 08:28:40 AM UTC 24 |
| Finished | Sep 04 08:29:55 AM UTC 24 |
| Peak memory | 262088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770409086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.2770409086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_intercept.843942317 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 3216540325 ps |
| CPU time | 13.36 seconds |
| Started | Sep 04 08:28:37 AM UTC 24 |
| Finished | Sep 04 08:28:51 AM UTC 24 |
| Peak memory | 235468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843942317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.843942317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mailbox.276059681 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 3887076954 ps |
| CPU time | 19.16 seconds |
| Started | Sep 04 08:28:37 AM UTC 24 |
| Finished | Sep 04 08:28:57 AM UTC 24 |
| Peak memory | 245860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276059681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.276059681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mem_parity.206829116 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 31407360 ps |
| CPU time | 1.42 seconds |
| Started | Sep 04 08:28:31 AM UTC 24 |
| Finished | Sep 04 08:28:34 AM UTC 24 |
| Peak memory | 229200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206829116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mem_parity.206829116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.635076575 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 60232343 ps |
| CPU time | 4.07 seconds |
| Started | Sep 04 08:28:37 AM UTC 24 |
| Finished | Sep 04 08:28:42 AM UTC 24 |
| Peak memory | 245800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635076575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.635076575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.1478083002 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 846987830 ps |
| CPU time | 6.31 seconds |
| Started | Sep 04 08:28:35 AM UTC 24 |
| Finished | Sep 04 08:28:42 AM UTC 24 |
| Peak memory | 242200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478083002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1478083002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.3536634773 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 452076949 ps |
| CPU time | 4.53 seconds |
| Started | Sep 04 08:28:41 AM UTC 24 |
| Finished | Sep 04 08:28:47 AM UTC 24 |
| Peak memory | 233844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536634773 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.3536634773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.1856751692 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 159495786005 ps |
| CPU time | 429.08 seconds |
| Started | Sep 04 08:28:42 AM UTC 24 |
| Finished | Sep 04 08:35:57 AM UTC 24 |
| Peak memory | 294916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856751692 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.1856751692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_all.831083702 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 741346768 ps |
| CPU time | 2.86 seconds |
| Started | Sep 04 08:28:32 AM UTC 24 |
| Finished | Sep 04 08:28:36 AM UTC 24 |
| Peak memory | 227768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831083702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.831083702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.176534708 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 893987055 ps |
| CPU time | 7.36 seconds |
| Started | Sep 04 08:28:31 AM UTC 24 |
| Finished | Sep 04 08:28:40 AM UTC 24 |
| Peak memory | 227944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176534708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.176534708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_rw.3490802113 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 135422651 ps |
| CPU time | 2.44 seconds |
| Started | Sep 04 08:28:35 AM UTC 24 |
| Finished | Sep 04 08:28:38 AM UTC 24 |
| Peak memory | 227976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490802113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3490802113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.1316405969 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 169975310 ps |
| CPU time | 1.38 seconds |
| Started | Sep 04 08:28:33 AM UTC 24 |
| Finished | Sep 04 08:28:36 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316405969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1316405969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_upload.1802569381 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 862798090 ps |
| CPU time | 7 seconds |
| Started | Sep 04 08:28:38 AM UTC 24 |
| Finished | Sep 04 08:28:46 AM UTC 24 |
| Peak memory | 245788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802569381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1802569381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/18.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_alert_test.3126841865 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 47395895 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 08:29:01 AM UTC 24 |
| Finished | Sep 04 08:29:03 AM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126841865 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.3126841865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_cfg_cmd.3741791437 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 939028856 ps |
| CPU time | 15.01 seconds |
| Started | Sep 04 08:28:53 AM UTC 24 |
| Finished | Sep 04 08:29:10 AM UTC 24 |
| Peak memory | 235528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741791437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3741791437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_csb_read.1792751995 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 19599676 ps |
| CPU time | 0.91 seconds |
| Started | Sep 04 08:28:45 AM UTC 24 |
| Finished | Sep 04 08:28:46 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792751995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1792751995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_all.926043945 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 3884982414 ps |
| CPU time | 60.99 seconds |
| Started | Sep 04 08:28:58 AM UTC 24 |
| Finished | Sep 04 08:30:00 AM UTC 24 |
| Peak memory | 262148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926043945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.926043945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.3128287108 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 4354983683 ps |
| CPU time | 50.92 seconds |
| Started | Sep 04 08:28:58 AM UTC 24 |
| Finished | Sep 04 08:29:50 AM UTC 24 |
| Peak memory | 262216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128287108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3128287108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.2050517699 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 24783823731 ps |
| CPU time | 278.44 seconds |
| Started | Sep 04 08:28:58 AM UTC 24 |
| Finished | Sep 04 08:33:40 AM UTC 24 |
| Peak memory | 264420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050517699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.2050517699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode.2070904380 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 8335495375 ps |
| CPU time | 65.06 seconds |
| Started | Sep 04 08:28:55 AM UTC 24 |
| Finished | Sep 04 08:30:02 AM UTC 24 |
| Peak memory | 264336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070904380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2070904380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_intercept.2766695177 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 2430720834 ps |
| CPU time | 22.97 seconds |
| Started | Sep 04 08:28:51 AM UTC 24 |
| Finished | Sep 04 08:29:15 AM UTC 24 |
| Peak memory | 245680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766695177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2766695177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mailbox.1752595069 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1426656507 ps |
| CPU time | 27.36 seconds |
| Started | Sep 04 08:28:52 AM UTC 24 |
| Finished | Sep 04 08:29:21 AM UTC 24 |
| Peak memory | 245600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752595069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1752595069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mem_parity.1677045401 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 66633404 ps |
| CPU time | 1.49 seconds |
| Started | Sep 04 08:28:46 AM UTC 24 |
| Finished | Sep 04 08:28:48 AM UTC 24 |
| Peak memory | 229264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677045401 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mem_parity.1677045401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.1361250018 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 16413467626 ps |
| CPU time | 18.88 seconds |
| Started | Sep 04 08:28:51 AM UTC 24 |
| Finished | Sep 04 08:29:11 AM UTC 24 |
| Peak memory | 235472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361250018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.1361250018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.3611714649 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 64824016 ps |
| CPU time | 3.19 seconds |
| Started | Sep 04 08:28:50 AM UTC 24 |
| Finished | Sep 04 08:28:54 AM UTC 24 |
| Peak memory | 245580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611714649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3611714649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.13614944 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 632701447 ps |
| CPU time | 3.89 seconds |
| Started | Sep 04 08:28:57 AM UTC 24 |
| Finished | Sep 04 08:29:01 AM UTC 24 |
| Peak memory | 231736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13614944 -assert nopostproc +UVM_TESTNAME=spi_device_bas e_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.13614944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_stress_all.2478116188 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 62403592569 ps |
| CPU time | 329.2 seconds |
| Started | Sep 04 08:29:01 AM UTC 24 |
| Finished | Sep 04 08:34:35 AM UTC 24 |
| Peak memory | 297064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478116188 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.2478116188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_all.3562235357 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 3674755807 ps |
| CPU time | 22.7 seconds |
| Started | Sep 04 08:28:47 AM UTC 24 |
| Finished | Sep 04 08:29:11 AM UTC 24 |
| Peak memory | 228056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562235357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3562235357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.1636566417 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 3903227406 ps |
| CPU time | 7.18 seconds |
| Started | Sep 04 08:28:47 AM UTC 24 |
| Finished | Sep 04 08:28:55 AM UTC 24 |
| Peak memory | 228024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636566417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1636566417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_rw.843232862 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 100865756 ps |
| CPU time | 1.51 seconds |
| Started | Sep 04 08:28:49 AM UTC 24 |
| Finished | Sep 04 08:28:51 AM UTC 24 |
| Peak memory | 217168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843232862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.843232862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.2435370846 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 50745824 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 08:28:48 AM UTC 24 |
| Finished | Sep 04 08:28:50 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435370846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2435370846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_upload.3106889795 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 372457419 ps |
| CPU time | 3.12 seconds |
| Started | Sep 04 08:28:52 AM UTC 24 |
| Finished | Sep 04 08:28:56 AM UTC 24 |
| Peak memory | 235400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106889795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3106889795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/19.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.1565032811 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 19583994 ps |
| CPU time | 1.09 seconds |
| Started | Sep 04 08:24:08 AM UTC 24 |
| Finished | Sep 04 08:24:10 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565032811 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1565032811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.257375700 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1472296888 ps |
| CPU time | 10.63 seconds |
| Started | Sep 04 08:23:54 AM UTC 24 |
| Finished | Sep 04 08:24:05 AM UTC 24 |
| Peak memory | 245636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257375700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.257375700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.1218948135 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 55820753 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 08:23:43 AM UTC 24 |
| Finished | Sep 04 08:23:45 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218948135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1218948135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.2618378808 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 176581033050 ps |
| CPU time | 323.96 seconds |
| Started | Sep 04 08:23:58 AM UTC 24 |
| Finished | Sep 04 08:29:27 AM UTC 24 |
| Peak memory | 262172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618378808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2618378808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.2687004273 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 654574083 ps |
| CPU time | 10.89 seconds |
| Started | Sep 04 08:23:56 AM UTC 24 |
| Finished | Sep 04 08:24:08 AM UTC 24 |
| Peak memory | 245540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687004273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2687004273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.479296940 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 30578720369 ps |
| CPU time | 80.6 seconds |
| Started | Sep 04 08:23:57 AM UTC 24 |
| Finished | Sep 04 08:25:19 AM UTC 24 |
| Peak memory | 268332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479296940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.479296940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.1305173008 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 6457469443 ps |
| CPU time | 16.84 seconds |
| Started | Sep 04 08:23:51 AM UTC 24 |
| Finished | Sep 04 08:24:09 AM UTC 24 |
| Peak memory | 235472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305173008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1305173008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.1685145525 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 6561974559 ps |
| CPU time | 91.42 seconds |
| Started | Sep 04 08:23:53 AM UTC 24 |
| Finished | Sep 04 08:25:26 AM UTC 24 |
| Peak memory | 245728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685145525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1685145525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.4057659706 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 499245624 ps |
| CPU time | 5.8 seconds |
| Started | Sep 04 08:23:50 AM UTC 24 |
| Finished | Sep 04 08:23:57 AM UTC 24 |
| Peak memory | 235408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057659706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.4057659706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.3595772115 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 2508316763 ps |
| CPU time | 6.23 seconds |
| Started | Sep 04 08:23:49 AM UTC 24 |
| Finished | Sep 04 08:23:56 AM UTC 24 |
| Peak memory | 235408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595772115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3595772115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.668904636 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 823175865 ps |
| CPU time | 6.53 seconds |
| Started | Sep 04 08:23:58 AM UTC 24 |
| Finished | Sep 04 08:24:06 AM UTC 24 |
| Peak memory | 231660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668904636 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.668904636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.4256604665 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 41971413 ps |
| CPU time | 1.6 seconds |
| Started | Sep 04 08:24:06 AM UTC 24 |
| Finished | Sep 04 08:24:09 AM UTC 24 |
| Peak memory | 257740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256604665 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.4256604665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.1514097161 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 205001466 ps |
| CPU time | 1.48 seconds |
| Started | Sep 04 08:24:06 AM UTC 24 |
| Finished | Sep 04 08:24:09 AM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514097161 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.1514097161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.1739803730 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1301113602 ps |
| CPU time | 5.77 seconds |
| Started | Sep 04 08:23:46 AM UTC 24 |
| Finished | Sep 04 08:23:53 AM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739803730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1739803730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.2100645399 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 156592317 ps |
| CPU time | 2.21 seconds |
| Started | Sep 04 08:23:48 AM UTC 24 |
| Finished | Sep 04 08:23:51 AM UTC 24 |
| Peak memory | 227780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100645399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2100645399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.2818347599 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 151386117 ps |
| CPU time | 1.33 seconds |
| Started | Sep 04 08:23:47 AM UTC 24 |
| Finished | Sep 04 08:23:49 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818347599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2818347599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.2901092594 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 64161622546 ps |
| CPU time | 75.72 seconds |
| Started | Sep 04 08:23:54 AM UTC 24 |
| Finished | Sep 04 08:25:11 AM UTC 24 |
| Peak memory | 245668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901092594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2901092594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/2.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_alert_test.3975998489 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 49138361 ps |
| CPU time | 1.08 seconds |
| Started | Sep 04 08:29:18 AM UTC 24 |
| Finished | Sep 04 08:29:20 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975998489 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.3975998489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/20.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_cfg_cmd.3962580207 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 1171298591 ps |
| CPU time | 3.99 seconds |
| Started | Sep 04 08:29:12 AM UTC 24 |
| Finished | Sep 04 08:29:17 AM UTC 24 |
| Peak memory | 235340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962580207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3962580207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/20.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_csb_read.496317604 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 17678440 ps |
| CPU time | 1.17 seconds |
| Started | Sep 04 08:29:02 AM UTC 24 |
| Finished | Sep 04 08:29:04 AM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496317604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.496317604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/20.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_all.3357896091 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1120878322 ps |
| CPU time | 34.88 seconds |
| Started | Sep 04 08:29:16 AM UTC 24 |
| Finished | Sep 04 08:29:52 AM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357896091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3357896091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/20.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.2639470498 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 3680525600 ps |
| CPU time | 41.28 seconds |
| Started | Sep 04 08:29:17 AM UTC 24 |
| Finished | Sep 04 08:30:00 AM UTC 24 |
| Peak memory | 252172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639470498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2639470498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.941962896 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 4194031186 ps |
| CPU time | 99.39 seconds |
| Started | Sep 04 08:29:17 AM UTC 24 |
| Finished | Sep 04 08:30:59 AM UTC 24 |
| Peak memory | 266464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941962896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.941962896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode.434204342 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 1087864826 ps |
| CPU time | 13.98 seconds |
| Started | Sep 04 08:29:13 AM UTC 24 |
| Finished | Sep 04 08:29:28 AM UTC 24 |
| Peak memory | 247720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434204342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.434204342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/20.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.1902440322 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 1224632203 ps |
| CPU time | 15.23 seconds |
| Started | Sep 04 08:29:13 AM UTC 24 |
| Finished | Sep 04 08:29:29 AM UTC 24 |
| Peak memory | 245796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902440322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.1902440322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_intercept.1300852060 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 3503259450 ps |
| CPU time | 35.7 seconds |
| Started | Sep 04 08:29:11 AM UTC 24 |
| Finished | Sep 04 08:29:48 AM UTC 24 |
| Peak memory | 235412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300852060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1300852060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/20.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_mailbox.3295876974 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 786112254 ps |
| CPU time | 4.28 seconds |
| Started | Sep 04 08:29:11 AM UTC 24 |
| Finished | Sep 04 08:29:16 AM UTC 24 |
| Peak memory | 235620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295876974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3295876974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/20.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.1958393442 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 2162250298 ps |
| CPU time | 6.62 seconds |
| Started | Sep 04 08:29:09 AM UTC 24 |
| Finished | Sep 04 08:29:17 AM UTC 24 |
| Peak memory | 235408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958393442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.1958393442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/20.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.3383853559 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 765488904 ps |
| CPU time | 4.59 seconds |
| Started | Sep 04 08:29:09 AM UTC 24 |
| Finished | Sep 04 08:29:15 AM UTC 24 |
| Peak memory | 235340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383853559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3383853559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/20.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.336124742 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 1512201681 ps |
| CPU time | 20.38 seconds |
| Started | Sep 04 08:29:16 AM UTC 24 |
| Finished | Sep 04 08:29:38 AM UTC 24 |
| Peak memory | 231660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336124742 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.336124742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/20.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_stress_all.3538215398 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 176016171843 ps |
| CPU time | 1057.13 seconds |
| Started | Sep 04 08:29:18 AM UTC 24 |
| Finished | Sep 04 08:47:08 AM UTC 24 |
| Peak memory | 284868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538215398 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.3538215398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/20.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_all.181253214 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 27783159763 ps |
| CPU time | 19.23 seconds |
| Started | Sep 04 08:29:04 AM UTC 24 |
| Finished | Sep 04 08:29:24 AM UTC 24 |
| Peak memory | 227956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181253214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.181253214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/20.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.500478006 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 1281739744 ps |
| CPU time | 3.31 seconds |
| Started | Sep 04 08:29:04 AM UTC 24 |
| Finished | Sep 04 08:29:08 AM UTC 24 |
| Peak memory | 217240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500478006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.500478006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/20.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_rw.294192252 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 92368699 ps |
| CPU time | 2.43 seconds |
| Started | Sep 04 08:29:08 AM UTC 24 |
| Finished | Sep 04 08:29:12 AM UTC 24 |
| Peak memory | 227952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294192252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.294192252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/20.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.1513536237 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 38411065 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 08:29:05 AM UTC 24 |
| Finished | Sep 04 08:29:07 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513536237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1513536237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/20.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_upload.2158332465 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 483462494 ps |
| CPU time | 4.95 seconds |
| Started | Sep 04 08:29:12 AM UTC 24 |
| Finished | Sep 04 08:29:18 AM UTC 24 |
| Peak memory | 235364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158332465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2158332465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/20.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_alert_test.2326086327 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 41925866 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 08:29:40 AM UTC 24 |
| Finished | Sep 04 08:29:42 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326086327 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.2326086327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/21.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_cfg_cmd.3781066852 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 280211144 ps |
| CPU time | 3.56 seconds |
| Started | Sep 04 08:29:29 AM UTC 24 |
| Finished | Sep 04 08:29:34 AM UTC 24 |
| Peak memory | 235332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781066852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3781066852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/21.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_csb_read.597744448 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 28196037 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 08:29:21 AM UTC 24 |
| Finished | Sep 04 08:29:23 AM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597744448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.597744448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/21.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_all.697365277 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 5962866946 ps |
| CPU time | 57.99 seconds |
| Started | Sep 04 08:29:35 AM UTC 24 |
| Finished | Sep 04 08:30:34 AM UTC 24 |
| Peak memory | 247752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697365277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.697365277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/21.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.1367275649 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 109933765412 ps |
| CPU time | 275.28 seconds |
| Started | Sep 04 08:29:39 AM UTC 24 |
| Finished | Sep 04 08:34:18 AM UTC 24 |
| Peak memory | 268328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367275649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1367275649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.393236707 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 28184782402 ps |
| CPU time | 67.56 seconds |
| Started | Sep 04 08:29:39 AM UTC 24 |
| Finished | Sep 04 08:30:48 AM UTC 24 |
| Peak memory | 264124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393236707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.393236707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode.3386301531 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 2004892660 ps |
| CPU time | 3.89 seconds |
| Started | Sep 04 08:29:29 AM UTC 24 |
| Finished | Sep 04 08:29:34 AM UTC 24 |
| Peak memory | 235404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386301531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3386301531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/21.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.810876120 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 10563397742 ps |
| CPU time | 47.7 seconds |
| Started | Sep 04 08:29:30 AM UTC 24 |
| Finished | Sep 04 08:30:20 AM UTC 24 |
| Peak memory | 262080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810876120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.810876120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_intercept.2204430722 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 5121846766 ps |
| CPU time | 21.96 seconds |
| Started | Sep 04 08:29:27 AM UTC 24 |
| Finished | Sep 04 08:29:50 AM UTC 24 |
| Peak memory | 245700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204430722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2204430722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/21.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_mailbox.63563599 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 545606524 ps |
| CPU time | 11.55 seconds |
| Started | Sep 04 08:29:28 AM UTC 24 |
| Finished | Sep 04 08:29:41 AM UTC 24 |
| Peak memory | 245516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63563599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.63563599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/21.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.3632017653 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 4793025414 ps |
| CPU time | 10.85 seconds |
| Started | Sep 04 08:29:27 AM UTC 24 |
| Finished | Sep 04 08:29:39 AM UTC 24 |
| Peak memory | 245736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632017653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.3632017653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/21.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.2290382511 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 391212590 ps |
| CPU time | 10.88 seconds |
| Started | Sep 04 08:29:26 AM UTC 24 |
| Finished | Sep 04 08:29:38 AM UTC 24 |
| Peak memory | 251944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290382511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2290382511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/21.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.155379543 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 246957656 ps |
| CPU time | 5.86 seconds |
| Started | Sep 04 08:29:35 AM UTC 24 |
| Finished | Sep 04 08:29:41 AM UTC 24 |
| Peak memory | 231796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155379543 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.155379543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/21.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_stress_all.4202866712 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 302765422353 ps |
| CPU time | 209.02 seconds |
| Started | Sep 04 08:29:40 AM UTC 24 |
| Finished | Sep 04 08:33:12 AM UTC 24 |
| Peak memory | 268292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202866712 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.4202866712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/21.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_all.4047451936 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 5254067325 ps |
| CPU time | 32.83 seconds |
| Started | Sep 04 08:29:25 AM UTC 24 |
| Finished | Sep 04 08:29:59 AM UTC 24 |
| Peak memory | 227992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047451936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.4047451936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/21.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.4281381684 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 10157582892 ps |
| CPU time | 20.72 seconds |
| Started | Sep 04 08:29:21 AM UTC 24 |
| Finished | Sep 04 08:29:43 AM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281381684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.4281381684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/21.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_rw.1882459540 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 457383525 ps |
| CPU time | 1.64 seconds |
| Started | Sep 04 08:29:26 AM UTC 24 |
| Finished | Sep 04 08:29:28 AM UTC 24 |
| Peak memory | 216504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882459540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1882459540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/21.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.2359758784 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 312260628 ps |
| CPU time | 1.38 seconds |
| Started | Sep 04 08:29:25 AM UTC 24 |
| Finished | Sep 04 08:29:27 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359758784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2359758784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/21.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/21.spi_device_upload.3586274055 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 15071233557 ps |
| CPU time | 31.4 seconds |
| Started | Sep 04 08:29:28 AM UTC 24 |
| Finished | Sep 04 08:30:01 AM UTC 24 |
| Peak memory | 245732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586274055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3586274055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/21.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_alert_test.2513019825 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 12582072 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 08:29:58 AM UTC 24 |
| Finished | Sep 04 08:30:00 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513019825 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.2513019825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/22.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_cfg_cmd.1762537197 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 2141187231 ps |
| CPU time | 23.72 seconds |
| Started | Sep 04 08:29:51 AM UTC 24 |
| Finished | Sep 04 08:30:16 AM UTC 24 |
| Peak memory | 235332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762537197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1762537197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/22.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_csb_read.2816557804 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 82338932 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 08:29:42 AM UTC 24 |
| Finished | Sep 04 08:29:46 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816557804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2816557804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/22.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_all.3459051220 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 4937660576 ps |
| CPU time | 58.65 seconds |
| Started | Sep 04 08:29:53 AM UTC 24 |
| Finished | Sep 04 08:30:53 AM UTC 24 |
| Peak memory | 262084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459051220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3459051220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/22.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.117563329 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 14431472033 ps |
| CPU time | 95.57 seconds |
| Started | Sep 04 08:29:54 AM UTC 24 |
| Finished | Sep 04 08:31:32 AM UTC 24 |
| Peak memory | 262148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117563329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.117563329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/22.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.735418797 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 6582366154 ps |
| CPU time | 140.56 seconds |
| Started | Sep 04 08:29:56 AM UTC 24 |
| Finished | Sep 04 08:32:19 AM UTC 24 |
| Peak memory | 262140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735418797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.735418797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode.1658954562 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 6639634784 ps |
| CPU time | 9.4 seconds |
| Started | Sep 04 08:29:51 AM UTC 24 |
| Finished | Sep 04 08:30:01 AM UTC 24 |
| Peak memory | 235664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658954562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1658954562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/22.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.3239273325 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 23457786488 ps |
| CPU time | 164.17 seconds |
| Started | Sep 04 08:29:52 AM UTC 24 |
| Finished | Sep 04 08:32:39 AM UTC 24 |
| Peak memory | 262280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239273325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.3239273325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_intercept.107990546 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 135323157 ps |
| CPU time | 3.79 seconds |
| Started | Sep 04 08:29:48 AM UTC 24 |
| Finished | Sep 04 08:29:53 AM UTC 24 |
| Peak memory | 245800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107990546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.107990546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/22.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_mailbox.2722921632 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 4880742328 ps |
| CPU time | 16.53 seconds |
| Started | Sep 04 08:29:49 AM UTC 24 |
| Finished | Sep 04 08:30:06 AM UTC 24 |
| Peak memory | 245668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722921632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2722921632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/22.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.3274252408 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 253687204 ps |
| CPU time | 3.4 seconds |
| Started | Sep 04 08:29:46 AM UTC 24 |
| Finished | Sep 04 08:29:51 AM UTC 24 |
| Peak memory | 235332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274252408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.3274252408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/22.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.183959191 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 611339045 ps |
| CPU time | 3.34 seconds |
| Started | Sep 04 08:29:46 AM UTC 24 |
| Finished | Sep 04 08:29:51 AM UTC 24 |
| Peak memory | 235472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183959191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.183959191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/22.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.4240773348 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 476339539 ps |
| CPU time | 3.47 seconds |
| Started | Sep 04 08:29:52 AM UTC 24 |
| Finished | Sep 04 08:29:56 AM UTC 24 |
| Peak memory | 234028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240773348 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.4240773348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/22.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_all.3853378105 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 2639407918 ps |
| CPU time | 16.14 seconds |
| Started | Sep 04 08:29:42 AM UTC 24 |
| Finished | Sep 04 08:30:00 AM UTC 24 |
| Peak memory | 228084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853378105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3853378105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/22.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.2924949334 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2377726858 ps |
| CPU time | 13.97 seconds |
| Started | Sep 04 08:29:42 AM UTC 24 |
| Finished | Sep 04 08:29:57 AM UTC 24 |
| Peak memory | 228088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924949334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2924949334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/22.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_rw.2810847710 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 241600866 ps |
| CPU time | 2.2 seconds |
| Started | Sep 04 08:29:44 AM UTC 24 |
| Finished | Sep 04 08:29:48 AM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810847710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2810847710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/22.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.2925797319 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 232825536 ps |
| CPU time | 1.24 seconds |
| Started | Sep 04 08:29:43 AM UTC 24 |
| Finished | Sep 04 08:29:46 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925797319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2925797319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/22.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_upload.317653191 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 209909831 ps |
| CPU time | 7.16 seconds |
| Started | Sep 04 08:29:51 AM UTC 24 |
| Finished | Sep 04 08:29:59 AM UTC 24 |
| Peak memory | 245772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317653191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.317653191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/22.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_alert_test.1604576239 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 11269867 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 08:30:11 AM UTC 24 |
| Finished | Sep 04 08:30:13 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604576239 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.1604576239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/23.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_cfg_cmd.3132608643 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 632089631 ps |
| CPU time | 3.08 seconds |
| Started | Sep 04 08:30:04 AM UTC 24 |
| Finished | Sep 04 08:30:08 AM UTC 24 |
| Peak memory | 235356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132608643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3132608643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/23.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_csb_read.1549757810 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 15714675 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 08:29:59 AM UTC 24 |
| Finished | Sep 04 08:30:02 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549757810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1549757810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/23.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_all.1758154110 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 39464951386 ps |
| CPU time | 113.73 seconds |
| Started | Sep 04 08:30:08 AM UTC 24 |
| Finished | Sep 04 08:32:04 AM UTC 24 |
| Peak memory | 266184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758154110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1758154110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/23.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.60750859 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 9727430801 ps |
| CPU time | 62.6 seconds |
| Started | Sep 04 08:30:09 AM UTC 24 |
| Finished | Sep 04 08:31:14 AM UTC 24 |
| Peak memory | 230220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60750859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.60750859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.11362425 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 176966058060 ps |
| CPU time | 487.01 seconds |
| Started | Sep 04 08:30:09 AM UTC 24 |
| Finished | Sep 04 08:38:23 AM UTC 24 |
| Peak memory | 278528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11362425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.11362425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode.1066396383 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 6420738294 ps |
| CPU time | 21.39 seconds |
| Started | Sep 04 08:30:04 AM UTC 24 |
| Finished | Sep 04 08:30:27 AM UTC 24 |
| Peak memory | 245932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066396383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1066396383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/23.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.3956674655 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 15203335702 ps |
| CPU time | 49.33 seconds |
| Started | Sep 04 08:30:05 AM UTC 24 |
| Finished | Sep 04 08:30:56 AM UTC 24 |
| Peak memory | 252040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956674655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.3956674655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_intercept.3754812037 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1063761966 ps |
| CPU time | 5.56 seconds |
| Started | Sep 04 08:30:03 AM UTC 24 |
| Finished | Sep 04 08:30:10 AM UTC 24 |
| Peak memory | 245576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754812037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3754812037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/23.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_mailbox.2177226627 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1909968296 ps |
| CPU time | 8.23 seconds |
| Started | Sep 04 08:30:03 AM UTC 24 |
| Finished | Sep 04 08:30:12 AM UTC 24 |
| Peak memory | 235332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177226627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2177226627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/23.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.108879437 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 667182639 ps |
| CPU time | 10.2 seconds |
| Started | Sep 04 08:30:02 AM UTC 24 |
| Finished | Sep 04 08:30:13 AM UTC 24 |
| Peak memory | 245512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108879437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.108879437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/23.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.139557568 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 514815740 ps |
| CPU time | 7.79 seconds |
| Started | Sep 04 08:30:02 AM UTC 24 |
| Finished | Sep 04 08:30:11 AM UTC 24 |
| Peak memory | 235280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139557568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.139557568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/23.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.4277770853 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 617063437 ps |
| CPU time | 10.28 seconds |
| Started | Sep 04 08:30:07 AM UTC 24 |
| Finished | Sep 04 08:30:19 AM UTC 24 |
| Peak memory | 233684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277770853 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.4277770853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/23.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.2590370723 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 43935421189 ps |
| CPU time | 341.74 seconds |
| Started | Sep 04 08:30:09 AM UTC 24 |
| Finished | Sep 04 08:35:56 AM UTC 24 |
| Peak memory | 284676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590370723 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.2590370723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/23.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_all.3520022860 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 9525619845 ps |
| CPU time | 35.36 seconds |
| Started | Sep 04 08:30:00 AM UTC 24 |
| Finished | Sep 04 08:30:38 AM UTC 24 |
| Peak memory | 228084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520022860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3520022860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/23.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.382384411 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 2504513301 ps |
| CPU time | 9.49 seconds |
| Started | Sep 04 08:30:00 AM UTC 24 |
| Finished | Sep 04 08:30:11 AM UTC 24 |
| Peak memory | 227836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382384411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.382384411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/23.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_rw.1857818846 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 549235576 ps |
| CPU time | 5.13 seconds |
| Started | Sep 04 08:30:02 AM UTC 24 |
| Finished | Sep 04 08:30:08 AM UTC 24 |
| Peak memory | 228020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857818846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1857818846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/23.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.3390914340 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 852452290 ps |
| CPU time | 1.48 seconds |
| Started | Sep 04 08:30:01 AM UTC 24 |
| Finished | Sep 04 08:30:03 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390914340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3390914340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/23.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_upload.3961835802 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 249697699 ps |
| CPU time | 4.3 seconds |
| Started | Sep 04 08:30:03 AM UTC 24 |
| Finished | Sep 04 08:30:09 AM UTC 24 |
| Peak memory | 235460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961835802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3961835802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/23.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_alert_test.1035357363 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 37315760 ps |
| CPU time | 1.05 seconds |
| Started | Sep 04 08:30:35 AM UTC 24 |
| Finished | Sep 04 08:30:37 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035357363 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.1035357363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/24.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_cfg_cmd.1666702339 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 4110312042 ps |
| CPU time | 28.24 seconds |
| Started | Sep 04 08:30:19 AM UTC 24 |
| Finished | Sep 04 08:30:49 AM UTC 24 |
| Peak memory | 235380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666702339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1666702339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/24.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_csb_read.3720692006 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 23393628 ps |
| CPU time | 1.15 seconds |
| Started | Sep 04 08:30:12 AM UTC 24 |
| Finished | Sep 04 08:30:14 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720692006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3720692006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/24.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.4109568673 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 7802809477 ps |
| CPU time | 67.25 seconds |
| Started | Sep 04 08:30:29 AM UTC 24 |
| Finished | Sep 04 08:31:38 AM UTC 24 |
| Peak memory | 245128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109568673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.4109568673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.3205296698 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 212804772 ps |
| CPU time | 7.81 seconds |
| Started | Sep 04 08:30:19 AM UTC 24 |
| Finished | Sep 04 08:30:28 AM UTC 24 |
| Peak memory | 245708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205296698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3205296698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/24.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.1980626342 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 15047029635 ps |
| CPU time | 32.42 seconds |
| Started | Sep 04 08:30:20 AM UTC 24 |
| Finished | Sep 04 08:30:54 AM UTC 24 |
| Peak memory | 245704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980626342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.1980626342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_intercept.3359348906 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 10024619446 ps |
| CPU time | 23.43 seconds |
| Started | Sep 04 08:30:17 AM UTC 24 |
| Finished | Sep 04 08:30:42 AM UTC 24 |
| Peak memory | 235660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359348906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3359348906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/24.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_mailbox.1756061981 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 21645464642 ps |
| CPU time | 42.83 seconds |
| Started | Sep 04 08:30:17 AM UTC 24 |
| Finished | Sep 04 08:31:01 AM UTC 24 |
| Peak memory | 235460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756061981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1756061981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/24.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.1261384374 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 2280783090 ps |
| CPU time | 11.78 seconds |
| Started | Sep 04 08:30:15 AM UTC 24 |
| Finished | Sep 04 08:30:28 AM UTC 24 |
| Peak memory | 235408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261384374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.1261384374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/24.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.3892749742 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 92049144 ps |
| CPU time | 3.04 seconds |
| Started | Sep 04 08:30:15 AM UTC 24 |
| Finished | Sep 04 08:30:19 AM UTC 24 |
| Peak memory | 245548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892749742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3892749742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/24.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.1135913838 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 590369135 ps |
| CPU time | 10.89 seconds |
| Started | Sep 04 08:30:27 AM UTC 24 |
| Finished | Sep 04 08:30:39 AM UTC 24 |
| Peak memory | 233908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135913838 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.1135913838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/24.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_all.124220684 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 1187541121 ps |
| CPU time | 10.47 seconds |
| Started | Sep 04 08:30:14 AM UTC 24 |
| Finished | Sep 04 08:30:25 AM UTC 24 |
| Peak memory | 230008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124220684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.124220684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/24.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.3330388281 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 40244351 ps |
| CPU time | 0.87 seconds |
| Started | Sep 04 08:30:13 AM UTC 24 |
| Finished | Sep 04 08:30:15 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330388281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3330388281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/24.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_rw.1991681499 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 104060617 ps |
| CPU time | 1.65 seconds |
| Started | Sep 04 08:30:14 AM UTC 24 |
| Finished | Sep 04 08:30:17 AM UTC 24 |
| Peak memory | 216596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991681499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1991681499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/24.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.3373315433 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 40635200 ps |
| CPU time | 1.31 seconds |
| Started | Sep 04 08:30:14 AM UTC 24 |
| Finished | Sep 04 08:30:16 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373315433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3373315433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/24.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_upload.1309249055 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2202425855 ps |
| CPU time | 10.24 seconds |
| Started | Sep 04 08:30:17 AM UTC 24 |
| Finished | Sep 04 08:30:28 AM UTC 24 |
| Peak memory | 245668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309249055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1309249055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/24.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_alert_test.1042797091 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 24070377 ps |
| CPU time | 1.07 seconds |
| Started | Sep 04 08:30:54 AM UTC 24 |
| Finished | Sep 04 08:30:56 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042797091 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.1042797091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/25.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_cfg_cmd.3198683325 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 259326295 ps |
| CPU time | 4.89 seconds |
| Started | Sep 04 08:30:48 AM UTC 24 |
| Finished | Sep 04 08:30:54 AM UTC 24 |
| Peak memory | 245544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198683325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3198683325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/25.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_csb_read.3516703283 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 19692328 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 08:30:35 AM UTC 24 |
| Finished | Sep 04 08:30:37 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516703283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3516703283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/25.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_all.4109281941 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 137968139804 ps |
| CPU time | 183.53 seconds |
| Started | Sep 04 08:30:52 AM UTC 24 |
| Finished | Sep 04 08:33:59 AM UTC 24 |
| Peak memory | 268424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109281941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.4109281941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/25.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.1735241276 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 47591288934 ps |
| CPU time | 123.72 seconds |
| Started | Sep 04 08:30:52 AM UTC 24 |
| Finished | Sep 04 08:32:58 AM UTC 24 |
| Peak memory | 264380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735241276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1735241276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.1005125415 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 6245581204 ps |
| CPU time | 80.06 seconds |
| Started | Sep 04 08:30:53 AM UTC 24 |
| Finished | Sep 04 08:32:15 AM UTC 24 |
| Peak memory | 266440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005125415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.1005125415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode.633300423 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 87151896 ps |
| CPU time | 4.38 seconds |
| Started | Sep 04 08:30:49 AM UTC 24 |
| Finished | Sep 04 08:30:54 AM UTC 24 |
| Peak memory | 245516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633300423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.633300423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/25.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.303959841 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 52424942773 ps |
| CPU time | 358.95 seconds |
| Started | Sep 04 08:30:50 AM UTC 24 |
| Finished | Sep 04 08:36:53 AM UTC 24 |
| Peak memory | 266464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303959841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.303959841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_intercept.2561106019 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1184192868 ps |
| CPU time | 12.73 seconds |
| Started | Sep 04 08:30:43 AM UTC 24 |
| Finished | Sep 04 08:30:56 AM UTC 24 |
| Peak memory | 235276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561106019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2561106019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/25.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_mailbox.3104144574 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 32450671 ps |
| CPU time | 2.33 seconds |
| Started | Sep 04 08:30:47 AM UTC 24 |
| Finished | Sep 04 08:30:50 AM UTC 24 |
| Peak memory | 234668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104144574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3104144574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/25.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.808415670 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 33044310 ps |
| CPU time | 2.89 seconds |
| Started | Sep 04 08:30:42 AM UTC 24 |
| Finished | Sep 04 08:30:46 AM UTC 24 |
| Peak memory | 245220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808415670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.808415670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/25.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.2174059066 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 637767810 ps |
| CPU time | 8.72 seconds |
| Started | Sep 04 08:30:41 AM UTC 24 |
| Finished | Sep 04 08:30:51 AM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174059066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2174059066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/25.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.460709519 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 110072782 ps |
| CPU time | 3.62 seconds |
| Started | Sep 04 08:30:51 AM UTC 24 |
| Finished | Sep 04 08:30:56 AM UTC 24 |
| Peak memory | 233980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460709519 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.460709519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/25.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.3336722393 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 27604461027 ps |
| CPU time | 261.31 seconds |
| Started | Sep 04 08:30:54 AM UTC 24 |
| Finished | Sep 04 08:35:19 AM UTC 24 |
| Peak memory | 262152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336722393 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.3336722393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/25.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_all.1105228802 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 1749441227 ps |
| CPU time | 38.6 seconds |
| Started | Sep 04 08:30:38 AM UTC 24 |
| Finished | Sep 04 08:31:18 AM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105228802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1105228802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/25.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.2956973424 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 20092471219 ps |
| CPU time | 15.1 seconds |
| Started | Sep 04 08:30:38 AM UTC 24 |
| Finished | Sep 04 08:30:54 AM UTC 24 |
| Peak memory | 228060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956973424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2956973424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/25.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_rw.2181579173 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 45530154 ps |
| CPU time | 1.34 seconds |
| Started | Sep 04 08:30:39 AM UTC 24 |
| Finished | Sep 04 08:30:42 AM UTC 24 |
| Peak memory | 215984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181579173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2181579173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/25.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.3311496359 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 73540356 ps |
| CPU time | 1.41 seconds |
| Started | Sep 04 08:30:38 AM UTC 24 |
| Finished | Sep 04 08:30:41 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311496359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3311496359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/25.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_upload.3835430155 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 456924515 ps |
| CPU time | 3.41 seconds |
| Started | Sep 04 08:30:48 AM UTC 24 |
| Finished | Sep 04 08:30:52 AM UTC 24 |
| Peak memory | 235308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835430155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3835430155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/25.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_alert_test.3190596996 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 23630196 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 08:31:15 AM UTC 24 |
| Finished | Sep 04 08:31:17 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190596996 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.3190596996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/26.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_cfg_cmd.1940342237 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 563480780 ps |
| CPU time | 2.35 seconds |
| Started | Sep 04 08:31:00 AM UTC 24 |
| Finished | Sep 04 08:31:03 AM UTC 24 |
| Peak memory | 235528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940342237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1940342237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/26.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_csb_read.1893026841 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 85586873 ps |
| CPU time | 1.22 seconds |
| Started | Sep 04 08:30:55 AM UTC 24 |
| Finished | Sep 04 08:30:58 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893026841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1893026841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/26.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.2789920473 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 3972624830 ps |
| CPU time | 71.09 seconds |
| Started | Sep 04 08:31:04 AM UTC 24 |
| Finished | Sep 04 08:32:17 AM UTC 24 |
| Peak memory | 266176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789920473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2789920473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/26.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.609709215 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 50556388297 ps |
| CPU time | 207.2 seconds |
| Started | Sep 04 08:31:07 AM UTC 24 |
| Finished | Sep 04 08:34:38 AM UTC 24 |
| Peak memory | 266444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609709215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.609709215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.2916697183 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 15256617945 ps |
| CPU time | 102.7 seconds |
| Started | Sep 04 08:31:09 AM UTC 24 |
| Finished | Sep 04 08:32:53 AM UTC 24 |
| Peak memory | 264220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916697183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.2916697183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode.2055788984 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 4464540403 ps |
| CPU time | 39.73 seconds |
| Started | Sep 04 08:31:00 AM UTC 24 |
| Finished | Sep 04 08:31:41 AM UTC 24 |
| Peak memory | 245732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055788984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2055788984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/26.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.3291907335 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 4558346857 ps |
| CPU time | 20.4 seconds |
| Started | Sep 04 08:31:02 AM UTC 24 |
| Finished | Sep 04 08:31:24 AM UTC 24 |
| Peak memory | 249800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291907335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.3291907335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_intercept.1247081971 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 2091542465 ps |
| CPU time | 9.92 seconds |
| Started | Sep 04 08:30:59 AM UTC 24 |
| Finished | Sep 04 08:31:10 AM UTC 24 |
| Peak memory | 245860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247081971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1247081971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/26.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_mailbox.3643817236 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 4024337420 ps |
| CPU time | 38.04 seconds |
| Started | Sep 04 08:30:59 AM UTC 24 |
| Finished | Sep 04 08:31:38 AM UTC 24 |
| Peak memory | 245724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643817236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3643817236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/26.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.27015398 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 2314482047 ps |
| CPU time | 3.61 seconds |
| Started | Sep 04 08:30:58 AM UTC 24 |
| Finished | Sep 04 08:31:02 AM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27015398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.27015398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/26.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.902119737 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 9227793892 ps |
| CPU time | 18.81 seconds |
| Started | Sep 04 08:30:58 AM UTC 24 |
| Finished | Sep 04 08:31:18 AM UTC 24 |
| Peak memory | 251456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902119737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.902119737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/26.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.2802405327 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 1156838047 ps |
| CPU time | 11.79 seconds |
| Started | Sep 04 08:31:03 AM UTC 24 |
| Finished | Sep 04 08:31:16 AM UTC 24 |
| Peak memory | 233780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802405327 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.2802405327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/26.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.1398113033 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 100393926 ps |
| CPU time | 1.5 seconds |
| Started | Sep 04 08:31:11 AM UTC 24 |
| Finished | Sep 04 08:31:14 AM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398113033 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.1398113033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/26.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_all.4206360328 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 3094969847 ps |
| CPU time | 19.27 seconds |
| Started | Sep 04 08:30:56 AM UTC 24 |
| Finished | Sep 04 08:31:16 AM UTC 24 |
| Peak memory | 227892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206360328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.4206360328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/26.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.543552281 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 14726354636 ps |
| CPU time | 10.06 seconds |
| Started | Sep 04 08:30:55 AM UTC 24 |
| Finished | Sep 04 08:31:07 AM UTC 24 |
| Peak memory | 228020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543552281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.543552281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/26.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_rw.3315430233 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 36092828 ps |
| CPU time | 1.25 seconds |
| Started | Sep 04 08:30:57 AM UTC 24 |
| Finished | Sep 04 08:30:59 AM UTC 24 |
| Peak memory | 215984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315430233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3315430233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/26.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.2744898211 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 37719432 ps |
| CPU time | 1.35 seconds |
| Started | Sep 04 08:30:57 AM UTC 24 |
| Finished | Sep 04 08:30:59 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744898211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2744898211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/26.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/26.spi_device_upload.4014852317 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 1495953533 ps |
| CPU time | 7.03 seconds |
| Started | Sep 04 08:31:00 AM UTC 24 |
| Finished | Sep 04 08:31:08 AM UTC 24 |
| Peak memory | 251684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014852317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.4014852317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/26.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_alert_test.3837034864 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 24724967 ps |
| CPU time | 1.09 seconds |
| Started | Sep 04 08:31:27 AM UTC 24 |
| Finished | Sep 04 08:31:30 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837034864 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.3837034864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/27.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_cfg_cmd.319765420 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 34784590 ps |
| CPU time | 2.96 seconds |
| Started | Sep 04 08:31:21 AM UTC 24 |
| Finished | Sep 04 08:31:25 AM UTC 24 |
| Peak memory | 245352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319765420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.319765420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/27.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_csb_read.4074116433 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 12979129 ps |
| CPU time | 1.15 seconds |
| Started | Sep 04 08:31:15 AM UTC 24 |
| Finished | Sep 04 08:31:17 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074116433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.4074116433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/27.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.2353190068 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 3078646711 ps |
| CPU time | 43.95 seconds |
| Started | Sep 04 08:31:25 AM UTC 24 |
| Finished | Sep 04 08:32:10 AM UTC 24 |
| Peak memory | 252104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353190068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2353190068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/27.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.2035708613 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 21884813354 ps |
| CPU time | 113.64 seconds |
| Started | Sep 04 08:31:25 AM UTC 24 |
| Finished | Sep 04 08:33:21 AM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035708613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2035708613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.313648940 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 6754150465 ps |
| CPU time | 76.56 seconds |
| Started | Sep 04 08:31:26 AM UTC 24 |
| Finished | Sep 04 08:32:45 AM UTC 24 |
| Peak memory | 262148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313648940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.313648940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode.3721942481 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 228920652 ps |
| CPU time | 5.63 seconds |
| Started | Sep 04 08:31:22 AM UTC 24 |
| Finished | Sep 04 08:31:28 AM UTC 24 |
| Peak memory | 235260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721942481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3721942481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/27.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.1893576414 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 25433890 ps |
| CPU time | 1.17 seconds |
| Started | Sep 04 08:31:24 AM UTC 24 |
| Finished | Sep 04 08:31:26 AM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893576414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.1893576414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_intercept.2077900709 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 62135408 ps |
| CPU time | 3.12 seconds |
| Started | Sep 04 08:31:18 AM UTC 24 |
| Finished | Sep 04 08:31:23 AM UTC 24 |
| Peak memory | 245392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077900709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2077900709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/27.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_mailbox.554111866 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 4849086478 ps |
| CPU time | 32.72 seconds |
| Started | Sep 04 08:31:20 AM UTC 24 |
| Finished | Sep 04 08:31:54 AM UTC 24 |
| Peak memory | 245924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554111866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.554111866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/27.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.3137123934 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 2414500098 ps |
| CPU time | 19.78 seconds |
| Started | Sep 04 08:31:18 AM UTC 24 |
| Finished | Sep 04 08:31:39 AM UTC 24 |
| Peak memory | 245708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137123934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.3137123934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/27.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.705250703 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 126148785 ps |
| CPU time | 4.6 seconds |
| Started | Sep 04 08:31:18 AM UTC 24 |
| Finished | Sep 04 08:31:24 AM UTC 24 |
| Peak memory | 245500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705250703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.705250703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/27.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.3507620511 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 899793115 ps |
| CPU time | 9.49 seconds |
| Started | Sep 04 08:31:25 AM UTC 24 |
| Finished | Sep 04 08:31:36 AM UTC 24 |
| Peak memory | 233716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507620511 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.3507620511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/27.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_all.3772607261 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 11712553322 ps |
| CPU time | 44.95 seconds |
| Started | Sep 04 08:31:16 AM UTC 24 |
| Finished | Sep 04 08:32:03 AM UTC 24 |
| Peak memory | 228144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772607261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3772607261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/27.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.600281019 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 278605054 ps |
| CPU time | 1.94 seconds |
| Started | Sep 04 08:31:16 AM UTC 24 |
| Finished | Sep 04 08:31:19 AM UTC 24 |
| Peak memory | 228024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600281019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.600281019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/27.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_rw.3040698132 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 336378328 ps |
| CPU time | 2.04 seconds |
| Started | Sep 04 08:31:17 AM UTC 24 |
| Finished | Sep 04 08:31:21 AM UTC 24 |
| Peak memory | 227952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040698132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3040698132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/27.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.3149936406 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 72460570 ps |
| CPU time | 1.25 seconds |
| Started | Sep 04 08:31:17 AM UTC 24 |
| Finished | Sep 04 08:31:20 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149936406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3149936406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/27.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_upload.1104576708 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 950848039 ps |
| CPU time | 5.94 seconds |
| Started | Sep 04 08:31:20 AM UTC 24 |
| Finished | Sep 04 08:31:27 AM UTC 24 |
| Peak memory | 235264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104576708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1104576708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/27.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_alert_test.1998014686 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 25527113 ps |
| CPU time | 1.09 seconds |
| Started | Sep 04 08:31:46 AM UTC 24 |
| Finished | Sep 04 08:31:48 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998014686 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.1998014686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/28.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_cfg_cmd.2050525469 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 1244450394 ps |
| CPU time | 6.08 seconds |
| Started | Sep 04 08:31:39 AM UTC 24 |
| Finished | Sep 04 08:31:46 AM UTC 24 |
| Peak memory | 245516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050525469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2050525469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/28.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_csb_read.3239483364 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 14094335 ps |
| CPU time | 1.15 seconds |
| Started | Sep 04 08:31:28 AM UTC 24 |
| Finished | Sep 04 08:31:31 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239483364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3239483364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/28.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.125487448 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 16102588305 ps |
| CPU time | 136.73 seconds |
| Started | Sep 04 08:31:42 AM UTC 24 |
| Finished | Sep 04 08:34:01 AM UTC 24 |
| Peak memory | 262280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125487448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.125487448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/28.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode.2684257377 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 3336843003 ps |
| CPU time | 68.55 seconds |
| Started | Sep 04 08:31:39 AM UTC 24 |
| Finished | Sep 04 08:32:50 AM UTC 24 |
| Peak memory | 262124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684257377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2684257377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/28.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.4092246296 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 6931895451 ps |
| CPU time | 31.84 seconds |
| Started | Sep 04 08:31:39 AM UTC 24 |
| Finished | Sep 04 08:32:13 AM UTC 24 |
| Peak memory | 245696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092246296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.4092246296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_intercept.2833898881 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 1825273562 ps |
| CPU time | 11.17 seconds |
| Started | Sep 04 08:31:35 AM UTC 24 |
| Finished | Sep 04 08:31:47 AM UTC 24 |
| Peak memory | 245612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833898881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2833898881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/28.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_mailbox.3192143913 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 125408798 ps |
| CPU time | 3.05 seconds |
| Started | Sep 04 08:31:36 AM UTC 24 |
| Finished | Sep 04 08:31:40 AM UTC 24 |
| Peak memory | 245252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192143913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3192143913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/28.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.3824855716 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 102576240 ps |
| CPU time | 2.26 seconds |
| Started | Sep 04 08:31:35 AM UTC 24 |
| Finished | Sep 04 08:31:38 AM UTC 24 |
| Peak memory | 233816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824855716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.3824855716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/28.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.173662439 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 511227297 ps |
| CPU time | 4.36 seconds |
| Started | Sep 04 08:31:33 AM UTC 24 |
| Finished | Sep 04 08:31:38 AM UTC 24 |
| Peak memory | 235536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173662439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.173662439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/28.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.2590478299 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 2036562480 ps |
| CPU time | 9.32 seconds |
| Started | Sep 04 08:31:39 AM UTC 24 |
| Finished | Sep 04 08:31:50 AM UTC 24 |
| Peak memory | 231664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590478299 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.2590478299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/28.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.642478239 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 51819519300 ps |
| CPU time | 351.96 seconds |
| Started | Sep 04 08:31:43 AM UTC 24 |
| Finished | Sep 04 08:37:40 AM UTC 24 |
| Peak memory | 268552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642478239 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.642478239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/28.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_all.248521084 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 3444019792 ps |
| CPU time | 22.25 seconds |
| Started | Sep 04 08:31:30 AM UTC 24 |
| Finished | Sep 04 08:31:54 AM UTC 24 |
| Peak memory | 227956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248521084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.248521084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/28.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.4271730366 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 1209057174 ps |
| CPU time | 8.05 seconds |
| Started | Sep 04 08:31:29 AM UTC 24 |
| Finished | Sep 04 08:31:38 AM UTC 24 |
| Peak memory | 227884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271730366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.4271730366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/28.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_rw.95328937 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 14437504 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 08:31:32 AM UTC 24 |
| Finished | Sep 04 08:31:34 AM UTC 24 |
| Peak memory | 215984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95328937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_devi ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.95328937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/28.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.1327755552 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 98683120 ps |
| CPU time | 1.63 seconds |
| Started | Sep 04 08:31:31 AM UTC 24 |
| Finished | Sep 04 08:31:34 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327755552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1327755552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/28.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_upload.2918117549 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 267658776 ps |
| CPU time | 6.08 seconds |
| Started | Sep 04 08:31:38 AM UTC 24 |
| Finished | Sep 04 08:31:45 AM UTC 24 |
| Peak memory | 245600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918117549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2918117549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/28.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_alert_test.3920790909 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 34634290 ps |
| CPU time | 1.09 seconds |
| Started | Sep 04 08:32:07 AM UTC 24 |
| Finished | Sep 04 08:32:09 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920790909 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.3920790909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/29.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_cfg_cmd.3959451748 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 78207316 ps |
| CPU time | 2.95 seconds |
| Started | Sep 04 08:31:59 AM UTC 24 |
| Finished | Sep 04 08:32:03 AM UTC 24 |
| Peak memory | 235336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959451748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3959451748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/29.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_csb_read.1281555785 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 66677395 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 08:31:47 AM UTC 24 |
| Finished | Sep 04 08:31:49 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281555785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1281555785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/29.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.4092213635 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 776948422 ps |
| CPU time | 23.82 seconds |
| Started | Sep 04 08:32:05 AM UTC 24 |
| Finished | Sep 04 08:32:30 AM UTC 24 |
| Peak memory | 245788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092213635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.4092213635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.1261435901 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 29414674809 ps |
| CPU time | 96.85 seconds |
| Started | Sep 04 08:32:07 AM UTC 24 |
| Finished | Sep 04 08:33:46 AM UTC 24 |
| Peak memory | 262368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261435901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.1261435901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode.3894562829 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 8256065609 ps |
| CPU time | 41.5 seconds |
| Started | Sep 04 08:32:00 AM UTC 24 |
| Finished | Sep 04 08:32:43 AM UTC 24 |
| Peak memory | 245732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894562829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3894562829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/29.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.3573828158 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 108277504 ps |
| CPU time | 1.01 seconds |
| Started | Sep 04 08:32:04 AM UTC 24 |
| Finished | Sep 04 08:32:06 AM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573828158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.3573828158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_intercept.3487991974 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 1368585362 ps |
| CPU time | 10.44 seconds |
| Started | Sep 04 08:31:55 AM UTC 24 |
| Finished | Sep 04 08:32:06 AM UTC 24 |
| Peak memory | 245864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487991974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3487991974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/29.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_mailbox.3867265490 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 25713463229 ps |
| CPU time | 51 seconds |
| Started | Sep 04 08:31:55 AM UTC 24 |
| Finished | Sep 04 08:32:47 AM UTC 24 |
| Peak memory | 247720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867265490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3867265490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/29.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.2662787078 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 7164880351 ps |
| CPU time | 32.09 seconds |
| Started | Sep 04 08:31:54 AM UTC 24 |
| Finished | Sep 04 08:32:27 AM UTC 24 |
| Peak memory | 245840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662787078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.2662787078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/29.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.3493531987 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 141054251 ps |
| CPU time | 3.47 seconds |
| Started | Sep 04 08:31:53 AM UTC 24 |
| Finished | Sep 04 08:31:58 AM UTC 24 |
| Peak memory | 245644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493531987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3493531987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/29.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.78548567 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 444783356 ps |
| CPU time | 5.5 seconds |
| Started | Sep 04 08:32:04 AM UTC 24 |
| Finished | Sep 04 08:32:10 AM UTC 24 |
| Peak memory | 233876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78548567 -assert nopostproc +UVM_TESTNAME=spi_device_bas e_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.78548567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/29.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_stress_all.3886945682 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 4573802638 ps |
| CPU time | 67.51 seconds |
| Started | Sep 04 08:32:07 AM UTC 24 |
| Finished | Sep 04 08:33:17 AM UTC 24 |
| Peak memory | 268512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886945682 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.3886945682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/29.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_all.4250302361 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 14857875596 ps |
| CPU time | 15.96 seconds |
| Started | Sep 04 08:31:49 AM UTC 24 |
| Finished | Sep 04 08:32:06 AM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250302361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.4250302361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/29.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.2776443865 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 5557277100 ps |
| CPU time | 16.75 seconds |
| Started | Sep 04 08:31:48 AM UTC 24 |
| Finished | Sep 04 08:32:06 AM UTC 24 |
| Peak memory | 227892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776443865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2776443865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/29.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_rw.38518426 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 47666881 ps |
| CPU time | 1.76 seconds |
| Started | Sep 04 08:31:50 AM UTC 24 |
| Finished | Sep 04 08:31:53 AM UTC 24 |
| Peak memory | 226952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38518426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_devi ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.38518426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/29.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.1537717137 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 141878428 ps |
| CPU time | 1.26 seconds |
| Started | Sep 04 08:31:50 AM UTC 24 |
| Finished | Sep 04 08:31:53 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537717137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1537717137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/29.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_upload.2824599894 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 1870463105 ps |
| CPU time | 14.97 seconds |
| Started | Sep 04 08:31:59 AM UTC 24 |
| Finished | Sep 04 08:32:15 AM UTC 24 |
| Peak memory | 245604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824599894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2824599894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/29.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.863600643 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 41430640 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 08:24:32 AM UTC 24 |
| Finished | Sep 04 08:24:34 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863600643 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.863600643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.1247618222 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 929734573 ps |
| CPU time | 12.77 seconds |
| Started | Sep 04 08:24:17 AM UTC 24 |
| Finished | Sep 04 08:24:31 AM UTC 24 |
| Peak memory | 245608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247618222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1247618222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.3741711896 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 40907737 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 08:24:09 AM UTC 24 |
| Finished | Sep 04 08:24:11 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741711896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3741711896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.306331535 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 48814359306 ps |
| CPU time | 376.08 seconds |
| Started | Sep 04 08:24:25 AM UTC 24 |
| Finished | Sep 04 08:30:47 AM UTC 24 |
| Peak memory | 268228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306331535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.306331535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.4077868276 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 105683583496 ps |
| CPU time | 151.73 seconds |
| Started | Sep 04 08:24:28 AM UTC 24 |
| Finished | Sep 04 08:27:03 AM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077868276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.4077868276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.3673345767 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 484322138 ps |
| CPU time | 11.65 seconds |
| Started | Sep 04 08:24:18 AM UTC 24 |
| Finished | Sep 04 08:24:31 AM UTC 24 |
| Peak memory | 235300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673345767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3673345767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.2220733458 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 5303305133 ps |
| CPU time | 86.74 seconds |
| Started | Sep 04 08:24:20 AM UTC 24 |
| Finished | Sep 04 08:25:49 AM UTC 24 |
| Peak memory | 262088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220733458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.2220733458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.3281335477 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3874237381 ps |
| CPU time | 14.38 seconds |
| Started | Sep 04 08:24:13 AM UTC 24 |
| Finished | Sep 04 08:24:29 AM UTC 24 |
| Peak memory | 235408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281335477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3281335477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.2121832544 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 111719000 ps |
| CPU time | 3.01 seconds |
| Started | Sep 04 08:24:15 AM UTC 24 |
| Finished | Sep 04 08:24:19 AM UTC 24 |
| Peak memory | 245224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121832544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2121832544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.382004964 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 24635374 ps |
| CPU time | 1.5 seconds |
| Started | Sep 04 08:24:09 AM UTC 24 |
| Finished | Sep 04 08:24:11 AM UTC 24 |
| Peak memory | 229260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382004964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_parity.382004964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.2490244324 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 16071715427 ps |
| CPU time | 11.03 seconds |
| Started | Sep 04 08:24:12 AM UTC 24 |
| Finished | Sep 04 08:24:25 AM UTC 24 |
| Peak memory | 245712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490244324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2490244324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.3442287659 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 338392096 ps |
| CPU time | 7.79 seconds |
| Started | Sep 04 08:24:21 AM UTC 24 |
| Finished | Sep 04 08:24:30 AM UTC 24 |
| Peak memory | 233952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442287659 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.3442287659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.607925543 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 124493407 ps |
| CPU time | 1.99 seconds |
| Started | Sep 04 08:24:31 AM UTC 24 |
| Finished | Sep 04 08:24:34 AM UTC 24 |
| Peak memory | 257736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607925543 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.607925543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.2225802507 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 64857712402 ps |
| CPU time | 748.76 seconds |
| Started | Sep 04 08:24:30 AM UTC 24 |
| Finished | Sep 04 08:37:08 AM UTC 24 |
| Peak memory | 294948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225802507 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.2225802507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.1836369587 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1578213609 ps |
| CPU time | 16.57 seconds |
| Started | Sep 04 08:24:10 AM UTC 24 |
| Finished | Sep 04 08:24:28 AM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836369587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1836369587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.826029823 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 3767931781 ps |
| CPU time | 13.17 seconds |
| Started | Sep 04 08:24:10 AM UTC 24 |
| Finished | Sep 04 08:24:24 AM UTC 24 |
| Peak memory | 227832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826029823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.826029823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.2986653111 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 806891168 ps |
| CPU time | 4 seconds |
| Started | Sep 04 08:24:10 AM UTC 24 |
| Finished | Sep 04 08:24:15 AM UTC 24 |
| Peak memory | 228040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986653111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2986653111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.2742219758 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 87924146 ps |
| CPU time | 1.31 seconds |
| Started | Sep 04 08:24:10 AM UTC 24 |
| Finished | Sep 04 08:24:12 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742219758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2742219758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.2120616901 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 5420341497 ps |
| CPU time | 28.16 seconds |
| Started | Sep 04 08:24:16 AM UTC 24 |
| Finished | Sep 04 08:24:45 AM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120616901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2120616901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/3.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_alert_test.461820762 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 12094928 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 08:32:31 AM UTC 24 |
| Finished | Sep 04 08:32:33 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461820762 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.461820762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/30.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_cfg_cmd.2920619904 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 417982739 ps |
| CPU time | 6.84 seconds |
| Started | Sep 04 08:32:18 AM UTC 24 |
| Finished | Sep 04 08:32:26 AM UTC 24 |
| Peak memory | 245708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920619904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2920619904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/30.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_csb_read.4034428034 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 18570034 ps |
| CPU time | 1.18 seconds |
| Started | Sep 04 08:32:08 AM UTC 24 |
| Finished | Sep 04 08:32:10 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034428034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.4034428034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/30.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_all.4018164968 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 50424723067 ps |
| CPU time | 313.13 seconds |
| Started | Sep 04 08:32:27 AM UTC 24 |
| Finished | Sep 04 08:37:45 AM UTC 24 |
| Peak memory | 262116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018164968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.4018164968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/30.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.832565479 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 128181097541 ps |
| CPU time | 476.3 seconds |
| Started | Sep 04 08:32:28 AM UTC 24 |
| Finished | Sep 04 08:40:30 AM UTC 24 |
| Peak memory | 268516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832565479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.832565479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/30.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.3497582993 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 33751558812 ps |
| CPU time | 323.99 seconds |
| Started | Sep 04 08:32:28 AM UTC 24 |
| Finished | Sep 04 08:37:56 AM UTC 24 |
| Peak memory | 262136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497582993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.3497582993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.1851835152 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 5775165414 ps |
| CPU time | 78 seconds |
| Started | Sep 04 08:32:22 AM UTC 24 |
| Finished | Sep 04 08:33:42 AM UTC 24 |
| Peak memory | 264136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851835152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.1851835152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_intercept.278503734 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 523803142 ps |
| CPU time | 9.82 seconds |
| Started | Sep 04 08:32:16 AM UTC 24 |
| Finished | Sep 04 08:32:27 AM UTC 24 |
| Peak memory | 235332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278503734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.278503734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/30.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_mailbox.2929385094 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 26188339275 ps |
| CPU time | 47.22 seconds |
| Started | Sep 04 08:32:16 AM UTC 24 |
| Finished | Sep 04 08:33:05 AM UTC 24 |
| Peak memory | 245696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929385094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2929385094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/30.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.768264365 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 46456604236 ps |
| CPU time | 24.76 seconds |
| Started | Sep 04 08:32:15 AM UTC 24 |
| Finished | Sep 04 08:32:41 AM UTC 24 |
| Peak memory | 245644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768264365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.768264365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/30.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.4195366461 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 7503447047 ps |
| CPU time | 30.24 seconds |
| Started | Sep 04 08:32:13 AM UTC 24 |
| Finished | Sep 04 08:32:44 AM UTC 24 |
| Peak memory | 245776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195366461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.4195366461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/30.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.3016361237 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 181451655 ps |
| CPU time | 5.35 seconds |
| Started | Sep 04 08:32:24 AM UTC 24 |
| Finished | Sep 04 08:32:30 AM UTC 24 |
| Peak memory | 233916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016361237 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.3016361237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/30.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.2705602908 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1898345174 ps |
| CPU time | 23.15 seconds |
| Started | Sep 04 08:32:29 AM UTC 24 |
| Finished | Sep 04 08:32:54 AM UTC 24 |
| Peak memory | 235464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705602908 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.2705602908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/30.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_all.3059638375 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 5550151159 ps |
| CPU time | 29.26 seconds |
| Started | Sep 04 08:32:11 AM UTC 24 |
| Finished | Sep 04 08:32:41 AM UTC 24 |
| Peak memory | 227928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059638375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3059638375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/30.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.3982957395 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 3363762869 ps |
| CPU time | 9.57 seconds |
| Started | Sep 04 08:32:11 AM UTC 24 |
| Finished | Sep 04 08:32:21 AM UTC 24 |
| Peak memory | 227876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982957395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3982957395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/30.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_rw.2193219326 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 326761920 ps |
| CPU time | 1.97 seconds |
| Started | Sep 04 08:32:12 AM UTC 24 |
| Finished | Sep 04 08:32:15 AM UTC 24 |
| Peak memory | 226924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193219326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2193219326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/30.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.499208280 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 383147539 ps |
| CPU time | 1.38 seconds |
| Started | Sep 04 08:32:12 AM UTC 24 |
| Finished | Sep 04 08:32:14 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499208280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.499208280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/30.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_upload.565667011 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 176064672 ps |
| CPU time | 5.64 seconds |
| Started | Sep 04 08:32:16 AM UTC 24 |
| Finished | Sep 04 08:32:23 AM UTC 24 |
| Peak memory | 245544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565667011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.565667011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/30.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_alert_test.3308422634 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 38544861 ps |
| CPU time | 1.09 seconds |
| Started | Sep 04 08:32:52 AM UTC 24 |
| Finished | Sep 04 08:32:54 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308422634 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.3308422634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/31.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_cfg_cmd.1373582707 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 751631093 ps |
| CPU time | 6 seconds |
| Started | Sep 04 08:32:43 AM UTC 24 |
| Finished | Sep 04 08:32:50 AM UTC 24 |
| Peak memory | 245512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373582707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1373582707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/31.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_csb_read.3540732129 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 22117091 ps |
| CPU time | 1.23 seconds |
| Started | Sep 04 08:32:31 AM UTC 24 |
| Finished | Sep 04 08:32:33 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540732129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3540732129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/31.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_all.72937181 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 1951875311 ps |
| CPU time | 31.05 seconds |
| Started | Sep 04 08:32:46 AM UTC 24 |
| Finished | Sep 04 08:33:20 AM UTC 24 |
| Peak memory | 261976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72937181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.72937181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/31.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.4066568730 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 95660663692 ps |
| CPU time | 491.13 seconds |
| Started | Sep 04 08:32:51 AM UTC 24 |
| Finished | Sep 04 08:41:09 AM UTC 24 |
| Peak memory | 278560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066568730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.4066568730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode.1839185760 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 346591370 ps |
| CPU time | 10.26 seconds |
| Started | Sep 04 08:32:44 AM UTC 24 |
| Finished | Sep 04 08:32:56 AM UTC 24 |
| Peak memory | 235340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839185760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1839185760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/31.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.857895194 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 35334217670 ps |
| CPU time | 281.13 seconds |
| Started | Sep 04 08:32:45 AM UTC 24 |
| Finished | Sep 04 08:37:31 AM UTC 24 |
| Peak memory | 264324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857895194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.857895194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_intercept.2199645822 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 2234942774 ps |
| CPU time | 19.99 seconds |
| Started | Sep 04 08:32:41 AM UTC 24 |
| Finished | Sep 04 08:33:02 AM UTC 24 |
| Peak memory | 235468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199645822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2199645822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/31.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_mailbox.1282622426 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 615017384 ps |
| CPU time | 9.43 seconds |
| Started | Sep 04 08:32:42 AM UTC 24 |
| Finished | Sep 04 08:32:53 AM UTC 24 |
| Peak memory | 245572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282622426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1282622426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/31.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.463342107 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 47925736099 ps |
| CPU time | 36.2 seconds |
| Started | Sep 04 08:32:40 AM UTC 24 |
| Finished | Sep 04 08:33:17 AM UTC 24 |
| Peak memory | 235436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463342107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.463342107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/31.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.67795681 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 271943642 ps |
| CPU time | 3.07 seconds |
| Started | Sep 04 08:32:38 AM UTC 24 |
| Finished | Sep 04 08:32:42 AM UTC 24 |
| Peak memory | 245576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67795681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.67795681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/31.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.1621739596 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 1010902642 ps |
| CPU time | 7.92 seconds |
| Started | Sep 04 08:32:45 AM UTC 24 |
| Finished | Sep 04 08:32:54 AM UTC 24 |
| Peak memory | 233684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621739596 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.1621739596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/31.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.2720894840 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 38392381646 ps |
| CPU time | 358.69 seconds |
| Started | Sep 04 08:32:51 AM UTC 24 |
| Finished | Sep 04 08:38:55 AM UTC 24 |
| Peak memory | 251972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720894840 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.2720894840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/31.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_all.465415249 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 1260120053 ps |
| CPU time | 25.42 seconds |
| Started | Sep 04 08:32:34 AM UTC 24 |
| Finished | Sep 04 08:33:01 AM UTC 24 |
| Peak memory | 231912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465415249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.465415249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/31.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.877714704 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 6278526967 ps |
| CPU time | 12.51 seconds |
| Started | Sep 04 08:32:32 AM UTC 24 |
| Finished | Sep 04 08:32:46 AM UTC 24 |
| Peak memory | 227888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877714704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.877714704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/31.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_rw.373063584 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 101061418 ps |
| CPU time | 1.55 seconds |
| Started | Sep 04 08:32:38 AM UTC 24 |
| Finished | Sep 04 08:32:40 AM UTC 24 |
| Peak memory | 216076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373063584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.373063584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/31.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.2870531064 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 64594619 ps |
| CPU time | 0.96 seconds |
| Started | Sep 04 08:32:34 AM UTC 24 |
| Finished | Sep 04 08:32:36 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870531064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2870531064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/31.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_upload.2943348422 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 629500464 ps |
| CPU time | 5.74 seconds |
| Started | Sep 04 08:32:42 AM UTC 24 |
| Finished | Sep 04 08:32:49 AM UTC 24 |
| Peak memory | 235268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943348422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2943348422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/31.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_alert_test.4129127154 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 20480891 ps |
| CPU time | 0.98 seconds |
| Started | Sep 04 08:33:04 AM UTC 24 |
| Finished | Sep 04 08:33:06 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129127154 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.4129127154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/32.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_cfg_cmd.843235254 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 5495508174 ps |
| CPU time | 21.29 seconds |
| Started | Sep 04 08:32:59 AM UTC 24 |
| Finished | Sep 04 08:33:21 AM UTC 24 |
| Peak memory | 245868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843235254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.843235254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/32.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_csb_read.1277227690 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 72148438 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 08:32:54 AM UTC 24 |
| Finished | Sep 04 08:32:56 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277227690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1277227690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/32.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_all.1206429956 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 3466113497 ps |
| CPU time | 35.19 seconds |
| Started | Sep 04 08:33:02 AM UTC 24 |
| Finished | Sep 04 08:33:39 AM UTC 24 |
| Peak memory | 247716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206429956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1206429956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/32.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.1460420928 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 9667428297 ps |
| CPU time | 134.31 seconds |
| Started | Sep 04 08:33:02 AM UTC 24 |
| Finished | Sep 04 08:35:19 AM UTC 24 |
| Peak memory | 280616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460420928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1460420928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.1582397642 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 57967358887 ps |
| CPU time | 562.49 seconds |
| Started | Sep 04 08:33:02 AM UTC 24 |
| Finished | Sep 04 08:42:32 AM UTC 24 |
| Peak memory | 278720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582397642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.1582397642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode.3747216814 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 2178827758 ps |
| CPU time | 16.26 seconds |
| Started | Sep 04 08:32:59 AM UTC 24 |
| Finished | Sep 04 08:33:16 AM UTC 24 |
| Peak memory | 235456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747216814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3747216814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/32.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.3310493180 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 13659790 ps |
| CPU time | 1.19 seconds |
| Started | Sep 04 08:32:59 AM UTC 24 |
| Finished | Sep 04 08:33:01 AM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310493180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.3310493180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_intercept.1739971084 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 261339722 ps |
| CPU time | 5.11 seconds |
| Started | Sep 04 08:32:57 AM UTC 24 |
| Finished | Sep 04 08:33:04 AM UTC 24 |
| Peak memory | 235340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739971084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1739971084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/32.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_mailbox.3166407129 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 104880790 ps |
| CPU time | 2.67 seconds |
| Started | Sep 04 08:32:58 AM UTC 24 |
| Finished | Sep 04 08:33:01 AM UTC 24 |
| Peak memory | 234996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166407129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3166407129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/32.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.911437259 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 105193527 ps |
| CPU time | 2.19 seconds |
| Started | Sep 04 08:32:56 AM UTC 24 |
| Finished | Sep 04 08:33:00 AM UTC 24 |
| Peak memory | 245224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911437259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.911437259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/32.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.3862939429 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 3985301362 ps |
| CPU time | 7.9 seconds |
| Started | Sep 04 08:32:55 AM UTC 24 |
| Finished | Sep 04 08:33:04 AM UTC 24 |
| Peak memory | 245900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862939429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3862939429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/32.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.3381555540 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 966348006 ps |
| CPU time | 10.87 seconds |
| Started | Sep 04 08:33:01 AM UTC 24 |
| Finished | Sep 04 08:33:13 AM UTC 24 |
| Peak memory | 233832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381555540 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.3381555540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/32.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.313123938 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 696217428 ps |
| CPU time | 1.65 seconds |
| Started | Sep 04 08:33:03 AM UTC 24 |
| Finished | Sep 04 08:33:06 AM UTC 24 |
| Peak memory | 216640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313123938 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.313123938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/32.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_all.1763251080 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 3296319375 ps |
| CPU time | 40.93 seconds |
| Started | Sep 04 08:32:54 AM UTC 24 |
| Finished | Sep 04 08:33:37 AM UTC 24 |
| Peak memory | 227636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763251080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1763251080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/32.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.2132662468 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 1202730827 ps |
| CPU time | 2.46 seconds |
| Started | Sep 04 08:32:54 AM UTC 24 |
| Finished | Sep 04 08:32:58 AM UTC 24 |
| Peak memory | 227700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132662468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2132662468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/32.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_rw.4071430162 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 62105389 ps |
| CPU time | 1.55 seconds |
| Started | Sep 04 08:32:55 AM UTC 24 |
| Finished | Sep 04 08:32:58 AM UTC 24 |
| Peak memory | 226724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071430162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.4071430162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/32.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.409871723 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 31636661 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 08:32:54 AM UTC 24 |
| Finished | Sep 04 08:32:56 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409871723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.409871723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/32.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_upload.4161434466 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 7305918836 ps |
| CPU time | 11.42 seconds |
| Started | Sep 04 08:32:58 AM UTC 24 |
| Finished | Sep 04 08:33:10 AM UTC 24 |
| Peak memory | 235460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161434466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.4161434466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/32.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_alert_test.3545959356 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 12922855 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 08:33:21 AM UTC 24 |
| Finished | Sep 04 08:33:23 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545959356 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.3545959356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/33.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_cfg_cmd.1917837461 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 184726711 ps |
| CPU time | 3.25 seconds |
| Started | Sep 04 08:33:14 AM UTC 24 |
| Finished | Sep 04 08:33:18 AM UTC 24 |
| Peak memory | 245276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917837461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1917837461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/33.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_csb_read.3991577799 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 65371788 ps |
| CPU time | 1.21 seconds |
| Started | Sep 04 08:33:05 AM UTC 24 |
| Finished | Sep 04 08:33:08 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991577799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3991577799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/33.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_all.51062937 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 66308629 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 08:33:18 AM UTC 24 |
| Finished | Sep 04 08:33:20 AM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51062937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.51062937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/33.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.2917141136 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 4222966736 ps |
| CPU time | 37.51 seconds |
| Started | Sep 04 08:33:19 AM UTC 24 |
| Finished | Sep 04 08:33:58 AM UTC 24 |
| Peak memory | 262216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917141136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.2917141136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode.2396158956 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 3275515337 ps |
| CPU time | 12.91 seconds |
| Started | Sep 04 08:33:17 AM UTC 24 |
| Finished | Sep 04 08:33:31 AM UTC 24 |
| Peak memory | 245740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396158956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2396158956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/33.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.1116669142 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 43378540190 ps |
| CPU time | 143.11 seconds |
| Started | Sep 04 08:33:17 AM UTC 24 |
| Finished | Sep 04 08:35:43 AM UTC 24 |
| Peak memory | 284616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116669142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.1116669142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_intercept.3496575352 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 309515235 ps |
| CPU time | 5.94 seconds |
| Started | Sep 04 08:33:11 AM UTC 24 |
| Finished | Sep 04 08:33:18 AM UTC 24 |
| Peak memory | 245580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496575352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3496575352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/33.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_mailbox.3684288185 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 1103588653 ps |
| CPU time | 15.2 seconds |
| Started | Sep 04 08:33:12 AM UTC 24 |
| Finished | Sep 04 08:33:28 AM UTC 24 |
| Peak memory | 261924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684288185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3684288185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/33.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.1898253087 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 6222058543 ps |
| CPU time | 14.55 seconds |
| Started | Sep 04 08:33:11 AM UTC 24 |
| Finished | Sep 04 08:33:26 AM UTC 24 |
| Peak memory | 245708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898253087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.1898253087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/33.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.1545339209 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 4879606978 ps |
| CPU time | 34.04 seconds |
| Started | Sep 04 08:33:11 AM UTC 24 |
| Finished | Sep 04 08:33:46 AM UTC 24 |
| Peak memory | 245704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545339209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1545339209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/33.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.278825059 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 10849846878 ps |
| CPU time | 14.91 seconds |
| Started | Sep 04 08:33:18 AM UTC 24 |
| Finished | Sep 04 08:33:34 AM UTC 24 |
| Peak memory | 233868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278825059 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.278825059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/33.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.1731870771 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 221890049 ps |
| CPU time | 1.6 seconds |
| Started | Sep 04 08:33:21 AM UTC 24 |
| Finished | Sep 04 08:33:23 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731870771 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.1731870771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/33.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_all.3898334535 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 4093117359 ps |
| CPU time | 20.01 seconds |
| Started | Sep 04 08:33:06 AM UTC 24 |
| Finished | Sep 04 08:33:28 AM UTC 24 |
| Peak memory | 227892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898334535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3898334535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/33.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.241297153 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 6084368031 ps |
| CPU time | 12.21 seconds |
| Started | Sep 04 08:33:05 AM UTC 24 |
| Finished | Sep 04 08:33:19 AM UTC 24 |
| Peak memory | 228012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241297153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.241297153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/33.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_rw.1691749877 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 23221854 ps |
| CPU time | 1.07 seconds |
| Started | Sep 04 08:33:09 AM UTC 24 |
| Finished | Sep 04 08:33:11 AM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691749877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1691749877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/33.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.4200407048 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 52741948 ps |
| CPU time | 1.25 seconds |
| Started | Sep 04 08:33:08 AM UTC 24 |
| Finished | Sep 04 08:33:10 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200407048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.4200407048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/33.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_upload.3648691743 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 543955507 ps |
| CPU time | 5.57 seconds |
| Started | Sep 04 08:33:13 AM UTC 24 |
| Finished | Sep 04 08:33:20 AM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648691743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3648691743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/33.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_alert_test.22708055 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 96235563 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 08:33:37 AM UTC 24 |
| Finished | Sep 04 08:33:39 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22708055 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.22708055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/34.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_cfg_cmd.2950311532 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 688850542 ps |
| CPU time | 5.61 seconds |
| Started | Sep 04 08:33:30 AM UTC 24 |
| Finished | Sep 04 08:33:36 AM UTC 24 |
| Peak memory | 235468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950311532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2950311532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/34.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_csb_read.3075280279 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 25879354 ps |
| CPU time | 1 seconds |
| Started | Sep 04 08:33:22 AM UTC 24 |
| Finished | Sep 04 08:33:24 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075280279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3075280279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/34.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_all.3247240723 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 3537512642 ps |
| CPU time | 78.61 seconds |
| Started | Sep 04 08:33:33 AM UTC 24 |
| Finished | Sep 04 08:34:53 AM UTC 24 |
| Peak memory | 276420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247240723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3247240723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/34.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.523092872 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 20336605671 ps |
| CPU time | 94.22 seconds |
| Started | Sep 04 08:33:34 AM UTC 24 |
| Finished | Sep 04 08:35:10 AM UTC 24 |
| Peak memory | 266380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523092872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.523092872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/34.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.3310273032 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 5859896629 ps |
| CPU time | 47.12 seconds |
| Started | Sep 04 08:33:35 AM UTC 24 |
| Finished | Sep 04 08:34:24 AM UTC 24 |
| Peak memory | 264264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310273032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.3310273032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode.1383842796 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 2798004372 ps |
| CPU time | 38.23 seconds |
| Started | Sep 04 08:33:31 AM UTC 24 |
| Finished | Sep 04 08:34:11 AM UTC 24 |
| Peak memory | 245904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383842796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1383842796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/34.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.2712200760 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 29619029305 ps |
| CPU time | 104.03 seconds |
| Started | Sep 04 08:33:32 AM UTC 24 |
| Finished | Sep 04 08:35:18 AM UTC 24 |
| Peak memory | 268260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712200760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.2712200760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_intercept.2386210336 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 74045772 ps |
| CPU time | 4.36 seconds |
| Started | Sep 04 08:33:27 AM UTC 24 |
| Finished | Sep 04 08:33:33 AM UTC 24 |
| Peak memory | 245772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386210336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2386210336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/34.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_mailbox.299311270 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 487295576 ps |
| CPU time | 8.9 seconds |
| Started | Sep 04 08:33:27 AM UTC 24 |
| Finished | Sep 04 08:33:37 AM UTC 24 |
| Peak memory | 245672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299311270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.299311270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/34.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.1926963692 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 607294671 ps |
| CPU time | 7.42 seconds |
| Started | Sep 04 08:33:26 AM UTC 24 |
| Finished | Sep 04 08:33:35 AM UTC 24 |
| Peak memory | 245580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926963692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.1926963692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/34.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.710280854 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 45145442216 ps |
| CPU time | 39.75 seconds |
| Started | Sep 04 08:33:24 AM UTC 24 |
| Finished | Sep 04 08:34:05 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710280854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.710280854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/34.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.3436154812 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 4290149923 ps |
| CPU time | 13.45 seconds |
| Started | Sep 04 08:33:33 AM UTC 24 |
| Finished | Sep 04 08:33:47 AM UTC 24 |
| Peak memory | 234572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436154812 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.3436154812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/34.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.4165629287 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 331023203691 ps |
| CPU time | 327.05 seconds |
| Started | Sep 04 08:33:36 AM UTC 24 |
| Finished | Sep 04 08:39:08 AM UTC 24 |
| Peak memory | 262276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165629287 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.4165629287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/34.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_all.1724079109 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 2528002964 ps |
| CPU time | 14.25 seconds |
| Started | Sep 04 08:33:22 AM UTC 24 |
| Finished | Sep 04 08:33:37 AM UTC 24 |
| Peak memory | 227976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724079109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1724079109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/34.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.974571293 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 2644039773 ps |
| CPU time | 6.46 seconds |
| Started | Sep 04 08:33:22 AM UTC 24 |
| Finished | Sep 04 08:33:29 AM UTC 24 |
| Peak memory | 227680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974571293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.974571293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/34.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_rw.3119733032 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 77823387 ps |
| CPU time | 1.73 seconds |
| Started | Sep 04 08:33:24 AM UTC 24 |
| Finished | Sep 04 08:33:27 AM UTC 24 |
| Peak memory | 228076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119733032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3119733032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/34.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.2855982011 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 1650066926 ps |
| CPU time | 1.63 seconds |
| Started | Sep 04 08:33:23 AM UTC 24 |
| Finished | Sep 04 08:33:26 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855982011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2855982011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/34.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_upload.3902561378 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 213739943 ps |
| CPU time | 2.93 seconds |
| Started | Sep 04 08:33:28 AM UTC 24 |
| Finished | Sep 04 08:33:32 AM UTC 24 |
| Peak memory | 234888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902561378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3902561378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/34.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_alert_test.1533669762 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 44939908 ps |
| CPU time | 1.01 seconds |
| Started | Sep 04 08:33:53 AM UTC 24 |
| Finished | Sep 04 08:33:55 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533669762 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.1533669762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/35.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_cfg_cmd.1451043821 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 130541047 ps |
| CPU time | 4.66 seconds |
| Started | Sep 04 08:33:46 AM UTC 24 |
| Finished | Sep 04 08:33:52 AM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451043821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1451043821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/35.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_csb_read.3744775150 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 123860505 ps |
| CPU time | 1.15 seconds |
| Started | Sep 04 08:33:37 AM UTC 24 |
| Finished | Sep 04 08:33:39 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744775150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3744775150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/35.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.1719820885 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 5509138639 ps |
| CPU time | 92.16 seconds |
| Started | Sep 04 08:33:48 AM UTC 24 |
| Finished | Sep 04 08:35:23 AM UTC 24 |
| Peak memory | 268228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719820885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1719820885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/35.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.372370878 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 48253145909 ps |
| CPU time | 309.22 seconds |
| Started | Sep 04 08:33:50 AM UTC 24 |
| Finished | Sep 04 08:39:03 AM UTC 24 |
| Peak memory | 262184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372370878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.372370878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.1688800756 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 2352293662 ps |
| CPU time | 61.94 seconds |
| Started | Sep 04 08:33:50 AM UTC 24 |
| Finished | Sep 04 08:34:53 AM UTC 24 |
| Peak memory | 268488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688800756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.1688800756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode.332660721 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 345619629 ps |
| CPU time | 2.9 seconds |
| Started | Sep 04 08:33:46 AM UTC 24 |
| Finished | Sep 04 08:33:50 AM UTC 24 |
| Peak memory | 245544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332660721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.332660721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/35.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.1692060780 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 645540712 ps |
| CPU time | 15.89 seconds |
| Started | Sep 04 08:33:47 AM UTC 24 |
| Finished | Sep 04 08:34:04 AM UTC 24 |
| Peak memory | 262088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692060780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.1692060780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_intercept.3444400113 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 862277397 ps |
| CPU time | 10.71 seconds |
| Started | Sep 04 08:33:43 AM UTC 24 |
| Finished | Sep 04 08:33:55 AM UTC 24 |
| Peak memory | 245544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444400113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3444400113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/35.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_mailbox.1906579487 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 1886332242 ps |
| CPU time | 12.11 seconds |
| Started | Sep 04 08:33:43 AM UTC 24 |
| Finished | Sep 04 08:33:56 AM UTC 24 |
| Peak memory | 245800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906579487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1906579487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/35.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.3614993663 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 6089262462 ps |
| CPU time | 10.75 seconds |
| Started | Sep 04 08:33:42 AM UTC 24 |
| Finished | Sep 04 08:33:54 AM UTC 24 |
| Peak memory | 245676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614993663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.3614993663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/35.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.3169540110 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 2137953846 ps |
| CPU time | 7.25 seconds |
| Started | Sep 04 08:33:41 AM UTC 24 |
| Finished | Sep 04 08:33:49 AM UTC 24 |
| Peak memory | 245576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169540110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3169540110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/35.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.2943920147 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 95482043 ps |
| CPU time | 5.67 seconds |
| Started | Sep 04 08:33:47 AM UTC 24 |
| Finished | Sep 04 08:33:54 AM UTC 24 |
| Peak memory | 234052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943920147 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.2943920147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/35.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.743792909 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 21489380993 ps |
| CPU time | 81.29 seconds |
| Started | Sep 04 08:33:51 AM UTC 24 |
| Finished | Sep 04 08:35:14 AM UTC 24 |
| Peak memory | 266268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743792909 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.743792909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/35.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_all.1257192523 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 4134320025 ps |
| CPU time | 22.06 seconds |
| Started | Sep 04 08:33:38 AM UTC 24 |
| Finished | Sep 04 08:34:02 AM UTC 24 |
| Peak memory | 232044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257192523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1257192523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/35.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.3483888390 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 1578876275 ps |
| CPU time | 5.88 seconds |
| Started | Sep 04 08:33:38 AM UTC 24 |
| Finished | Sep 04 08:33:45 AM UTC 24 |
| Peak memory | 227692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483888390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3483888390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/35.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_rw.3968136202 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 102376312 ps |
| CPU time | 1.47 seconds |
| Started | Sep 04 08:33:41 AM UTC 24 |
| Finished | Sep 04 08:33:43 AM UTC 24 |
| Peak memory | 215984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968136202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3968136202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/35.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.3435218029 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 73299339 ps |
| CPU time | 1.26 seconds |
| Started | Sep 04 08:33:39 AM UTC 24 |
| Finished | Sep 04 08:33:42 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435218029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3435218029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/35.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_upload.87097147 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 459220783 ps |
| CPU time | 4.17 seconds |
| Started | Sep 04 08:33:44 AM UTC 24 |
| Finished | Sep 04 08:33:49 AM UTC 24 |
| Peak memory | 245600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87097147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_devi ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.87097147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/35.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_alert_test.2076981760 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 22092371 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 08:34:06 AM UTC 24 |
| Finished | Sep 04 08:34:08 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076981760 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.2076981760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/36.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_cfg_cmd.1384566549 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 317982686 ps |
| CPU time | 6.02 seconds |
| Started | Sep 04 08:33:59 AM UTC 24 |
| Finished | Sep 04 08:34:06 AM UTC 24 |
| Peak memory | 235276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384566549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1384566549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/36.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_csb_read.1537556274 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 17209452 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 08:33:54 AM UTC 24 |
| Finished | Sep 04 08:33:56 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537556274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1537556274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/36.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_all.1709498873 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 3076768040 ps |
| CPU time | 26.87 seconds |
| Started | Sep 04 08:34:02 AM UTC 24 |
| Finished | Sep 04 08:34:30 AM UTC 24 |
| Peak memory | 247748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709498873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1709498873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/36.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.609443893 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 41768750930 ps |
| CPU time | 358.81 seconds |
| Started | Sep 04 08:34:03 AM UTC 24 |
| Finished | Sep 04 08:40:07 AM UTC 24 |
| Peak memory | 266252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609443893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.609443893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/36.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.2241533302 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 2530980702 ps |
| CPU time | 50.22 seconds |
| Started | Sep 04 08:34:03 AM UTC 24 |
| Finished | Sep 04 08:34:55 AM UTC 24 |
| Peak memory | 266184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241533302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.2241533302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode.301671637 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 1110850954 ps |
| CPU time | 17.79 seconds |
| Started | Sep 04 08:34:00 AM UTC 24 |
| Finished | Sep 04 08:34:19 AM UTC 24 |
| Peak memory | 262028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301671637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.301671637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/36.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.3121321027 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 4116056511 ps |
| CPU time | 56.8 seconds |
| Started | Sep 04 08:34:00 AM UTC 24 |
| Finished | Sep 04 08:34:58 AM UTC 24 |
| Peak memory | 262080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121321027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.3121321027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_intercept.2439784259 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 5598731393 ps |
| CPU time | 9.21 seconds |
| Started | Sep 04 08:33:57 AM UTC 24 |
| Finished | Sep 04 08:34:08 AM UTC 24 |
| Peak memory | 235664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439784259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2439784259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/36.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_mailbox.3986939592 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 14479379741 ps |
| CPU time | 54.23 seconds |
| Started | Sep 04 08:33:57 AM UTC 24 |
| Finished | Sep 04 08:34:53 AM UTC 24 |
| Peak memory | 245640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986939592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3986939592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/36.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.4147606150 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 285131844 ps |
| CPU time | 3.34 seconds |
| Started | Sep 04 08:33:55 AM UTC 24 |
| Finished | Sep 04 08:34:00 AM UTC 24 |
| Peak memory | 245548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147606150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.4147606150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/36.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.4006266669 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 354272689 ps |
| CPU time | 5.58 seconds |
| Started | Sep 04 08:33:55 AM UTC 24 |
| Finished | Sep 04 08:34:02 AM UTC 24 |
| Peak memory | 235336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006266669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.4006266669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/36.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.1880216401 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 190912740 ps |
| CPU time | 5.31 seconds |
| Started | Sep 04 08:34:01 AM UTC 24 |
| Finished | Sep 04 08:34:07 AM UTC 24 |
| Peak memory | 231668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880216401 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.1880216401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/36.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.1793741441 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 4736132113 ps |
| CPU time | 75.11 seconds |
| Started | Sep 04 08:34:05 AM UTC 24 |
| Finished | Sep 04 08:35:22 AM UTC 24 |
| Peak memory | 262172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793741441 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.1793741441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/36.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_all.1014328459 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 14634576893 ps |
| CPU time | 40.88 seconds |
| Started | Sep 04 08:33:54 AM UTC 24 |
| Finished | Sep 04 08:34:36 AM UTC 24 |
| Peak memory | 227920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014328459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1014328459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/36.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.520534357 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 1319950397 ps |
| CPU time | 10.95 seconds |
| Started | Sep 04 08:33:54 AM UTC 24 |
| Finished | Sep 04 08:34:06 AM UTC 24 |
| Peak memory | 227972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520534357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.520534357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/36.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_rw.338855768 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 86110996 ps |
| CPU time | 1.7 seconds |
| Started | Sep 04 08:33:55 AM UTC 24 |
| Finished | Sep 04 08:33:58 AM UTC 24 |
| Peak memory | 226932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338855768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.338855768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/36.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.4129124413 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 345653011 ps |
| CPU time | 1.3 seconds |
| Started | Sep 04 08:33:55 AM UTC 24 |
| Finished | Sep 04 08:33:57 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129124413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.4129124413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/36.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_upload.1253497643 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 345893090 ps |
| CPU time | 8.48 seconds |
| Started | Sep 04 08:33:58 AM UTC 24 |
| Finished | Sep 04 08:34:08 AM UTC 24 |
| Peak memory | 245600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253497643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1253497643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/36.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_alert_test.2538408331 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 12156690 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 08:34:25 AM UTC 24 |
| Finished | Sep 04 08:34:27 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538408331 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.2538408331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/37.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_cfg_cmd.3146005940 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 8506643880 ps |
| CPU time | 20.71 seconds |
| Started | Sep 04 08:34:15 AM UTC 24 |
| Finished | Sep 04 08:34:37 AM UTC 24 |
| Peak memory | 245668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146005940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3146005940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/37.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_csb_read.3909109105 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 47410588 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 08:34:06 AM UTC 24 |
| Finished | Sep 04 08:34:08 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909109105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3909109105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/37.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.102960511 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 431200355 ps |
| CPU time | 5.53 seconds |
| Started | Sep 04 08:34:20 AM UTC 24 |
| Finished | Sep 04 08:34:26 AM UTC 24 |
| Peak memory | 245576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102960511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.102960511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/37.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.295750517 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 5947775182 ps |
| CPU time | 102.87 seconds |
| Started | Sep 04 08:34:23 AM UTC 24 |
| Finished | Sep 04 08:36:08 AM UTC 24 |
| Peak memory | 266276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295750517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.295750517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/37.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1626823602 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 25171122473 ps |
| CPU time | 182.01 seconds |
| Started | Sep 04 08:34:24 AM UTC 24 |
| Finished | Sep 04 08:37:29 AM UTC 24 |
| Peak memory | 268264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626823602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.1626823602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode.414086197 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 7151909533 ps |
| CPU time | 15.95 seconds |
| Started | Sep 04 08:34:16 AM UTC 24 |
| Finished | Sep 04 08:34:33 AM UTC 24 |
| Peak memory | 235468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414086197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.414086197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/37.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.295928247 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 16418308444 ps |
| CPU time | 119.49 seconds |
| Started | Sep 04 08:34:16 AM UTC 24 |
| Finished | Sep 04 08:36:18 AM UTC 24 |
| Peak memory | 266176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295928247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.295928247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_intercept.2203331561 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 1021808687 ps |
| CPU time | 11.47 seconds |
| Started | Sep 04 08:34:10 AM UTC 24 |
| Finished | Sep 04 08:34:23 AM UTC 24 |
| Peak memory | 235472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203331561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2203331561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/37.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_mailbox.1433267585 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 3445118054 ps |
| CPU time | 27.77 seconds |
| Started | Sep 04 08:34:12 AM UTC 24 |
| Finished | Sep 04 08:34:41 AM UTC 24 |
| Peak memory | 245668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433267585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1433267585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/37.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.1433167983 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 362580963 ps |
| CPU time | 4.22 seconds |
| Started | Sep 04 08:34:10 AM UTC 24 |
| Finished | Sep 04 08:34:15 AM UTC 24 |
| Peak memory | 245548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433167983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.1433167983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/37.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.1568771473 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 2542098023 ps |
| CPU time | 13.07 seconds |
| Started | Sep 04 08:34:09 AM UTC 24 |
| Finished | Sep 04 08:34:23 AM UTC 24 |
| Peak memory | 245772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568771473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1568771473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/37.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.4252615718 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 269428615 ps |
| CPU time | 3.98 seconds |
| Started | Sep 04 08:34:18 AM UTC 24 |
| Finished | Sep 04 08:34:24 AM UTC 24 |
| Peak memory | 231668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252615718 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.4252615718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/37.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.3795549875 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 204287445224 ps |
| CPU time | 823.05 seconds |
| Started | Sep 04 08:34:24 AM UTC 24 |
| Finished | Sep 04 08:48:17 AM UTC 24 |
| Peak memory | 282860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795549875 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.3795549875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/37.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_all.19649374 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 3938175188 ps |
| CPU time | 22.62 seconds |
| Started | Sep 04 08:34:07 AM UTC 24 |
| Finished | Sep 04 08:34:31 AM UTC 24 |
| Peak memory | 227988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19649374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.19649374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/37.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.2568959198 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 2333066079 ps |
| CPU time | 12.62 seconds |
| Started | Sep 04 08:34:07 AM UTC 24 |
| Finished | Sep 04 08:34:21 AM UTC 24 |
| Peak memory | 228052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568959198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2568959198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/37.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_rw.362240556 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 175835760 ps |
| CPU time | 4.03 seconds |
| Started | Sep 04 08:34:09 AM UTC 24 |
| Finished | Sep 04 08:34:14 AM UTC 24 |
| Peak memory | 228048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362240556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.362240556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/37.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.1739062457 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 92279716 ps |
| CPU time | 1.17 seconds |
| Started | Sep 04 08:34:09 AM UTC 24 |
| Finished | Sep 04 08:34:11 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739062457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1739062457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/37.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_upload.1538278783 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 1389699461 ps |
| CPU time | 10.2 seconds |
| Started | Sep 04 08:34:12 AM UTC 24 |
| Finished | Sep 04 08:34:24 AM UTC 24 |
| Peak memory | 245512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538278783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1538278783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/37.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_alert_test.1029439955 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 32229874 ps |
| CPU time | 1.08 seconds |
| Started | Sep 04 08:34:40 AM UTC 24 |
| Finished | Sep 04 08:34:42 AM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029439955 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.1029439955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/38.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_cfg_cmd.4293841515 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 109556850 ps |
| CPU time | 3.07 seconds |
| Started | Sep 04 08:34:36 AM UTC 24 |
| Finished | Sep 04 08:34:40 AM UTC 24 |
| Peak memory | 245280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293841515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.4293841515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/38.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_csb_read.588444433 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 15288672 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 08:34:25 AM UTC 24 |
| Finished | Sep 04 08:34:28 AM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588444433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.588444433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/38.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_all.1495464482 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 6260014393 ps |
| CPU time | 33.68 seconds |
| Started | Sep 04 08:34:38 AM UTC 24 |
| Finished | Sep 04 08:35:13 AM UTC 24 |
| Peak memory | 252036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495464482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1495464482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/38.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.1444674533 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 9405125602 ps |
| CPU time | 104.49 seconds |
| Started | Sep 04 08:34:39 AM UTC 24 |
| Finished | Sep 04 08:36:26 AM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444674533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1444674533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/38.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.358512758 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 49157129054 ps |
| CPU time | 422.56 seconds |
| Started | Sep 04 08:34:39 AM UTC 24 |
| Finished | Sep 04 08:41:47 AM UTC 24 |
| Peak memory | 280728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358512758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.358512758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode.675266944 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 2694426071 ps |
| CPU time | 6.3 seconds |
| Started | Sep 04 08:34:36 AM UTC 24 |
| Finished | Sep 04 08:34:43 AM UTC 24 |
| Peak memory | 235596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675266944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.675266944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/38.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.2691337854 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 147454482250 ps |
| CPU time | 286.21 seconds |
| Started | Sep 04 08:34:37 AM UTC 24 |
| Finished | Sep 04 08:39:27 AM UTC 24 |
| Peak memory | 268232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691337854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.2691337854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_intercept.3500601047 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 208826584 ps |
| CPU time | 5.08 seconds |
| Started | Sep 04 08:34:32 AM UTC 24 |
| Finished | Sep 04 08:34:39 AM UTC 24 |
| Peak memory | 235404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500601047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3500601047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/38.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_mailbox.3613084673 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 187418718 ps |
| CPU time | 11.01 seconds |
| Started | Sep 04 08:34:33 AM UTC 24 |
| Finished | Sep 04 08:34:45 AM UTC 24 |
| Peak memory | 245576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613084673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3613084673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/38.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.4180215792 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 2686860645 ps |
| CPU time | 9.03 seconds |
| Started | Sep 04 08:34:32 AM UTC 24 |
| Finished | Sep 04 08:34:43 AM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180215792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.4180215792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/38.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.2230925199 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 130816409 ps |
| CPU time | 4.7 seconds |
| Started | Sep 04 08:34:31 AM UTC 24 |
| Finished | Sep 04 08:34:37 AM UTC 24 |
| Peak memory | 235332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230925199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2230925199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/38.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.4232460725 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 1470148149 ps |
| CPU time | 11.76 seconds |
| Started | Sep 04 08:34:38 AM UTC 24 |
| Finished | Sep 04 08:34:51 AM UTC 24 |
| Peak memory | 231608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232460725 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.4232460725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/38.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.3749240275 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 150655483095 ps |
| CPU time | 329.56 seconds |
| Started | Sep 04 08:34:39 AM UTC 24 |
| Finished | Sep 04 08:40:13 AM UTC 24 |
| Peak memory | 280608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749240275 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.3749240275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/38.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_all.1536920705 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 31121755395 ps |
| CPU time | 51.08 seconds |
| Started | Sep 04 08:34:27 AM UTC 24 |
| Finished | Sep 04 08:35:20 AM UTC 24 |
| Peak memory | 227888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536920705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1536920705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/38.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.2721206514 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 5332867617 ps |
| CPU time | 15.45 seconds |
| Started | Sep 04 08:34:25 AM UTC 24 |
| Finished | Sep 04 08:34:42 AM UTC 24 |
| Peak memory | 227828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721206514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2721206514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/38.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_rw.2874847365 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 61155065 ps |
| CPU time | 1.72 seconds |
| Started | Sep 04 08:34:28 AM UTC 24 |
| Finished | Sep 04 08:34:31 AM UTC 24 |
| Peak memory | 226392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874847365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2874847365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/38.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.1301568164 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 51089592 ps |
| CPU time | 1.45 seconds |
| Started | Sep 04 08:34:28 AM UTC 24 |
| Finished | Sep 04 08:34:31 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301568164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1301568164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/38.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_upload.1557745565 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 13990812894 ps |
| CPU time | 19.91 seconds |
| Started | Sep 04 08:34:35 AM UTC 24 |
| Finished | Sep 04 08:34:56 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557745565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1557745565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/38.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_alert_test.577522942 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 86614133 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 08:34:58 AM UTC 24 |
| Finished | Sep 04 08:35:00 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577522942 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.577522942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/39.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_cfg_cmd.445485013 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 1256581449 ps |
| CPU time | 4.46 seconds |
| Started | Sep 04 08:34:51 AM UTC 24 |
| Finished | Sep 04 08:34:57 AM UTC 24 |
| Peak memory | 245548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445485013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.445485013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/39.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_csb_read.3146488093 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 20774771 ps |
| CPU time | 1.25 seconds |
| Started | Sep 04 08:34:42 AM UTC 24 |
| Finished | Sep 04 08:34:45 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146488093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3146488093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/39.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.865896685 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 38514432947 ps |
| CPU time | 316.47 seconds |
| Started | Sep 04 08:34:54 AM UTC 24 |
| Finished | Sep 04 08:40:15 AM UTC 24 |
| Peak memory | 266248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865896685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.865896685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/39.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.1975523395 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 21404190148 ps |
| CPU time | 85.84 seconds |
| Started | Sep 04 08:34:54 AM UTC 24 |
| Finished | Sep 04 08:36:22 AM UTC 24 |
| Peak memory | 262368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975523395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1975523395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/39.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.1787937941 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 36486153062 ps |
| CPU time | 387.38 seconds |
| Started | Sep 04 08:34:56 AM UTC 24 |
| Finished | Sep 04 08:41:29 AM UTC 24 |
| Peak memory | 268356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787937941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.1787937941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.2810919255 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 2299422570 ps |
| CPU time | 7.18 seconds |
| Started | Sep 04 08:34:52 AM UTC 24 |
| Finished | Sep 04 08:35:01 AM UTC 24 |
| Peak memory | 235404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810919255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.2810919255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_intercept.3667970783 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 754997198 ps |
| CPU time | 3.77 seconds |
| Started | Sep 04 08:34:47 AM UTC 24 |
| Finished | Sep 04 08:34:52 AM UTC 24 |
| Peak memory | 235276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667970783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3667970783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/39.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_mailbox.3080002439 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 2656869423 ps |
| CPU time | 24.79 seconds |
| Started | Sep 04 08:34:47 AM UTC 24 |
| Finished | Sep 04 08:35:13 AM UTC 24 |
| Peak memory | 249732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080002439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3080002439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/39.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.3196465889 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 417311020 ps |
| CPU time | 11.93 seconds |
| Started | Sep 04 08:34:46 AM UTC 24 |
| Finished | Sep 04 08:34:59 AM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196465889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.3196465889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/39.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.1745574549 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 930734908 ps |
| CPU time | 11.17 seconds |
| Started | Sep 04 08:34:46 AM UTC 24 |
| Finished | Sep 04 08:34:58 AM UTC 24 |
| Peak memory | 235472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745574549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1745574549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/39.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.2708087368 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 100262471 ps |
| CPU time | 4.03 seconds |
| Started | Sep 04 08:34:54 AM UTC 24 |
| Finished | Sep 04 08:34:59 AM UTC 24 |
| Peak memory | 234536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708087368 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.2708087368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/39.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.2956436086 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 10670316598 ps |
| CPU time | 100.06 seconds |
| Started | Sep 04 08:34:57 AM UTC 24 |
| Finished | Sep 04 08:36:39 AM UTC 24 |
| Peak memory | 268488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956436086 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.2956436086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/39.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.1159719120 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 30861893 ps |
| CPU time | 1.08 seconds |
| Started | Sep 04 08:34:44 AM UTC 24 |
| Finished | Sep 04 08:34:46 AM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159719120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1159719120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/39.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.2161464951 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 862300609 ps |
| CPU time | 6.81 seconds |
| Started | Sep 04 08:34:43 AM UTC 24 |
| Finished | Sep 04 08:34:50 AM UTC 24 |
| Peak memory | 227696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161464951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2161464951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/39.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_rw.3199289777 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 16233037 ps |
| CPU time | 1.5 seconds |
| Started | Sep 04 08:34:45 AM UTC 24 |
| Finished | Sep 04 08:34:47 AM UTC 24 |
| Peak memory | 215624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199289777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3199289777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/39.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.2365667967 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 145921569 ps |
| CPU time | 1.37 seconds |
| Started | Sep 04 08:34:44 AM UTC 24 |
| Finished | Sep 04 08:34:46 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365667967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2365667967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/39.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_upload.3291137895 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 11187561370 ps |
| CPU time | 17.84 seconds |
| Started | Sep 04 08:34:48 AM UTC 24 |
| Finished | Sep 04 08:35:07 AM UTC 24 |
| Peak memory | 245704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291137895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3291137895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/39.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.1545428845 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 50803176 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 08:24:51 AM UTC 24 |
| Finished | Sep 04 08:24:53 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545428845 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1545428845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.1688321849 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 924159527 ps |
| CPU time | 6.01 seconds |
| Started | Sep 04 08:24:42 AM UTC 24 |
| Finished | Sep 04 08:24:49 AM UTC 24 |
| Peak memory | 245736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688321849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1688321849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.3807934162 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 227423107 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 08:24:32 AM UTC 24 |
| Finished | Sep 04 08:24:34 AM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807934162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3807934162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.4091829590 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 14685308332 ps |
| CPU time | 67.87 seconds |
| Started | Sep 04 08:24:44 AM UTC 24 |
| Finished | Sep 04 08:25:54 AM UTC 24 |
| Peak memory | 251876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091829590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.4091829590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.1896785355 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1076541462 ps |
| CPU time | 11.37 seconds |
| Started | Sep 04 08:24:39 AM UTC 24 |
| Finished | Sep 04 08:24:51 AM UTC 24 |
| Peak memory | 245612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896785355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1896785355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.3630772899 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 24334393461 ps |
| CPU time | 103.58 seconds |
| Started | Sep 04 08:24:39 AM UTC 24 |
| Finished | Sep 04 08:26:24 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630772899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3630772899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.2406892079 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 36564093 ps |
| CPU time | 1.23 seconds |
| Started | Sep 04 08:24:32 AM UTC 24 |
| Finished | Sep 04 08:24:34 AM UTC 24 |
| Peak memory | 229140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406892079 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_parity.2406892079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.1682548322 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 6598845743 ps |
| CPU time | 9.87 seconds |
| Started | Sep 04 08:24:37 AM UTC 24 |
| Finished | Sep 04 08:24:49 AM UTC 24 |
| Peak memory | 235412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682548322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.1682548322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.1769818207 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 8857924616 ps |
| CPU time | 12.14 seconds |
| Started | Sep 04 08:24:35 AM UTC 24 |
| Finished | Sep 04 08:24:49 AM UTC 24 |
| Peak memory | 245712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769818207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1769818207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.4217718471 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 245372844 ps |
| CPU time | 4.83 seconds |
| Started | Sep 04 08:24:46 AM UTC 24 |
| Finished | Sep 04 08:24:52 AM UTC 24 |
| Peak memory | 231612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217718471 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.4217718471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.3528224882 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 176073711 ps |
| CPU time | 1.86 seconds |
| Started | Sep 04 08:24:50 AM UTC 24 |
| Finished | Sep 04 08:24:52 AM UTC 24 |
| Peak memory | 257740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528224882 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3528224882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.1653467103 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 59392205225 ps |
| CPU time | 113.05 seconds |
| Started | Sep 04 08:24:50 AM UTC 24 |
| Finished | Sep 04 08:26:45 AM UTC 24 |
| Peak memory | 268300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653467103 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.1653467103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.2554322161 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2173974064 ps |
| CPU time | 9.37 seconds |
| Started | Sep 04 08:24:35 AM UTC 24 |
| Finished | Sep 04 08:24:46 AM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554322161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2554322161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.1787603284 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 1936540597 ps |
| CPU time | 7.85 seconds |
| Started | Sep 04 08:24:32 AM UTC 24 |
| Finished | Sep 04 08:24:41 AM UTC 24 |
| Peak memory | 227888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787603284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1787603284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.4118323164 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 33228676 ps |
| CPU time | 1 seconds |
| Started | Sep 04 08:24:35 AM UTC 24 |
| Finished | Sep 04 08:24:38 AM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118323164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.4118323164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.3461777384 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 141861229 ps |
| CPU time | 1.15 seconds |
| Started | Sep 04 08:24:35 AM UTC 24 |
| Finished | Sep 04 08:24:38 AM UTC 24 |
| Peak memory | 215900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461777384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3461777384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.834991158 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 876761566 ps |
| CPU time | 9.16 seconds |
| Started | Sep 04 08:24:40 AM UTC 24 |
| Finished | Sep 04 08:24:50 AM UTC 24 |
| Peak memory | 245792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834991158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.834991158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/4.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.4055965403 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 46034780 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 08:35:15 AM UTC 24 |
| Finished | Sep 04 08:35:17 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055965403 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.4055965403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/40.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_cfg_cmd.3940387455 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 56722403 ps |
| CPU time | 3.27 seconds |
| Started | Sep 04 08:35:07 AM UTC 24 |
| Finished | Sep 04 08:35:11 AM UTC 24 |
| Peak memory | 235468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940387455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3940387455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/40.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_csb_read.3085857602 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 18155988 ps |
| CPU time | 1.18 seconds |
| Started | Sep 04 08:34:58 AM UTC 24 |
| Finished | Sep 04 08:35:00 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085857602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3085857602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/40.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.2460928631 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 41004349969 ps |
| CPU time | 79.9 seconds |
| Started | Sep 04 08:35:11 AM UTC 24 |
| Finished | Sep 04 08:36:33 AM UTC 24 |
| Peak memory | 278500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460928631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2460928631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/40.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.189262915 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 119365370460 ps |
| CPU time | 140.72 seconds |
| Started | Sep 04 08:35:12 AM UTC 24 |
| Finished | Sep 04 08:37:35 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189262915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.189262915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.3749198983 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 2092440613 ps |
| CPU time | 46.49 seconds |
| Started | Sep 04 08:35:14 AM UTC 24 |
| Finished | Sep 04 08:36:02 AM UTC 24 |
| Peak memory | 262048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749198983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.3749198983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.1201288048 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 9613521394 ps |
| CPU time | 107.69 seconds |
| Started | Sep 04 08:35:07 AM UTC 24 |
| Finished | Sep 04 08:36:57 AM UTC 24 |
| Peak memory | 264144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201288048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1201288048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/40.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.2854997956 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 40303992804 ps |
| CPU time | 98.43 seconds |
| Started | Sep 04 08:35:08 AM UTC 24 |
| Finished | Sep 04 08:36:48 AM UTC 24 |
| Peak memory | 264132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854997956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.2854997956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_intercept.930373092 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 200119300 ps |
| CPU time | 3.48 seconds |
| Started | Sep 04 08:35:01 AM UTC 24 |
| Finished | Sep 04 08:35:06 AM UTC 24 |
| Peak memory | 235336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930373092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.930373092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/40.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.3759217107 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 2748227641 ps |
| CPU time | 29.36 seconds |
| Started | Sep 04 08:35:03 AM UTC 24 |
| Finished | Sep 04 08:35:34 AM UTC 24 |
| Peak memory | 245288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759217107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3759217107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/40.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.3547776771 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 58497993 ps |
| CPU time | 3.4 seconds |
| Started | Sep 04 08:35:01 AM UTC 24 |
| Finished | Sep 04 08:35:06 AM UTC 24 |
| Peak memory | 242300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547776771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.3547776771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/40.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.2559358974 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 439330005 ps |
| CPU time | 11.57 seconds |
| Started | Sep 04 08:35:01 AM UTC 24 |
| Finished | Sep 04 08:35:14 AM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559358974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2559358974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/40.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.535597998 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 209506300 ps |
| CPU time | 6.54 seconds |
| Started | Sep 04 08:35:09 AM UTC 24 |
| Finished | Sep 04 08:35:17 AM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535597998 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.535597998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/40.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.329432857 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 2261648058 ps |
| CPU time | 52.05 seconds |
| Started | Sep 04 08:35:14 AM UTC 24 |
| Finished | Sep 04 08:36:08 AM UTC 24 |
| Peak memory | 245756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329432857 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.329432857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/40.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.2905046633 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 8960081828 ps |
| CPU time | 26.53 seconds |
| Started | Sep 04 08:34:59 AM UTC 24 |
| Finished | Sep 04 08:35:27 AM UTC 24 |
| Peak memory | 227980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905046633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2905046633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/40.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.3731666534 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 1415526186 ps |
| CPU time | 7.62 seconds |
| Started | Sep 04 08:34:59 AM UTC 24 |
| Finished | Sep 04 08:35:08 AM UTC 24 |
| Peak memory | 227688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731666534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3731666534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/40.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_rw.679278889 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 64574031 ps |
| CPU time | 2.75 seconds |
| Started | Sep 04 08:35:00 AM UTC 24 |
| Finished | Sep 04 08:35:04 AM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679278889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.679278889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/40.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.4023662433 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 62875200 ps |
| CPU time | 1.36 seconds |
| Started | Sep 04 08:35:00 AM UTC 24 |
| Finished | Sep 04 08:35:02 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023662433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.4023662433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/40.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.4240680008 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 816963930 ps |
| CPU time | 13.65 seconds |
| Started | Sep 04 08:35:04 AM UTC 24 |
| Finished | Sep 04 08:35:19 AM UTC 24 |
| Peak memory | 245600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240680008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.4240680008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/40.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.310267254 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 15533888 ps |
| CPU time | 1.07 seconds |
| Started | Sep 04 08:35:27 AM UTC 24 |
| Finished | Sep 04 08:35:30 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310267254 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.310267254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/41.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.3243787211 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 174823346 ps |
| CPU time | 4.67 seconds |
| Started | Sep 04 08:35:22 AM UTC 24 |
| Finished | Sep 04 08:35:28 AM UTC 24 |
| Peak memory | 235276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243787211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3243787211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/41.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.820168789 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 32620167 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 08:35:15 AM UTC 24 |
| Finished | Sep 04 08:35:17 AM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820168789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.820168789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/41.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.2823343715 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 15775891806 ps |
| CPU time | 41.79 seconds |
| Started | Sep 04 08:35:26 AM UTC 24 |
| Finished | Sep 04 08:36:10 AM UTC 24 |
| Peak memory | 245896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823343715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2823343715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/41.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.3301412323 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 4204517829 ps |
| CPU time | 34.44 seconds |
| Started | Sep 04 08:35:26 AM UTC 24 |
| Finished | Sep 04 08:36:02 AM UTC 24 |
| Peak memory | 235688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301412323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3301412323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.2446323657 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 59070630890 ps |
| CPU time | 248.58 seconds |
| Started | Sep 04 08:35:26 AM UTC 24 |
| Finished | Sep 04 08:39:38 AM UTC 24 |
| Peak memory | 262340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446323657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.2446323657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.500199065 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 384307797 ps |
| CPU time | 8.38 seconds |
| Started | Sep 04 08:35:22 AM UTC 24 |
| Finished | Sep 04 08:35:31 AM UTC 24 |
| Peak memory | 235344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500199065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.500199065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/41.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2857177086 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 329611852 ps |
| CPU time | 1.46 seconds |
| Started | Sep 04 08:35:23 AM UTC 24 |
| Finished | Sep 04 08:35:25 AM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857177086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.2857177086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.990367549 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 189641101 ps |
| CPU time | 4.91 seconds |
| Started | Sep 04 08:35:21 AM UTC 24 |
| Finished | Sep 04 08:35:27 AM UTC 24 |
| Peak memory | 245580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990367549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.990367549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/41.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.852961754 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 29037852020 ps |
| CPU time | 75.73 seconds |
| Started | Sep 04 08:35:21 AM UTC 24 |
| Finished | Sep 04 08:36:38 AM UTC 24 |
| Peak memory | 252008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852961754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.852961754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/41.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.576636077 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 820029185 ps |
| CPU time | 7.09 seconds |
| Started | Sep 04 08:35:20 AM UTC 24 |
| Finished | Sep 04 08:35:28 AM UTC 24 |
| Peak memory | 247624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576636077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.576636077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/41.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.2964548389 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 1270715820 ps |
| CPU time | 6.14 seconds |
| Started | Sep 04 08:35:20 AM UTC 24 |
| Finished | Sep 04 08:35:27 AM UTC 24 |
| Peak memory | 235340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964548389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2964548389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/41.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.459437575 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 935851146 ps |
| CPU time | 7.71 seconds |
| Started | Sep 04 08:35:23 AM UTC 24 |
| Finished | Sep 04 08:35:32 AM UTC 24 |
| Peak memory | 231608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459437575 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.459437575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/41.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.360259254 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 83602783615 ps |
| CPU time | 813.32 seconds |
| Started | Sep 04 08:35:27 AM UTC 24 |
| Finished | Sep 04 08:49:10 AM UTC 24 |
| Peak memory | 301076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360259254 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.360259254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/41.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.4261165277 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 3570824646 ps |
| CPU time | 6.24 seconds |
| Started | Sep 04 08:35:18 AM UTC 24 |
| Finished | Sep 04 08:35:26 AM UTC 24 |
| Peak memory | 232048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261165277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.4261165277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/41.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.2516629284 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 15683805588 ps |
| CPU time | 34.54 seconds |
| Started | Sep 04 08:35:17 AM UTC 24 |
| Finished | Sep 04 08:35:53 AM UTC 24 |
| Peak memory | 227912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516629284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2516629284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/41.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.2329221936 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 174089950 ps |
| CPU time | 1.92 seconds |
| Started | Sep 04 08:35:18 AM UTC 24 |
| Finished | Sep 04 08:35:21 AM UTC 24 |
| Peak memory | 216704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329221936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2329221936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/41.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.3668434535 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 82279158 ps |
| CPU time | 1.46 seconds |
| Started | Sep 04 08:35:18 AM UTC 24 |
| Finished | Sep 04 08:35:21 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668434535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3668434535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/41.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.4065093445 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 1409440452 ps |
| CPU time | 15.17 seconds |
| Started | Sep 04 08:35:22 AM UTC 24 |
| Finished | Sep 04 08:35:38 AM UTC 24 |
| Peak memory | 245540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065093445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.4065093445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/41.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.1167975084 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 13007727 ps |
| CPU time | 1.07 seconds |
| Started | Sep 04 08:35:44 AM UTC 24 |
| Finished | Sep 04 08:35:46 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167975084 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.1167975084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/42.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3390602119 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 266129029 ps |
| CPU time | 4.42 seconds |
| Started | Sep 04 08:35:35 AM UTC 24 |
| Finished | Sep 04 08:35:41 AM UTC 24 |
| Peak memory | 235308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390602119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3390602119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/42.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.3836850645 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 13613046 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 08:35:28 AM UTC 24 |
| Finished | Sep 04 08:35:30 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836850645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3836850645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/42.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.209511970 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 10616589498 ps |
| CPU time | 93.24 seconds |
| Started | Sep 04 08:35:39 AM UTC 24 |
| Finished | Sep 04 08:37:14 AM UTC 24 |
| Peak memory | 262372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209511970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.209511970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/42.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.3108657013 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 2729465693 ps |
| CPU time | 40.03 seconds |
| Started | Sep 04 08:35:40 AM UTC 24 |
| Finished | Sep 04 08:36:21 AM UTC 24 |
| Peak memory | 264224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108657013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3108657013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.3060308031 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 55101444158 ps |
| CPU time | 242.63 seconds |
| Started | Sep 04 08:35:40 AM UTC 24 |
| Finished | Sep 04 08:39:46 AM UTC 24 |
| Peak memory | 264196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060308031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.3060308031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.755608722 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 122557411 ps |
| CPU time | 5.91 seconds |
| Started | Sep 04 08:35:37 AM UTC 24 |
| Finished | Sep 04 08:35:44 AM UTC 24 |
| Peak memory | 249676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755608722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.755608722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/42.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.3297978074 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 955093210 ps |
| CPU time | 7.81 seconds |
| Started | Sep 04 08:35:38 AM UTC 24 |
| Finished | Sep 04 08:35:47 AM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297978074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.3297978074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.2190258612 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 38282536 ps |
| CPU time | 3.24 seconds |
| Started | Sep 04 08:35:32 AM UTC 24 |
| Finished | Sep 04 08:35:36 AM UTC 24 |
| Peak memory | 245548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190258612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2190258612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/42.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.3830243879 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 17404236599 ps |
| CPU time | 37.73 seconds |
| Started | Sep 04 08:35:33 AM UTC 24 |
| Finished | Sep 04 08:36:12 AM UTC 24 |
| Peak memory | 251872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830243879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3830243879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/42.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.2318476175 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 420391605 ps |
| CPU time | 4.34 seconds |
| Started | Sep 04 08:35:32 AM UTC 24 |
| Finished | Sep 04 08:35:37 AM UTC 24 |
| Peak memory | 235268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318476175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.2318476175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/42.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.638615759 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 9871134454 ps |
| CPU time | 17.04 seconds |
| Started | Sep 04 08:35:31 AM UTC 24 |
| Finished | Sep 04 08:35:49 AM UTC 24 |
| Peak memory | 235468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638615759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.638615759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/42.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.207744855 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 746169022 ps |
| CPU time | 5.34 seconds |
| Started | Sep 04 08:35:38 AM UTC 24 |
| Finished | Sep 04 08:35:45 AM UTC 24 |
| Peak memory | 231856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207744855 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.207744855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/42.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.2227296461 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 49588796 ps |
| CPU time | 1.55 seconds |
| Started | Sep 04 08:35:42 AM UTC 24 |
| Finished | Sep 04 08:35:44 AM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227296461 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.2227296461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/42.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.3470872701 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 5144398868 ps |
| CPU time | 38.89 seconds |
| Started | Sep 04 08:35:29 AM UTC 24 |
| Finished | Sep 04 08:36:09 AM UTC 24 |
| Peak memory | 227980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470872701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3470872701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/42.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.1924130431 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 1868277851 ps |
| CPU time | 9.3 seconds |
| Started | Sep 04 08:35:29 AM UTC 24 |
| Finished | Sep 04 08:35:39 AM UTC 24 |
| Peak memory | 227920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924130431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1924130431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/42.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.3869402710 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 18481768 ps |
| CPU time | 1.17 seconds |
| Started | Sep 04 08:35:31 AM UTC 24 |
| Finished | Sep 04 08:35:33 AM UTC 24 |
| Peak memory | 215984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869402710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3869402710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/42.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.1725825311 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 21505611 ps |
| CPU time | 1.2 seconds |
| Started | Sep 04 08:35:29 AM UTC 24 |
| Finished | Sep 04 08:35:31 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725825311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1725825311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/42.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.4002148139 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 13352682812 ps |
| CPU time | 23.9 seconds |
| Started | Sep 04 08:35:34 AM UTC 24 |
| Finished | Sep 04 08:35:59 AM UTC 24 |
| Peak memory | 245672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002148139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.4002148139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/42.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.2938613390 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 32084110 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 08:35:59 AM UTC 24 |
| Finished | Sep 04 08:36:02 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938613390 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.2938613390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/43.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.1732187756 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 31665631 ps |
| CPU time | 2.87 seconds |
| Started | Sep 04 08:35:55 AM UTC 24 |
| Finished | Sep 04 08:35:58 AM UTC 24 |
| Peak memory | 234868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732187756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1732187756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/43.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.4083015790 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 78152684 ps |
| CPU time | 1.15 seconds |
| Started | Sep 04 08:35:45 AM UTC 24 |
| Finished | Sep 04 08:35:47 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083015790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4083015790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/43.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.4141182007 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 2830844193 ps |
| CPU time | 28.77 seconds |
| Started | Sep 04 08:35:57 AM UTC 24 |
| Finished | Sep 04 08:36:27 AM UTC 24 |
| Peak memory | 245712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141182007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.4141182007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/43.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.2405580703 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 2908671499 ps |
| CPU time | 31.87 seconds |
| Started | Sep 04 08:35:57 AM UTC 24 |
| Finished | Sep 04 08:36:30 AM UTC 24 |
| Peak memory | 235524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405580703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2405580703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.3400614466 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 36926406921 ps |
| CPU time | 315.05 seconds |
| Started | Sep 04 08:35:58 AM UTC 24 |
| Finished | Sep 04 08:41:18 AM UTC 24 |
| Peak memory | 276484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400614466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.3400614466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.3467461914 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 428311203 ps |
| CPU time | 11.25 seconds |
| Started | Sep 04 08:35:55 AM UTC 24 |
| Finished | Sep 04 08:36:07 AM UTC 24 |
| Peak memory | 245176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467461914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3467461914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/43.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.2441343471 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 9483750471 ps |
| CPU time | 91.86 seconds |
| Started | Sep 04 08:35:55 AM UTC 24 |
| Finished | Sep 04 08:37:29 AM UTC 24 |
| Peak memory | 262280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441343471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.2441343471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.1318236033 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 667854746 ps |
| CPU time | 5.96 seconds |
| Started | Sep 04 08:35:49 AM UTC 24 |
| Finished | Sep 04 08:35:56 AM UTC 24 |
| Peak memory | 244220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318236033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1318236033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/43.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.3817075830 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 107345723 ps |
| CPU time | 2.32 seconds |
| Started | Sep 04 08:35:50 AM UTC 24 |
| Finished | Sep 04 08:35:54 AM UTC 24 |
| Peak memory | 245284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817075830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3817075830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/43.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.1348656655 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 4098372804 ps |
| CPU time | 9.36 seconds |
| Started | Sep 04 08:35:48 AM UTC 24 |
| Finished | Sep 04 08:35:59 AM UTC 24 |
| Peak memory | 235660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348656655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.1348656655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/43.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.933930592 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 260867255 ps |
| CPU time | 4.08 seconds |
| Started | Sep 04 08:35:48 AM UTC 24 |
| Finished | Sep 04 08:35:53 AM UTC 24 |
| Peak memory | 245580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933930592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.933930592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/43.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.4284843220 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 1174824604 ps |
| CPU time | 5.93 seconds |
| Started | Sep 04 08:35:56 AM UTC 24 |
| Finished | Sep 04 08:36:03 AM UTC 24 |
| Peak memory | 231856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284843220 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.4284843220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/43.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.2432537703 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 47843204896 ps |
| CPU time | 262.96 seconds |
| Started | Sep 04 08:35:58 AM UTC 24 |
| Finished | Sep 04 08:40:25 AM UTC 24 |
| Peak memory | 284964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432537703 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.2432537703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/43.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.1745498596 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 1119545583 ps |
| CPU time | 6.34 seconds |
| Started | Sep 04 08:35:46 AM UTC 24 |
| Finished | Sep 04 08:35:53 AM UTC 24 |
| Peak memory | 227740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745498596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1745498596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/43.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.2708749629 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 2890076418 ps |
| CPU time | 9.3 seconds |
| Started | Sep 04 08:35:45 AM UTC 24 |
| Finished | Sep 04 08:35:55 AM UTC 24 |
| Peak memory | 228068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708749629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2708749629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/43.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.3167198435 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 1832947408 ps |
| CPU time | 8.35 seconds |
| Started | Sep 04 08:35:48 AM UTC 24 |
| Finished | Sep 04 08:35:58 AM UTC 24 |
| Peak memory | 227952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167198435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3167198435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/43.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.4292110011 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 142174208 ps |
| CPU time | 1.23 seconds |
| Started | Sep 04 08:35:47 AM UTC 24 |
| Finished | Sep 04 08:35:49 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292110011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.4292110011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/43.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.2019353904 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 4008139885 ps |
| CPU time | 4.97 seconds |
| Started | Sep 04 08:35:54 AM UTC 24 |
| Finished | Sep 04 08:36:00 AM UTC 24 |
| Peak memory | 235428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019353904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2019353904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/43.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.4150104982 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 30882597 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 08:36:15 AM UTC 24 |
| Finished | Sep 04 08:36:17 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150104982 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.4150104982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/44.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.1581032342 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 164530579 ps |
| CPU time | 4.52 seconds |
| Started | Sep 04 08:36:08 AM UTC 24 |
| Finished | Sep 04 08:36:14 AM UTC 24 |
| Peak memory | 229876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581032342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1581032342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/44.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.998802064 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 80913451 ps |
| CPU time | 1.21 seconds |
| Started | Sep 04 08:35:59 AM UTC 24 |
| Finished | Sep 04 08:36:02 AM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998802064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.998802064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/44.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.62976871 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 77421740678 ps |
| CPU time | 160.87 seconds |
| Started | Sep 04 08:36:10 AM UTC 24 |
| Finished | Sep 04 08:38:54 AM UTC 24 |
| Peak memory | 264328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62976871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.62976871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/44.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.2372494141 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 15163703151 ps |
| CPU time | 63.07 seconds |
| Started | Sep 04 08:36:10 AM UTC 24 |
| Finished | Sep 04 08:37:15 AM UTC 24 |
| Peak memory | 250060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372494141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2372494141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.2118677079 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 30513910419 ps |
| CPU time | 383.28 seconds |
| Started | Sep 04 08:36:10 AM UTC 24 |
| Finished | Sep 04 08:42:39 AM UTC 24 |
| Peak memory | 278556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118677079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.2118677079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.217237492 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 12457058896 ps |
| CPU time | 25.29 seconds |
| Started | Sep 04 08:36:08 AM UTC 24 |
| Finished | Sep 04 08:36:35 AM UTC 24 |
| Peak memory | 245736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217237492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.217237492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/44.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.2083304629 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 31426524103 ps |
| CPU time | 150.58 seconds |
| Started | Sep 04 08:36:09 AM UTC 24 |
| Finished | Sep 04 08:38:43 AM UTC 24 |
| Peak memory | 278472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083304629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.2083304629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.4169828008 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 1483758318 ps |
| CPU time | 3.98 seconds |
| Started | Sep 04 08:36:04 AM UTC 24 |
| Finished | Sep 04 08:36:09 AM UTC 24 |
| Peak memory | 235340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169828008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.4169828008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/44.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.3044452234 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 1558182399 ps |
| CPU time | 20.78 seconds |
| Started | Sep 04 08:36:06 AM UTC 24 |
| Finished | Sep 04 08:36:28 AM UTC 24 |
| Peak memory | 245512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044452234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3044452234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/44.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.1132230595 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 19631268842 ps |
| CPU time | 32.15 seconds |
| Started | Sep 04 08:36:03 AM UTC 24 |
| Finished | Sep 04 08:36:36 AM UTC 24 |
| Peak memory | 249800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132230595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.1132230595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/44.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.2358554776 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 212103123 ps |
| CPU time | 3.4 seconds |
| Started | Sep 04 08:36:03 AM UTC 24 |
| Finished | Sep 04 08:36:07 AM UTC 24 |
| Peak memory | 245580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358554776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2358554776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/44.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.4006584601 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 253696267 ps |
| CPU time | 4.52 seconds |
| Started | Sep 04 08:36:09 AM UTC 24 |
| Finished | Sep 04 08:36:15 AM UTC 24 |
| Peak memory | 234028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006584601 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.4006584601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/44.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.2980092045 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 195616568 ps |
| CPU time | 1.48 seconds |
| Started | Sep 04 08:36:13 AM UTC 24 |
| Finished | Sep 04 08:36:16 AM UTC 24 |
| Peak memory | 216412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980092045 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.2980092045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/44.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.358492797 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 10296300659 ps |
| CPU time | 26.31 seconds |
| Started | Sep 04 08:36:00 AM UTC 24 |
| Finished | Sep 04 08:36:28 AM UTC 24 |
| Peak memory | 228152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358492797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.358492797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/44.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.3033238585 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 40279615031 ps |
| CPU time | 17.36 seconds |
| Started | Sep 04 08:36:00 AM UTC 24 |
| Finished | Sep 04 08:36:19 AM UTC 24 |
| Peak memory | 227912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033238585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3033238585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/44.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.10431253 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 165480330 ps |
| CPU time | 3.7 seconds |
| Started | Sep 04 08:36:03 AM UTC 24 |
| Finished | Sep 04 08:36:07 AM UTC 24 |
| Peak memory | 227800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10431253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_devi ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.10431253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/44.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.1672846623 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 18173039 ps |
| CPU time | 1.15 seconds |
| Started | Sep 04 08:36:03 AM UTC 24 |
| Finished | Sep 04 08:36:05 AM UTC 24 |
| Peak memory | 215924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672846623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1672846623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/44.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.3992425944 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 1958730044 ps |
| CPU time | 9.33 seconds |
| Started | Sep 04 08:36:08 AM UTC 24 |
| Finished | Sep 04 08:36:18 AM UTC 24 |
| Peak memory | 245572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992425944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3992425944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/44.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.2964068366 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 49636303 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 08:36:32 AM UTC 24 |
| Finished | Sep 04 08:36:34 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964068366 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.2964068366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/45.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.3284499840 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 304045717 ps |
| CPU time | 2.88 seconds |
| Started | Sep 04 08:36:26 AM UTC 24 |
| Finished | Sep 04 08:36:30 AM UTC 24 |
| Peak memory | 245544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284499840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3284499840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/45.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.1278027164 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 24613941 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 08:36:16 AM UTC 24 |
| Finished | Sep 04 08:36:18 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278027164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1278027164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/45.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.545051434 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 32880352827 ps |
| CPU time | 150.8 seconds |
| Started | Sep 04 08:36:29 AM UTC 24 |
| Finished | Sep 04 08:39:03 AM UTC 24 |
| Peak memory | 278468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545051434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.545051434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/45.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.519666126 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 24189369713 ps |
| CPU time | 115.75 seconds |
| Started | Sep 04 08:36:29 AM UTC 24 |
| Finished | Sep 04 08:38:27 AM UTC 24 |
| Peak memory | 268520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519666126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.519666126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.1342346684 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 79481346027 ps |
| CPU time | 322.52 seconds |
| Started | Sep 04 08:36:31 AM UTC 24 |
| Finished | Sep 04 08:41:58 AM UTC 24 |
| Peak memory | 266312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342346684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.1342346684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.1814054052 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 783466663 ps |
| CPU time | 14.67 seconds |
| Started | Sep 04 08:36:27 AM UTC 24 |
| Finished | Sep 04 08:36:43 AM UTC 24 |
| Peak memory | 247624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814054052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1814054052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/45.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.1119796096 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 49711343706 ps |
| CPU time | 49.08 seconds |
| Started | Sep 04 08:36:28 AM UTC 24 |
| Finished | Sep 04 08:37:19 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119796096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.1119796096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.3447545374 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 10852885141 ps |
| CPU time | 17.56 seconds |
| Started | Sep 04 08:36:22 AM UTC 24 |
| Finished | Sep 04 08:36:41 AM UTC 24 |
| Peak memory | 235468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447545374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3447545374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/45.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.247950473 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 1783189272 ps |
| CPU time | 7.85 seconds |
| Started | Sep 04 08:36:22 AM UTC 24 |
| Finished | Sep 04 08:36:31 AM UTC 24 |
| Peak memory | 245800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247950473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.247950473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/45.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.1031316002 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 26286636107 ps |
| CPU time | 29.74 seconds |
| Started | Sep 04 08:36:20 AM UTC 24 |
| Finished | Sep 04 08:36:51 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031316002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.1031316002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/45.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.758075528 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 6862178546 ps |
| CPU time | 13.88 seconds |
| Started | Sep 04 08:36:19 AM UTC 24 |
| Finished | Sep 04 08:36:34 AM UTC 24 |
| Peak memory | 235408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758075528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.758075528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/45.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.4182498400 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 1607141075 ps |
| CPU time | 5.71 seconds |
| Started | Sep 04 08:36:28 AM UTC 24 |
| Finished | Sep 04 08:36:35 AM UTC 24 |
| Peak memory | 229612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182498400 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.4182498400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/45.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.1200880519 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 112485423 ps |
| CPU time | 1.63 seconds |
| Started | Sep 04 08:36:31 AM UTC 24 |
| Finished | Sep 04 08:36:34 AM UTC 24 |
| Peak memory | 226748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200880519 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.1200880519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/45.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.2938200113 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 3616420689 ps |
| CPU time | 31.98 seconds |
| Started | Sep 04 08:36:18 AM UTC 24 |
| Finished | Sep 04 08:36:51 AM UTC 24 |
| Peak memory | 232072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938200113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2938200113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/45.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.1509393522 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 5959027505 ps |
| CPU time | 29.53 seconds |
| Started | Sep 04 08:36:17 AM UTC 24 |
| Finished | Sep 04 08:36:48 AM UTC 24 |
| Peak memory | 227832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509393522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1509393522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/45.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.3871242590 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 255905546 ps |
| CPU time | 4.77 seconds |
| Started | Sep 04 08:36:19 AM UTC 24 |
| Finished | Sep 04 08:36:25 AM UTC 24 |
| Peak memory | 227740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871242590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3871242590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/45.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.2781324121 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 212458401 ps |
| CPU time | 1.35 seconds |
| Started | Sep 04 08:36:19 AM UTC 24 |
| Finished | Sep 04 08:36:22 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781324121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2781324121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/45.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.605469924 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 101043269 ps |
| CPU time | 2.19 seconds |
| Started | Sep 04 08:36:23 AM UTC 24 |
| Finished | Sep 04 08:36:27 AM UTC 24 |
| Peak memory | 234948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605469924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.605469924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/45.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.2609668341 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 34036530 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 08:36:48 AM UTC 24 |
| Finished | Sep 04 08:36:51 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609668341 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.2609668341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/46.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.4164172167 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 1180300267 ps |
| CPU time | 17.42 seconds |
| Started | Sep 04 08:36:39 AM UTC 24 |
| Finished | Sep 04 08:36:58 AM UTC 24 |
| Peak memory | 235368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164172167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4164172167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/46.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.3656152051 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 85366821 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 08:36:33 AM UTC 24 |
| Finished | Sep 04 08:36:36 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656152051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3656152051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/46.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.1524972981 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 8369495314 ps |
| CPU time | 54.74 seconds |
| Started | Sep 04 08:36:42 AM UTC 24 |
| Finished | Sep 04 08:37:39 AM UTC 24 |
| Peak memory | 264328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524972981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1524972981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/46.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.1793822091 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 38549747582 ps |
| CPU time | 242.47 seconds |
| Started | Sep 04 08:36:43 AM UTC 24 |
| Finished | Sep 04 08:40:51 AM UTC 24 |
| Peak memory | 282636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793822091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1793822091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/46.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.3586609716 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 9724469912 ps |
| CPU time | 44.63 seconds |
| Started | Sep 04 08:36:45 AM UTC 24 |
| Finished | Sep 04 08:37:31 AM UTC 24 |
| Peak memory | 251872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586609716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.3586609716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.2296994916 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 527749600 ps |
| CPU time | 15.89 seconds |
| Started | Sep 04 08:36:39 AM UTC 24 |
| Finished | Sep 04 08:36:56 AM UTC 24 |
| Peak memory | 245576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296994916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2296994916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/46.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.2076245691 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 356980396 ps |
| CPU time | 7.51 seconds |
| Started | Sep 04 08:36:38 AM UTC 24 |
| Finished | Sep 04 08:36:46 AM UTC 24 |
| Peak memory | 245604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076245691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2076245691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/46.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.621553258 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 1828575723 ps |
| CPU time | 7.84 seconds |
| Started | Sep 04 08:36:38 AM UTC 24 |
| Finished | Sep 04 08:36:47 AM UTC 24 |
| Peak memory | 245604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621553258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.621553258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/46.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.1636072110 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 16885145652 ps |
| CPU time | 19.52 seconds |
| Started | Sep 04 08:36:37 AM UTC 24 |
| Finished | Sep 04 08:36:58 AM UTC 24 |
| Peak memory | 235436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636072110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.1636072110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/46.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.4160621740 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 3225916301 ps |
| CPU time | 10.47 seconds |
| Started | Sep 04 08:36:36 AM UTC 24 |
| Finished | Sep 04 08:36:48 AM UTC 24 |
| Peak memory | 235400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160621740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.4160621740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/46.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.1591016880 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 1248506276 ps |
| CPU time | 12.03 seconds |
| Started | Sep 04 08:36:41 AM UTC 24 |
| Finished | Sep 04 08:36:55 AM UTC 24 |
| Peak memory | 231668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591016880 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.1591016880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/46.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.2540101920 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 142616703 ps |
| CPU time | 1.64 seconds |
| Started | Sep 04 08:36:47 AM UTC 24 |
| Finished | Sep 04 08:36:51 AM UTC 24 |
| Peak memory | 216408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540101920 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.2540101920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/46.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.1037994193 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 3281387275 ps |
| CPU time | 7.54 seconds |
| Started | Sep 04 08:36:35 AM UTC 24 |
| Finished | Sep 04 08:36:44 AM UTC 24 |
| Peak memory | 228172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037994193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1037994193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/46.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.4017232907 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 19201168 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 08:36:34 AM UTC 24 |
| Finished | Sep 04 08:36:37 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017232907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.4017232907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/46.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.1556934517 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 35043025 ps |
| CPU time | 1.2 seconds |
| Started | Sep 04 08:36:36 AM UTC 24 |
| Finished | Sep 04 08:36:38 AM UTC 24 |
| Peak memory | 216504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556934517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1556934517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/46.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.2135800247 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 23985250 ps |
| CPU time | 1.09 seconds |
| Started | Sep 04 08:36:36 AM UTC 24 |
| Finished | Sep 04 08:36:38 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135800247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2135800247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/46.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.166235434 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 8068583210 ps |
| CPU time | 23.56 seconds |
| Started | Sep 04 08:36:39 AM UTC 24 |
| Finished | Sep 04 08:37:04 AM UTC 24 |
| Peak memory | 245660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166235434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.166235434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/46.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.3669937806 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 32634027 ps |
| CPU time | 1.09 seconds |
| Started | Sep 04 08:36:59 AM UTC 24 |
| Finished | Sep 04 08:37:01 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669937806 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.3669937806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/47.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.1043428549 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 113573468 ps |
| CPU time | 3.22 seconds |
| Started | Sep 04 08:36:55 AM UTC 24 |
| Finished | Sep 04 08:37:00 AM UTC 24 |
| Peak memory | 245152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043428549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1043428549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/47.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.666832027 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 25963806 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 08:36:49 AM UTC 24 |
| Finished | Sep 04 08:36:52 AM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666832027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.666832027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/47.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.4245210118 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 123107636258 ps |
| CPU time | 290.31 seconds |
| Started | Sep 04 08:36:56 AM UTC 24 |
| Finished | Sep 04 08:41:51 AM UTC 24 |
| Peak memory | 262308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245210118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4245210118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/47.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3065597314 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 4211409570 ps |
| CPU time | 63.41 seconds |
| Started | Sep 04 08:36:58 AM UTC 24 |
| Finished | Sep 04 08:38:03 AM UTC 24 |
| Peak memory | 262088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065597314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3065597314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.3825865252 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 5049226693 ps |
| CPU time | 125.83 seconds |
| Started | Sep 04 08:36:58 AM UTC 24 |
| Finished | Sep 04 08:39:06 AM UTC 24 |
| Peak memory | 268384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825865252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.3825865252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.1084983448 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 180147134 ps |
| CPU time | 8.18 seconds |
| Started | Sep 04 08:36:55 AM UTC 24 |
| Finished | Sep 04 08:37:05 AM UTC 24 |
| Peak memory | 245612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084983448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1084983448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/47.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.3402511247 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 28716738825 ps |
| CPU time | 68.9 seconds |
| Started | Sep 04 08:36:55 AM UTC 24 |
| Finished | Sep 04 08:38:06 AM UTC 24 |
| Peak memory | 262084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402511247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.3402511247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.538329314 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 857507851 ps |
| CPU time | 4.14 seconds |
| Started | Sep 04 08:36:52 AM UTC 24 |
| Finished | Sep 04 08:36:57 AM UTC 24 |
| Peak memory | 245608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538329314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.538329314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/47.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.578382951 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 532479627 ps |
| CPU time | 8.2 seconds |
| Started | Sep 04 08:36:54 AM UTC 24 |
| Finished | Sep 04 08:37:03 AM UTC 24 |
| Peak memory | 245612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578382951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.578382951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/47.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.2067621953 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 60524241980 ps |
| CPU time | 22.73 seconds |
| Started | Sep 04 08:36:52 AM UTC 24 |
| Finished | Sep 04 08:37:16 AM UTC 24 |
| Peak memory | 245840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067621953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.2067621953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/47.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.3609772587 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 7280049757 ps |
| CPU time | 15.35 seconds |
| Started | Sep 04 08:36:52 AM UTC 24 |
| Finished | Sep 04 08:37:08 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609772587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3609772587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/47.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.2403804249 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 8328132445 ps |
| CPU time | 15.03 seconds |
| Started | Sep 04 08:36:56 AM UTC 24 |
| Finished | Sep 04 08:37:13 AM UTC 24 |
| Peak memory | 231788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403804249 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.2403804249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/47.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.3174809109 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 257555646077 ps |
| CPU time | 1058.56 seconds |
| Started | Sep 04 08:36:59 AM UTC 24 |
| Finished | Sep 04 08:54:50 AM UTC 24 |
| Peak memory | 297000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174809109 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.3174809109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/47.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.470395761 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 5084592421 ps |
| CPU time | 31.83 seconds |
| Started | Sep 04 08:36:49 AM UTC 24 |
| Finished | Sep 04 08:37:23 AM UTC 24 |
| Peak memory | 227988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470395761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.470395761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/47.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.164449013 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 825639297 ps |
| CPU time | 5.25 seconds |
| Started | Sep 04 08:36:49 AM UTC 24 |
| Finished | Sep 04 08:36:56 AM UTC 24 |
| Peak memory | 217208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164449013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.164449013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/47.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.2518135840 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 49285733 ps |
| CPU time | 1.77 seconds |
| Started | Sep 04 08:36:52 AM UTC 24 |
| Finished | Sep 04 08:36:55 AM UTC 24 |
| Peak memory | 226924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518135840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2518135840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/47.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.515565503 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 145867458 ps |
| CPU time | 1.32 seconds |
| Started | Sep 04 08:36:52 AM UTC 24 |
| Finished | Sep 04 08:36:54 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515565503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.515565503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/47.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.4180307762 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 475508607 ps |
| CPU time | 7.66 seconds |
| Started | Sep 04 08:36:55 AM UTC 24 |
| Finished | Sep 04 08:37:04 AM UTC 24 |
| Peak memory | 245552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180307762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4180307762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/47.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.2256199268 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 14801761 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 08:37:16 AM UTC 24 |
| Finished | Sep 04 08:37:18 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256199268 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.2256199268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/48.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.1185587817 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 2228857423 ps |
| CPU time | 22.83 seconds |
| Started | Sep 04 08:37:11 AM UTC 24 |
| Finished | Sep 04 08:37:35 AM UTC 24 |
| Peak memory | 245900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185587817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1185587817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/48.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.2714705895 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 37622312 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 08:37:01 AM UTC 24 |
| Finished | Sep 04 08:37:03 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714705895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2714705895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/48.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.2956132945 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 1536898709 ps |
| CPU time | 31.49 seconds |
| Started | Sep 04 08:37:14 AM UTC 24 |
| Finished | Sep 04 08:37:47 AM UTC 24 |
| Peak memory | 262152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956132945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2956132945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/48.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.3733769061 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 41206661088 ps |
| CPU time | 165.01 seconds |
| Started | Sep 04 08:37:14 AM UTC 24 |
| Finished | Sep 04 08:40:02 AM UTC 24 |
| Peak memory | 278536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733769061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3733769061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.1585891923 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 24514182165 ps |
| CPU time | 60.51 seconds |
| Started | Sep 04 08:37:15 AM UTC 24 |
| Finished | Sep 04 08:38:17 AM UTC 24 |
| Peak memory | 249824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585891923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.1585891923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.442001607 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 1198898619 ps |
| CPU time | 10.2 seconds |
| Started | Sep 04 08:37:12 AM UTC 24 |
| Finished | Sep 04 08:37:23 AM UTC 24 |
| Peak memory | 245580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442001607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.442001607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/48.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.3663679588 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 21717622 ps |
| CPU time | 1.26 seconds |
| Started | Sep 04 08:37:12 AM UTC 24 |
| Finished | Sep 04 08:37:14 AM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663679588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.3663679588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.3897410770 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 218397771 ps |
| CPU time | 4.9 seconds |
| Started | Sep 04 08:37:07 AM UTC 24 |
| Finished | Sep 04 08:37:13 AM UTC 24 |
| Peak memory | 235340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897410770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3897410770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/48.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.3578260488 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 754554453 ps |
| CPU time | 17.67 seconds |
| Started | Sep 04 08:37:08 AM UTC 24 |
| Finished | Sep 04 08:37:27 AM UTC 24 |
| Peak memory | 245568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578260488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3578260488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/48.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.2173499106 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 958391263 ps |
| CPU time | 4.17 seconds |
| Started | Sep 04 08:37:05 AM UTC 24 |
| Finished | Sep 04 08:37:10 AM UTC 24 |
| Peak memory | 235280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173499106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.2173499106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/48.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.4133928570 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 69993535 ps |
| CPU time | 4.22 seconds |
| Started | Sep 04 08:37:05 AM UTC 24 |
| Finished | Sep 04 08:37:10 AM UTC 24 |
| Peak memory | 245608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133928570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.4133928570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/48.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2619833433 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 2533269084 ps |
| CPU time | 8.13 seconds |
| Started | Sep 04 08:37:12 AM UTC 24 |
| Finished | Sep 04 08:37:21 AM UTC 24 |
| Peak memory | 233844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619833433 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.2619833433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/48.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.2075854075 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 99414325 ps |
| CPU time | 1.55 seconds |
| Started | Sep 04 08:37:15 AM UTC 24 |
| Finished | Sep 04 08:37:18 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075854075 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.2075854075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/48.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.1402418000 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 3612018214 ps |
| CPU time | 21.1 seconds |
| Started | Sep 04 08:37:04 AM UTC 24 |
| Finished | Sep 04 08:37:26 AM UTC 24 |
| Peak memory | 231988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402418000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1402418000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/48.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.4198400456 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 3427687414 ps |
| CPU time | 6.1 seconds |
| Started | Sep 04 08:37:02 AM UTC 24 |
| Finished | Sep 04 08:37:10 AM UTC 24 |
| Peak memory | 227820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198400456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.4198400456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/48.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.285151793 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 81545947 ps |
| CPU time | 5.88 seconds |
| Started | Sep 04 08:37:04 AM UTC 24 |
| Finished | Sep 04 08:37:11 AM UTC 24 |
| Peak memory | 227756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285151793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.285151793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/48.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.3783655782 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 92078950 ps |
| CPU time | 1.2 seconds |
| Started | Sep 04 08:37:04 AM UTC 24 |
| Finished | Sep 04 08:37:06 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783655782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3783655782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/48.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.1606765779 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 388037176 ps |
| CPU time | 4.46 seconds |
| Started | Sep 04 08:37:09 AM UTC 24 |
| Finished | Sep 04 08:37:15 AM UTC 24 |
| Peak memory | 235336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606765779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1606765779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/48.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.2641273333 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 47158730 ps |
| CPU time | 1.08 seconds |
| Started | Sep 04 08:37:31 AM UTC 24 |
| Finished | Sep 04 08:37:34 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641273333 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.2641273333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/49.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.3857444240 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 504878880 ps |
| CPU time | 5.29 seconds |
| Started | Sep 04 08:37:26 AM UTC 24 |
| Finished | Sep 04 08:37:32 AM UTC 24 |
| Peak memory | 235328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857444240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3857444240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/49.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.76490367 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 32079497 ps |
| CPU time | 1.19 seconds |
| Started | Sep 04 08:37:16 AM UTC 24 |
| Finished | Sep 04 08:37:18 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76490367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.76490367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/49.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.2189329182 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 2586740989 ps |
| CPU time | 72.12 seconds |
| Started | Sep 04 08:37:29 AM UTC 24 |
| Finished | Sep 04 08:38:43 AM UTC 24 |
| Peak memory | 268204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189329182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2189329182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/49.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.677730501 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 702039563 ps |
| CPU time | 12.34 seconds |
| Started | Sep 04 08:37:30 AM UTC 24 |
| Finished | Sep 04 08:37:44 AM UTC 24 |
| Peak memory | 235304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677730501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.677730501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.1346850483 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 25934836106 ps |
| CPU time | 56.69 seconds |
| Started | Sep 04 08:37:30 AM UTC 24 |
| Finished | Sep 04 08:38:29 AM UTC 24 |
| Peak memory | 245764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346850483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.1346850483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.1064872283 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 25307302534 ps |
| CPU time | 50.71 seconds |
| Started | Sep 04 08:37:26 AM UTC 24 |
| Finished | Sep 04 08:38:18 AM UTC 24 |
| Peak memory | 266212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064872283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1064872283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/49.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.663467984 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 2241597748 ps |
| CPU time | 51.6 seconds |
| Started | Sep 04 08:37:27 AM UTC 24 |
| Finished | Sep 04 08:38:20 AM UTC 24 |
| Peak memory | 262112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663467984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.663467984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.2650470350 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 732441086 ps |
| CPU time | 7.56 seconds |
| Started | Sep 04 08:37:23 AM UTC 24 |
| Finished | Sep 04 08:37:31 AM UTC 24 |
| Peak memory | 245580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650470350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2650470350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/49.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.2007394377 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 6826285765 ps |
| CPU time | 53.53 seconds |
| Started | Sep 04 08:37:24 AM UTC 24 |
| Finished | Sep 04 08:38:19 AM UTC 24 |
| Peak memory | 245728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007394377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2007394377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/49.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.1202466938 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 105916956 ps |
| CPU time | 2.95 seconds |
| Started | Sep 04 08:37:22 AM UTC 24 |
| Finished | Sep 04 08:37:26 AM UTC 24 |
| Peak memory | 235508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202466938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.1202466938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/49.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.3558853004 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 1147756186 ps |
| CPU time | 9.94 seconds |
| Started | Sep 04 08:37:20 AM UTC 24 |
| Finished | Sep 04 08:37:31 AM UTC 24 |
| Peak memory | 235536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558853004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3558853004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/49.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.1766926397 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 137530081 ps |
| CPU time | 4.92 seconds |
| Started | Sep 04 08:37:28 AM UTC 24 |
| Finished | Sep 04 08:37:34 AM UTC 24 |
| Peak memory | 233984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766926397 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.1766926397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/49.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.2866040685 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 110844211 ps |
| CPU time | 1.57 seconds |
| Started | Sep 04 08:37:31 AM UTC 24 |
| Finished | Sep 04 08:37:34 AM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866040685 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.2866040685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/49.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.2112807219 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 2995262168 ps |
| CPU time | 13.94 seconds |
| Started | Sep 04 08:37:18 AM UTC 24 |
| Finished | Sep 04 08:37:33 AM UTC 24 |
| Peak memory | 227956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112807219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2112807219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/49.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.142520498 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 3649726256 ps |
| CPU time | 10.81 seconds |
| Started | Sep 04 08:37:17 AM UTC 24 |
| Finished | Sep 04 08:37:29 AM UTC 24 |
| Peak memory | 227912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142520498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.142520498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/49.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.790591279 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 999417072 ps |
| CPU time | 4.38 seconds |
| Started | Sep 04 08:37:19 AM UTC 24 |
| Finished | Sep 04 08:37:25 AM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790591279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.790591279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/49.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.1083482877 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 14174021 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 08:37:19 AM UTC 24 |
| Finished | Sep 04 08:37:22 AM UTC 24 |
| Peak memory | 215792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083482877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1083482877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/49.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.2561120797 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 9548971087 ps |
| CPU time | 15.51 seconds |
| Started | Sep 04 08:37:24 AM UTC 24 |
| Finished | Sep 04 08:37:40 AM UTC 24 |
| Peak memory | 245700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561120797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2561120797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/49.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.3726083866 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 32137837 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 08:25:18 AM UTC 24 |
| Finished | Sep 04 08:25:20 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726083866 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3726083866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.2315823571 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 368425989 ps |
| CPU time | 3.46 seconds |
| Started | Sep 04 08:25:05 AM UTC 24 |
| Finished | Sep 04 08:25:09 AM UTC 24 |
| Peak memory | 245732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315823571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2315823571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.3574431945 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 93303411 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 08:24:52 AM UTC 24 |
| Finished | Sep 04 08:24:54 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574431945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3574431945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.1024960996 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 5535180927 ps |
| CPU time | 33.89 seconds |
| Started | Sep 04 08:25:12 AM UTC 24 |
| Finished | Sep 04 08:25:47 AM UTC 24 |
| Peak memory | 264140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024960996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1024960996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.1030373807 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 32393075232 ps |
| CPU time | 66.74 seconds |
| Started | Sep 04 08:25:15 AM UTC 24 |
| Finished | Sep 04 08:26:24 AM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030373807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1030373807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.1912891964 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 114032004691 ps |
| CPU time | 614.51 seconds |
| Started | Sep 04 08:25:15 AM UTC 24 |
| Finished | Sep 04 08:35:38 AM UTC 24 |
| Peak memory | 274636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912891964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.1912891964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.2269629868 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 3595305943 ps |
| CPU time | 32.65 seconds |
| Started | Sep 04 08:25:06 AM UTC 24 |
| Finished | Sep 04 08:25:40 AM UTC 24 |
| Peak memory | 235460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269629868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2269629868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.2977659314 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 3611176810 ps |
| CPU time | 55.88 seconds |
| Started | Sep 04 08:25:09 AM UTC 24 |
| Finished | Sep 04 08:26:06 AM UTC 24 |
| Peak memory | 247820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977659314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.2977659314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.3394948727 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 86451336 ps |
| CPU time | 4.98 seconds |
| Started | Sep 04 08:24:59 AM UTC 24 |
| Finished | Sep 04 08:25:05 AM UTC 24 |
| Peak memory | 245552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394948727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3394948727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.3015197918 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 4919657608 ps |
| CPU time | 52.45 seconds |
| Started | Sep 04 08:25:01 AM UTC 24 |
| Finished | Sep 04 08:25:55 AM UTC 24 |
| Peak memory | 247776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015197918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3015197918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.2841279958 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 48976538 ps |
| CPU time | 1.5 seconds |
| Started | Sep 04 08:24:53 AM UTC 24 |
| Finished | Sep 04 08:24:55 AM UTC 24 |
| Peak memory | 229200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841279958 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mem_parity.2841279958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.970576576 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 1194263881 ps |
| CPU time | 16.9 seconds |
| Started | Sep 04 08:24:59 AM UTC 24 |
| Finished | Sep 04 08:25:16 AM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970576576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.970576576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.3729795127 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 7819986467 ps |
| CPU time | 20.4 seconds |
| Started | Sep 04 08:24:58 AM UTC 24 |
| Finished | Sep 04 08:25:20 AM UTC 24 |
| Peak memory | 245772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729795127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3729795127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.1703573371 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 2133959629 ps |
| CPU time | 19.41 seconds |
| Started | Sep 04 08:25:10 AM UTC 24 |
| Finished | Sep 04 08:25:31 AM UTC 24 |
| Peak memory | 231612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703573371 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.1703573371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.957651967 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 15854522210 ps |
| CPU time | 24.97 seconds |
| Started | Sep 04 08:24:54 AM UTC 24 |
| Finished | Sep 04 08:25:20 AM UTC 24 |
| Peak memory | 227972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957651967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.957651967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2793305421 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 4473583123 ps |
| CPU time | 13.84 seconds |
| Started | Sep 04 08:24:53 AM UTC 24 |
| Finished | Sep 04 08:25:08 AM UTC 24 |
| Peak memory | 228080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793305421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2793305421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.1913283270 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 60178866 ps |
| CPU time | 2.2 seconds |
| Started | Sep 04 08:24:56 AM UTC 24 |
| Finished | Sep 04 08:24:59 AM UTC 24 |
| Peak memory | 227756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913283270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1913283270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.2402943001 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 22572318 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 08:24:55 AM UTC 24 |
| Finished | Sep 04 08:24:57 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402943001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2402943001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.2701326400 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 2452324173 ps |
| CPU time | 9.34 seconds |
| Started | Sep 04 08:25:04 AM UTC 24 |
| Finished | Sep 04 08:25:14 AM UTC 24 |
| Peak memory | 235676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701326400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2701326400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/5.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.2849471532 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 12365930 ps |
| CPU time | 0.85 seconds |
| Started | Sep 04 08:25:32 AM UTC 24 |
| Finished | Sep 04 08:25:34 AM UTC 24 |
| Peak memory | 215640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849471532 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2849471532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.1619366282 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 452902129 ps |
| CPU time | 6.53 seconds |
| Started | Sep 04 08:25:27 AM UTC 24 |
| Finished | Sep 04 08:25:34 AM UTC 24 |
| Peak memory | 245736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619366282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1619366282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.3637672027 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 44178286 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 08:25:19 AM UTC 24 |
| Finished | Sep 04 08:25:21 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637672027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3637672027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.1356338255 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 59157699863 ps |
| CPU time | 120.95 seconds |
| Started | Sep 04 08:25:29 AM UTC 24 |
| Finished | Sep 04 08:27:33 AM UTC 24 |
| Peak memory | 262084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356338255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1356338255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.40260857 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 17508081445 ps |
| CPU time | 176.98 seconds |
| Started | Sep 04 08:25:31 AM UTC 24 |
| Finished | Sep 04 08:28:30 AM UTC 24 |
| Peak memory | 262460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40260857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.40260857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.1413427237 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 17635212586 ps |
| CPU time | 29.53 seconds |
| Started | Sep 04 08:25:32 AM UTC 24 |
| Finished | Sep 04 08:26:03 AM UTC 24 |
| Peak memory | 264420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413427237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.1413427237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.2258255691 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 220622682 ps |
| CPU time | 10.82 seconds |
| Started | Sep 04 08:25:27 AM UTC 24 |
| Finished | Sep 04 08:25:39 AM UTC 24 |
| Peak memory | 245572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258255691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2258255691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.3308403474 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 468396769 ps |
| CPU time | 13.64 seconds |
| Started | Sep 04 08:25:28 AM UTC 24 |
| Finished | Sep 04 08:25:43 AM UTC 24 |
| Peak memory | 235336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308403474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.3308403474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.4218241639 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 240141087 ps |
| CPU time | 6.58 seconds |
| Started | Sep 04 08:25:24 AM UTC 24 |
| Finished | Sep 04 08:25:31 AM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218241639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.4218241639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.390751686 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1790080694 ps |
| CPU time | 27.98 seconds |
| Started | Sep 04 08:25:25 AM UTC 24 |
| Finished | Sep 04 08:25:54 AM UTC 24 |
| Peak memory | 245532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390751686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.390751686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.2064791387 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 44383588 ps |
| CPU time | 1.58 seconds |
| Started | Sep 04 08:25:20 AM UTC 24 |
| Finished | Sep 04 08:25:23 AM UTC 24 |
| Peak memory | 229200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064791387 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mem_parity.2064791387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1400778363 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 104430891771 ps |
| CPU time | 38.81 seconds |
| Started | Sep 04 08:25:22 AM UTC 24 |
| Finished | Sep 04 08:26:03 AM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400778363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.1400778363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.2869532075 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 3980223787 ps |
| CPU time | 7.16 seconds |
| Started | Sep 04 08:25:22 AM UTC 24 |
| Finished | Sep 04 08:25:31 AM UTC 24 |
| Peak memory | 247756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869532075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2869532075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2512560701 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 3069016579 ps |
| CPU time | 16.06 seconds |
| Started | Sep 04 08:25:29 AM UTC 24 |
| Finished | Sep 04 08:25:47 AM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512560701 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.2512560701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.2257526270 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 39183875032 ps |
| CPU time | 122.34 seconds |
| Started | Sep 04 08:25:32 AM UTC 24 |
| Finished | Sep 04 08:27:37 AM UTC 24 |
| Peak memory | 278724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257526270 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.2257526270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.852136096 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 2034602181 ps |
| CPU time | 11.19 seconds |
| Started | Sep 04 08:25:21 AM UTC 24 |
| Finished | Sep 04 08:25:33 AM UTC 24 |
| Peak memory | 227820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852136096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.852136096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.1140283255 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 4695862466 ps |
| CPU time | 7.06 seconds |
| Started | Sep 04 08:25:21 AM UTC 24 |
| Finished | Sep 04 08:25:29 AM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140283255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1140283255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.3012378625 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1826439765 ps |
| CPU time | 2.86 seconds |
| Started | Sep 04 08:25:22 AM UTC 24 |
| Finished | Sep 04 08:25:26 AM UTC 24 |
| Peak memory | 227884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012378625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3012378625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.1721482446 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 87113615 ps |
| CPU time | 1.21 seconds |
| Started | Sep 04 08:25:21 AM UTC 24 |
| Finished | Sep 04 08:25:23 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721482446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1721482446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.3165981547 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 479619136 ps |
| CPU time | 5.86 seconds |
| Started | Sep 04 08:25:27 AM UTC 24 |
| Finished | Sep 04 08:25:34 AM UTC 24 |
| Peak memory | 245660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165981547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3165981547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/6.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.3489245991 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 46886190 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 08:25:49 AM UTC 24 |
| Finished | Sep 04 08:25:51 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489245991 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3489245991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.847871742 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 672407446 ps |
| CPU time | 9.29 seconds |
| Started | Sep 04 08:25:41 AM UTC 24 |
| Finished | Sep 04 08:25:52 AM UTC 24 |
| Peak memory | 245540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847871742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.847871742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.4262683311 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 158399436 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 08:25:32 AM UTC 24 |
| Finished | Sep 04 08:25:34 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262683311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.4262683311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.3745943339 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 106218628336 ps |
| CPU time | 234.06 seconds |
| Started | Sep 04 08:25:43 AM UTC 24 |
| Finished | Sep 04 08:29:41 AM UTC 24 |
| Peak memory | 268492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745943339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3745943339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.832028774 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 6930299273 ps |
| CPU time | 53.71 seconds |
| Started | Sep 04 08:25:43 AM UTC 24 |
| Finished | Sep 04 08:26:39 AM UTC 24 |
| Peak memory | 245240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832028774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.832028774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.3594733486 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 744179909 ps |
| CPU time | 12.34 seconds |
| Started | Sep 04 08:25:41 AM UTC 24 |
| Finished | Sep 04 08:25:55 AM UTC 24 |
| Peak memory | 235464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594733486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3594733486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.4092995312 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 3573394548 ps |
| CPU time | 29.09 seconds |
| Started | Sep 04 08:25:41 AM UTC 24 |
| Finished | Sep 04 08:26:12 AM UTC 24 |
| Peak memory | 235660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092995312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.4092995312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.578493803 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 269988071 ps |
| CPU time | 5.21 seconds |
| Started | Sep 04 08:25:39 AM UTC 24 |
| Finished | Sep 04 08:25:45 AM UTC 24 |
| Peak memory | 235276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578493803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.578493803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.2816222688 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 4164436239 ps |
| CPU time | 39.96 seconds |
| Started | Sep 04 08:25:40 AM UTC 24 |
| Finished | Sep 04 08:26:22 AM UTC 24 |
| Peak memory | 251872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816222688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2816222688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.1511286193 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 58906255 ps |
| CPU time | 1.47 seconds |
| Started | Sep 04 08:25:34 AM UTC 24 |
| Finished | Sep 04 08:25:37 AM UTC 24 |
| Peak memory | 229140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511286193 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mem_parity.1511286193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3227557094 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 551165610 ps |
| CPU time | 7.66 seconds |
| Started | Sep 04 08:25:38 AM UTC 24 |
| Finished | Sep 04 08:25:47 AM UTC 24 |
| Peak memory | 245648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227557094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.3227557094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.2542418405 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 3426340811 ps |
| CPU time | 18.59 seconds |
| Started | Sep 04 08:25:37 AM UTC 24 |
| Finished | Sep 04 08:25:57 AM UTC 24 |
| Peak memory | 235536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542418405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2542418405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.2950493701 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 1761216102 ps |
| CPU time | 18.67 seconds |
| Started | Sep 04 08:25:41 AM UTC 24 |
| Finished | Sep 04 08:26:02 AM UTC 24 |
| Peak memory | 231612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950493701 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.2950493701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.1075577338 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 16658618975 ps |
| CPU time | 29.82 seconds |
| Started | Sep 04 08:25:48 AM UTC 24 |
| Finished | Sep 04 08:26:19 AM UTC 24 |
| Peak memory | 249864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075577338 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.1075577338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.3961500813 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 303555531 ps |
| CPU time | 3.47 seconds |
| Started | Sep 04 08:25:35 AM UTC 24 |
| Finished | Sep 04 08:25:40 AM UTC 24 |
| Peak memory | 227764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961500813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3961500813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1406666410 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 22402804 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 08:25:35 AM UTC 24 |
| Finished | Sep 04 08:25:38 AM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406666410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1406666410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.1260794546 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 13749040 ps |
| CPU time | 1.08 seconds |
| Started | Sep 04 08:25:35 AM UTC 24 |
| Finished | Sep 04 08:25:38 AM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260794546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1260794546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.651117203 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 150778843 ps |
| CPU time | 1.33 seconds |
| Started | Sep 04 08:25:35 AM UTC 24 |
| Finished | Sep 04 08:25:38 AM UTC 24 |
| Peak memory | 215920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651117203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.651117203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.973262791 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 31777723318 ps |
| CPU time | 31.65 seconds |
| Started | Sep 04 08:25:40 AM UTC 24 |
| Finished | Sep 04 08:26:13 AM UTC 24 |
| Peak memory | 235460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973262791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.973262791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/7.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.806548474 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 56965712 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 08:26:03 AM UTC 24 |
| Finished | Sep 04 08:26:05 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806548474 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.806548474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.37986838 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 440419018 ps |
| CPU time | 7.91 seconds |
| Started | Sep 04 08:25:56 AM UTC 24 |
| Finished | Sep 04 08:26:05 AM UTC 24 |
| Peak memory | 245544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37986838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.37986838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.3230557228 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 19965779 ps |
| CPU time | 1.18 seconds |
| Started | Sep 04 08:25:49 AM UTC 24 |
| Finished | Sep 04 08:25:51 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230557228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3230557228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.781576245 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 6967341221 ps |
| CPU time | 30.34 seconds |
| Started | Sep 04 08:26:00 AM UTC 24 |
| Finished | Sep 04 08:26:32 AM UTC 24 |
| Peak memory | 250020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781576245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.781576245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.1045649890 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 1244543425 ps |
| CPU time | 27 seconds |
| Started | Sep 04 08:25:57 AM UTC 24 |
| Finished | Sep 04 08:26:25 AM UTC 24 |
| Peak memory | 251940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045649890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1045649890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.4194970307 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 183523725 ps |
| CPU time | 3.48 seconds |
| Started | Sep 04 08:25:54 AM UTC 24 |
| Finished | Sep 04 08:25:59 AM UTC 24 |
| Peak memory | 245580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194970307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4194970307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.3057559543 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 1396783159 ps |
| CPU time | 22.95 seconds |
| Started | Sep 04 08:25:56 AM UTC 24 |
| Finished | Sep 04 08:26:20 AM UTC 24 |
| Peak memory | 247624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057559543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3057559543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.1977748511 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 41922577 ps |
| CPU time | 1.43 seconds |
| Started | Sep 04 08:25:49 AM UTC 24 |
| Finished | Sep 04 08:25:51 AM UTC 24 |
| Peak memory | 229140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977748511 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mem_parity.1977748511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.4262250949 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 345601884 ps |
| CPU time | 4.39 seconds |
| Started | Sep 04 08:25:54 AM UTC 24 |
| Finished | Sep 04 08:26:00 AM UTC 24 |
| Peak memory | 235340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262250949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.4262250949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2639238355 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 170233540 ps |
| CPU time | 3.33 seconds |
| Started | Sep 04 08:25:53 AM UTC 24 |
| Finished | Sep 04 08:25:58 AM UTC 24 |
| Peak memory | 245616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639238355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2639238355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.3600993591 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 3936352278 ps |
| CPU time | 13.05 seconds |
| Started | Sep 04 08:25:59 AM UTC 24 |
| Finished | Sep 04 08:26:13 AM UTC 24 |
| Peak memory | 233876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600993591 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.3600993591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.1740532148 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 675404481805 ps |
| CPU time | 568.9 seconds |
| Started | Sep 04 08:26:03 AM UTC 24 |
| Finished | Sep 04 08:35:39 AM UTC 24 |
| Peak memory | 276488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740532148 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.1740532148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.2918266061 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 3407479827 ps |
| CPU time | 22.36 seconds |
| Started | Sep 04 08:25:52 AM UTC 24 |
| Finished | Sep 04 08:26:16 AM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918266061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2918266061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.3180184257 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 5927718360 ps |
| CPU time | 12.55 seconds |
| Started | Sep 04 08:25:50 AM UTC 24 |
| Finished | Sep 04 08:26:04 AM UTC 24 |
| Peak memory | 227832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180184257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3180184257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.3954683234 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 112476782 ps |
| CPU time | 1.6 seconds |
| Started | Sep 04 08:25:52 AM UTC 24 |
| Finished | Sep 04 08:25:55 AM UTC 24 |
| Peak memory | 216976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954683234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3954683234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.180788229 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 41084740 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 08:25:52 AM UTC 24 |
| Finished | Sep 04 08:25:55 AM UTC 24 |
| Peak memory | 215920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180788229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.180788229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.3885190107 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 169460317 ps |
| CPU time | 2.71 seconds |
| Started | Sep 04 08:25:56 AM UTC 24 |
| Finished | Sep 04 08:26:00 AM UTC 24 |
| Peak memory | 235328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885190107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3885190107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/8.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.1040050354 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 16819232 ps |
| CPU time | 0.97 seconds |
| Started | Sep 04 08:26:19 AM UTC 24 |
| Finished | Sep 04 08:26:21 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040050354 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1040050354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.3738989279 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 414730863 ps |
| CPU time | 3.5 seconds |
| Started | Sep 04 08:26:11 AM UTC 24 |
| Finished | Sep 04 08:26:16 AM UTC 24 |
| Peak memory | 235532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738989279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3738989279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.3781198831 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 33061681 ps |
| CPU time | 0.97 seconds |
| Started | Sep 04 08:26:03 AM UTC 24 |
| Finished | Sep 04 08:26:05 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781198831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3781198831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.1895748228 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 144198199623 ps |
| CPU time | 305.86 seconds |
| Started | Sep 04 08:26:14 AM UTC 24 |
| Finished | Sep 04 08:31:24 AM UTC 24 |
| Peak memory | 266188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895748228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1895748228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2488620961 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 5005410735 ps |
| CPU time | 12.75 seconds |
| Started | Sep 04 08:26:17 AM UTC 24 |
| Finished | Sep 04 08:26:30 AM UTC 24 |
| Peak memory | 245736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488620961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.2488620961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.2501050118 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 38417422 ps |
| CPU time | 3.28 seconds |
| Started | Sep 04 08:26:13 AM UTC 24 |
| Finished | Sep 04 08:26:17 AM UTC 24 |
| Peak memory | 245604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501050118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2501050118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.2614082232 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 21066891152 ps |
| CPU time | 45.35 seconds |
| Started | Sep 04 08:26:07 AM UTC 24 |
| Finished | Sep 04 08:26:54 AM UTC 24 |
| Peak memory | 244348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614082232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2614082232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.4052189340 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 11419559149 ps |
| CPU time | 42.59 seconds |
| Started | Sep 04 08:26:07 AM UTC 24 |
| Finished | Sep 04 08:26:51 AM UTC 24 |
| Peak memory | 235460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052189340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4052189340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.4098859662 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 83297071 ps |
| CPU time | 1.2 seconds |
| Started | Sep 04 08:26:03 AM UTC 24 |
| Finished | Sep 04 08:26:06 AM UTC 24 |
| Peak memory | 229200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098859662 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mem_parity.4098859662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.273725133 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2472752806 ps |
| CPU time | 15.32 seconds |
| Started | Sep 04 08:26:07 AM UTC 24 |
| Finished | Sep 04 08:26:23 AM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273725133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.273725133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.2474131816 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 8076388950 ps |
| CPU time | 21.53 seconds |
| Started | Sep 04 08:26:06 AM UTC 24 |
| Finished | Sep 04 08:26:28 AM UTC 24 |
| Peak memory | 235604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474131816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2474131816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.2220470118 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 225603415 ps |
| CPU time | 6.01 seconds |
| Started | Sep 04 08:26:14 AM UTC 24 |
| Finished | Sep 04 08:26:21 AM UTC 24 |
| Peak memory | 231860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220470118 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.2220470118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.1929892633 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 5515187484 ps |
| CPU time | 19.56 seconds |
| Started | Sep 04 08:26:18 AM UTC 24 |
| Finished | Sep 04 08:26:38 AM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929892633 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.1929892633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.3689048439 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 3208956478 ps |
| CPU time | 41.09 seconds |
| Started | Sep 04 08:26:06 AM UTC 24 |
| Finished | Sep 04 08:26:48 AM UTC 24 |
| Peak memory | 227892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689048439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3689048439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.1117089278 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 754219602 ps |
| CPU time | 8.01 seconds |
| Started | Sep 04 08:26:04 AM UTC 24 |
| Finished | Sep 04 08:26:13 AM UTC 24 |
| Peak memory | 227944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117089278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1117089278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.2332167273 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 759778581 ps |
| CPU time | 3.17 seconds |
| Started | Sep 04 08:26:06 AM UTC 24 |
| Finished | Sep 04 08:26:10 AM UTC 24 |
| Peak memory | 227600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332167273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2332167273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.2878614195 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 80161780 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 08:26:06 AM UTC 24 |
| Finished | Sep 04 08:26:08 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878614195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2878614195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.581988497 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1587532752 ps |
| CPU time | 7.05 seconds |
| Started | Sep 04 08:26:09 AM UTC 24 |
| Finished | Sep 04 08:26:17 AM UTC 24 |
| Peak memory | 245608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581988497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.581988497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/9.spi_device_upload/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |