| T838 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.535597998 |
|
|
Sep 04 08:35:09 AM UTC 24 |
Sep 04 08:35:17 AM UTC 24 |
209506300 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.820168789 |
|
|
Sep 04 08:35:15 AM UTC 24 |
Sep 04 08:35:17 AM UTC 24 |
32620167 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.4055965403 |
|
|
Sep 04 08:35:15 AM UTC 24 |
Sep 04 08:35:17 AM UTC 24 |
46034780 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.2712200760 |
|
|
Sep 04 08:33:32 AM UTC 24 |
Sep 04 08:35:18 AM UTC 24 |
29619029305 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.1460420928 |
|
|
Sep 04 08:33:02 AM UTC 24 |
Sep 04 08:35:19 AM UTC 24 |
9667428297 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.4240680008 |
|
|
Sep 04 08:35:04 AM UTC 24 |
Sep 04 08:35:19 AM UTC 24 |
816963930 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.3336722393 |
|
|
Sep 04 08:30:54 AM UTC 24 |
Sep 04 08:35:19 AM UTC 24 |
27604461027 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_all.1536920705 |
|
|
Sep 04 08:34:27 AM UTC 24 |
Sep 04 08:35:20 AM UTC 24 |
31121755395 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.3668434535 |
|
|
Sep 04 08:35:18 AM UTC 24 |
Sep 04 08:35:21 AM UTC 24 |
82279158 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.2178876672 |
|
|
Sep 04 08:34:51 AM UTC 24 |
Sep 04 08:35:21 AM UTC 24 |
10221400082 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.2329221936 |
|
|
Sep 04 08:35:18 AM UTC 24 |
Sep 04 08:35:21 AM UTC 24 |
174089950 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.1793741441 |
|
|
Sep 04 08:34:05 AM UTC 24 |
Sep 04 08:35:22 AM UTC 24 |
4736132113 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.1719820885 |
|
|
Sep 04 08:33:48 AM UTC 24 |
Sep 04 08:35:23 AM UTC 24 |
5509138639 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2857177086 |
|
|
Sep 04 08:35:23 AM UTC 24 |
Sep 04 08:35:25 AM UTC 24 |
329611852 ps |
| T41 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.3955965965 |
|
|
Sep 04 08:32:48 AM UTC 24 |
Sep 04 08:35:26 AM UTC 24 |
22139555978 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.4261165277 |
|
|
Sep 04 08:35:18 AM UTC 24 |
Sep 04 08:35:26 AM UTC 24 |
3570824646 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.990367549 |
|
|
Sep 04 08:35:21 AM UTC 24 |
Sep 04 08:35:27 AM UTC 24 |
189641101 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.2905046633 |
|
|
Sep 04 08:34:59 AM UTC 24 |
Sep 04 08:35:27 AM UTC 24 |
8960081828 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.2964548389 |
|
|
Sep 04 08:35:20 AM UTC 24 |
Sep 04 08:35:27 AM UTC 24 |
1270715820 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.758075528 |
|
|
Sep 04 08:36:19 AM UTC 24 |
Sep 04 08:36:34 AM UTC 24 |
6862178546 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.576636077 |
|
|
Sep 04 08:35:20 AM UTC 24 |
Sep 04 08:35:28 AM UTC 24 |
820029185 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.2683610794 |
|
|
Sep 04 08:31:42 AM UTC 24 |
Sep 04 08:35:28 AM UTC 24 |
25914289831 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.310267254 |
|
|
Sep 04 08:35:27 AM UTC 24 |
Sep 04 08:35:30 AM UTC 24 |
15533888 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.3836850645 |
|
|
Sep 04 08:35:28 AM UTC 24 |
Sep 04 08:35:30 AM UTC 24 |
13613046 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.1725825311 |
|
|
Sep 04 08:35:29 AM UTC 24 |
Sep 04 08:35:31 AM UTC 24 |
21505611 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.500199065 |
|
|
Sep 04 08:35:22 AM UTC 24 |
Sep 04 08:35:31 AM UTC 24 |
384307797 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.459437575 |
|
|
Sep 04 08:35:23 AM UTC 24 |
Sep 04 08:35:32 AM UTC 24 |
935851146 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.3869402710 |
|
|
Sep 04 08:35:31 AM UTC 24 |
Sep 04 08:35:33 AM UTC 24 |
18481768 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.3759217107 |
|
|
Sep 04 08:35:03 AM UTC 24 |
Sep 04 08:35:34 AM UTC 24 |
2748227641 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.2190258612 |
|
|
Sep 04 08:35:32 AM UTC 24 |
Sep 04 08:35:36 AM UTC 24 |
38282536 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.2318476175 |
|
|
Sep 04 08:35:32 AM UTC 24 |
Sep 04 08:35:37 AM UTC 24 |
420391605 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.4065093445 |
|
|
Sep 04 08:35:22 AM UTC 24 |
Sep 04 08:35:38 AM UTC 24 |
1409440452 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.1912891964 |
|
|
Sep 04 08:25:15 AM UTC 24 |
Sep 04 08:35:38 AM UTC 24 |
114032004691 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.1740532148 |
|
|
Sep 04 08:26:03 AM UTC 24 |
Sep 04 08:35:39 AM UTC 24 |
675404481805 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.1924130431 |
|
|
Sep 04 08:35:29 AM UTC 24 |
Sep 04 08:35:39 AM UTC 24 |
1868277851 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3390602119 |
|
|
Sep 04 08:35:35 AM UTC 24 |
Sep 04 08:35:41 AM UTC 24 |
266129029 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.1116669142 |
|
|
Sep 04 08:33:17 AM UTC 24 |
Sep 04 08:35:43 AM UTC 24 |
43378540190 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.755608722 |
|
|
Sep 04 08:35:37 AM UTC 24 |
Sep 04 08:35:44 AM UTC 24 |
122557411 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.2227296461 |
|
|
Sep 04 08:35:42 AM UTC 24 |
Sep 04 08:35:44 AM UTC 24 |
49588796 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.207744855 |
|
|
Sep 04 08:35:38 AM UTC 24 |
Sep 04 08:35:45 AM UTC 24 |
746169022 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.1167975084 |
|
|
Sep 04 08:35:44 AM UTC 24 |
Sep 04 08:35:46 AM UTC 24 |
13007727 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.4083015790 |
|
|
Sep 04 08:35:45 AM UTC 24 |
Sep 04 08:35:47 AM UTC 24 |
78152684 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.3297978074 |
|
|
Sep 04 08:35:38 AM UTC 24 |
Sep 04 08:35:47 AM UTC 24 |
955093210 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.2653564111 |
|
|
Sep 04 08:26:49 AM UTC 24 |
Sep 04 08:35:48 AM UTC 24 |
183008352564 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.638615759 |
|
|
Sep 04 08:35:31 AM UTC 24 |
Sep 04 08:35:49 AM UTC 24 |
9871134454 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.4292110011 |
|
|
Sep 04 08:35:47 AM UTC 24 |
Sep 04 08:35:49 AM UTC 24 |
142174208 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.2516629284 |
|
|
Sep 04 08:35:17 AM UTC 24 |
Sep 04 08:35:53 AM UTC 24 |
15683805588 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.933930592 |
|
|
Sep 04 08:35:48 AM UTC 24 |
Sep 04 08:35:53 AM UTC 24 |
260867255 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.1745498596 |
|
|
Sep 04 08:35:46 AM UTC 24 |
Sep 04 08:35:53 AM UTC 24 |
1119545583 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.3817075830 |
|
|
Sep 04 08:35:50 AM UTC 24 |
Sep 04 08:35:54 AM UTC 24 |
107345723 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.2708749629 |
|
|
Sep 04 08:35:45 AM UTC 24 |
Sep 04 08:35:55 AM UTC 24 |
2890076418 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.2590370723 |
|
|
Sep 04 08:30:09 AM UTC 24 |
Sep 04 08:35:56 AM UTC 24 |
43935421189 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.1318236033 |
|
|
Sep 04 08:35:49 AM UTC 24 |
Sep 04 08:35:56 AM UTC 24 |
667854746 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.1856751692 |
|
|
Sep 04 08:28:42 AM UTC 24 |
Sep 04 08:35:57 AM UTC 24 |
159495786005 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.3167198435 |
|
|
Sep 04 08:35:48 AM UTC 24 |
Sep 04 08:35:58 AM UTC 24 |
1832947408 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.1732187756 |
|
|
Sep 04 08:35:55 AM UTC 24 |
Sep 04 08:35:58 AM UTC 24 |
31665631 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.1348656655 |
|
|
Sep 04 08:35:48 AM UTC 24 |
Sep 04 08:35:59 AM UTC 24 |
4098372804 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.4002148139 |
|
|
Sep 04 08:35:34 AM UTC 24 |
Sep 04 08:35:59 AM UTC 24 |
13352682812 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.2019353904 |
|
|
Sep 04 08:35:54 AM UTC 24 |
Sep 04 08:36:00 AM UTC 24 |
4008139885 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.2938613390 |
|
|
Sep 04 08:35:59 AM UTC 24 |
Sep 04 08:36:02 AM UTC 24 |
32084110 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.3749198983 |
|
|
Sep 04 08:35:14 AM UTC 24 |
Sep 04 08:36:02 AM UTC 24 |
2092440613 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.3301412323 |
|
|
Sep 04 08:35:26 AM UTC 24 |
Sep 04 08:36:02 AM UTC 24 |
4204517829 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.998802064 |
|
|
Sep 04 08:35:59 AM UTC 24 |
Sep 04 08:36:02 AM UTC 24 |
80913451 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.4284843220 |
|
|
Sep 04 08:35:56 AM UTC 24 |
Sep 04 08:36:03 AM UTC 24 |
1174824604 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.1672846623 |
|
|
Sep 04 08:36:03 AM UTC 24 |
Sep 04 08:36:05 AM UTC 24 |
18173039 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.3467461914 |
|
|
Sep 04 08:35:55 AM UTC 24 |
Sep 04 08:36:07 AM UTC 24 |
428311203 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.2358554776 |
|
|
Sep 04 08:36:03 AM UTC 24 |
Sep 04 08:36:07 AM UTC 24 |
212103123 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.10431253 |
|
|
Sep 04 08:36:03 AM UTC 24 |
Sep 04 08:36:07 AM UTC 24 |
165480330 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.329432857 |
|
|
Sep 04 08:35:14 AM UTC 24 |
Sep 04 08:36:08 AM UTC 24 |
2261648058 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.295750517 |
|
|
Sep 04 08:34:23 AM UTC 24 |
Sep 04 08:36:08 AM UTC 24 |
5947775182 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.3470872701 |
|
|
Sep 04 08:35:29 AM UTC 24 |
Sep 04 08:36:09 AM UTC 24 |
5144398868 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.4169828008 |
|
|
Sep 04 08:36:04 AM UTC 24 |
Sep 04 08:36:09 AM UTC 24 |
1483758318 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.2823343715 |
|
|
Sep 04 08:35:26 AM UTC 24 |
Sep 04 08:36:10 AM UTC 24 |
15775891806 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.3830243879 |
|
|
Sep 04 08:35:33 AM UTC 24 |
Sep 04 08:36:12 AM UTC 24 |
17404236599 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.1581032342 |
|
|
Sep 04 08:36:08 AM UTC 24 |
Sep 04 08:36:14 AM UTC 24 |
164530579 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.4006584601 |
|
|
Sep 04 08:36:09 AM UTC 24 |
Sep 04 08:36:15 AM UTC 24 |
253696267 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.2980092045 |
|
|
Sep 04 08:36:13 AM UTC 24 |
Sep 04 08:36:16 AM UTC 24 |
195616568 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.4150104982 |
|
|
Sep 04 08:36:15 AM UTC 24 |
Sep 04 08:36:17 AM UTC 24 |
30882597 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.1278027164 |
|
|
Sep 04 08:36:16 AM UTC 24 |
Sep 04 08:36:18 AM UTC 24 |
24613941 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.295928247 |
|
|
Sep 04 08:34:16 AM UTC 24 |
Sep 04 08:36:18 AM UTC 24 |
16418308444 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.3992425944 |
|
|
Sep 04 08:36:08 AM UTC 24 |
Sep 04 08:36:18 AM UTC 24 |
1958730044 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.3033238585 |
|
|
Sep 04 08:36:00 AM UTC 24 |
Sep 04 08:36:19 AM UTC 24 |
40279615031 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.2964068366 |
|
|
Sep 04 08:36:32 AM UTC 24 |
Sep 04 08:36:34 AM UTC 24 |
49636303 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.3108657013 |
|
|
Sep 04 08:35:40 AM UTC 24 |
Sep 04 08:36:21 AM UTC 24 |
2729465693 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.2781324121 |
|
|
Sep 04 08:36:19 AM UTC 24 |
Sep 04 08:36:22 AM UTC 24 |
212458401 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.1975523395 |
|
|
Sep 04 08:34:54 AM UTC 24 |
Sep 04 08:36:22 AM UTC 24 |
21404190148 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.3871242590 |
|
|
Sep 04 08:36:19 AM UTC 24 |
Sep 04 08:36:25 AM UTC 24 |
255905546 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.1444674533 |
|
|
Sep 04 08:34:39 AM UTC 24 |
Sep 04 08:36:26 AM UTC 24 |
9405125602 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.605469924 |
|
|
Sep 04 08:36:23 AM UTC 24 |
Sep 04 08:36:27 AM UTC 24 |
101043269 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.4141182007 |
|
|
Sep 04 08:35:57 AM UTC 24 |
Sep 04 08:36:27 AM UTC 24 |
2830844193 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.358492797 |
|
|
Sep 04 08:36:00 AM UTC 24 |
Sep 04 08:36:28 AM UTC 24 |
10296300659 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.3044452234 |
|
|
Sep 04 08:36:06 AM UTC 24 |
Sep 04 08:36:28 AM UTC 24 |
1558182399 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.3284499840 |
|
|
Sep 04 08:36:26 AM UTC 24 |
Sep 04 08:36:30 AM UTC 24 |
304045717 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.2405580703 |
|
|
Sep 04 08:35:57 AM UTC 24 |
Sep 04 08:36:30 AM UTC 24 |
2908671499 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.247950473 |
|
|
Sep 04 08:36:22 AM UTC 24 |
Sep 04 08:36:31 AM UTC 24 |
1783189272 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.2460928631 |
|
|
Sep 04 08:35:11 AM UTC 24 |
Sep 04 08:36:33 AM UTC 24 |
41004349969 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.1200880519 |
|
|
Sep 04 08:36:31 AM UTC 24 |
Sep 04 08:36:34 AM UTC 24 |
112485423 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.4182498400 |
|
|
Sep 04 08:36:28 AM UTC 24 |
Sep 04 08:36:35 AM UTC 24 |
1607141075 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.217237492 |
|
|
Sep 04 08:36:08 AM UTC 24 |
Sep 04 08:36:35 AM UTC 24 |
12457058896 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.3656152051 |
|
|
Sep 04 08:36:33 AM UTC 24 |
Sep 04 08:36:36 AM UTC 24 |
85366821 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.1132230595 |
|
|
Sep 04 08:36:03 AM UTC 24 |
Sep 04 08:36:36 AM UTC 24 |
19631268842 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.4017232907 |
|
|
Sep 04 08:36:34 AM UTC 24 |
Sep 04 08:36:37 AM UTC 24 |
19201168 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.3857444240 |
|
|
Sep 04 08:37:26 AM UTC 24 |
Sep 04 08:37:32 AM UTC 24 |
504878880 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.2135800247 |
|
|
Sep 04 08:36:36 AM UTC 24 |
Sep 04 08:36:38 AM UTC 24 |
23985250 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.1556934517 |
|
|
Sep 04 08:36:36 AM UTC 24 |
Sep 04 08:36:38 AM UTC 24 |
35043025 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.852961754 |
|
|
Sep 04 08:35:21 AM UTC 24 |
Sep 04 08:36:38 AM UTC 24 |
29037852020 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.2956436086 |
|
|
Sep 04 08:34:57 AM UTC 24 |
Sep 04 08:36:39 AM UTC 24 |
10670316598 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.3958234793 |
|
|
Sep 04 08:32:04 AM UTC 24 |
Sep 04 08:36:40 AM UTC 24 |
125339670027 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.3447545374 |
|
|
Sep 04 08:36:22 AM UTC 24 |
Sep 04 08:36:41 AM UTC 24 |
10852885141 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.1814054052 |
|
|
Sep 04 08:36:27 AM UTC 24 |
Sep 04 08:36:43 AM UTC 24 |
783466663 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.1037994193 |
|
|
Sep 04 08:36:35 AM UTC 24 |
Sep 04 08:36:44 AM UTC 24 |
3281387275 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.2076245691 |
|
|
Sep 04 08:36:38 AM UTC 24 |
Sep 04 08:36:46 AM UTC 24 |
356980396 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.621553258 |
|
|
Sep 04 08:36:38 AM UTC 24 |
Sep 04 08:36:47 AM UTC 24 |
1828575723 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.4160621740 |
|
|
Sep 04 08:36:36 AM UTC 24 |
Sep 04 08:36:48 AM UTC 24 |
3225916301 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.1509393522 |
|
|
Sep 04 08:36:17 AM UTC 24 |
Sep 04 08:36:48 AM UTC 24 |
5959027505 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.2854997956 |
|
|
Sep 04 08:35:08 AM UTC 24 |
Sep 04 08:36:48 AM UTC 24 |
40303992804 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.2540101920 |
|
|
Sep 04 08:36:47 AM UTC 24 |
Sep 04 08:36:51 AM UTC 24 |
142616703 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.2609668341 |
|
|
Sep 04 08:36:48 AM UTC 24 |
Sep 04 08:36:51 AM UTC 24 |
34036530 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.2938200113 |
|
|
Sep 04 08:36:18 AM UTC 24 |
Sep 04 08:36:51 AM UTC 24 |
3616420689 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.1031316002 |
|
|
Sep 04 08:36:20 AM UTC 24 |
Sep 04 08:36:51 AM UTC 24 |
26286636107 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.666832027 |
|
|
Sep 04 08:36:49 AM UTC 24 |
Sep 04 08:36:52 AM UTC 24 |
25963806 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.303959841 |
|
|
Sep 04 08:30:50 AM UTC 24 |
Sep 04 08:36:53 AM UTC 24 |
52424942773 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.687479228 |
|
|
Sep 04 08:33:19 AM UTC 24 |
Sep 04 08:36:54 AM UTC 24 |
38480625569 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.515565503 |
|
|
Sep 04 08:36:52 AM UTC 24 |
Sep 04 08:36:54 AM UTC 24 |
145867458 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.2518135840 |
|
|
Sep 04 08:36:52 AM UTC 24 |
Sep 04 08:36:55 AM UTC 24 |
49285733 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.1591016880 |
|
|
Sep 04 08:36:41 AM UTC 24 |
Sep 04 08:36:55 AM UTC 24 |
1248506276 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.164449013 |
|
|
Sep 04 08:36:49 AM UTC 24 |
Sep 04 08:36:56 AM UTC 24 |
825639297 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.2296994916 |
|
|
Sep 04 08:36:39 AM UTC 24 |
Sep 04 08:36:56 AM UTC 24 |
527749600 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.1201288048 |
|
|
Sep 04 08:35:07 AM UTC 24 |
Sep 04 08:36:57 AM UTC 24 |
9613521394 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.538329314 |
|
|
Sep 04 08:36:52 AM UTC 24 |
Sep 04 08:36:57 AM UTC 24 |
857507851 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.1636072110 |
|
|
Sep 04 08:36:37 AM UTC 24 |
Sep 04 08:36:58 AM UTC 24 |
16885145652 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.4164172167 |
|
|
Sep 04 08:36:39 AM UTC 24 |
Sep 04 08:36:58 AM UTC 24 |
1180300267 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.1043428549 |
|
|
Sep 04 08:36:55 AM UTC 24 |
Sep 04 08:37:00 AM UTC 24 |
113573468 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.3669937806 |
|
|
Sep 04 08:36:59 AM UTC 24 |
Sep 04 08:37:01 AM UTC 24 |
32634027 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.2714705895 |
|
|
Sep 04 08:37:01 AM UTC 24 |
Sep 04 08:37:03 AM UTC 24 |
37622312 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.578382951 |
|
|
Sep 04 08:36:54 AM UTC 24 |
Sep 04 08:37:03 AM UTC 24 |
532479627 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.166235434 |
|
|
Sep 04 08:36:39 AM UTC 24 |
Sep 04 08:37:04 AM UTC 24 |
8068583210 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.4180307762 |
|
|
Sep 04 08:36:55 AM UTC 24 |
Sep 04 08:37:04 AM UTC 24 |
475508607 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.1084983448 |
|
|
Sep 04 08:36:55 AM UTC 24 |
Sep 04 08:37:05 AM UTC 24 |
180147134 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.3783655782 |
|
|
Sep 04 08:37:04 AM UTC 24 |
Sep 04 08:37:06 AM UTC 24 |
92078950 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.2225802507 |
|
|
Sep 04 08:24:30 AM UTC 24 |
Sep 04 08:37:08 AM UTC 24 |
64857712402 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.3609772587 |
|
|
Sep 04 08:36:52 AM UTC 24 |
Sep 04 08:37:08 AM UTC 24 |
7280049757 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.4198400456 |
|
|
Sep 04 08:37:02 AM UTC 24 |
Sep 04 08:37:10 AM UTC 24 |
3427687414 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.2173499106 |
|
|
Sep 04 08:37:05 AM UTC 24 |
Sep 04 08:37:10 AM UTC 24 |
958391263 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.4133928570 |
|
|
Sep 04 08:37:05 AM UTC 24 |
Sep 04 08:37:10 AM UTC 24 |
69993535 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.285151793 |
|
|
Sep 04 08:37:04 AM UTC 24 |
Sep 04 08:37:11 AM UTC 24 |
81545947 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.2403804249 |
|
|
Sep 04 08:36:56 AM UTC 24 |
Sep 04 08:37:13 AM UTC 24 |
8328132445 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.3897410770 |
|
|
Sep 04 08:37:07 AM UTC 24 |
Sep 04 08:37:13 AM UTC 24 |
218397771 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.209511970 |
|
|
Sep 04 08:35:39 AM UTC 24 |
Sep 04 08:37:14 AM UTC 24 |
10616589498 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.3663679588 |
|
|
Sep 04 08:37:12 AM UTC 24 |
Sep 04 08:37:14 AM UTC 24 |
21717622 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.1606765779 |
|
|
Sep 04 08:37:09 AM UTC 24 |
Sep 04 08:37:15 AM UTC 24 |
388037176 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.2372494141 |
|
|
Sep 04 08:36:10 AM UTC 24 |
Sep 04 08:37:15 AM UTC 24 |
15163703151 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.2067621953 |
|
|
Sep 04 08:36:52 AM UTC 24 |
Sep 04 08:37:16 AM UTC 24 |
60524241980 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.2075854075 |
|
|
Sep 04 08:37:15 AM UTC 24 |
Sep 04 08:37:18 AM UTC 24 |
99414325 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.2256199268 |
|
|
Sep 04 08:37:16 AM UTC 24 |
Sep 04 08:37:18 AM UTC 24 |
14801761 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.76490367 |
|
|
Sep 04 08:37:16 AM UTC 24 |
Sep 04 08:37:18 AM UTC 24 |
32079497 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.1119796096 |
|
|
Sep 04 08:36:28 AM UTC 24 |
Sep 04 08:37:19 AM UTC 24 |
49711343706 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2619833433 |
|
|
Sep 04 08:37:12 AM UTC 24 |
Sep 04 08:37:21 AM UTC 24 |
2533269084 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.1083482877 |
|
|
Sep 04 08:37:19 AM UTC 24 |
Sep 04 08:37:22 AM UTC 24 |
14174021 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.470395761 |
|
|
Sep 04 08:36:49 AM UTC 24 |
Sep 04 08:37:23 AM UTC 24 |
5084592421 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.442001607 |
|
|
Sep 04 08:37:12 AM UTC 24 |
Sep 04 08:37:23 AM UTC 24 |
1198898619 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.790591279 |
|
|
Sep 04 08:37:19 AM UTC 24 |
Sep 04 08:37:25 AM UTC 24 |
999417072 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.1202466938 |
|
|
Sep 04 08:37:22 AM UTC 24 |
Sep 04 08:37:26 AM UTC 24 |
105916956 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.1402418000 |
|
|
Sep 04 08:37:04 AM UTC 24 |
Sep 04 08:37:26 AM UTC 24 |
3612018214 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.3578260488 |
|
|
Sep 04 08:37:08 AM UTC 24 |
Sep 04 08:37:27 AM UTC 24 |
754554453 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.2441343471 |
|
|
Sep 04 08:35:55 AM UTC 24 |
Sep 04 08:37:29 AM UTC 24 |
9483750471 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1626823602 |
|
|
Sep 04 08:34:24 AM UTC 24 |
Sep 04 08:37:29 AM UTC 24 |
25171122473 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.142520498 |
|
|
Sep 04 08:37:17 AM UTC 24 |
Sep 04 08:37:29 AM UTC 24 |
3649726256 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.3558853004 |
|
|
Sep 04 08:37:20 AM UTC 24 |
Sep 04 08:37:31 AM UTC 24 |
1147756186 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.857895194 |
|
|
Sep 04 08:32:45 AM UTC 24 |
Sep 04 08:37:31 AM UTC 24 |
35334217670 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.2650470350 |
|
|
Sep 04 08:37:23 AM UTC 24 |
Sep 04 08:37:31 AM UTC 24 |
732441086 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.3586609716 |
|
|
Sep 04 08:36:45 AM UTC 24 |
Sep 04 08:37:31 AM UTC 24 |
9724469912 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.2112807219 |
|
|
Sep 04 08:37:18 AM UTC 24 |
Sep 04 08:37:33 AM UTC 24 |
2995262168 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.1766926397 |
|
|
Sep 04 08:37:28 AM UTC 24 |
Sep 04 08:37:34 AM UTC 24 |
137530081 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.2866040685 |
|
|
Sep 04 08:37:31 AM UTC 24 |
Sep 04 08:37:34 AM UTC 24 |
110844211 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.1185587817 |
|
|
Sep 04 08:37:11 AM UTC 24 |
Sep 04 08:37:35 AM UTC 24 |
2228857423 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.189262915 |
|
|
Sep 04 08:35:12 AM UTC 24 |
Sep 04 08:37:35 AM UTC 24 |
119365370460 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.1524972981 |
|
|
Sep 04 08:36:42 AM UTC 24 |
Sep 04 08:37:39 AM UTC 24 |
8369495314 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.642478239 |
|
|
Sep 04 08:31:43 AM UTC 24 |
Sep 04 08:37:40 AM UTC 24 |
51819519300 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.2561120797 |
|
|
Sep 04 08:37:24 AM UTC 24 |
Sep 04 08:37:40 AM UTC 24 |
9548971087 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.677730501 |
|
|
Sep 04 08:37:30 AM UTC 24 |
Sep 04 08:37:44 AM UTC 24 |
702039563 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_all.4018164968 |
|
|
Sep 04 08:32:27 AM UTC 24 |
Sep 04 08:37:45 AM UTC 24 |
50424723067 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.2956132945 |
|
|
Sep 04 08:37:14 AM UTC 24 |
Sep 04 08:37:47 AM UTC 24 |
1536898709 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.3497582993 |
|
|
Sep 04 08:32:28 AM UTC 24 |
Sep 04 08:37:56 AM UTC 24 |
33751558812 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3065597314 |
|
|
Sep 04 08:36:58 AM UTC 24 |
Sep 04 08:38:03 AM UTC 24 |
4211409570 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.3402511247 |
|
|
Sep 04 08:36:55 AM UTC 24 |
Sep 04 08:38:06 AM UTC 24 |
28716738825 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.1585891923 |
|
|
Sep 04 08:37:15 AM UTC 24 |
Sep 04 08:38:17 AM UTC 24 |
24514182165 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.1064872283 |
|
|
Sep 04 08:37:26 AM UTC 24 |
Sep 04 08:38:18 AM UTC 24 |
25307302534 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.2007394377 |
|
|
Sep 04 08:37:24 AM UTC 24 |
Sep 04 08:38:19 AM UTC 24 |
6826285765 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.663467984 |
|
|
Sep 04 08:37:27 AM UTC 24 |
Sep 04 08:38:20 AM UTC 24 |
2241597748 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.11362425 |
|
|
Sep 04 08:30:09 AM UTC 24 |
Sep 04 08:38:23 AM UTC 24 |
176966058060 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.519666126 |
|
|
Sep 04 08:36:29 AM UTC 24 |
Sep 04 08:38:27 AM UTC 24 |
24189369713 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.1346850483 |
|
|
Sep 04 08:37:30 AM UTC 24 |
Sep 04 08:38:29 AM UTC 24 |
25934836106 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.2083304629 |
|
|
Sep 04 08:36:09 AM UTC 24 |
Sep 04 08:38:43 AM UTC 24 |
31426524103 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.2189329182 |
|
|
Sep 04 08:37:29 AM UTC 24 |
Sep 04 08:38:43 AM UTC 24 |
2586740989 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.62976871 |
|
|
Sep 04 08:36:10 AM UTC 24 |
Sep 04 08:38:54 AM UTC 24 |
77421740678 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.2720894840 |
|
|
Sep 04 08:32:51 AM UTC 24 |
Sep 04 08:38:55 AM UTC 24 |
38392381646 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.545051434 |
|
|
Sep 04 08:36:29 AM UTC 24 |
Sep 04 08:39:03 AM UTC 24 |
32880352827 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.372370878 |
|
|
Sep 04 08:33:50 AM UTC 24 |
Sep 04 08:39:03 AM UTC 24 |
48253145909 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.3825865252 |
|
|
Sep 04 08:36:58 AM UTC 24 |
Sep 04 08:39:06 AM UTC 24 |
5049226693 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.4165629287 |
|
|
Sep 04 08:33:36 AM UTC 24 |
Sep 04 08:39:08 AM UTC 24 |
331023203691 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.2691337854 |
|
|
Sep 04 08:34:37 AM UTC 24 |
Sep 04 08:39:27 AM UTC 24 |
147454482250 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.2446323657 |
|
|
Sep 04 08:35:26 AM UTC 24 |
Sep 04 08:39:38 AM UTC 24 |
59070630890 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.3060308031 |
|
|
Sep 04 08:35:40 AM UTC 24 |
Sep 04 08:39:46 AM UTC 24 |
55101444158 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.2859912632 |
|
|
Sep 04 08:36:40 AM UTC 24 |
Sep 04 08:39:54 AM UTC 24 |
13340195824 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.3733769061 |
|
|
Sep 04 08:37:14 AM UTC 24 |
Sep 04 08:40:02 AM UTC 24 |
41206661088 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.609443893 |
|
|
Sep 04 08:34:03 AM UTC 24 |
Sep 04 08:40:07 AM UTC 24 |
41768750930 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.3749240275 |
|
|
Sep 04 08:34:39 AM UTC 24 |
Sep 04 08:40:13 AM UTC 24 |
150655483095 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.865896685 |
|
|
Sep 04 08:34:54 AM UTC 24 |
Sep 04 08:40:15 AM UTC 24 |
38514432947 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.2432537703 |
|
|
Sep 04 08:35:58 AM UTC 24 |
Sep 04 08:40:25 AM UTC 24 |
47843204896 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.120064670 |
|
|
Sep 04 08:27:42 AM UTC 24 |
Sep 04 08:40:25 AM UTC 24 |
170936851505 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.832565479 |
|
|
Sep 04 08:32:28 AM UTC 24 |
Sep 04 08:40:30 AM UTC 24 |
128181097541 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.1793822091 |
|
|
Sep 04 08:36:43 AM UTC 24 |
Sep 04 08:40:51 AM UTC 24 |
38549747582 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.4066568730 |
|
|
Sep 04 08:32:51 AM UTC 24 |
Sep 04 08:41:09 AM UTC 24 |
95660663692 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.3400614466 |
|
|
Sep 04 08:35:58 AM UTC 24 |
Sep 04 08:41:18 AM UTC 24 |
36926406921 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.1787937941 |
|
|
Sep 04 08:34:56 AM UTC 24 |
Sep 04 08:41:29 AM UTC 24 |
36486153062 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.358512758 |
|
|
Sep 04 08:34:39 AM UTC 24 |
Sep 04 08:41:47 AM UTC 24 |
49157129054 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.4245210118 |
|
|
Sep 04 08:36:56 AM UTC 24 |
Sep 04 08:41:51 AM UTC 24 |
123107636258 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.1342346684 |
|
|
Sep 04 08:36:31 AM UTC 24 |
Sep 04 08:41:58 AM UTC 24 |
79481346027 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.1582397642 |
|
|
Sep 04 08:33:02 AM UTC 24 |
Sep 04 08:42:32 AM UTC 24 |
57967358887 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.2118677079 |
|
|
Sep 04 08:36:10 AM UTC 24 |
Sep 04 08:42:39 AM UTC 24 |
30513910419 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/20.spi_device_stress_all.3538215398 |
|
|
Sep 04 08:29:18 AM UTC 24 |
Sep 04 08:47:08 AM UTC 24 |
176016171843 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.3795549875 |
|
|
Sep 04 08:34:24 AM UTC 24 |
Sep 04 08:48:17 AM UTC 24 |
204287445224 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.360259254 |
|
|
Sep 04 08:35:27 AM UTC 24 |
Sep 04 08:49:10 AM UTC 24 |
83602783615 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.3174809109 |
|
|
Sep 04 08:36:59 AM UTC 24 |
Sep 04 08:54:50 AM UTC 24 |
257555646077 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.1991795799 |
|
|
Sep 04 12:41:16 PM UTC 24 |
Sep 04 12:41:18 PM UTC 24 |
14462661 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.3796973177 |
|
|
Sep 04 12:41:16 PM UTC 24 |
Sep 04 12:41:18 PM UTC 24 |
31430836 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3031428542 |
|
|
Sep 04 12:41:16 PM UTC 24 |
Sep 04 12:41:18 PM UTC 24 |
20225399 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.3179200655 |
|
|
Sep 04 12:41:16 PM UTC 24 |
Sep 04 12:41:18 PM UTC 24 |
171522899 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3445642915 |
|
|
Sep 04 12:41:16 PM UTC 24 |
Sep 04 12:41:18 PM UTC 24 |
129871283 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1928501289 |
|
|
Sep 04 12:41:16 PM UTC 24 |
Sep 04 12:41:20 PM UTC 24 |
422089524 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1606253793 |
|
|
Sep 04 12:41:16 PM UTC 24 |
Sep 04 12:41:20 PM UTC 24 |
284937814 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2104371719 |
|
|
Sep 04 12:41:16 PM UTC 24 |
Sep 04 12:41:20 PM UTC 24 |
45781797 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1761173665 |
|
|
Sep 04 12:41:20 PM UTC 24 |
Sep 04 12:41:24 PM UTC 24 |
67482849 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.3108590477 |
|
|
Sep 04 12:41:14 PM UTC 24 |
Sep 04 12:41:25 PM UTC 24 |
442721847 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1360621730 |
|
|
Sep 04 12:41:19 PM UTC 24 |
Sep 04 12:41:28 PM UTC 24 |
47198395 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3688852930 |
|
|
Sep 04 12:41:26 PM UTC 24 |
Sep 04 12:41:28 PM UTC 24 |
22792216 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.3078386173 |
|
|
Sep 04 12:41:26 PM UTC 24 |
Sep 04 12:41:28 PM UTC 24 |
72877894 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.1580593231 |
|
|
Sep 04 12:41:19 PM UTC 24 |
Sep 04 12:41:29 PM UTC 24 |
29442182 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.1771868100 |
|
|
Sep 04 12:41:26 PM UTC 24 |
Sep 04 12:41:29 PM UTC 24 |
525542827 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.3758428692 |
|
|
Sep 04 12:41:34 PM UTC 24 |
Sep 04 12:41:41 PM UTC 24 |
98735721 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3562485868 |
|
|
Sep 04 12:41:20 PM UTC 24 |
Sep 04 12:41:29 PM UTC 24 |
224468614 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.183170826 |
|
|
Sep 04 12:41:25 PM UTC 24 |
Sep 04 12:41:29 PM UTC 24 |
33535268 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.1299459667 |
|
|
Sep 04 12:41:25 PM UTC 24 |
Sep 04 12:41:29 PM UTC 24 |
14868103 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.398553370 |
|
|
Sep 04 12:41:20 PM UTC 24 |
Sep 04 12:41:30 PM UTC 24 |
11437150 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.3554762300 |
|
|
Sep 04 12:41:22 PM UTC 24 |
Sep 04 12:41:31 PM UTC 24 |
39211649 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2669527791 |
|
|
Sep 04 12:41:25 PM UTC 24 |
Sep 04 12:41:31 PM UTC 24 |
466681099 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2647555932 |
|
|
Sep 04 12:41:19 PM UTC 24 |
Sep 04 12:41:31 PM UTC 24 |
14619519 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.701510721 |
|
|
Sep 04 12:41:19 PM UTC 24 |
Sep 04 12:41:31 PM UTC 24 |
51301448 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3612862891 |
|
|
Sep 04 12:41:24 PM UTC 24 |
Sep 04 12:41:31 PM UTC 24 |
475932700 ps |