| T634 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_all.3662233614 |
|
|
Sep 11 05:14:22 PM UTC 24 |
Sep 11 05:14:56 PM UTC 24 |
13895179420 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.846364248 |
|
|
Sep 11 05:14:53 PM UTC 24 |
Sep 11 05:14:59 PM UTC 24 |
119920936 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_rw.3120035502 |
|
|
Sep 11 05:14:53 PM UTC 24 |
Sep 11 05:14:59 PM UTC 24 |
133066258 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_intercept.205512131 |
|
|
Sep 11 05:14:53 PM UTC 24 |
Sep 11 05:15:01 PM UTC 24 |
156566072 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.2636039348 |
|
|
Sep 11 05:14:59 PM UTC 24 |
Sep 11 05:15:02 PM UTC 24 |
23577812 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.1632309346 |
|
|
Sep 11 05:13:56 PM UTC 24 |
Sep 11 05:15:02 PM UTC 24 |
24816870118 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_upload.3482958033 |
|
|
Sep 11 05:14:40 PM UTC 24 |
Sep 11 05:15:03 PM UTC 24 |
3104932284 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_alert_test.2020951839 |
|
|
Sep 11 05:15:03 PM UTC 24 |
Sep 11 05:15:05 PM UTC 24 |
12541771 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.2484773851 |
|
|
Sep 11 05:13:00 PM UTC 24 |
Sep 11 05:15:05 PM UTC 24 |
15281331032 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_csb_read.687498010 |
|
|
Sep 11 05:15:04 PM UTC 24 |
Sep 11 05:15:06 PM UTC 24 |
35160577 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.1391333856 |
|
|
Sep 11 05:14:56 PM UTC 24 |
Sep 11 05:15:07 PM UTC 24 |
580872398 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_all.2430188256 |
|
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Sep 11 05:14:51 PM UTC 24 |
Sep 11 05:15:08 PM UTC 24 |
11132013726 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_upload.2013010572 |
|
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Sep 11 05:14:54 PM UTC 24 |
Sep 11 05:15:08 PM UTC 24 |
12735615051 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_cfg_cmd.1067150527 |
|
|
Sep 11 05:14:54 PM UTC 24 |
Sep 11 05:15:09 PM UTC 24 |
868724967 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.100126503 |
|
|
Sep 11 05:15:07 PM UTC 24 |
Sep 11 05:15:09 PM UTC 24 |
193096970 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_rw.2567290353 |
|
|
Sep 11 05:15:08 PM UTC 24 |
Sep 11 05:15:11 PM UTC 24 |
16770624 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.2641664680 |
|
|
Sep 11 05:14:45 PM UTC 24 |
Sep 11 05:15:11 PM UTC 24 |
8409422309 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.3491146372 |
|
|
Sep 11 05:15:06 PM UTC 24 |
Sep 11 05:15:12 PM UTC 24 |
1479596578 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_mailbox.3522413535 |
|
|
Sep 11 05:14:37 PM UTC 24 |
Sep 11 05:15:14 PM UTC 24 |
9700221328 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_upload.291032235 |
|
|
Sep 11 05:15:11 PM UTC 24 |
Sep 11 05:15:16 PM UTC 24 |
41913880 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.2241658047 |
|
|
Sep 11 05:14:53 PM UTC 24 |
Sep 11 05:15:18 PM UTC 24 |
3181248041 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode.3713390967 |
|
|
Sep 11 05:15:13 PM UTC 24 |
Sep 11 05:15:18 PM UTC 24 |
398143698 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.3564510631 |
|
|
Sep 11 05:15:09 PM UTC 24 |
Sep 11 05:15:20 PM UTC 24 |
279403874 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_cfg_cmd.1647171418 |
|
|
Sep 11 05:15:13 PM UTC 24 |
Sep 11 05:15:23 PM UTC 24 |
2199636310 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_mailbox.809921243 |
|
|
Sep 11 05:14:14 PM UTC 24 |
Sep 11 05:15:25 PM UTC 24 |
7745141337 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_alert_test.3271843454 |
|
|
Sep 11 05:15:25 PM UTC 24 |
Sep 11 05:15:27 PM UTC 24 |
41670561 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.2890348251 |
|
|
Sep 11 05:14:47 PM UTC 24 |
Sep 11 05:15:27 PM UTC 24 |
10483023162 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.1804714204 |
|
|
Sep 11 05:12:36 PM UTC 24 |
Sep 11 05:15:30 PM UTC 24 |
42763381479 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_csb_read.4035041219 |
|
|
Sep 11 05:15:28 PM UTC 24 |
Sep 11 05:15:31 PM UTC 24 |
52529307 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.4240936620 |
|
|
Sep 11 05:15:21 PM UTC 24 |
Sep 11 05:15:32 PM UTC 24 |
919904365 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_intercept.1390386399 |
|
|
Sep 11 05:15:10 PM UTC 24 |
Sep 11 05:15:32 PM UTC 24 |
1258409334 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.1133177259 |
|
|
Sep 11 05:15:17 PM UTC 24 |
Sep 11 05:15:33 PM UTC 24 |
5089981061 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.3402630649 |
|
|
Sep 11 05:15:31 PM UTC 24 |
Sep 11 05:15:34 PM UTC 24 |
118434515 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.1899477614 |
|
|
Sep 11 05:10:53 PM UTC 24 |
Sep 11 05:15:34 PM UTC 24 |
57138093262 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.4195694884 |
|
|
Sep 11 05:14:55 PM UTC 24 |
Sep 11 05:15:35 PM UTC 24 |
5470742352 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_rw.450082115 |
|
|
Sep 11 05:15:33 PM UTC 24 |
Sep 11 05:15:35 PM UTC 24 |
210690191 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.2953188162 |
|
|
Sep 11 05:11:09 PM UTC 24 |
Sep 11 05:15:39 PM UTC 24 |
33779858758 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.1677716237 |
|
|
Sep 11 05:15:34 PM UTC 24 |
Sep 11 05:15:39 PM UTC 24 |
236022407 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_upload.2986496203 |
|
|
Sep 11 05:15:36 PM UTC 24 |
Sep 11 05:15:40 PM UTC 24 |
37433749 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_all.614556584 |
|
|
Sep 11 05:15:06 PM UTC 24 |
Sep 11 05:15:41 PM UTC 24 |
4399311855 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.1472394052 |
|
|
Sep 11 05:12:58 PM UTC 24 |
Sep 11 05:15:41 PM UTC 24 |
70292364461 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_cfg_cmd.1796745878 |
|
|
Sep 11 05:15:36 PM UTC 24 |
Sep 11 05:15:42 PM UTC 24 |
195819932 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.1447562177 |
|
|
Sep 11 05:15:33 PM UTC 24 |
Sep 11 05:15:43 PM UTC 24 |
1260427857 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_all.1650802044 |
|
|
Sep 11 05:15:31 PM UTC 24 |
Sep 11 05:15:44 PM UTC 24 |
6721126375 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.634004308 |
|
|
Sep 11 05:15:41 PM UTC 24 |
Sep 11 05:15:44 PM UTC 24 |
111373167 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.2408275426 |
|
|
Sep 11 05:15:09 PM UTC 24 |
Sep 11 05:15:44 PM UTC 24 |
7431821373 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_alert_test.1536650370 |
|
|
Sep 11 05:15:45 PM UTC 24 |
Sep 11 05:15:47 PM UTC 24 |
23418267 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_csb_read.2307282089 |
|
|
Sep 11 05:15:45 PM UTC 24 |
Sep 11 05:15:47 PM UTC 24 |
28376020 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.4141481794 |
|
|
Sep 11 05:15:28 PM UTC 24 |
Sep 11 05:15:48 PM UTC 24 |
74285663361 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode.3782853181 |
|
|
Sep 11 05:15:40 PM UTC 24 |
Sep 11 05:15:49 PM UTC 24 |
875086754 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.2789387236 |
|
|
Sep 11 05:15:48 PM UTC 24 |
Sep 11 05:15:50 PM UTC 24 |
39406768 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.3667596028 |
|
|
Sep 11 05:15:50 PM UTC 24 |
Sep 11 05:15:54 PM UTC 24 |
31447286 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.1572573416 |
|
|
Sep 11 05:15:45 PM UTC 24 |
Sep 11 05:15:54 PM UTC 24 |
4034999223 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.2458672198 |
|
|
Sep 11 05:15:00 PM UTC 24 |
Sep 11 05:15:54 PM UTC 24 |
5322582628 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.1207717331 |
|
|
Sep 11 05:15:50 PM UTC 24 |
Sep 11 05:15:55 PM UTC 24 |
196355367 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_rw.2993595812 |
|
|
Sep 11 05:15:50 PM UTC 24 |
Sep 11 05:15:55 PM UTC 24 |
297888698 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_intercept.2973242116 |
|
|
Sep 11 05:15:51 PM UTC 24 |
Sep 11 05:15:55 PM UTC 24 |
230641432 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.4078453120 |
|
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Sep 11 05:15:41 PM UTC 24 |
Sep 11 05:15:59 PM UTC 24 |
1117298571 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_intercept.4185085253 |
|
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Sep 11 05:15:35 PM UTC 24 |
Sep 11 05:15:59 PM UTC 24 |
4723423050 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_all.3962382737 |
|
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Sep 11 05:15:48 PM UTC 24 |
Sep 11 05:16:02 PM UTC 24 |
5272603938 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode.3940687972 |
|
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Sep 11 05:14:54 PM UTC 24 |
Sep 11 05:16:03 PM UTC 24 |
3541416976 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.1887480972 |
|
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Sep 11 05:15:56 PM UTC 24 |
Sep 11 05:16:03 PM UTC 24 |
543272275 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_mailbox.1970312557 |
|
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Sep 11 05:15:35 PM UTC 24 |
Sep 11 05:16:06 PM UTC 24 |
8426615536 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_all.3301130447 |
|
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Sep 11 05:15:59 PM UTC 24 |
Sep 11 05:16:06 PM UTC 24 |
287407912 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_stress_all.4191501727 |
|
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Sep 11 05:11:46 PM UTC 24 |
Sep 11 05:16:06 PM UTC 24 |
13221938541 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_alert_test.3374673457 |
|
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Sep 11 05:16:05 PM UTC 24 |
Sep 11 05:16:08 PM UTC 24 |
14138409 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_csb_read.3899215742 |
|
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Sep 11 05:16:06 PM UTC 24 |
Sep 11 05:16:08 PM UTC 24 |
52080563 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.4098431845 |
|
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Sep 11 05:16:07 PM UTC 24 |
Sep 11 05:16:09 PM UTC 24 |
173523844 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.225508001 |
|
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Sep 11 05:13:31 PM UTC 24 |
Sep 11 05:16:10 PM UTC 24 |
10724447401 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_upload.420565582 |
|
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Sep 11 05:15:55 PM UTC 24 |
Sep 11 05:16:10 PM UTC 24 |
2407024356 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.3208749974 |
|
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Sep 11 05:15:40 PM UTC 24 |
Sep 11 05:16:12 PM UTC 24 |
2115126385 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_rw.4042157517 |
|
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Sep 11 05:16:09 PM UTC 24 |
Sep 11 05:16:12 PM UTC 24 |
185379940 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.239905550 |
|
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Sep 11 05:12:37 PM UTC 24 |
Sep 11 05:16:12 PM UTC 24 |
46406770192 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.1879929122 |
|
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Sep 11 05:15:42 PM UTC 24 |
Sep 11 05:16:13 PM UTC 24 |
7111613034 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_cfg_cmd.4049926205 |
|
|
Sep 11 05:16:12 PM UTC 24 |
Sep 11 05:16:16 PM UTC 24 |
36353246 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.2393576435 |
|
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Sep 11 05:16:10 PM UTC 24 |
Sep 11 05:16:19 PM UTC 24 |
244178127 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_all.3263276065 |
|
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Sep 11 05:16:07 PM UTC 24 |
Sep 11 05:16:22 PM UTC 24 |
1845236515 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_mailbox.372506588 |
|
|
Sep 11 05:16:11 PM UTC 24 |
Sep 11 05:16:22 PM UTC 24 |
376023953 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_cfg_cmd.1629871480 |
|
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Sep 11 05:15:56 PM UTC 24 |
Sep 11 05:16:22 PM UTC 24 |
2186523541 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_intercept.2337089577 |
|
|
Sep 11 05:16:11 PM UTC 24 |
Sep 11 05:16:23 PM UTC 24 |
2750357883 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_all.213408872 |
|
|
Sep 11 05:16:20 PM UTC 24 |
Sep 11 05:16:23 PM UTC 24 |
60221174 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_all.4123070672 |
|
|
Sep 11 05:10:49 PM UTC 24 |
Sep 11 05:16:23 PM UTC 24 |
91228652440 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_alert_test.3936270609 |
|
|
Sep 11 05:16:24 PM UTC 24 |
Sep 11 05:16:26 PM UTC 24 |
10791135 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_csb_read.3677623590 |
|
|
Sep 11 05:16:24 PM UTC 24 |
Sep 11 05:16:26 PM UTC 24 |
19970015 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.167375590 |
|
|
Sep 11 05:16:24 PM UTC 24 |
Sep 11 05:16:26 PM UTC 24 |
53926098 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode.1117535820 |
|
|
Sep 11 05:15:56 PM UTC 24 |
Sep 11 05:16:28 PM UTC 24 |
4571162731 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_mailbox.1735596464 |
|
|
Sep 11 05:15:10 PM UTC 24 |
Sep 11 05:16:29 PM UTC 24 |
7684071053 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.3782475980 |
|
|
Sep 11 05:16:27 PM UTC 24 |
Sep 11 05:16:29 PM UTC 24 |
13471203 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_rw.1256629190 |
|
|
Sep 11 05:16:27 PM UTC 24 |
Sep 11 05:16:30 PM UTC 24 |
100289068 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.10875326 |
|
|
Sep 11 05:16:07 PM UTC 24 |
Sep 11 05:16:31 PM UTC 24 |
53067339030 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.432095024 |
|
|
Sep 11 05:16:17 PM UTC 24 |
Sep 11 05:16:32 PM UTC 24 |
4442882863 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.1203091654 |
|
|
Sep 11 05:15:15 PM UTC 24 |
Sep 11 05:16:32 PM UTC 24 |
10424286997 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.74560261 |
|
|
Sep 11 05:15:19 PM UTC 24 |
Sep 11 05:16:32 PM UTC 24 |
8211538340 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.360438070 |
|
|
Sep 11 05:16:24 PM UTC 24 |
Sep 11 05:16:33 PM UTC 24 |
4391694293 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.3750974587 |
|
|
Sep 11 05:14:00 PM UTC 24 |
Sep 11 05:16:35 PM UTC 24 |
34453306157 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.3023821543 |
|
|
Sep 11 05:16:23 PM UTC 24 |
Sep 11 05:16:37 PM UTC 24 |
3015601398 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_mailbox.1293591576 |
|
|
Sep 11 05:16:32 PM UTC 24 |
Sep 11 05:16:38 PM UTC 24 |
474640615 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_cfg_cmd.2629384224 |
|
|
Sep 11 05:16:34 PM UTC 24 |
Sep 11 05:16:39 PM UTC 24 |
51270948 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.1505891238 |
|
|
Sep 11 05:16:34 PM UTC 24 |
Sep 11 05:16:39 PM UTC 24 |
258820386 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.1736632552 |
|
|
Sep 11 05:10:52 PM UTC 24 |
Sep 11 05:16:40 PM UTC 24 |
48514408199 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.2503948281 |
|
|
Sep 11 05:16:09 PM UTC 24 |
Sep 11 05:16:41 PM UTC 24 |
9635294042 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_alert_test.3163111516 |
|
|
Sep 11 05:16:39 PM UTC 24 |
Sep 11 05:16:42 PM UTC 24 |
23572562 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.2422068072 |
|
|
Sep 11 05:13:56 PM UTC 24 |
Sep 11 05:16:42 PM UTC 24 |
40272198313 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_all.50551874 |
|
|
Sep 11 05:16:27 PM UTC 24 |
Sep 11 05:16:43 PM UTC 24 |
5625553167 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_csb_read.3686457732 |
|
|
Sep 11 05:16:41 PM UTC 24 |
Sep 11 05:16:43 PM UTC 24 |
60195270 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_upload.3618353204 |
|
|
Sep 11 05:16:32 PM UTC 24 |
Sep 11 05:16:44 PM UTC 24 |
2493797356 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.806261465 |
|
|
Sep 11 05:16:43 PM UTC 24 |
Sep 11 05:16:45 PM UTC 24 |
82963002 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.3060548437 |
|
|
Sep 11 05:16:29 PM UTC 24 |
Sep 11 05:16:46 PM UTC 24 |
3573082152 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.1843151868 |
|
|
Sep 11 05:11:45 PM UTC 24 |
Sep 11 05:16:46 PM UTC 24 |
200075133845 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.4178189372 |
|
|
Sep 11 05:16:00 PM UTC 24 |
Sep 11 05:16:46 PM UTC 24 |
1744331306 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.1101747910 |
|
|
Sep 11 05:14:44 PM UTC 24 |
Sep 11 05:16:47 PM UTC 24 |
14118696409 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.1533464384 |
|
|
Sep 11 05:16:41 PM UTC 24 |
Sep 11 05:16:47 PM UTC 24 |
2503406496 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.118715335 |
|
|
Sep 11 05:16:44 PM UTC 24 |
Sep 11 05:16:47 PM UTC 24 |
84765754 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_intercept.1993423255 |
|
|
Sep 11 05:16:30 PM UTC 24 |
Sep 11 05:16:47 PM UTC 24 |
5475015762 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.4239646381 |
|
|
Sep 11 05:16:29 PM UTC 24 |
Sep 11 05:16:48 PM UTC 24 |
1373293668 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.3122035611 |
|
|
Sep 11 05:16:44 PM UTC 24 |
Sep 11 05:16:48 PM UTC 24 |
281841381 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_rw.2537972372 |
|
|
Sep 11 05:16:44 PM UTC 24 |
Sep 11 05:16:48 PM UTC 24 |
186333189 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode.1059520946 |
|
|
Sep 11 05:16:34 PM UTC 24 |
Sep 11 05:16:49 PM UTC 24 |
631770596 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.2915242346 |
|
|
Sep 11 05:16:49 PM UTC 24 |
Sep 11 05:16:51 PM UTC 24 |
72215144 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_alert_test.2076277980 |
|
|
Sep 11 05:16:49 PM UTC 24 |
Sep 11 05:16:51 PM UTC 24 |
13442909 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_cfg_cmd.3426210209 |
|
|
Sep 11 05:16:47 PM UTC 24 |
Sep 11 05:16:52 PM UTC 24 |
156884932 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_csb_read.3390038270 |
|
|
Sep 11 05:16:50 PM UTC 24 |
Sep 11 05:16:52 PM UTC 24 |
114517985 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.3932382123 |
|
|
Sep 11 05:16:49 PM UTC 24 |
Sep 11 05:16:54 PM UTC 24 |
390340982 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.538124971 |
|
|
Sep 11 05:16:53 PM UTC 24 |
Sep 11 05:16:55 PM UTC 24 |
72896140 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_all.1144739621 |
|
|
Sep 11 05:16:42 PM UTC 24 |
Sep 11 05:16:55 PM UTC 24 |
859804899 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_rw.932685605 |
|
|
Sep 11 05:16:53 PM UTC 24 |
Sep 11 05:16:56 PM UTC 24 |
74228688 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_mailbox.1160680301 |
|
|
Sep 11 05:16:46 PM UTC 24 |
Sep 11 05:16:57 PM UTC 24 |
872348313 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.2172650996 |
|
|
Sep 11 05:16:52 PM UTC 24 |
Sep 11 05:16:58 PM UTC 24 |
1965313861 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.1858040306 |
|
|
Sep 11 05:16:49 PM UTC 24 |
Sep 11 05:16:58 PM UTC 24 |
1429723053 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_intercept.1741562361 |
|
|
Sep 11 05:16:45 PM UTC 24 |
Sep 11 05:16:59 PM UTC 24 |
3853331750 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.1404969632 |
|
|
Sep 11 05:16:56 PM UTC 24 |
Sep 11 05:17:00 PM UTC 24 |
28426750 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_mailbox.2535950927 |
|
|
Sep 11 05:14:53 PM UTC 24 |
Sep 11 05:17:01 PM UTC 24 |
12397478249 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_intercept.2288506670 |
|
|
Sep 11 05:16:56 PM UTC 24 |
Sep 11 05:17:03 PM UTC 24 |
465630059 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode.2404306458 |
|
|
Sep 11 05:17:00 PM UTC 24 |
Sep 11 05:17:04 PM UTC 24 |
40821408 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_all.4148360648 |
|
|
Sep 11 05:16:52 PM UTC 24 |
Sep 11 05:17:04 PM UTC 24 |
8356557983 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.1928582118 |
|
|
Sep 11 05:16:03 PM UTC 24 |
Sep 11 05:17:04 PM UTC 24 |
28980129188 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_cfg_cmd.3835203630 |
|
|
Sep 11 05:16:59 PM UTC 24 |
Sep 11 05:17:06 PM UTC 24 |
272254917 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_mailbox.1868852788 |
|
|
Sep 11 05:16:56 PM UTC 24 |
Sep 11 05:17:07 PM UTC 24 |
2195131744 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.1760104673 |
|
|
Sep 11 05:16:55 PM UTC 24 |
Sep 11 05:17:07 PM UTC 24 |
1042451698 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_alert_test.3069806646 |
|
|
Sep 11 05:17:05 PM UTC 24 |
Sep 11 05:17:07 PM UTC 24 |
32469008 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_upload.2596189162 |
|
|
Sep 11 05:16:12 PM UTC 24 |
Sep 11 05:17:08 PM UTC 24 |
64911764871 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_csb_read.2028361559 |
|
|
Sep 11 05:17:07 PM UTC 24 |
Sep 11 05:17:09 PM UTC 24 |
65387471 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_all.55590106 |
|
|
Sep 11 05:17:07 PM UTC 24 |
Sep 11 05:17:10 PM UTC 24 |
26649645 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.2802563319 |
|
|
Sep 11 05:17:08 PM UTC 24 |
Sep 11 05:17:11 PM UTC 24 |
38660515 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_upload.2088915582 |
|
|
Sep 11 05:16:47 PM UTC 24 |
Sep 11 05:17:12 PM UTC 24 |
7312540170 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.1256765128 |
|
|
Sep 11 05:17:07 PM UTC 24 |
Sep 11 05:17:14 PM UTC 24 |
524738768 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.1975210986 |
|
|
Sep 11 05:15:42 PM UTC 24 |
Sep 11 05:17:15 PM UTC 24 |
6111222723 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.2307290599 |
|
|
Sep 11 05:17:11 PM UTC 24 |
Sep 11 05:17:16 PM UTC 24 |
623516107 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.2865220256 |
|
|
Sep 11 05:14:46 PM UTC 24 |
Sep 11 05:17:18 PM UTC 24 |
38730433951 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.3626311959 |
|
|
Sep 11 05:17:01 PM UTC 24 |
Sep 11 05:17:19 PM UTC 24 |
2654075993 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_upload.2637031253 |
|
|
Sep 11 05:17:15 PM UTC 24 |
Sep 11 05:17:19 PM UTC 24 |
172315491 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_intercept.852794347 |
|
|
Sep 11 05:17:12 PM UTC 24 |
Sep 11 05:17:20 PM UTC 24 |
420130236 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode.2175423618 |
|
|
Sep 11 05:16:47 PM UTC 24 |
Sep 11 05:17:20 PM UTC 24 |
8801213808 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_cfg_cmd.389424860 |
|
|
Sep 11 05:17:16 PM UTC 24 |
Sep 11 05:17:21 PM UTC 24 |
64533651 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_rw.2512650814 |
|
|
Sep 11 05:17:10 PM UTC 24 |
Sep 11 05:17:25 PM UTC 24 |
1215373720 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.447967809 |
|
|
Sep 11 05:15:24 PM UTC 24 |
Sep 11 05:17:25 PM UTC 24 |
21710592969 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_upload.2315736592 |
|
|
Sep 11 05:16:57 PM UTC 24 |
Sep 11 05:17:26 PM UTC 24 |
71447568639 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_stress_all.3083561577 |
|
|
Sep 11 05:14:03 PM UTC 24 |
Sep 11 05:17:28 PM UTC 24 |
15132860566 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_alert_test.4064950900 |
|
|
Sep 11 05:17:26 PM UTC 24 |
Sep 11 05:17:28 PM UTC 24 |
53875060 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_csb_read.2929022993 |
|
|
Sep 11 05:17:26 PM UTC 24 |
Sep 11 05:17:28 PM UTC 24 |
43611937 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.2397412405 |
|
|
Sep 11 05:17:11 PM UTC 24 |
Sep 11 05:17:29 PM UTC 24 |
17870309219 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.1695166423 |
|
|
Sep 11 05:17:27 PM UTC 24 |
Sep 11 05:17:31 PM UTC 24 |
651778683 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_rw.3803296821 |
|
|
Sep 11 05:17:29 PM UTC 24 |
Sep 11 05:17:31 PM UTC 24 |
11551299 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.771336591 |
|
|
Sep 11 05:17:29 PM UTC 24 |
Sep 11 05:17:31 PM UTC 24 |
26533428 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.3586009457 |
|
|
Sep 11 05:17:20 PM UTC 24 |
Sep 11 05:17:33 PM UTC 24 |
868976140 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_all.2167175421 |
|
|
Sep 11 05:17:29 PM UTC 24 |
Sep 11 05:17:37 PM UTC 24 |
492272544 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.2458924599 |
|
|
Sep 11 05:17:32 PM UTC 24 |
Sep 11 05:17:37 PM UTC 24 |
48034375 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.2543015043 |
|
|
Sep 11 05:16:47 PM UTC 24 |
Sep 11 05:17:37 PM UTC 24 |
6766796255 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.2892086054 |
|
|
Sep 11 05:12:20 PM UTC 24 |
Sep 11 05:17:38 PM UTC 24 |
67682797145 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_all.2945292980 |
|
|
Sep 11 05:16:49 PM UTC 24 |
Sep 11 05:17:39 PM UTC 24 |
14265377990 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_intercept.3216214441 |
|
|
Sep 11 05:17:32 PM UTC 24 |
Sep 11 05:17:39 PM UTC 24 |
372755575 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.3908666156 |
|
|
Sep 11 05:14:23 PM UTC 24 |
Sep 11 05:17:39 PM UTC 24 |
36222789435 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode.1622464360 |
|
|
Sep 11 05:16:13 PM UTC 24 |
Sep 11 05:17:40 PM UTC 24 |
48512206437 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.3125329443 |
|
|
Sep 11 05:17:01 PM UTC 24 |
Sep 11 05:17:45 PM UTC 24 |
1328254218 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.3481867093 |
|
|
Sep 11 05:17:20 PM UTC 24 |
Sep 11 05:17:45 PM UTC 24 |
2447817298 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_upload.767967255 |
|
|
Sep 11 05:17:34 PM UTC 24 |
Sep 11 05:17:46 PM UTC 24 |
5559512380 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.1397070669 |
|
|
Sep 11 05:17:40 PM UTC 24 |
Sep 11 05:17:46 PM UTC 24 |
161042568 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_alert_test.3886608319 |
|
|
Sep 11 05:17:46 PM UTC 24 |
Sep 11 05:17:48 PM UTC 24 |
24219093 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_csb_read.4292212233 |
|
|
Sep 11 05:17:46 PM UTC 24 |
Sep 11 05:17:49 PM UTC 24 |
59274566 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.2244208424 |
|
|
Sep 11 05:17:49 PM UTC 24 |
Sep 11 05:17:51 PM UTC 24 |
31820031 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_mailbox.3903903789 |
|
|
Sep 11 05:17:13 PM UTC 24 |
Sep 11 05:17:52 PM UTC 24 |
14105534199 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_rw.4000304664 |
|
|
Sep 11 05:17:49 PM UTC 24 |
Sep 11 05:17:52 PM UTC 24 |
41214923 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.2201601887 |
|
|
Sep 11 05:17:47 PM UTC 24 |
Sep 11 05:17:52 PM UTC 24 |
233742021 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.4108456284 |
|
|
Sep 11 05:16:37 PM UTC 24 |
Sep 11 05:17:52 PM UTC 24 |
24251632186 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_all.3364500785 |
|
|
Sep 11 05:17:47 PM UTC 24 |
Sep 11 05:17:57 PM UTC 24 |
6568073964 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode.2413942351 |
|
|
Sep 11 05:17:37 PM UTC 24 |
Sep 11 05:17:58 PM UTC 24 |
1255319092 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_mailbox.211290943 |
|
|
Sep 11 05:15:55 PM UTC 24 |
Sep 11 05:17:58 PM UTC 24 |
52055744503 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_intercept.450717403 |
|
|
Sep 11 05:17:52 PM UTC 24 |
Sep 11 05:17:58 PM UTC 24 |
317145174 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_mailbox.2072780670 |
|
|
Sep 11 05:17:52 PM UTC 24 |
Sep 11 05:17:59 PM UTC 24 |
1132950377 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_cfg_cmd.4247597537 |
|
|
Sep 11 05:17:37 PM UTC 24 |
Sep 11 05:17:59 PM UTC 24 |
12724245754 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.2240599777 |
|
|
Sep 11 05:17:30 PM UTC 24 |
Sep 11 05:18:03 PM UTC 24 |
5093101132 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.2032755466 |
|
|
Sep 11 05:17:52 PM UTC 24 |
Sep 11 05:18:04 PM UTC 24 |
1409590833 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.681468396 |
|
|
Sep 11 05:17:59 PM UTC 24 |
Sep 11 05:18:07 PM UTC 24 |
613615972 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.673576719 |
|
|
Sep 11 05:17:52 PM UTC 24 |
Sep 11 05:18:08 PM UTC 24 |
1987200810 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_stress_all.1290932240 |
|
|
Sep 11 05:13:02 PM UTC 24 |
Sep 11 05:18:10 PM UTC 24 |
68779487509 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_alert_test.4128642887 |
|
|
Sep 11 05:18:08 PM UTC 24 |
Sep 11 05:18:10 PM UTC 24 |
21582550 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.1214527854 |
|
|
Sep 11 05:17:21 PM UTC 24 |
Sep 11 05:18:11 PM UTC 24 |
5354951956 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_csb_read.2207739739 |
|
|
Sep 11 05:18:09 PM UTC 24 |
Sep 11 05:18:11 PM UTC 24 |
30395344 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.2355955021 |
|
|
Sep 11 05:17:40 PM UTC 24 |
Sep 11 05:18:12 PM UTC 24 |
18373679707 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_mailbox.3980292440 |
|
|
Sep 11 05:17:32 PM UTC 24 |
Sep 11 05:18:13 PM UTC 24 |
3434929528 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.3532220059 |
|
|
Sep 11 05:18:13 PM UTC 24 |
Sep 11 05:18:15 PM UTC 24 |
40180431 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_rw.3472199773 |
|
|
Sep 11 05:18:13 PM UTC 24 |
Sep 11 05:18:15 PM UTC 24 |
83142698 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.2212182940 |
|
|
Sep 11 05:10:25 PM UTC 24 |
Sep 11 05:18:15 PM UTC 24 |
58728734643 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.3657076097 |
|
|
Sep 11 05:18:13 PM UTC 24 |
Sep 11 05:18:17 PM UTC 24 |
675841228 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode.816056542 |
|
|
Sep 11 05:17:59 PM UTC 24 |
Sep 11 05:18:17 PM UTC 24 |
1285783490 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_upload.2063186231 |
|
|
Sep 11 05:17:54 PM UTC 24 |
Sep 11 05:18:18 PM UTC 24 |
3253451241 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.2171848709 |
|
|
Sep 11 05:13:45 PM UTC 24 |
Sep 11 05:18:20 PM UTC 24 |
86821326624 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_all.197789935 |
|
|
Sep 11 05:17:02 PM UTC 24 |
Sep 11 05:18:22 PM UTC 24 |
60738981898 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_all.1121057433 |
|
|
Sep 11 05:18:11 PM UTC 24 |
Sep 11 05:18:22 PM UTC 24 |
1186956505 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.3317371050 |
|
|
Sep 11 05:18:10 PM UTC 24 |
Sep 11 05:18:23 PM UTC 24 |
18476990090 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_cfg_cmd.2731570481 |
|
|
Sep 11 05:18:18 PM UTC 24 |
Sep 11 05:18:25 PM UTC 24 |
222324523 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_cfg_cmd.2894666509 |
|
|
Sep 11 05:17:58 PM UTC 24 |
Sep 11 05:18:26 PM UTC 24 |
1906067948 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_intercept.2070768843 |
|
|
Sep 11 05:18:16 PM UTC 24 |
Sep 11 05:18:28 PM UTC 24 |
4595540687 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.1655435471 |
|
|
Sep 11 05:18:00 PM UTC 24 |
Sep 11 05:18:28 PM UTC 24 |
3439709981 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.2630266167 |
|
|
Sep 11 05:16:23 PM UTC 24 |
Sep 11 05:18:29 PM UTC 24 |
6105236136 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_upload.1000351198 |
|
|
Sep 11 05:18:16 PM UTC 24 |
Sep 11 05:18:30 PM UTC 24 |
427228823 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_alert_test.223473166 |
|
|
Sep 11 05:18:28 PM UTC 24 |
Sep 11 05:18:30 PM UTC 24 |
45853874 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_csb_read.1143414799 |
|
|
Sep 11 05:18:28 PM UTC 24 |
Sep 11 05:18:31 PM UTC 24 |
31941798 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.1986940511 |
|
|
Sep 11 05:18:21 PM UTC 24 |
Sep 11 05:18:32 PM UTC 24 |
1513208976 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.1092434370 |
|
|
Sep 11 05:18:28 PM UTC 24 |
Sep 11 05:18:32 PM UTC 24 |
243295602 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.2885078758 |
|
|
Sep 11 05:18:31 PM UTC 24 |
Sep 11 05:18:33 PM UTC 24 |
108106289 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.3059142065 |
|
|
Sep 11 05:11:32 PM UTC 24 |
Sep 11 05:18:33 PM UTC 24 |
163176072895 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode.367068509 |
|
|
Sep 11 05:17:16 PM UTC 24 |
Sep 11 05:18:34 PM UTC 24 |
5787891149 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_rw.1207718832 |
|
|
Sep 11 05:18:33 PM UTC 24 |
Sep 11 05:18:36 PM UTC 24 |
99201025 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.3575984201 |
|
|
Sep 11 05:18:33 PM UTC 24 |
Sep 11 05:18:37 PM UTC 24 |
77329599 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.1555017604 |
|
|
Sep 11 05:18:14 PM UTC 24 |
Sep 11 05:18:38 PM UTC 24 |
3760332904 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_all.1205994601 |
|
|
Sep 11 05:15:19 PM UTC 24 |
Sep 11 05:18:38 PM UTC 24 |
99158164819 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_cfg_cmd.2378659038 |
|
|
Sep 11 05:18:35 PM UTC 24 |
Sep 11 05:18:40 PM UTC 24 |
891928088 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.3628354968 |
|
|
Sep 11 05:18:23 PM UTC 24 |
Sep 11 05:18:43 PM UTC 24 |
6045717390 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.1944157863 |
|
|
Sep 11 05:18:37 PM UTC 24 |
Sep 11 05:18:45 PM UTC 24 |
990094578 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_intercept.1919911908 |
|
|
Sep 11 05:18:33 PM UTC 24 |
Sep 11 05:18:45 PM UTC 24 |
754227346 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.3016924963 |
|
|
Sep 11 05:18:39 PM UTC 24 |
Sep 11 05:18:45 PM UTC 24 |
332058754 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.1750129578 |
|
|
Sep 11 05:15:02 PM UTC 24 |
Sep 11 05:18:47 PM UTC 24 |
40556102965 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_alert_test.1655709968 |
|
|
Sep 11 05:18:46 PM UTC 24 |
Sep 11 05:18:48 PM UTC 24 |
14121201 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.541016359 |
|
|
Sep 11 05:18:46 PM UTC 24 |
Sep 11 05:18:48 PM UTC 24 |
460090357 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.3580613727 |
|
|
Sep 11 05:18:33 PM UTC 24 |
Sep 11 05:18:49 PM UTC 24 |
13895248728 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_csb_read.816321250 |
|
|
Sep 11 05:18:48 PM UTC 24 |
Sep 11 05:18:50 PM UTC 24 |
80634388 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.3453840132 |
|
|
Sep 11 05:18:19 PM UTC 24 |
Sep 11 05:18:51 PM UTC 24 |
8406999220 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.3523570041 |
|
|
Sep 11 05:18:50 PM UTC 24 |
Sep 11 05:18:52 PM UTC 24 |
375352407 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_rw.2835519677 |
|
|
Sep 11 05:18:50 PM UTC 24 |
Sep 11 05:18:52 PM UTC 24 |
21378192 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.1722566027 |
|
|
Sep 11 05:18:31 PM UTC 24 |
Sep 11 05:18:53 PM UTC 24 |
18071253425 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.704888857 |
|
|
Sep 11 05:12:16 PM UTC 24 |
Sep 11 05:18:53 PM UTC 24 |
39068437386 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.1717326166 |
|
|
Sep 11 05:16:36 PM UTC 24 |
Sep 11 05:18:55 PM UTC 24 |
10462908340 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_upload.1865072233 |
|
|
Sep 11 05:18:35 PM UTC 24 |
Sep 11 05:18:57 PM UTC 24 |
667222414 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_mailbox.4234950404 |
|
|
Sep 11 05:18:35 PM UTC 24 |
Sep 11 05:18:58 PM UTC 24 |
1006107980 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.1882259368 |
|
|
Sep 11 05:18:57 PM UTC 24 |
Sep 11 05:19:03 PM UTC 24 |
184609307 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.2553758133 |
|
|
Sep 11 05:18:48 PM UTC 24 |
Sep 11 05:19:04 PM UTC 24 |
14328791568 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_intercept.3420945326 |
|
|
Sep 11 05:18:54 PM UTC 24 |
Sep 11 05:19:04 PM UTC 24 |
1667592668 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.4282522334 |
|
|
Sep 11 05:17:21 PM UTC 24 |
Sep 11 05:19:07 PM UTC 24 |
10798643135 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.3565676390 |
|
|
Sep 11 05:18:44 PM UTC 24 |
Sep 11 05:19:08 PM UTC 24 |
3711200724 ps |