| T838 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.638543463 |
|
|
Sep 11 05:18:52 PM UTC 24 |
Sep 11 05:19:09 PM UTC 24 |
7453217181 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.4004568289 |
|
|
Sep 11 05:18:52 PM UTC 24 |
Sep 11 05:19:10 PM UTC 24 |
8154902664 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.3537032565 |
|
|
Sep 11 05:19:09 PM UTC 24 |
Sep 11 05:19:11 PM UTC 24 |
23485041 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.107458253 |
|
|
Sep 11 05:18:59 PM UTC 24 |
Sep 11 05:19:12 PM UTC 24 |
3014421015 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_cfg_cmd.2253946668 |
|
|
Sep 11 05:18:54 PM UTC 24 |
Sep 11 05:19:13 PM UTC 24 |
6411561220 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.1377458905 |
|
|
Sep 11 05:19:11 PM UTC 24 |
Sep 11 05:19:13 PM UTC 24 |
33794022 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.2814889356 |
|
|
Sep 11 05:18:54 PM UTC 24 |
Sep 11 05:19:14 PM UTC 24 |
2897176109 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.3587943181 |
|
|
Sep 11 05:19:13 PM UTC 24 |
Sep 11 05:19:16 PM UTC 24 |
24294903 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.902839513 |
|
|
Sep 11 05:19:13 PM UTC 24 |
Sep 11 05:19:16 PM UTC 24 |
37113598 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.3417905631 |
|
|
Sep 11 05:19:16 PM UTC 24 |
Sep 11 05:19:20 PM UTC 24 |
30333155 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.3353787841 |
|
|
Sep 11 05:19:11 PM UTC 24 |
Sep 11 05:19:22 PM UTC 24 |
3821063814 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.3634656535 |
|
|
Sep 11 05:16:39 PM UTC 24 |
Sep 11 05:19:22 PM UTC 24 |
34597825589 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode.4076478620 |
|
|
Sep 11 05:18:18 PM UTC 24 |
Sep 11 05:19:22 PM UTC 24 |
7402157018 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.4252471895 |
|
|
Sep 11 05:18:50 PM UTC 24 |
Sep 11 05:19:25 PM UTC 24 |
41813463425 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.2634936468 |
|
|
Sep 11 05:19:15 PM UTC 24 |
Sep 11 05:19:26 PM UTC 24 |
316100076 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.3994704492 |
|
|
Sep 11 05:17:05 PM UTC 24 |
Sep 11 05:19:28 PM UTC 24 |
38145148387 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.83763204 |
|
|
Sep 11 05:14:44 PM UTC 24 |
Sep 11 05:19:30 PM UTC 24 |
137187239933 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.230618735 |
|
|
Sep 11 05:19:18 PM UTC 24 |
Sep 11 05:19:31 PM UTC 24 |
3329755134 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.3220682472 |
|
|
Sep 11 05:19:18 PM UTC 24 |
Sep 11 05:19:33 PM UTC 24 |
12264291853 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.1277482505 |
|
|
Sep 11 05:18:59 PM UTC 24 |
Sep 11 05:19:34 PM UTC 24 |
4301631666 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.4154404417 |
|
|
Sep 11 05:19:33 PM UTC 24 |
Sep 11 05:19:35 PM UTC 24 |
25221341 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.2677779763 |
|
|
Sep 11 05:15:03 PM UTC 24 |
Sep 11 05:19:35 PM UTC 24 |
153465620216 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.4020145602 |
|
|
Sep 11 05:19:34 PM UTC 24 |
Sep 11 05:19:36 PM UTC 24 |
72850528 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.2734405761 |
|
|
Sep 11 05:17:03 PM UTC 24 |
Sep 11 05:19:36 PM UTC 24 |
34175029072 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.1433852952 |
|
|
Sep 11 05:19:36 PM UTC 24 |
Sep 11 05:19:38 PM UTC 24 |
362263496 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_all.1741753078 |
|
|
Sep 11 05:16:34 PM UTC 24 |
Sep 11 05:19:38 PM UTC 24 |
21937645957 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.2426447482 |
|
|
Sep 11 05:19:27 PM UTC 24 |
Sep 11 05:19:38 PM UTC 24 |
3185742658 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.851118787 |
|
|
Sep 11 05:19:23 PM UTC 24 |
Sep 11 05:19:39 PM UTC 24 |
3134595096 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.1725532730 |
|
|
Sep 11 05:19:21 PM UTC 24 |
Sep 11 05:19:42 PM UTC 24 |
5722330829 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.1271406069 |
|
|
Sep 11 05:19:37 PM UTC 24 |
Sep 11 05:19:43 PM UTC 24 |
351487672 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.663426650 |
|
|
Sep 11 05:19:23 PM UTC 24 |
Sep 11 05:19:45 PM UTC 24 |
462794934 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3159273264 |
|
|
Sep 11 05:19:42 PM UTC 24 |
Sep 11 05:19:49 PM UTC 24 |
588900068 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.1225647189 |
|
|
Sep 11 05:19:39 PM UTC 24 |
Sep 11 05:19:50 PM UTC 24 |
800901156 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.12868109 |
|
|
Sep 11 05:19:40 PM UTC 24 |
Sep 11 05:19:51 PM UTC 24 |
1682979732 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.1959689004 |
|
|
Sep 11 05:19:37 PM UTC 24 |
Sep 11 05:19:51 PM UTC 24 |
835474901 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.3131349921 |
|
|
Sep 11 05:18:04 PM UTC 24 |
Sep 11 05:19:53 PM UTC 24 |
11872256770 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.1817546561 |
|
|
Sep 11 05:19:43 PM UTC 24 |
Sep 11 05:19:54 PM UTC 24 |
318889494 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.1120433940 |
|
|
Sep 11 05:18:39 PM UTC 24 |
Sep 11 05:19:55 PM UTC 24 |
19566827969 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.3766374051 |
|
|
Sep 11 05:19:36 PM UTC 24 |
Sep 11 05:19:56 PM UTC 24 |
4207906258 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.620519307 |
|
|
Sep 11 05:19:54 PM UTC 24 |
Sep 11 05:19:56 PM UTC 24 |
188590841 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2468514194 |
|
|
Sep 11 05:19:51 PM UTC 24 |
Sep 11 05:19:56 PM UTC 24 |
231118115 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.3012971150 |
|
|
Sep 11 05:19:55 PM UTC 24 |
Sep 11 05:19:57 PM UTC 24 |
14726681 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.669665363 |
|
|
Sep 11 05:19:55 PM UTC 24 |
Sep 11 05:19:57 PM UTC 24 |
98671572 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.3008453698 |
|
|
Sep 11 05:19:35 PM UTC 24 |
Sep 11 05:19:59 PM UTC 24 |
6072171467 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.1995149891 |
|
|
Sep 11 05:19:57 PM UTC 24 |
Sep 11 05:20:00 PM UTC 24 |
33727153 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.3193881041 |
|
|
Sep 11 05:19:57 PM UTC 24 |
Sep 11 05:20:00 PM UTC 24 |
96548655 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.760385521 |
|
|
Sep 11 05:19:13 PM UTC 24 |
Sep 11 05:20:02 PM UTC 24 |
39956827547 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.3066121920 |
|
|
Sep 11 05:19:56 PM UTC 24 |
Sep 11 05:20:06 PM UTC 24 |
3674300765 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_mailbox.2727953080 |
|
|
Sep 11 05:18:16 PM UTC 24 |
Sep 11 05:20:08 PM UTC 24 |
24413543317 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.3590269373 |
|
|
Sep 11 05:19:39 PM UTC 24 |
Sep 11 05:20:09 PM UTC 24 |
31186181402 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.2341916890 |
|
|
Sep 11 05:20:03 PM UTC 24 |
Sep 11 05:20:10 PM UTC 24 |
400969583 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.3211142779 |
|
|
Sep 11 05:19:39 PM UTC 24 |
Sep 11 05:20:10 PM UTC 24 |
12429024077 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.3655048656 |
|
|
Sep 11 05:19:59 PM UTC 24 |
Sep 11 05:20:11 PM UTC 24 |
2441903148 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.4159928331 |
|
|
Sep 11 05:16:34 PM UTC 24 |
Sep 11 05:20:12 PM UTC 24 |
126415818151 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.249665246 |
|
|
Sep 11 05:19:56 PM UTC 24 |
Sep 11 05:20:13 PM UTC 24 |
7044198290 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.2731715770 |
|
|
Sep 11 05:13:30 PM UTC 24 |
Sep 11 05:20:13 PM UTC 24 |
38735277547 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.232796409 |
|
|
Sep 11 05:20:01 PM UTC 24 |
Sep 11 05:20:14 PM UTC 24 |
1496243695 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.2775088534 |
|
|
Sep 11 05:20:14 PM UTC 24 |
Sep 11 05:20:16 PM UTC 24 |
11372336 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.3053518069 |
|
|
Sep 11 05:20:14 PM UTC 24 |
Sep 11 05:20:16 PM UTC 24 |
18695993 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.2224509303 |
|
|
Sep 11 05:19:59 PM UTC 24 |
Sep 11 05:20:18 PM UTC 24 |
5489047105 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.3007124770 |
|
|
Sep 11 05:20:17 PM UTC 24 |
Sep 11 05:20:19 PM UTC 24 |
65727242 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.3344705371 |
|
|
Sep 11 05:20:00 PM UTC 24 |
Sep 11 05:20:19 PM UTC 24 |
1682587883 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.3151606443 |
|
|
Sep 11 05:20:10 PM UTC 24 |
Sep 11 05:20:20 PM UTC 24 |
1624313651 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.3929577761 |
|
|
Sep 11 05:20:01 PM UTC 24 |
Sep 11 05:20:21 PM UTC 24 |
4079933196 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.2534999078 |
|
|
Sep 11 05:17:19 PM UTC 24 |
Sep 11 05:20:26 PM UTC 24 |
24591602618 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.2097107331 |
|
|
Sep 11 05:20:21 PM UTC 24 |
Sep 11 05:20:27 PM UTC 24 |
559831931 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.932323284 |
|
|
Sep 11 05:20:19 PM UTC 24 |
Sep 11 05:20:28 PM UTC 24 |
184879424 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.2587764513 |
|
|
Sep 11 05:20:11 PM UTC 24 |
Sep 11 05:20:38 PM UTC 24 |
14534499906 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.347450715 |
|
|
Sep 11 05:20:20 PM UTC 24 |
Sep 11 05:20:38 PM UTC 24 |
6912879401 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.2943603328 |
|
|
Sep 11 05:20:28 PM UTC 24 |
Sep 11 05:20:38 PM UTC 24 |
482564377 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.29457608 |
|
|
Sep 11 05:20:29 PM UTC 24 |
Sep 11 05:20:39 PM UTC 24 |
198065122 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.2899558576 |
|
|
Sep 11 05:19:05 PM UTC 24 |
Sep 11 05:20:40 PM UTC 24 |
21153399186 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.1440344868 |
|
|
Sep 11 05:18:39 PM UTC 24 |
Sep 11 05:20:43 PM UTC 24 |
10045162978 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.951221796 |
|
|
Sep 11 05:13:30 PM UTC 24 |
Sep 11 05:20:45 PM UTC 24 |
154766940929 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.234724363 |
|
|
Sep 11 05:20:39 PM UTC 24 |
Sep 11 05:20:45 PM UTC 24 |
198749796 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.621566501 |
|
|
Sep 11 05:20:07 PM UTC 24 |
Sep 11 05:20:46 PM UTC 24 |
11423759794 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.1157022588 |
|
|
Sep 11 05:20:15 PM UTC 24 |
Sep 11 05:20:48 PM UTC 24 |
28674832276 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.2784001888 |
|
|
Sep 11 05:20:46 PM UTC 24 |
Sep 11 05:20:48 PM UTC 24 |
13803237 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.2207597465 |
|
|
Sep 11 05:20:46 PM UTC 24 |
Sep 11 05:20:48 PM UTC 24 |
18044893 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.1020948567 |
|
|
Sep 11 05:20:20 PM UTC 24 |
Sep 11 05:20:50 PM UTC 24 |
26434191055 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.349751193 |
|
|
Sep 11 05:20:17 PM UTC 24 |
Sep 11 05:20:51 PM UTC 24 |
4977552547 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.1823105292 |
|
|
Sep 11 05:20:49 PM UTC 24 |
Sep 11 05:20:52 PM UTC 24 |
224050931 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.730653019 |
|
|
Sep 11 05:20:49 PM UTC 24 |
Sep 11 05:20:53 PM UTC 24 |
50395231 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.2078566438 |
|
|
Sep 11 05:19:46 PM UTC 24 |
Sep 11 05:20:53 PM UTC 24 |
16395487115 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.2519290534 |
|
|
Sep 11 05:17:41 PM UTC 24 |
Sep 11 05:20:55 PM UTC 24 |
12457579460 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_all.750506138 |
|
|
Sep 11 05:18:23 PM UTC 24 |
Sep 11 05:20:58 PM UTC 24 |
12196913857 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.3952289460 |
|
|
Sep 11 05:20:27 PM UTC 24 |
Sep 11 05:20:58 PM UTC 24 |
26645002598 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.3006689934 |
|
|
Sep 11 05:19:52 PM UTC 24 |
Sep 11 05:20:59 PM UTC 24 |
11146884796 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.3582583429 |
|
|
Sep 11 05:20:54 PM UTC 24 |
Sep 11 05:20:59 PM UTC 24 |
368008323 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.2927099866 |
|
|
Sep 11 05:20:53 PM UTC 24 |
Sep 11 05:21:00 PM UTC 24 |
131726010 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.1208665490 |
|
|
Sep 11 05:17:37 PM UTC 24 |
Sep 11 05:21:01 PM UTC 24 |
49968020718 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.1841987429 |
|
|
Sep 11 05:20:47 PM UTC 24 |
Sep 11 05:21:02 PM UTC 24 |
2114974309 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.3648388183 |
|
|
Sep 11 05:20:54 PM UTC 24 |
Sep 11 05:21:03 PM UTC 24 |
1578323418 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.3406328423 |
|
|
Sep 11 05:20:49 PM UTC 24 |
Sep 11 05:21:04 PM UTC 24 |
2274356024 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.3627314515 |
|
|
Sep 11 05:20:53 PM UTC 24 |
Sep 11 05:21:05 PM UTC 24 |
2850571570 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.648260201 |
|
|
Sep 11 05:21:04 PM UTC 24 |
Sep 11 05:21:06 PM UTC 24 |
37382726 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.882527402 |
|
|
Sep 11 05:20:11 PM UTC 24 |
Sep 11 05:21:06 PM UTC 24 |
3206951134 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.3186089483 |
|
|
Sep 11 05:21:04 PM UTC 24 |
Sep 11 05:21:06 PM UTC 24 |
343809835 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.1310101570 |
|
|
Sep 11 05:21:05 PM UTC 24 |
Sep 11 05:21:07 PM UTC 24 |
12585221 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_all.331466138 |
|
|
Sep 11 05:17:40 PM UTC 24 |
Sep 11 05:21:07 PM UTC 24 |
22362234005 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.4000908759 |
|
|
Sep 11 05:21:00 PM UTC 24 |
Sep 11 05:21:08 PM UTC 24 |
1341160130 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.777159976 |
|
|
Sep 11 05:20:56 PM UTC 24 |
Sep 11 05:21:09 PM UTC 24 |
1259233495 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.1262464657 |
|
|
Sep 11 05:21:07 PM UTC 24 |
Sep 11 05:21:09 PM UTC 24 |
216356833 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.2785039284 |
|
|
Sep 11 05:21:07 PM UTC 24 |
Sep 11 05:21:10 PM UTC 24 |
355945850 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.1755670034 |
|
|
Sep 11 05:21:08 PM UTC 24 |
Sep 11 05:21:12 PM UTC 24 |
146330101 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.3873982609 |
|
|
Sep 11 05:21:08 PM UTC 24 |
Sep 11 05:21:12 PM UTC 24 |
96225884 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.2882165057 |
|
|
Sep 11 05:18:54 PM UTC 24 |
Sep 11 05:21:13 PM UTC 24 |
215034457690 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.355108530 |
|
|
Sep 11 05:21:07 PM UTC 24 |
Sep 11 05:21:15 PM UTC 24 |
1131658739 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.204776469 |
|
|
Sep 11 05:21:10 PM UTC 24 |
Sep 11 05:21:15 PM UTC 24 |
435622758 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.4153779725 |
|
|
Sep 11 05:20:12 PM UTC 24 |
Sep 11 05:21:17 PM UTC 24 |
2960501795 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.19874299 |
|
|
Sep 11 05:21:59 PM UTC 24 |
Sep 11 05:22:05 PM UTC 24 |
842631378 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.1021611837 |
|
|
Sep 11 05:19:05 PM UTC 24 |
Sep 11 05:21:18 PM UTC 24 |
31508243979 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.1705959409 |
|
|
Sep 11 05:18:00 PM UTC 24 |
Sep 11 05:21:20 PM UTC 24 |
17802878670 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.2701616084 |
|
|
Sep 11 05:21:15 PM UTC 24 |
Sep 11 05:21:21 PM UTC 24 |
271848860 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.3992729223 |
|
|
Sep 11 05:21:21 PM UTC 24 |
Sep 11 05:21:23 PM UTC 24 |
21100904 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.2838169845 |
|
|
Sep 11 05:21:21 PM UTC 24 |
Sep 11 05:21:23 PM UTC 24 |
21578202 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.3549748760 |
|
|
Sep 11 05:20:40 PM UTC 24 |
Sep 11 05:21:24 PM UTC 24 |
9184859298 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.3215631936 |
|
|
Sep 11 05:10:28 PM UTC 24 |
Sep 11 05:21:24 PM UTC 24 |
139994113122 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.3838739417 |
|
|
Sep 11 05:21:01 PM UTC 24 |
Sep 11 05:21:24 PM UTC 24 |
5855286531 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.1165630636 |
|
|
Sep 11 05:21:24 PM UTC 24 |
Sep 11 05:21:26 PM UTC 24 |
83918163 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.3370087000 |
|
|
Sep 11 05:21:24 PM UTC 24 |
Sep 11 05:21:27 PM UTC 24 |
200214469 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.991613309 |
|
|
Sep 11 05:21:09 PM UTC 24 |
Sep 11 05:21:29 PM UTC 24 |
2001806423 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.1647059548 |
|
|
Sep 11 05:21:06 PM UTC 24 |
Sep 11 05:21:29 PM UTC 24 |
17089205913 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.3013522502 |
|
|
Sep 11 05:16:03 PM UTC 24 |
Sep 11 05:21:30 PM UTC 24 |
58558010194 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.2837955390 |
|
|
Sep 11 05:21:25 PM UTC 24 |
Sep 11 05:21:30 PM UTC 24 |
248634552 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.2145860896 |
|
|
Sep 11 05:16:13 PM UTC 24 |
Sep 11 05:21:31 PM UTC 24 |
124830068705 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.1699481286 |
|
|
Sep 11 05:21:30 PM UTC 24 |
Sep 11 05:21:34 PM UTC 24 |
50863323 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.1191129353 |
|
|
Sep 11 05:21:31 PM UTC 24 |
Sep 11 05:21:36 PM UTC 24 |
844504808 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.3420838807 |
|
|
Sep 11 05:20:22 PM UTC 24 |
Sep 11 05:21:36 PM UTC 24 |
15380505238 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.2533094090 |
|
|
Sep 11 05:21:24 PM UTC 24 |
Sep 11 05:21:38 PM UTC 24 |
26398088124 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.4072097381 |
|
|
Sep 11 05:14:24 PM UTC 24 |
Sep 11 05:21:38 PM UTC 24 |
129022760592 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.4157388706 |
|
|
Sep 11 05:21:27 PM UTC 24 |
Sep 11 05:21:39 PM UTC 24 |
4415516609 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.2939117541 |
|
|
Sep 11 05:20:51 PM UTC 24 |
Sep 11 05:21:40 PM UTC 24 |
40921067235 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.623776146 |
|
|
Sep 11 05:21:29 PM UTC 24 |
Sep 11 05:21:40 PM UTC 24 |
699979664 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.2388793307 |
|
|
Sep 11 05:21:39 PM UTC 24 |
Sep 11 05:21:41 PM UTC 24 |
42922105 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.672583720 |
|
|
Sep 11 05:18:05 PM UTC 24 |
Sep 11 05:22:05 PM UTC 24 |
10236719100 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.1703321795 |
|
|
Sep 11 05:20:59 PM UTC 24 |
Sep 11 05:21:42 PM UTC 24 |
2839345364 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.1543961057 |
|
|
Sep 11 05:21:40 PM UTC 24 |
Sep 11 05:21:43 PM UTC 24 |
14767305 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.3444512226 |
|
|
Sep 11 05:21:09 PM UTC 24 |
Sep 11 05:21:45 PM UTC 24 |
1940825905 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.1226008555 |
|
|
Sep 11 05:19:05 PM UTC 24 |
Sep 11 05:21:45 PM UTC 24 |
31212832069 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.1468436695 |
|
|
Sep 11 05:21:44 PM UTC 24 |
Sep 11 05:21:46 PM UTC 24 |
25748593 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.845686543 |
|
|
Sep 11 05:21:44 PM UTC 24 |
Sep 11 05:21:46 PM UTC 24 |
16133786 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.1374358541 |
|
|
Sep 11 05:21:34 PM UTC 24 |
Sep 11 05:21:47 PM UTC 24 |
3763557454 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.4272545223 |
|
|
Sep 11 05:21:24 PM UTC 24 |
Sep 11 05:21:47 PM UTC 24 |
4359617165 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.2700515618 |
|
|
Sep 11 05:15:56 PM UTC 24 |
Sep 11 05:21:48 PM UTC 24 |
129605537041 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.818769829 |
|
|
Sep 11 05:12:18 PM UTC 24 |
Sep 11 05:21:49 PM UTC 24 |
68432508723 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.490841896 |
|
|
Sep 11 05:19:53 PM UTC 24 |
Sep 11 05:21:49 PM UTC 24 |
10754506404 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.2650716270 |
|
|
Sep 11 05:21:46 PM UTC 24 |
Sep 11 05:21:50 PM UTC 24 |
126870529 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.2502158217 |
|
|
Sep 11 05:17:21 PM UTC 24 |
Sep 11 05:21:50 PM UTC 24 |
34398077078 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.4255354449 |
|
|
Sep 11 05:21:31 PM UTC 24 |
Sep 11 05:21:50 PM UTC 24 |
2856958950 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.4080314409 |
|
|
Sep 11 05:21:47 PM UTC 24 |
Sep 11 05:21:51 PM UTC 24 |
78662535 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.672013089 |
|
|
Sep 11 05:20:11 PM UTC 24 |
Sep 11 05:21:53 PM UTC 24 |
41111760128 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.251399796 |
|
|
Sep 11 05:21:48 PM UTC 24 |
Sep 11 05:21:53 PM UTC 24 |
80970937 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.431307446 |
|
|
Sep 11 05:21:46 PM UTC 24 |
Sep 11 05:21:54 PM UTC 24 |
268485131 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.2175162175 |
|
|
Sep 11 05:21:52 PM UTC 24 |
Sep 11 05:21:54 PM UTC 24 |
202225840 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.430869765 |
|
|
Sep 11 05:19:31 PM UTC 24 |
Sep 11 05:21:55 PM UTC 24 |
11869781508 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2542018159 |
|
|
Sep 11 05:21:50 PM UTC 24 |
Sep 11 05:21:56 PM UTC 24 |
252132758 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.375895678 |
|
|
Sep 11 05:21:54 PM UTC 24 |
Sep 11 05:21:56 PM UTC 24 |
11703824 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.2434109774 |
|
|
Sep 11 05:21:48 PM UTC 24 |
Sep 11 05:21:56 PM UTC 24 |
1810472482 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.4212963946 |
|
|
Sep 11 05:21:55 PM UTC 24 |
Sep 11 05:21:57 PM UTC 24 |
14831626 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.27365205 |
|
|
Sep 11 05:21:41 PM UTC 24 |
Sep 11 05:21:57 PM UTC 24 |
10399409393 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.3583698429 |
|
|
Sep 11 05:21:55 PM UTC 24 |
Sep 11 05:21:58 PM UTC 24 |
45406719 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.1042011261 |
|
|
Sep 11 05:21:56 PM UTC 24 |
Sep 11 05:21:58 PM UTC 24 |
12697826 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.1764898244 |
|
|
Sep 11 05:21:55 PM UTC 24 |
Sep 11 05:21:59 PM UTC 24 |
75145007 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.3376784478 |
|
|
Sep 11 05:21:56 PM UTC 24 |
Sep 11 05:21:59 PM UTC 24 |
415214613 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.3053018527 |
|
|
Sep 11 05:18:27 PM UTC 24 |
Sep 11 05:21:59 PM UTC 24 |
72195380491 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.1165083642 |
|
|
Sep 11 05:21:47 PM UTC 24 |
Sep 11 05:22:00 PM UTC 24 |
577561088 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.3050280701 |
|
|
Sep 11 05:21:13 PM UTC 24 |
Sep 11 05:22:01 PM UTC 24 |
11818827805 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.362437200 |
|
|
Sep 11 05:21:57 PM UTC 24 |
Sep 11 05:22:01 PM UTC 24 |
1313368226 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.3426312533 |
|
|
Sep 11 05:21:43 PM UTC 24 |
Sep 11 05:22:02 PM UTC 24 |
4409500937 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.17489595 |
|
|
Sep 11 05:21:57 PM UTC 24 |
Sep 11 05:22:03 PM UTC 24 |
783846329 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.1543771780 |
|
|
Sep 11 05:18:41 PM UTC 24 |
Sep 11 05:22:05 PM UTC 24 |
39183942390 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.3319860533 |
|
|
Sep 11 05:22:04 PM UTC 24 |
Sep 11 05:22:06 PM UTC 24 |
16240095 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.3820465552 |
|
|
Sep 11 05:21:58 PM UTC 24 |
Sep 11 05:22:07 PM UTC 24 |
1141566734 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.2528434805 |
|
|
Sep 11 05:21:19 PM UTC 24 |
Sep 11 05:22:07 PM UTC 24 |
11878976232 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.3688722670 |
|
|
Sep 11 05:21:10 PM UTC 24 |
Sep 11 05:22:09 PM UTC 24 |
43657764124 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.2522840133 |
|
|
Sep 11 05:22:00 PM UTC 24 |
Sep 11 05:22:10 PM UTC 24 |
294272694 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.1795927857 |
|
|
Sep 11 05:21:57 PM UTC 24 |
Sep 11 05:22:11 PM UTC 24 |
2985827301 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.2375437546 |
|
|
Sep 11 05:21:49 PM UTC 24 |
Sep 11 05:22:11 PM UTC 24 |
14505681725 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.1484192721 |
|
|
Sep 11 05:19:23 PM UTC 24 |
Sep 11 05:22:12 PM UTC 24 |
17545574692 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.523594198 |
|
|
Sep 11 05:22:00 PM UTC 24 |
Sep 11 05:22:13 PM UTC 24 |
5108861799 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.3464608890 |
|
|
Sep 11 05:21:37 PM UTC 24 |
Sep 11 05:22:15 PM UTC 24 |
12527098958 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.1567805768 |
|
|
Sep 11 05:21:16 PM UTC 24 |
Sep 11 05:22:15 PM UTC 24 |
2550530139 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.324649494 |
|
|
Sep 11 05:22:02 PM UTC 24 |
Sep 11 05:22:16 PM UTC 24 |
885149392 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.2271874810 |
|
|
Sep 11 05:14:01 PM UTC 24 |
Sep 11 05:22:18 PM UTC 24 |
55403374228 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.2534093793 |
|
|
Sep 11 05:21:18 PM UTC 24 |
Sep 11 05:22:18 PM UTC 24 |
15775088020 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.1583321271 |
|
|
Sep 11 05:13:46 PM UTC 24 |
Sep 11 05:22:19 PM UTC 24 |
47747744939 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.1978434481 |
|
|
Sep 11 05:19:52 PM UTC 24 |
Sep 11 05:22:21 PM UTC 24 |
29672372797 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.890349089 |
|
|
Sep 11 05:21:16 PM UTC 24 |
Sep 11 05:22:21 PM UTC 24 |
5687510566 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.1293510279 |
|
|
Sep 11 05:22:00 PM UTC 24 |
Sep 11 05:22:22 PM UTC 24 |
933711650 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.3123005557 |
|
|
Sep 11 05:17:59 PM UTC 24 |
Sep 11 05:22:26 PM UTC 24 |
38796301558 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.402199860 |
|
|
Sep 11 05:20:59 PM UTC 24 |
Sep 11 05:22:30 PM UTC 24 |
17409725381 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.2598787056 |
|
|
Sep 11 05:21:12 PM UTC 24 |
Sep 11 05:22:34 PM UTC 24 |
35017086230 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.2844455972 |
|
|
Sep 11 05:20:39 PM UTC 24 |
Sep 11 05:22:39 PM UTC 24 |
61740899750 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.3698781358 |
|
|
Sep 11 05:21:30 PM UTC 24 |
Sep 11 05:22:46 PM UTC 24 |
8326998480 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.2047985020 |
|
|
Sep 11 05:14:24 PM UTC 24 |
Sep 11 05:22:50 PM UTC 24 |
47055906182 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.2334018404 |
|
|
Sep 11 05:14:21 PM UTC 24 |
Sep 11 05:22:54 PM UTC 24 |
133687982008 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.3089073351 |
|
|
Sep 11 05:21:57 PM UTC 24 |
Sep 11 05:22:55 PM UTC 24 |
7107563822 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.64716909 |
|
|
Sep 11 05:21:01 PM UTC 24 |
Sep 11 05:22:59 PM UTC 24 |
41007518135 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.148288618 |
|
|
Sep 11 05:20:41 PM UTC 24 |
Sep 11 05:23:00 PM UTC 24 |
8681446259 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.3983331827 |
|
|
Sep 11 05:18:27 PM UTC 24 |
Sep 11 05:23:05 PM UTC 24 |
22340854979 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.1399854270 |
|
|
Sep 11 05:22:02 PM UTC 24 |
Sep 11 05:23:12 PM UTC 24 |
36404067193 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.800668295 |
|
|
Sep 11 05:20:09 PM UTC 24 |
Sep 11 05:23:15 PM UTC 24 |
70607400742 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1497654823 |
|
|
Sep 11 05:20:40 PM UTC 24 |
Sep 11 05:23:15 PM UTC 24 |
9078718765 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.590508075 |
|
|
Sep 11 05:21:52 PM UTC 24 |
Sep 11 05:23:18 PM UTC 24 |
6892847246 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.4175905579 |
|
|
Sep 11 05:17:05 PM UTC 24 |
Sep 11 05:23:27 PM UTC 24 |
307919324214 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.2703063299 |
|
|
Sep 11 05:21:00 PM UTC 24 |
Sep 11 05:23:29 PM UTC 24 |
22364629337 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.1697265617 |
|
|
Sep 11 05:21:39 PM UTC 24 |
Sep 11 05:24:04 PM UTC 24 |
60851271048 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.796321827 |
|
|
Sep 11 05:22:01 PM UTC 24 |
Sep 11 05:24:28 PM UTC 24 |
69384251176 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.1586572444 |
|
|
Sep 11 05:19:09 PM UTC 24 |
Sep 11 05:24:30 PM UTC 24 |
28447221381 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.2662047593 |
|
|
Sep 11 05:19:29 PM UTC 24 |
Sep 11 05:25:02 PM UTC 24 |
358029378560 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.4123661035 |
|
|
Sep 11 05:21:32 PM UTC 24 |
Sep 11 05:25:02 PM UTC 24 |
90583073002 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.1313387501 |
|
|
Sep 11 05:20:44 PM UTC 24 |
Sep 11 05:25:28 PM UTC 24 |
135496954840 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.3646127640 |
|
|
Sep 11 05:21:39 PM UTC 24 |
Sep 11 05:25:33 PM UTC 24 |
40873127506 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.2896539756 |
|
|
Sep 11 05:09:32 PM UTC 24 |
Sep 11 05:25:44 PM UTC 24 |
408828796064 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.3980099894 |
|
|
Sep 11 05:19:31 PM UTC 24 |
Sep 11 05:25:47 PM UTC 24 |
31923502704 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.4232642257 |
|
|
Sep 11 05:17:41 PM UTC 24 |
Sep 11 05:26:07 PM UTC 24 |
113627948448 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.3454889064 |
|
|
Sep 11 05:06:18 PM UTC 24 |
Sep 11 05:26:55 PM UTC 24 |
100252711602 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3364862324 |
|
|
Sep 11 05:21:37 PM UTC 24 |
Sep 11 05:27:14 PM UTC 24 |
241965520283 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.1315733001 |
|
|
Sep 11 05:22:03 PM UTC 24 |
Sep 11 05:27:25 PM UTC 24 |
29086219088 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.2318182928 |
|
|
Sep 11 05:19:27 PM UTC 24 |
Sep 11 05:27:45 PM UTC 24 |
95826655576 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.1671225958 |
|
|
Sep 11 05:21:50 PM UTC 24 |
Sep 11 05:28:10 PM UTC 24 |
209827731388 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.3664121055 |
|
|
Sep 11 05:21:50 PM UTC 24 |
Sep 11 05:29:57 PM UTC 24 |
40562634015 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.791987101 |
|
|
Sep 11 05:16:49 PM UTC 24 |
Sep 11 05:30:01 PM UTC 24 |
135088557925 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_stress_all.2949125227 |
|
|
Sep 11 05:15:44 PM UTC 24 |
Sep 11 05:34:44 PM UTC 24 |
120444990076 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.757825735 |
|
|
Sep 11 06:47:26 PM UTC 24 |
Sep 11 06:47:30 PM UTC 24 |
110153140 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.4073983105 |
|
|
Sep 11 06:47:28 PM UTC 24 |
Sep 11 06:47:30 PM UTC 24 |
32143349 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.3484894195 |
|
|
Sep 11 06:47:08 PM UTC 24 |
Sep 11 06:47:10 PM UTC 24 |
10681497 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2800605651 |
|
|
Sep 11 06:47:08 PM UTC 24 |
Sep 11 06:47:10 PM UTC 24 |
13011464 ps |
| T1038 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.222200666 |
|
|
Sep 11 06:47:08 PM UTC 24 |
Sep 11 06:47:11 PM UTC 24 |
23328316 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1880867671 |
|
|
Sep 11 06:47:08 PM UTC 24 |
Sep 11 06:47:11 PM UTC 24 |
99838970 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.626117268 |
|
|
Sep 11 06:47:09 PM UTC 24 |
Sep 11 06:47:12 PM UTC 24 |
204607151 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3666524725 |
|
|
Sep 11 06:47:08 PM UTC 24 |
Sep 11 06:47:12 PM UTC 24 |
114811583 ps |
| T1039 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.223709893 |
|
|
Sep 11 06:47:10 PM UTC 24 |
Sep 11 06:47:12 PM UTC 24 |
34187866 ps |
| T1040 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.600794191 |
|
|
Sep 11 06:47:10 PM UTC 24 |
Sep 11 06:47:13 PM UTC 24 |
11808117 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2847859099 |
|
|
Sep 11 06:47:10 PM UTC 24 |
Sep 11 06:47:13 PM UTC 24 |
44770818 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.280217111 |
|
|
Sep 11 06:47:09 PM UTC 24 |
Sep 11 06:47:13 PM UTC 24 |
575424951 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.434731873 |
|
|
Sep 11 06:47:07 PM UTC 24 |
Sep 11 06:47:13 PM UTC 24 |
162448411 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.90108948 |
|
|
Sep 11 06:47:10 PM UTC 24 |
Sep 11 06:47:14 PM UTC 24 |
29866245 ps |
| T1041 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.2136652974 |
|
|
Sep 11 06:47:11 PM UTC 24 |
Sep 11 06:47:14 PM UTC 24 |
13443538 ps |
| T1042 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.5557987 |
|
|
Sep 11 06:47:11 PM UTC 24 |
Sep 11 06:47:14 PM UTC 24 |
12866096 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.3259545338 |
|
|
Sep 11 06:47:10 PM UTC 24 |
Sep 11 06:47:15 PM UTC 24 |
1311487545 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1741755493 |
|
|
Sep 11 06:47:09 PM UTC 24 |
Sep 11 06:47:15 PM UTC 24 |
178447285 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1853647099 |
|
|
Sep 11 06:47:13 PM UTC 24 |
Sep 11 06:47:16 PM UTC 24 |
43170931 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.2707667424 |
|
|
Sep 11 06:47:07 PM UTC 24 |
Sep 11 06:47:16 PM UTC 24 |
281125541 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.762527915 |
|
|
Sep 11 06:47:11 PM UTC 24 |
Sep 11 06:47:16 PM UTC 24 |
142350309 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.2980386942 |
|
|
Sep 11 06:47:11 PM UTC 24 |
Sep 11 06:47:17 PM UTC 24 |
2458873109 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.2070411857 |
|
|
Sep 11 06:47:13 PM UTC 24 |
Sep 11 06:47:17 PM UTC 24 |
73231073 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.3076523763 |
|
|
Sep 11 06:47:30 PM UTC 24 |
Sep 11 06:47:33 PM UTC 24 |
142368882 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3371794142 |
|
|
Sep 11 06:47:14 PM UTC 24 |
Sep 11 06:47:17 PM UTC 24 |
27340592 ps |