Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1150
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T1043 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.2918936469 Sep 11 06:47:15 PM UTC 24 Sep 11 06:47:17 PM UTC 24 14072235 ps
T1044 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.67572592 Sep 11 06:47:26 PM UTC 24 Sep 11 06:47:30 PM UTC 24 217744875 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2829851985 Sep 11 06:47:11 PM UTC 24 Sep 11 06:47:17 PM UTC 24 603083706 ps
T1045 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.2395732795 Sep 11 06:47:15 PM UTC 24 Sep 11 06:47:17 PM UTC 24 62935327 ps
T1046 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.1191474654 Sep 11 06:47:14 PM UTC 24 Sep 11 06:47:17 PM UTC 24 100880431 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2440926292 Sep 11 06:47:15 PM UTC 24 Sep 11 06:47:17 PM UTC 24 23334395 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.2869251448 Sep 11 06:47:15 PM UTC 24 Sep 11 06:47:18 PM UTC 24 33231402 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3306156140 Sep 11 06:47:14 PM UTC 24 Sep 11 06:47:18 PM UTC 24 123204974 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.3849648351 Sep 11 06:47:14 PM UTC 24 Sep 11 06:47:19 PM UTC 24 534737193 ps
T1047 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.64194814 Sep 11 06:47:31 PM UTC 24 Sep 11 06:47:33 PM UTC 24 11857908 ps
T1048 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.4038453312 Sep 11 06:47:18 PM UTC 24 Sep 11 06:47:20 PM UTC 24 16865440 ps
T1049 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.1271862101 Sep 11 06:47:18 PM UTC 24 Sep 11 06:47:20 PM UTC 24 35379281 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1407060205 Sep 11 06:47:18 PM UTC 24 Sep 11 06:47:20 PM UTC 24 57997502 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.2431849957 Sep 11 06:47:16 PM UTC 24 Sep 11 06:47:21 PM UTC 24 37105322 ps
T1050 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.222946644 Sep 11 06:47:16 PM UTC 24 Sep 11 06:47:21 PM UTC 24 384642880 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.2280424562 Sep 11 06:47:18 PM UTC 24 Sep 11 06:47:21 PM UTC 24 139166369 ps
T1051 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.3375258861 Sep 11 06:47:18 PM UTC 24 Sep 11 06:47:21 PM UTC 24 90611082 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.977584105 Sep 11 06:47:09 PM UTC 24 Sep 11 06:47:22 PM UTC 24 212478938 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.4278626420 Sep 11 06:47:18 PM UTC 24 Sep 11 06:47:22 PM UTC 24 125094729 ps
T1052 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.198767389 Sep 11 06:47:21 PM UTC 24 Sep 11 06:47:22 PM UTC 24 70851480 ps
T1053 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1658591172 Sep 11 06:47:19 PM UTC 24 Sep 11 06:47:23 PM UTC 24 240648603 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2546944849 Sep 11 06:47:18 PM UTC 24 Sep 11 06:47:23 PM UTC 24 105287592 ps
T1054 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.2655016133 Sep 11 06:47:14 PM UTC 24 Sep 11 06:47:23 PM UTC 24 427242215 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3712756931 Sep 11 06:47:19 PM UTC 24 Sep 11 06:47:23 PM UTC 24 95281428 ps
T1055 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.3994357695 Sep 11 06:47:21 PM UTC 24 Sep 11 06:47:25 PM UTC 24 322098044 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.3133836828 Sep 11 06:47:19 PM UTC 24 Sep 11 06:47:25 PM UTC 24 122807228 ps
T1056 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1455674255 Sep 11 06:47:22 PM UTC 24 Sep 11 06:47:25 PM UTC 24 47835553 ps
T1057 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.2958534262 Sep 11 06:47:23 PM UTC 24 Sep 11 06:47:25 PM UTC 24 57570164 ps
T1058 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.2409107421 Sep 11 06:47:22 PM UTC 24 Sep 11 06:47:25 PM UTC 24 77099421 ps
T1059 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3047892012 Sep 11 06:47:22 PM UTC 24 Sep 11 06:47:25 PM UTC 24 28276667 ps
T1060 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.2607261861 Sep 11 06:47:24 PM UTC 24 Sep 11 06:47:27 PM UTC 24 34252249 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.4294695273 Sep 11 06:47:16 PM UTC 24 Sep 11 06:47:27 PM UTC 24 1226902791 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.1115460797 Sep 11 06:47:11 PM UTC 24 Sep 11 06:47:27 PM UTC 24 554899915 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.3762186820 Sep 11 06:47:23 PM UTC 24 Sep 11 06:47:27 PM UTC 24 152000352 ps
T1061 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1228840975 Sep 11 06:47:23 PM UTC 24 Sep 11 06:47:27 PM UTC 24 73964452 ps
T1062 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.3601785512 Sep 11 06:47:24 PM UTC 24 Sep 11 06:47:27 PM UTC 24 34838780 ps
T1063 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.603487662 Sep 11 06:47:16 PM UTC 24 Sep 11 06:47:28 PM UTC 24 743257248 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4005691674 Sep 11 06:47:23 PM UTC 24 Sep 11 06:47:28 PM UTC 24 753619535 ps
T1064 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.2307967968 Sep 11 06:47:26 PM UTC 24 Sep 11 06:47:28 PM UTC 24 19935633 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.3044286693 Sep 11 06:47:23 PM UTC 24 Sep 11 06:47:28 PM UTC 24 152553781 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.1600694767 Sep 11 06:47:26 PM UTC 24 Sep 11 06:47:29 PM UTC 24 1054075642 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.3918507867 Sep 11 06:47:09 PM UTC 24 Sep 11 06:47:30 PM UTC 24 4106225318 ps
T1065 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3167190622 Sep 11 06:47:26 PM UTC 24 Sep 11 06:47:30 PM UTC 24 89957333 ps
T1066 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2462870944 Sep 11 06:47:24 PM UTC 24 Sep 11 06:47:31 PM UTC 24 229983848 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.807399611 Sep 11 06:47:09 PM UTC 24 Sep 11 06:47:31 PM UTC 24 837510992 ps
T1067 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2364152222 Sep 11 06:47:28 PM UTC 24 Sep 11 06:47:31 PM UTC 24 26832368 ps
T1068 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2292451862 Sep 11 06:47:27 PM UTC 24 Sep 11 06:47:31 PM UTC 24 179904959 ps
T1069 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.2394233268 Sep 11 06:47:28 PM UTC 24 Sep 11 06:47:33 PM UTC 24 99810631 ps
T1070 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.1595678735 Sep 11 06:47:11 PM UTC 24 Sep 11 06:47:31 PM UTC 24 314055068 ps
T1071 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.840039123 Sep 11 06:47:30 PM UTC 24 Sep 11 06:47:32 PM UTC 24 103426591 ps
T1072 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.931585772 Sep 11 06:47:23 PM UTC 24 Sep 11 06:47:32 PM UTC 24 562274911 ps
T1073 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1874481094 Sep 11 06:47:28 PM UTC 24 Sep 11 06:47:33 PM UTC 24 125943016 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.912907353 Sep 11 06:47:27 PM UTC 24 Sep 11 06:47:33 PM UTC 24 719447066 ps
T1074 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.159568393 Sep 11 06:47:31 PM UTC 24 Sep 11 06:47:34 PM UTC 24 26028498 ps
T1075 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.3332569070 Sep 11 06:47:32 PM UTC 24 Sep 11 06:47:35 PM UTC 24 15027055 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1968454227 Sep 11 06:47:14 PM UTC 24 Sep 11 06:47:35 PM UTC 24 4576731245 ps
T1076 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.2681561607 Sep 11 06:47:31 PM UTC 24 Sep 11 06:47:35 PM UTC 24 347403360 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.758263187 Sep 11 06:47:32 PM UTC 24 Sep 11 06:47:35 PM UTC 24 41588255 ps
T1077 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4042829419 Sep 11 06:47:32 PM UTC 24 Sep 11 06:47:35 PM UTC 24 98882460 ps
T1078 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1825218275 Sep 11 06:47:32 PM UTC 24 Sep 11 06:47:35 PM UTC 24 27415633 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.2917149985 Sep 11 06:47:29 PM UTC 24 Sep 11 06:47:36 PM UTC 24 61832044 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.839825897 Sep 11 06:47:32 PM UTC 24 Sep 11 06:47:36 PM UTC 24 70830960 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.907505967 Sep 11 06:47:31 PM UTC 24 Sep 11 06:47:36 PM UTC 24 573940647 ps
T1079 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.2694087619 Sep 11 06:47:34 PM UTC 24 Sep 11 06:47:36 PM UTC 24 54583780 ps
T1080 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2852906142 Sep 11 06:47:34 PM UTC 24 Sep 11 06:47:37 PM UTC 24 25725113 ps
T1081 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3825130527 Sep 11 06:47:14 PM UTC 24 Sep 11 06:47:37 PM UTC 24 1460824723 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.3489647991 Sep 11 06:47:35 PM UTC 24 Sep 11 06:47:38 PM UTC 24 63372734 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.1171182521 Sep 11 06:47:30 PM UTC 24 Sep 11 06:47:38 PM UTC 24 3488922847 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.2103553702 Sep 11 06:47:32 PM UTC 24 Sep 11 06:47:47 PM UTC 24 3900850982 ps
T1082 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1788232603 Sep 11 06:47:43 PM UTC 24 Sep 11 06:47:47 PM UTC 24 133094048 ps
T1083 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.2299782510 Sep 11 06:47:32 PM UTC 24 Sep 11 06:47:38 PM UTC 24 499879276 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2923185048 Sep 11 06:47:34 PM UTC 24 Sep 11 06:47:38 PM UTC 24 299617573 ps
T1084 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.639780846 Sep 11 06:47:35 PM UTC 24 Sep 11 06:47:38 PM UTC 24 91354169 ps
T1085 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.1693397681 Sep 11 06:47:37 PM UTC 24 Sep 11 06:47:39 PM UTC 24 18654917 ps
T1086 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.3795051186 Sep 11 06:47:37 PM UTC 24 Sep 11 06:47:39 PM UTC 24 39085027 ps
T1087 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1094632217 Sep 11 06:47:35 PM UTC 24 Sep 11 06:47:39 PM UTC 24 41826184 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.3213569297 Sep 11 06:47:19 PM UTC 24 Sep 11 06:47:39 PM UTC 24 3699968613 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.3474450572 Sep 11 06:47:18 PM UTC 24 Sep 11 06:47:40 PM UTC 24 304960359 ps
T1088 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.1731551104 Sep 11 06:47:35 PM UTC 24 Sep 11 06:47:40 PM UTC 24 157429129 ps
T1089 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.657841928 Sep 11 06:47:37 PM UTC 24 Sep 11 06:47:40 PM UTC 24 125666794 ps
T1090 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.1302339274 Sep 11 06:47:34 PM UTC 24 Sep 11 06:47:40 PM UTC 24 221029595 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.3120114035 Sep 11 06:47:28 PM UTC 24 Sep 11 06:47:40 PM UTC 24 813635982 ps
T1091 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.512725531 Sep 11 06:47:37 PM UTC 24 Sep 11 06:47:40 PM UTC 24 612581077 ps
T1092 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2415194539 Sep 11 06:47:37 PM UTC 24 Sep 11 06:47:40 PM UTC 24 118423274 ps
T1093 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.2387413853 Sep 11 06:47:37 PM UTC 24 Sep 11 06:47:41 PM UTC 24 97630636 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.3935162350 Sep 11 06:47:24 PM UTC 24 Sep 11 06:47:41 PM UTC 24 280360031 ps
T1094 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.204750630 Sep 11 06:47:37 PM UTC 24 Sep 11 06:47:41 PM UTC 24 174190958 ps
T1095 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.1859889001 Sep 11 06:47:40 PM UTC 24 Sep 11 06:47:42 PM UTC 24 26527051 ps
T1096 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.3112930617 Sep 11 06:47:40 PM UTC 24 Sep 11 06:47:42 PM UTC 24 43638037 ps
T1097 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1317268936 Sep 11 06:47:37 PM UTC 24 Sep 11 06:47:42 PM UTC 24 807480978 ps
T1098 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.442792988 Sep 11 06:47:40 PM UTC 24 Sep 11 06:47:42 PM UTC 24 19547117 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.1394393189 Sep 11 06:47:40 PM UTC 24 Sep 11 06:47:42 PM UTC 24 97518251 ps
T1099 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2069334208 Sep 11 06:47:40 PM UTC 24 Sep 11 06:47:43 PM UTC 24 97519145 ps
T1100 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.627275966 Sep 11 06:47:40 PM UTC 24 Sep 11 06:47:43 PM UTC 24 169121292 ps
T1101 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2112228353 Sep 11 06:47:38 PM UTC 24 Sep 11 06:47:43 PM UTC 24 578799483 ps
T1102 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.2771934427 Sep 11 06:47:47 PM UTC 24 Sep 11 06:47:48 PM UTC 24 45561598 ps
T1103 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.1192258855 Sep 11 06:47:38 PM UTC 24 Sep 11 06:47:43 PM UTC 24 663872944 ps
T1104 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.2110867157 Sep 11 06:47:42 PM UTC 24 Sep 11 06:47:44 PM UTC 24 24646410 ps
T1105 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.831062894 Sep 11 06:47:42 PM UTC 24 Sep 11 06:47:44 PM UTC 24 41450493 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.1940960561 Sep 11 06:47:20 PM UTC 24 Sep 11 06:47:44 PM UTC 24 1777137481 ps
T1106 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.97989957 Sep 11 06:47:42 PM UTC 24 Sep 11 06:47:44 PM UTC 24 413624726 ps
T1107 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.743700112 Sep 11 06:47:42 PM UTC 24 Sep 11 06:47:44 PM UTC 24 128777773 ps
T1108 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3041639707 Sep 11 06:47:42 PM UTC 24 Sep 11 06:47:44 PM UTC 24 61486572 ps
T1109 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3394697232 Sep 11 06:47:42 PM UTC 24 Sep 11 06:47:44 PM UTC 24 29977871 ps
T1110 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.2054618132 Sep 11 06:47:42 PM UTC 24 Sep 11 06:47:45 PM UTC 24 267269345 ps
T1111 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.898086267 Sep 11 06:47:43 PM UTC 24 Sep 11 06:47:45 PM UTC 24 12221583 ps
T1112 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.878121479 Sep 11 06:47:40 PM UTC 24 Sep 11 06:47:45 PM UTC 24 175592498 ps
T1113 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.3374775475 Sep 11 06:47:43 PM UTC 24 Sep 11 06:47:45 PM UTC 24 41303608 ps
T1114 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1717263666 Sep 11 06:47:43 PM UTC 24 Sep 11 06:47:45 PM UTC 24 15829057 ps
T1115 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.2340219654 Sep 11 06:47:43 PM UTC 24 Sep 11 06:47:45 PM UTC 24 21613872 ps
T1116 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.3891465485 Sep 11 06:47:43 PM UTC 24 Sep 11 06:47:45 PM UTC 24 45321261 ps
T1117 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.917024816 Sep 11 06:47:37 PM UTC 24 Sep 11 06:47:45 PM UTC 24 338568182 ps
T1118 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.3348456427 Sep 11 06:47:43 PM UTC 24 Sep 11 06:47:45 PM UTC 24 40784608 ps
T1119 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.1475567744 Sep 11 06:47:40 PM UTC 24 Sep 11 06:47:45 PM UTC 24 663833697 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.1113457646 Sep 11 06:47:31 PM UTC 24 Sep 11 06:47:46 PM UTC 24 1415034487 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.3643669355 Sep 11 06:47:26 PM UTC 24 Sep 11 06:47:46 PM UTC 24 3164153862 ps
T1120 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.4161785368 Sep 11 06:47:34 PM UTC 24 Sep 11 06:47:46 PM UTC 24 207407278 ps
T1121 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.474297628 Sep 11 06:47:45 PM UTC 24 Sep 11 06:47:46 PM UTC 24 39386519 ps
T1122 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.2511520677 Sep 11 06:47:45 PM UTC 24 Sep 11 06:47:47 PM UTC 24 35473768 ps
T1123 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3423159072 Sep 11 06:47:41 PM UTC 24 Sep 11 06:47:47 PM UTC 24 103874676 ps
T1124 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.903213899 Sep 11 06:47:46 PM UTC 24 Sep 11 06:47:48 PM UTC 24 54287073 ps
T1125 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.3885511007 Sep 11 06:47:45 PM UTC 24 Sep 11 06:47:47 PM UTC 24 50147359 ps
T1126 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.887728522 Sep 11 06:47:45 PM UTC 24 Sep 11 06:47:47 PM UTC 24 14535849 ps
T1127 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.1866918334 Sep 11 06:47:45 PM UTC 24 Sep 11 06:47:47 PM UTC 24 110067871 ps
T1128 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.1747515577 Sep 11 06:47:45 PM UTC 24 Sep 11 06:47:47 PM UTC 24 37730072 ps
T1129 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1133724159 Sep 11 06:47:42 PM UTC 24 Sep 11 06:47:47 PM UTC 24 510132768 ps
T1130 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.93038108 Sep 11 06:47:45 PM UTC 24 Sep 11 06:47:47 PM UTC 24 16766324 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.1612094247 Sep 11 06:47:41 PM UTC 24 Sep 11 06:47:47 PM UTC 24 159273926 ps
T1131 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.3108526433 Sep 11 06:47:46 PM UTC 24 Sep 11 06:47:48 PM UTC 24 50387701 ps
T1132 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.1971637271 Sep 11 06:47:46 PM UTC 24 Sep 11 06:47:48 PM UTC 24 16795305 ps
T1133 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.4120221274 Sep 11 06:47:46 PM UTC 24 Sep 11 06:47:48 PM UTC 24 16477204 ps
T1134 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.1905639013 Sep 11 06:47:47 PM UTC 24 Sep 11 06:47:48 PM UTC 24 12317016 ps
T1135 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.1109840036 Sep 11 06:47:46 PM UTC 24 Sep 11 06:47:48 PM UTC 24 24914533 ps
T1136 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.4256977723 Sep 11 06:47:47 PM UTC 24 Sep 11 06:47:48 PM UTC 24 20188092 ps
T1137 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.1497142646 Sep 11 06:47:47 PM UTC 24 Sep 11 06:47:49 PM UTC 24 47186688 ps
T1138 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.1569107290 Sep 11 06:47:47 PM UTC 24 Sep 11 06:47:49 PM UTC 24 34472361 ps
T1139 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.3515266894 Sep 11 06:47:47 PM UTC 24 Sep 11 06:47:49 PM UTC 24 14621467 ps
T1140 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3894070422 Sep 11 06:47:10 PM UTC 24 Sep 11 06:47:49 PM UTC 24 2708443811 ps
T1141 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.2025543409 Sep 11 06:47:47 PM UTC 24 Sep 11 06:47:49 PM UTC 24 50217238 ps
T1142 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.3497892737 Sep 11 06:47:47 PM UTC 24 Sep 11 06:47:49 PM UTC 24 16499569 ps
T1143 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.3867544085 Sep 11 06:47:47 PM UTC 24 Sep 11 06:47:49 PM UTC 24 13063872 ps
T1144 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.512463594 Sep 11 06:47:47 PM UTC 24 Sep 11 06:47:49 PM UTC 24 15222815 ps
T1145 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.4015293604 Sep 11 06:47:47 PM UTC 24 Sep 11 06:47:49 PM UTC 24 12930827 ps
T1146 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.4234200123 Sep 11 06:47:42 PM UTC 24 Sep 11 06:47:49 PM UTC 24 1045519738 ps
T1147 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.3025765979 Sep 11 06:47:48 PM UTC 24 Sep 11 06:47:50 PM UTC 24 51691358 ps
T1148 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.802905723 Sep 11 06:47:37 PM UTC 24 Sep 11 06:47:50 PM UTC 24 588438271 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.3680500876 Sep 11 06:47:38 PM UTC 24 Sep 11 06:47:53 PM UTC 24 2103067177 ps
T1149 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.318834344 Sep 11 06:47:18 PM UTC 24 Sep 11 06:47:53 PM UTC 24 3681035391 ps
T1150 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.2958197306 Sep 11 06:47:40 PM UTC 24 Sep 11 06:47:54 PM UTC 24 4924886373 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.2963538832 Sep 11 06:47:41 PM UTC 24 Sep 11 06:47:57 PM UTC 24 4182839202 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.976765091
Short name T9
Test name
Test status
Simulation time 18112271 ps
CPU time 0.99 seconds
Started Sep 11 05:06:12 PM UTC 24
Finished Sep 11 05:06:14 PM UTC 24
Peak memory 215912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976765091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.976765091
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.2845914788
Short name T16
Test name
Test status
Simulation time 855395293 ps
CPU time 5.78 seconds
Started Sep 11 05:06:11 PM UTC 24
Finished Sep 11 05:06:18 PM UTC 24
Peak memory 251792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845914788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.2845914788
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.2522326960
Short name T35
Test name
Test status
Simulation time 2291249426 ps
CPU time 43.17 seconds
Started Sep 11 05:06:11 PM UTC 24
Finished Sep 11 05:06:56 PM UTC 24
Peak memory 266132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522326960 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.2522326960
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.2019975584
Short name T58
Test name
Test status
Simulation time 2554523620 ps
CPU time 68.16 seconds
Started Sep 11 05:06:11 PM UTC 24
Finished Sep 11 05:07:21 PM UTC 24
Peak memory 268288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019975584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2019975584
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.2535857690
Short name T38
Test name
Test status
Simulation time 4082392700 ps
CPU time 106.08 seconds
Started Sep 11 05:07:42 PM UTC 24
Finished Sep 11 05:09:31 PM UTC 24
Peak memory 268480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535857690 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.2535857690
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.2487321330
Short name T12
Test name
Test status
Simulation time 141269335 ps
CPU time 3.55 seconds
Started Sep 11 05:06:11 PM UTC 24
Finished Sep 11 05:06:16 PM UTC 24
Peak memory 233848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487321330 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.2487321330
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2829851985
Short name T131
Test name
Test status
Simulation time 603083706 ps
CPU time 4.25 seconds
Started Sep 11 06:47:11 PM UTC 24
Finished Sep 11 06:47:17 PM UTC 24
Peak memory 226240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2829851985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.spi_device_csr_mem_rw_with_rand_reset.2829851985
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.4263924064
Short name T28
Test name
Test status
Simulation time 140562566 ps
CPU time 2.8 seconds
Started Sep 11 05:06:20 PM UTC 24
Finished Sep 11 05:06:24 PM UTC 24
Peak memory 227880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263924064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.4263924064
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.1849613037
Short name T187
Test name
Test status
Simulation time 11848248026 ps
CPU time 109.89 seconds
Started Sep 11 05:06:11 PM UTC 24
Finished Sep 11 05:08:03 PM UTC 24
Peak memory 262096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849613037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.1849613037
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.3135822159
Short name T68
Test name
Test status
Simulation time 25990819604 ps
CPU time 110.51 seconds
Started Sep 11 05:08:02 PM UTC 24
Finished Sep 11 05:09:54 PM UTC 24
Peak memory 276512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135822159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3135822159
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.1369276139
Short name T1
Test name
Test status
Simulation time 31397492 ps
CPU time 0.81 seconds
Started Sep 11 05:06:10 PM UTC 24
Finished Sep 11 05:06:12 PM UTC 24
Peak memory 226828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369276139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1369276139
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.874891972
Short name T66
Test name
Test status
Simulation time 38370293963 ps
CPU time 160.99 seconds
Started Sep 11 05:06:16 PM UTC 24
Finished Sep 11 05:09:00 PM UTC 24
Peak memory 268296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874891972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.874891972
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.2667514461
Short name T7
Test name
Test status
Simulation time 224373343 ps
CPU time 1 seconds
Started Sep 11 05:06:11 PM UTC 24
Finished Sep 11 05:06:13 PM UTC 24
Peak memory 257352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667514461 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2667514461
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.276325281
Short name T261
Test name
Test status
Simulation time 135740179130 ps
CPU time 391.16 seconds
Started Sep 11 05:08:05 PM UTC 24
Finished Sep 11 05:14:41 PM UTC 24
Peak memory 278476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276325281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.276325281
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.3133814274
Short name T223
Test name
Test status
Simulation time 50282734224 ps
CPU time 377.41 seconds
Started Sep 11 05:07:39 PM UTC 24
Finished Sep 11 05:14:02 PM UTC 24
Peak memory 268392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133814274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.3133814274
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.1357620099
Short name T389
Test name
Test status
Simulation time 13498429756 ps
CPU time 28.68 seconds
Started Sep 11 05:07:47 PM UTC 24
Finished Sep 11 05:08:16 PM UTC 24
Peak memory 227964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357620099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1357620099
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.3885812370
Short name T50
Test name
Test status
Simulation time 30825557984 ps
CPU time 162.31 seconds
Started Sep 11 05:09:07 PM UTC 24
Finished Sep 11 05:11:52 PM UTC 24
Peak memory 278552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885812370 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.3885812370
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_stress_all.2459193768
Short name T225
Test name
Test status
Simulation time 38830500141 ps
CPU time 206.9 seconds
Started Sep 11 05:11:13 PM UTC 24
Finished Sep 11 05:14:43 PM UTC 24
Peak memory 282648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459193768 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.2459193768
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.977584105
Short name T122
Test name
Test status
Simulation time 212478938 ps
CPU time 12.15 seconds
Started Sep 11 06:47:09 PM UTC 24
Finished Sep 11 06:47:22 PM UTC 24
Peak memory 226512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977584105 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.977584105
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3666524725
Short name T140
Test name
Test status
Simulation time 114811583 ps
CPU time 2.53 seconds
Started Sep 11 06:47:08 PM UTC 24
Finished Sep 11 06:47:12 PM UTC 24
Peak memory 224132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666524725 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3666524725
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.704888857
Short name T359
Test name
Test status
Simulation time 39068437386 ps
CPU time 391.53 seconds
Started Sep 11 05:12:16 PM UTC 24
Finished Sep 11 05:18:53 PM UTC 24
Peak memory 284604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704888857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.704888857
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.2484773851
Short name T331
Test name
Test status
Simulation time 15281331032 ps
CPU time 122.7 seconds
Started Sep 11 05:13:00 PM UTC 24
Finished Sep 11 05:15:05 PM UTC 24
Peak memory 280768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484773851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.2484773851
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.912907353
Short name T130
Test name
Test status
Simulation time 719447066 ps
CPU time 5.1 seconds
Started Sep 11 06:47:27 PM UTC 24
Finished Sep 11 06:47:33 PM UTC 24
Peak memory 224276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912907353 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.912907353
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.795477000
Short name T205
Test name
Test status
Simulation time 4336112912 ps
CPU time 94.23 seconds
Started Sep 11 05:07:59 PM UTC 24
Finished Sep 11 05:09:36 PM UTC 24
Peak memory 262088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795477000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.795477000
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.1487871622
Short name T5
Test name
Test status
Simulation time 26451410 ps
CPU time 1.17 seconds
Started Sep 11 05:06:10 PM UTC 24
Finished Sep 11 05:06:12 PM UTC 24
Peak memory 229192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487871622 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_parity.1487871622
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.3702272571
Short name T65
Test name
Test status
Simulation time 4447682100 ps
CPU time 105.35 seconds
Started Sep 11 05:06:16 PM UTC 24
Finished Sep 11 05:08:03 PM UTC 24
Peak memory 264452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702272571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3702272571
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.4159928331
Short name T211
Test name
Test status
Simulation time 126415818151 ps
CPU time 213.96 seconds
Started Sep 11 05:16:34 PM UTC 24
Finished Sep 11 05:20:12 PM UTC 24
Peak memory 262272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159928331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.4159928331
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.2806733291
Short name T89
Test name
Test status
Simulation time 3053132126 ps
CPU time 58.13 seconds
Started Sep 11 05:06:25 PM UTC 24
Finished Sep 11 05:07:25 PM UTC 24
Peak memory 266268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806733291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2806733291
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.640523471
Short name T399
Test name
Test status
Simulation time 3894142349 ps
CPU time 44.67 seconds
Started Sep 11 05:10:27 PM UTC 24
Finished Sep 11 05:11:13 PM UTC 24
Peak memory 252092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640523471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.640523471
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.239905550
Short name T74
Test name
Test status
Simulation time 46406770192 ps
CPU time 211.98 seconds
Started Sep 11 05:12:37 PM UTC 24
Finished Sep 11 05:16:12 PM UTC 24
Peak memory 278524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239905550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.239905550
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.386997870
Short name T171
Test name
Test status
Simulation time 219337439904 ps
CPU time 159.16 seconds
Started Sep 11 05:12:02 PM UTC 24
Finished Sep 11 05:14:45 PM UTC 24
Peak memory 278548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386997870 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.386997870
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.797495358
Short name T218
Test name
Test status
Simulation time 24407429931 ps
CPU time 248.73 seconds
Started Sep 11 05:06:25 PM UTC 24
Finished Sep 11 05:10:37 PM UTC 24
Peak memory 278660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797495358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.797495358
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.2700515618
Short name T375
Test name
Test status
Simulation time 129605537041 ps
CPU time 347.37 seconds
Started Sep 11 05:15:56 PM UTC 24
Finished Sep 11 05:21:48 PM UTC 24
Peak memory 268444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700515618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.2700515618
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.375777156
Short name T37
Test name
Test status
Simulation time 6768901768 ps
CPU time 27.21 seconds
Started Sep 11 05:07:09 PM UTC 24
Finished Sep 11 05:07:38 PM UTC 24
Peak memory 251928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375777156 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.375777156
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.3781831608
Short name T67
Test name
Test status
Simulation time 2146858651 ps
CPU time 44.83 seconds
Started Sep 11 05:08:30 PM UTC 24
Finished Sep 11 05:09:16 PM UTC 24
Peak memory 278476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781831608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.3781831608
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.1278810751
Short name T6
Test name
Test status
Simulation time 29593043 ps
CPU time 0.99 seconds
Started Sep 11 05:06:11 PM UTC 24
Finished Sep 11 05:06:13 PM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278810751 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1278810751
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.466658184
Short name T249
Test name
Test status
Simulation time 1515166930 ps
CPU time 23.26 seconds
Started Sep 11 05:07:59 PM UTC 24
Finished Sep 11 05:08:24 PM UTC 24
Peak memory 245576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466658184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.466658184
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.95308756
Short name T22
Test name
Test status
Simulation time 298164137 ps
CPU time 6.05 seconds
Started Sep 11 05:06:14 PM UTC 24
Finished Sep 11 05:06:21 PM UTC 24
Peak memory 245544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95308756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.95308756
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.2963538832
Short name T196
Test name
Test status
Simulation time 4182839202 ps
CPU time 14.9 seconds
Started Sep 11 06:47:41 PM UTC 24
Finished Sep 11 06:47:57 PM UTC 24
Peak memory 224176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963538832 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.2963538832
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.1130915927
Short name T397
Test name
Test status
Simulation time 35456808428 ps
CPU time 77.71 seconds
Started Sep 11 05:08:37 PM UTC 24
Finished Sep 11 05:09:57 PM UTC 24
Peak memory 245756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130915927 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.1130915927
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.3215631936
Short name T367
Test name
Test status
Simulation time 139994113122 ps
CPU time 647.63 seconds
Started Sep 11 05:10:28 PM UTC 24
Finished Sep 11 05:21:24 PM UTC 24
Peak memory 266240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215631936 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.3215631936
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_stress_all.2949125227
Short name T78
Test name
Test status
Simulation time 120444990076 ps
CPU time 1127.54 seconds
Started Sep 11 05:15:44 PM UTC 24
Finished Sep 11 05:34:44 PM UTC 24
Peak memory 294908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949125227 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.2949125227
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/29.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_stress_all.452455405
Short name T324
Test name
Test status
Simulation time 5006164913 ps
CPU time 145.14 seconds
Started Sep 11 05:12:20 PM UTC 24
Finished Sep 11 05:14:48 PM UTC 24
Peak memory 280592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452455405 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.452455405
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.663426650
Short name T865
Test name
Test status
Simulation time 462794934 ps
CPU time 20.62 seconds
Started Sep 11 05:19:23 PM UTC 24
Finished Sep 11 05:19:45 PM UTC 24
Peak memory 251516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663426650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.663426650
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/41.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.2793241370
Short name T181
Test name
Test status
Simulation time 14162808083 ps
CPU time 71.28 seconds
Started Sep 11 05:10:23 PM UTC 24
Finished Sep 11 05:11:36 PM UTC 24
Peak memory 278468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793241370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.2793241370
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1741755493
Short name T118
Test name
Test status
Simulation time 178447285 ps
CPU time 4.9 seconds
Started Sep 11 06:47:09 PM UTC 24
Finished Sep 11 06:47:15 PM UTC 24
Peak memory 226256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741755493 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1741755493
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.3454889064
Short name T77
Test name
Test status
Simulation time 100252711602 ps
CPU time 1221.82 seconds
Started Sep 11 05:06:18 PM UTC 24
Finished Sep 11 05:26:55 PM UTC 24
Peak memory 294604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454889064 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.3454889064
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.2896539756
Short name T355
Test name
Test status
Simulation time 408828796064 ps
CPU time 960.42 seconds
Started Sep 11 05:09:32 PM UTC 24
Finished Sep 11 05:25:44 PM UTC 24
Peak memory 301084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896539756 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.2896539756
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.2890348251
Short name T172
Test name
Test status
Simulation time 10483023162 ps
CPU time 38.55 seconds
Started Sep 11 05:14:47 PM UTC 24
Finished Sep 11 05:15:27 PM UTC 24
Peak memory 262152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890348251 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.2890348251
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/26.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.672013089
Short name T362
Test name
Test status
Simulation time 41111760128 ps
CPU time 99.74 seconds
Started Sep 11 05:20:11 PM UTC 24
Finished Sep 11 05:21:53 PM UTC 24
Peak memory 262108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672013089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.672013089
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/43.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.1187276947
Short name T51
Test name
Test status
Simulation time 4684340684 ps
CPU time 58.04 seconds
Started Sep 11 05:06:11 PM UTC 24
Finished Sep 11 05:07:11 PM UTC 24
Peak memory 262068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187276947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1187276947
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.1505338095
Short name T46
Test name
Test status
Simulation time 10213858370 ps
CPU time 31.52 seconds
Started Sep 11 05:06:10 PM UTC 24
Finished Sep 11 05:06:43 PM UTC 24
Peak memory 227876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505338095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1505338095
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.3106566183
Short name T393
Test name
Test status
Simulation time 4132970389 ps
CPU time 20.59 seconds
Started Sep 11 05:09:26 PM UTC 24
Finished Sep 11 05:09:48 PM UTC 24
Peak memory 232116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106566183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.3106566183
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.3157599532
Short name T97
Test name
Test status
Simulation time 17078439274 ps
CPU time 77.45 seconds
Started Sep 11 05:09:53 PM UTC 24
Finished Sep 11 05:11:13 PM UTC 24
Peak memory 262112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157599532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3157599532
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.2905180398
Short name T319
Test name
Test status
Simulation time 101270911060 ps
CPU time 285.99 seconds
Started Sep 11 05:09:56 PM UTC 24
Finished Sep 11 05:14:46 PM UTC 24
Peak memory 266436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905180398 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.2905180398
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.2865220256
Short name T326
Test name
Test status
Simulation time 38730433951 ps
CPU time 149.57 seconds
Started Sep 11 05:14:46 PM UTC 24
Finished Sep 11 05:17:18 PM UTC 24
Peak memory 284672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865220256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.2865220256
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.3908885426
Short name T111
Test name
Test status
Simulation time 1073551074 ps
CPU time 7.54 seconds
Started Sep 11 05:13:44 PM UTC 24
Finished Sep 11 05:13:53 PM UTC 24
Peak memory 233924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908885426 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.3908885426
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/23.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.2299782510
Short name T1083
Test name
Test status
Simulation time 499879276 ps
CPU time 4.88 seconds
Started Sep 11 06:47:32 PM UTC 24
Finished Sep 11 06:47:38 PM UTC 24
Peak memory 224380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299782510 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.2299782510
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.2528703908
Short name T56
Test name
Test status
Simulation time 13860578766 ps
CPU time 32.4 seconds
Started Sep 11 05:06:10 PM UTC 24
Finished Sep 11 05:06:44 PM UTC 24
Peak memory 245704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528703908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2528703908
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1853647099
Short name T101
Test name
Test status
Simulation time 43170931 ps
CPU time 1.82 seconds
Started Sep 11 06:47:13 PM UTC 24
Finished Sep 11 06:47:16 PM UTC 24
Peak memory 225512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853647099 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.1853647099
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.2677779763
Short name T43
Test name
Test status
Simulation time 153465620216 ps
CPU time 268.16 seconds
Started Sep 11 05:15:03 PM UTC 24
Finished Sep 11 05:19:35 PM UTC 24
Peak memory 278520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677779763 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.2677779763
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/27.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.3918507867
Short name T149
Test name
Test status
Simulation time 4106225318 ps
CPU time 20.27 seconds
Started Sep 11 06:47:09 PM UTC 24
Finished Sep 11 06:47:30 PM UTC 24
Peak memory 224104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918507867 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.3918507867
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.807399611
Short name T150
Test name
Test status
Simulation time 837510992 ps
CPU time 21.34 seconds
Started Sep 11 06:47:09 PM UTC 24
Finished Sep 11 06:47:31 PM UTC 24
Peak memory 224048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807399611 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.807399611
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.222200666
Short name T1038
Test name
Test status
Simulation time 23328316 ps
CPU time 1.18 seconds
Started Sep 11 06:47:08 PM UTC 24
Finished Sep 11 06:47:11 PM UTC 24
Peak memory 213348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222200666 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.222200666
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.626117268
Short name T116
Test name
Test status
Simulation time 204607151 ps
CPU time 2.35 seconds
Started Sep 11 06:47:09 PM UTC 24
Finished Sep 11 06:47:12 PM UTC 24
Peak memory 224308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=626117268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.spi_device_csr_mem_rw_with_rand_reset.626117268
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2800605651
Short name T1037
Test name
Test status
Simulation time 13011464 ps
CPU time 1.11 seconds
Started Sep 11 06:47:08 PM UTC 24
Finished Sep 11 06:47:10 PM UTC 24
Peak memory 211120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800605651 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2800605651
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1880867671
Short name T139
Test name
Test status
Simulation time 99838970 ps
CPU time 1.79 seconds
Started Sep 11 06:47:08 PM UTC 24
Finished Sep 11 06:47:11 PM UTC 24
Peak memory 222920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880867671 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.1880867671
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.3484894195
Short name T1036
Test name
Test status
Simulation time 10681497 ps
CPU time 0.98 seconds
Started Sep 11 06:47:08 PM UTC 24
Finished Sep 11 06:47:10 PM UTC 24
Peak memory 211368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484894195 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.3484894195
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.280217111
Short name T155
Test name
Test status
Simulation time 575424951 ps
CPU time 3.2 seconds
Started Sep 11 06:47:09 PM UTC 24
Finished Sep 11 06:47:13 PM UTC 24
Peak memory 226344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280217111 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstanding.280217111
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.434731873
Short name T117
Test name
Test status
Simulation time 162448411 ps
CPU time 5.02 seconds
Started Sep 11 06:47:07 PM UTC 24
Finished Sep 11 06:47:13 PM UTC 24
Peak memory 224184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434731873 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.434731873
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.2707667424
Short name T119
Test name
Test status
Simulation time 281125541 ps
CPU time 7.84 seconds
Started Sep 11 06:47:07 PM UTC 24
Finished Sep 11 06:47:16 PM UTC 24
Peak memory 224068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707667424 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.2707667424
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.1595678735
Short name T1070
Test name
Test status
Simulation time 314055068 ps
CPU time 18.43 seconds
Started Sep 11 06:47:11 PM UTC 24
Finished Sep 11 06:47:31 PM UTC 24
Peak memory 226180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595678735 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.1595678735
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3894070422
Short name T1140
Test name
Test status
Simulation time 2708443811 ps
CPU time 36.45 seconds
Started Sep 11 06:47:10 PM UTC 24
Finished Sep 11 06:47:49 PM UTC 24
Peak memory 213852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894070422 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.3894070422
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2847859099
Short name T100
Test name
Test status
Simulation time 44770818 ps
CPU time 1.14 seconds
Started Sep 11 06:47:10 PM UTC 24
Finished Sep 11 06:47:13 PM UTC 24
Peak memory 213172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847859099 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.2847859099
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.3259545338
Short name T156
Test name
Test status
Simulation time 1311487545 ps
CPU time 2.85 seconds
Started Sep 11 06:47:10 PM UTC 24
Finished Sep 11 06:47:15 PM UTC 24
Peak memory 224120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259545338 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3259545338
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.223709893
Short name T1039
Test name
Test status
Simulation time 34187866 ps
CPU time 0.98 seconds
Started Sep 11 06:47:10 PM UTC 24
Finished Sep 11 06:47:12 PM UTC 24
Peak memory 211392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223709893 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.223709893
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.90108948
Short name T141
Test name
Test status
Simulation time 29866245 ps
CPU time 2.14 seconds
Started Sep 11 06:47:10 PM UTC 24
Finished Sep 11 06:47:14 PM UTC 24
Peak memory 224324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90108948 -assert nopostpro
c +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.90108948
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.600794191
Short name T1040
Test name
Test status
Simulation time 11808117 ps
CPU time 1.01 seconds
Started Sep 11 06:47:10 PM UTC 24
Finished Sep 11 06:47:13 PM UTC 24
Peak memory 211376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600794191 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.600794191
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.762527915
Short name T157
Test name
Test status
Simulation time 142350309 ps
CPU time 3.42 seconds
Started Sep 11 06:47:11 PM UTC 24
Finished Sep 11 06:47:16 PM UTC 24
Peak memory 224308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762527915 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstanding.762527915
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.159568393
Short name T1074
Test name
Test status
Simulation time 26028498 ps
CPU time 1.51 seconds
Started Sep 11 06:47:31 PM UTC 24
Finished Sep 11 06:47:34 PM UTC 24
Peak memory 222972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=159568393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
10.spi_device_csr_mem_rw_with_rand_reset.159568393
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.3076523763
Short name T143
Test name
Test status
Simulation time 142368882 ps
CPU time 1.77 seconds
Started Sep 11 06:47:30 PM UTC 24
Finished Sep 11 06:47:33 PM UTC 24
Peak memory 222856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076523763 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.3076523763
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.840039123
Short name T1071
Test name
Test status
Simulation time 103426591 ps
CPU time 1.05 seconds
Started Sep 11 06:47:30 PM UTC 24
Finished Sep 11 06:47:32 PM UTC 24
Peak memory 211452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840039123 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.840039123
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.907505967
Short name T168
Test name
Test status
Simulation time 573940647 ps
CPU time 3.89 seconds
Started Sep 11 06:47:31 PM UTC 24
Finished Sep 11 06:47:36 PM UTC 24
Peak memory 224064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907505967 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstanding.907505967
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.2917149985
Short name T134
Test name
Test status
Simulation time 61832044 ps
CPU time 4.77 seconds
Started Sep 11 06:47:29 PM UTC 24
Finished Sep 11 06:47:36 PM UTC 24
Peak memory 226252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917149985 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.2917149985
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.1171182521
Short name T199
Test name
Test status
Simulation time 3488922847 ps
CPU time 7.35 seconds
Started Sep 11 06:47:30 PM UTC 24
Finished Sep 11 06:47:38 PM UTC 24
Peak memory 224328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171182521 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.1171182521
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1825218275
Short name T1078
Test name
Test status
Simulation time 27415633 ps
CPU time 1.91 seconds
Started Sep 11 06:47:32 PM UTC 24
Finished Sep 11 06:47:35 PM UTC 24
Peak memory 225032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1825218275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
11.spi_device_csr_mem_rw_with_rand_reset.1825218275
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.758263187
Short name T166
Test name
Test status
Simulation time 41588255 ps
CPU time 1.82 seconds
Started Sep 11 06:47:32 PM UTC 24
Finished Sep 11 06:47:35 PM UTC 24
Peak memory 222856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758263187 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.758263187
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.64194814
Short name T1047
Test name
Test status
Simulation time 11857908 ps
CPU time 0.84 seconds
Started Sep 11 06:47:31 PM UTC 24
Finished Sep 11 06:47:33 PM UTC 24
Peak memory 211368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64194814 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.64194814
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4042829419
Short name T1077
Test name
Test status
Simulation time 98882460 ps
CPU time 1.75 seconds
Started Sep 11 06:47:32 PM UTC 24
Finished Sep 11 06:47:35 PM UTC 24
Peak memory 223508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042829419 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstanding.4042829419
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.2681561607
Short name T1076
Test name
Test status
Simulation time 347403360 ps
CPU time 2.73 seconds
Started Sep 11 06:47:31 PM UTC 24
Finished Sep 11 06:47:35 PM UTC 24
Peak memory 224132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681561607 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.2681561607
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.1113457646
Short name T203
Test name
Test status
Simulation time 1415034487 ps
CPU time 13.63 seconds
Started Sep 11 06:47:31 PM UTC 24
Finished Sep 11 06:47:46 PM UTC 24
Peak memory 224376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113457646 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.1113457646
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2852906142
Short name T1080
Test name
Test status
Simulation time 25725113 ps
CPU time 2.39 seconds
Started Sep 11 06:47:34 PM UTC 24
Finished Sep 11 06:47:37 PM UTC 24
Peak memory 226444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2852906142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
12.spi_device_csr_mem_rw_with_rand_reset.2852906142
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.839825897
Short name T167
Test name
Test status
Simulation time 70830960 ps
CPU time 2.29 seconds
Started Sep 11 06:47:32 PM UTC 24
Finished Sep 11 06:47:36 PM UTC 24
Peak memory 224128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839825897 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.839825897
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.3332569070
Short name T1075
Test name
Test status
Simulation time 15027055 ps
CPU time 1.06 seconds
Started Sep 11 06:47:32 PM UTC 24
Finished Sep 11 06:47:35 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332569070 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.3332569070
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2923185048
Short name T169
Test name
Test status
Simulation time 299617573 ps
CPU time 3.76 seconds
Started Sep 11 06:47:34 PM UTC 24
Finished Sep 11 06:47:38 PM UTC 24
Peak memory 224184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923185048 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstanding.2923185048
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.2103553702
Short name T200
Test name
Test status
Simulation time 3900850982 ps
CPU time 13.4 seconds
Started Sep 11 06:47:32 PM UTC 24
Finished Sep 11 06:47:47 PM UTC 24
Peak memory 226444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103553702 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.2103553702
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1094632217
Short name T1087
Test name
Test status
Simulation time 41826184 ps
CPU time 3.01 seconds
Started Sep 11 06:47:35 PM UTC 24
Finished Sep 11 06:47:39 PM UTC 24
Peak memory 226240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1094632217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
13.spi_device_csr_mem_rw_with_rand_reset.1094632217
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.3489647991
Short name T151
Test name
Test status
Simulation time 63372734 ps
CPU time 1.92 seconds
Started Sep 11 06:47:35 PM UTC 24
Finished Sep 11 06:47:38 PM UTC 24
Peak memory 222856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489647991 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.3489647991
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.2694087619
Short name T1079
Test name
Test status
Simulation time 54583780 ps
CPU time 1.12 seconds
Started Sep 11 06:47:34 PM UTC 24
Finished Sep 11 06:47:36 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694087619 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.2694087619
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.639780846
Short name T1084
Test name
Test status
Simulation time 91354169 ps
CPU time 2.37 seconds
Started Sep 11 06:47:35 PM UTC 24
Finished Sep 11 06:47:38 PM UTC 24
Peak memory 213644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639780846 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstanding.639780846
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.1302339274
Short name T1090
Test name
Test status
Simulation time 221029595 ps
CPU time 5.5 seconds
Started Sep 11 06:47:34 PM UTC 24
Finished Sep 11 06:47:40 PM UTC 24
Peak memory 226316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302339274 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.1302339274
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.4161785368
Short name T1120
Test name
Test status
Simulation time 207407278 ps
CPU time 11.26 seconds
Started Sep 11 06:47:34 PM UTC 24
Finished Sep 11 06:47:46 PM UTC 24
Peak memory 226180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161785368 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.4161785368
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2415194539
Short name T1092
Test name
Test status
Simulation time 118423274 ps
CPU time 2.68 seconds
Started Sep 11 06:47:37 PM UTC 24
Finished Sep 11 06:47:40 PM UTC 24
Peak memory 228288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2415194539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
14.spi_device_csr_mem_rw_with_rand_reset.2415194539
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.2387413853
Short name T1093
Test name
Test status
Simulation time 97630636 ps
CPU time 3.13 seconds
Started Sep 11 06:47:37 PM UTC 24
Finished Sep 11 06:47:41 PM UTC 24
Peak memory 224124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387413853 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.2387413853
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.1693397681
Short name T1085
Test name
Test status
Simulation time 18654917 ps
CPU time 1.15 seconds
Started Sep 11 06:47:37 PM UTC 24
Finished Sep 11 06:47:39 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693397681 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.1693397681
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1317268936
Short name T1097
Test name
Test status
Simulation time 807480978 ps
CPU time 4.27 seconds
Started Sep 11 06:47:37 PM UTC 24
Finished Sep 11 06:47:42 PM UTC 24
Peak memory 224336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317268936 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstanding.1317268936
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.1731551104
Short name T1088
Test name
Test status
Simulation time 157429129 ps
CPU time 3.93 seconds
Started Sep 11 06:47:35 PM UTC 24
Finished Sep 11 06:47:40 PM UTC 24
Peak memory 224244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731551104 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.1731551104
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.802905723
Short name T1148
Test name
Test status
Simulation time 588438271 ps
CPU time 12.44 seconds
Started Sep 11 06:47:37 PM UTC 24
Finished Sep 11 06:47:50 PM UTC 24
Peak memory 226104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802905723 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.802905723
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2112228353
Short name T1101
Test name
Test status
Simulation time 578799483 ps
CPU time 3.97 seconds
Started Sep 11 06:47:38 PM UTC 24
Finished Sep 11 06:47:43 PM UTC 24
Peak memory 226240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2112228353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
15.spi_device_csr_mem_rw_with_rand_reset.2112228353
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.657841928
Short name T1089
Test name
Test status
Simulation time 125666794 ps
CPU time 2.36 seconds
Started Sep 11 06:47:37 PM UTC 24
Finished Sep 11 06:47:40 PM UTC 24
Peak memory 213600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657841928 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.657841928
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.3795051186
Short name T1086
Test name
Test status
Simulation time 39085027 ps
CPU time 0.96 seconds
Started Sep 11 06:47:37 PM UTC 24
Finished Sep 11 06:47:39 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795051186 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.3795051186
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.512725531
Short name T1091
Test name
Test status
Simulation time 612581077 ps
CPU time 2.47 seconds
Started Sep 11 06:47:37 PM UTC 24
Finished Sep 11 06:47:40 PM UTC 24
Peak memory 213856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512725531 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstanding.512725531
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.204750630
Short name T1094
Test name
Test status
Simulation time 174190958 ps
CPU time 3.29 seconds
Started Sep 11 06:47:37 PM UTC 24
Finished Sep 11 06:47:41 PM UTC 24
Peak memory 224468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204750630 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.204750630
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.917024816
Short name T1117
Test name
Test status
Simulation time 338568182 ps
CPU time 7.3 seconds
Started Sep 11 06:47:37 PM UTC 24
Finished Sep 11 06:47:45 PM UTC 24
Peak memory 224056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917024816 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.917024816
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.878121479
Short name T1112
Test name
Test status
Simulation time 175592498 ps
CPU time 4.1 seconds
Started Sep 11 06:47:40 PM UTC 24
Finished Sep 11 06:47:45 PM UTC 24
Peak memory 228224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=878121479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.spi_device_csr_mem_rw_with_rand_reset.878121479
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.1394393189
Short name T153
Test name
Test status
Simulation time 97518251 ps
CPU time 1.63 seconds
Started Sep 11 06:47:40 PM UTC 24
Finished Sep 11 06:47:42 PM UTC 24
Peak memory 222856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394393189 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.1394393189
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.1859889001
Short name T1095
Test name
Test status
Simulation time 26527051 ps
CPU time 1.15 seconds
Started Sep 11 06:47:40 PM UTC 24
Finished Sep 11 06:47:42 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859889001 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.1859889001
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2069334208
Short name T1099
Test name
Test status
Simulation time 97519145 ps
CPU time 1.82 seconds
Started Sep 11 06:47:40 PM UTC 24
Finished Sep 11 06:47:43 PM UTC 24
Peak memory 223596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069334208 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstanding.2069334208
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.1192258855
Short name T1103
Test name
Test status
Simulation time 663872944 ps
CPU time 3.96 seconds
Started Sep 11 06:47:38 PM UTC 24
Finished Sep 11 06:47:43 PM UTC 24
Peak memory 226308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192258855 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.1192258855
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.3680500876
Short name T201
Test name
Test status
Simulation time 2103067177 ps
CPU time 13.24 seconds
Started Sep 11 06:47:38 PM UTC 24
Finished Sep 11 06:47:53 PM UTC 24
Peak memory 226376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680500876 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.3680500876
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3423159072
Short name T1123
Test name
Test status
Simulation time 103874676 ps
CPU time 4.1 seconds
Started Sep 11 06:47:41 PM UTC 24
Finished Sep 11 06:47:47 PM UTC 24
Peak memory 226312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3423159072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
17.spi_device_csr_mem_rw_with_rand_reset.3423159072
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.442792988
Short name T1098
Test name
Test status
Simulation time 19547117 ps
CPU time 1.22 seconds
Started Sep 11 06:47:40 PM UTC 24
Finished Sep 11 06:47:42 PM UTC 24
Peak memory 212636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442792988 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.442792988
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.3112930617
Short name T1096
Test name
Test status
Simulation time 43638037 ps
CPU time 0.98 seconds
Started Sep 11 06:47:40 PM UTC 24
Finished Sep 11 06:47:42 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112930617 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.3112930617
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.627275966
Short name T1100
Test name
Test status
Simulation time 169121292 ps
CPU time 1.91 seconds
Started Sep 11 06:47:40 PM UTC 24
Finished Sep 11 06:47:43 PM UTC 24
Peak memory 223528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627275966 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstanding.627275966
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.1475567744
Short name T1119
Test name
Test status
Simulation time 663833697 ps
CPU time 4.55 seconds
Started Sep 11 06:47:40 PM UTC 24
Finished Sep 11 06:47:45 PM UTC 24
Peak memory 224224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475567744 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.1475567744
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.2958197306
Short name T1150
Test name
Test status
Simulation time 4924886373 ps
CPU time 13.02 seconds
Started Sep 11 06:47:40 PM UTC 24
Finished Sep 11 06:47:54 PM UTC 24
Peak memory 226164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958197306 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.2958197306
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3041639707
Short name T1108
Test name
Test status
Simulation time 61486572 ps
CPU time 1.7 seconds
Started Sep 11 06:47:42 PM UTC 24
Finished Sep 11 06:47:44 PM UTC 24
Peak memory 222984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3041639707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
18.spi_device_csr_mem_rw_with_rand_reset.3041639707
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.2054618132
Short name T1110
Test name
Test status
Simulation time 267269345 ps
CPU time 2.25 seconds
Started Sep 11 06:47:42 PM UTC 24
Finished Sep 11 06:47:45 PM UTC 24
Peak memory 224320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054618132 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.2054618132
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.2110867157
Short name T1104
Test name
Test status
Simulation time 24646410 ps
CPU time 1.07 seconds
Started Sep 11 06:47:42 PM UTC 24
Finished Sep 11 06:47:44 PM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110867157 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.2110867157
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3394697232
Short name T1109
Test name
Test status
Simulation time 29977871 ps
CPU time 1.77 seconds
Started Sep 11 06:47:42 PM UTC 24
Finished Sep 11 06:47:44 PM UTC 24
Peak memory 225180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394697232 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstanding.3394697232
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.1612094247
Short name T193
Test name
Test status
Simulation time 159273926 ps
CPU time 4.71 seconds
Started Sep 11 06:47:41 PM UTC 24
Finished Sep 11 06:47:47 PM UTC 24
Peak memory 226292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612094247 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.1612094247
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1788232603
Short name T1082
Test name
Test status
Simulation time 133094048 ps
CPU time 3.37 seconds
Started Sep 11 06:47:43 PM UTC 24
Finished Sep 11 06:47:47 PM UTC 24
Peak memory 226252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1788232603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
19.spi_device_csr_mem_rw_with_rand_reset.1788232603
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.743700112
Short name T1107
Test name
Test status
Simulation time 128777773 ps
CPU time 1.55 seconds
Started Sep 11 06:47:42 PM UTC 24
Finished Sep 11 06:47:44 PM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743700112 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.743700112
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.831062894
Short name T1105
Test name
Test status
Simulation time 41450493 ps
CPU time 0.97 seconds
Started Sep 11 06:47:42 PM UTC 24
Finished Sep 11 06:47:44 PM UTC 24
Peak memory 211392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831062894 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.831062894
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1133724159
Short name T1129
Test name
Test status
Simulation time 510132768 ps
CPU time 3.76 seconds
Started Sep 11 06:47:42 PM UTC 24
Finished Sep 11 06:47:47 PM UTC 24
Peak memory 224132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133724159 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstanding.1133724159
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.97989957
Short name T1106
Test name
Test status
Simulation time 413624726 ps
CPU time 1.56 seconds
Started Sep 11 06:47:42 PM UTC 24
Finished Sep 11 06:47:44 PM UTC 24
Peak memory 225036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97989957 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.97989957
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.4234200123
Short name T1146
Test name
Test status
Simulation time 1045519738 ps
CPU time 6.33 seconds
Started Sep 11 06:47:42 PM UTC 24
Finished Sep 11 06:47:49 PM UTC 24
Peak memory 226312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234200123 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.4234200123
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.2655016133
Short name T1054
Test name
Test status
Simulation time 427242215 ps
CPU time 7.79 seconds
Started Sep 11 06:47:14 PM UTC 24
Finished Sep 11 06:47:23 PM UTC 24
Peak memory 224144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655016133 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.2655016133
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3825130527
Short name T1081
Test name
Test status
Simulation time 1460824723 ps
CPU time 22.37 seconds
Started Sep 11 06:47:14 PM UTC 24
Finished Sep 11 06:47:37 PM UTC 24
Peak memory 213828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825130527 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.3825130527
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3306156140
Short name T135
Test name
Test status
Simulation time 123204974 ps
CPU time 3.41 seconds
Started Sep 11 06:47:14 PM UTC 24
Finished Sep 11 06:47:18 PM UTC 24
Peak memory 228060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3306156140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.spi_device_csr_mem_rw_with_rand_reset.3306156140
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.1191474654
Short name T1046
Test name
Test status
Simulation time 100880431 ps
CPU time 2.44 seconds
Started Sep 11 06:47:14 PM UTC 24
Finished Sep 11 06:47:17 PM UTC 24
Peak memory 224256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191474654 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1191474654
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.2136652974
Short name T1041
Test name
Test status
Simulation time 13443538 ps
CPU time 1.11 seconds
Started Sep 11 06:47:11 PM UTC 24
Finished Sep 11 06:47:14 PM UTC 24
Peak memory 211516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136652974 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2136652974
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.2070411857
Short name T142
Test name
Test status
Simulation time 73231073 ps
CPU time 2.9 seconds
Started Sep 11 06:47:13 PM UTC 24
Finished Sep 11 06:47:17 PM UTC 24
Peak memory 224324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070411857 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.2070411857
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.5557987
Short name T1042
Test name
Test status
Simulation time 12866096 ps
CPU time 1.01 seconds
Started Sep 11 06:47:11 PM UTC 24
Finished Sep 11 06:47:14 PM UTC 24
Peak memory 211444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5557987 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.5557987
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3371794142
Short name T158
Test name
Test status
Simulation time 27340592 ps
CPU time 2.16 seconds
Started Sep 11 06:47:14 PM UTC 24
Finished Sep 11 06:47:17 PM UTC 24
Peak memory 224032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371794142 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstanding.3371794142
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.2980386942
Short name T120
Test name
Test status
Simulation time 2458873109 ps
CPU time 3.53 seconds
Started Sep 11 06:47:11 PM UTC 24
Finished Sep 11 06:47:17 PM UTC 24
Peak memory 224236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980386942 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2980386942
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.1115460797
Short name T123
Test name
Test status
Simulation time 554899915 ps
CPU time 14.18 seconds
Started Sep 11 06:47:11 PM UTC 24
Finished Sep 11 06:47:27 PM UTC 24
Peak memory 226072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115460797 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.1115460797
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.898086267
Short name T1111
Test name
Test status
Simulation time 12221583 ps
CPU time 0.81 seconds
Started Sep 11 06:47:43 PM UTC 24
Finished Sep 11 06:47:45 PM UTC 24
Peak memory 211392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898086267 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.898086267
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/20.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.3374775475
Short name T1113
Test name
Test status
Simulation time 41303608 ps
CPU time 0.99 seconds
Started Sep 11 06:47:43 PM UTC 24
Finished Sep 11 06:47:45 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374775475 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.3374775475
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/21.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.3891465485
Short name T1116
Test name
Test status
Simulation time 45321261 ps
CPU time 1.05 seconds
Started Sep 11 06:47:43 PM UTC 24
Finished Sep 11 06:47:45 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891465485 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.3891465485
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/22.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1717263666
Short name T1114
Test name
Test status
Simulation time 15829057 ps
CPU time 0.92 seconds
Started Sep 11 06:47:43 PM UTC 24
Finished Sep 11 06:47:45 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717263666 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.1717263666
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/23.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.2340219654
Short name T1115
Test name
Test status
Simulation time 21613872 ps
CPU time 0.87 seconds
Started Sep 11 06:47:43 PM UTC 24
Finished Sep 11 06:47:45 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340219654 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.2340219654
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/24.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.3348456427
Short name T1118
Test name
Test status
Simulation time 40784608 ps
CPU time 1.01 seconds
Started Sep 11 06:47:43 PM UTC 24
Finished Sep 11 06:47:45 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348456427 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.3348456427
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/25.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.1866918334
Short name T1127
Test name
Test status
Simulation time 110067871 ps
CPU time 1.12 seconds
Started Sep 11 06:47:45 PM UTC 24
Finished Sep 11 06:47:47 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866918334 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.1866918334
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/26.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.474297628
Short name T1121
Test name
Test status
Simulation time 39386519 ps
CPU time 0.87 seconds
Started Sep 11 06:47:45 PM UTC 24
Finished Sep 11 06:47:46 PM UTC 24
Peak memory 211392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474297628 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.474297628
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/27.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.3885511007
Short name T1125
Test name
Test status
Simulation time 50147359 ps
CPU time 0.94 seconds
Started Sep 11 06:47:45 PM UTC 24
Finished Sep 11 06:47:47 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885511007 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.3885511007
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/28.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.2511520677
Short name T1122
Test name
Test status
Simulation time 35473768 ps
CPU time 0.83 seconds
Started Sep 11 06:47:45 PM UTC 24
Finished Sep 11 06:47:47 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511520677 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.2511520677
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/29.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.4294695273
Short name T147
Test name
Test status
Simulation time 1226902791 ps
CPU time 9.48 seconds
Started Sep 11 06:47:16 PM UTC 24
Finished Sep 11 06:47:27 PM UTC 24
Peak memory 213892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294695273 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.4294695273
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.603487662
Short name T1063
Test name
Test status
Simulation time 743257248 ps
CPU time 10.34 seconds
Started Sep 11 06:47:16 PM UTC 24
Finished Sep 11 06:47:28 PM UTC 24
Peak memory 213824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603487662 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.603487662
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2440926292
Short name T102
Test name
Test status
Simulation time 23334395 ps
CPU time 1.13 seconds
Started Sep 11 06:47:15 PM UTC 24
Finished Sep 11 06:47:17 PM UTC 24
Peak memory 213052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440926292 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.2440926292
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2546944849
Short name T132
Test name
Test status
Simulation time 105287592 ps
CPU time 3.98 seconds
Started Sep 11 06:47:18 PM UTC 24
Finished Sep 11 06:47:23 PM UTC 24
Peak memory 226216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2546944849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.spi_device_csr_mem_rw_with_rand_reset.2546944849
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.2431849957
Short name T145
Test name
Test status
Simulation time 37105322 ps
CPU time 3.04 seconds
Started Sep 11 06:47:16 PM UTC 24
Finished Sep 11 06:47:21 PM UTC 24
Peak memory 224104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431849957 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2431849957
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.2918936469
Short name T1043
Test name
Test status
Simulation time 14072235 ps
CPU time 1.07 seconds
Started Sep 11 06:47:15 PM UTC 24
Finished Sep 11 06:47:17 PM UTC 24
Peak memory 211516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918936469 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2918936469
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.2869251448
Short name T144
Test name
Test status
Simulation time 33231402 ps
CPU time 1.63 seconds
Started Sep 11 06:47:15 PM UTC 24
Finished Sep 11 06:47:18 PM UTC 24
Peak memory 222920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869251448 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.2869251448
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.2395732795
Short name T1045
Test name
Test status
Simulation time 62935327 ps
CPU time 1 seconds
Started Sep 11 06:47:15 PM UTC 24
Finished Sep 11 06:47:17 PM UTC 24
Peak memory 211444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395732795 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.2395732795
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.222946644
Short name T1050
Test name
Test status
Simulation time 384642880 ps
CPU time 3 seconds
Started Sep 11 06:47:16 PM UTC 24
Finished Sep 11 06:47:21 PM UTC 24
Peak memory 224112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222946644 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstanding.222946644
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.3849648351
Short name T121
Test name
Test status
Simulation time 534737193 ps
CPU time 3.55 seconds
Started Sep 11 06:47:14 PM UTC 24
Finished Sep 11 06:47:19 PM UTC 24
Peak memory 226580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849648351 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3849648351
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1968454227
Short name T198
Test name
Test status
Simulation time 4576731245 ps
CPU time 19.36 seconds
Started Sep 11 06:47:14 PM UTC 24
Finished Sep 11 06:47:35 PM UTC 24
Peak memory 224192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968454227 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.1968454227
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.887728522
Short name T1126
Test name
Test status
Simulation time 14535849 ps
CPU time 0.88 seconds
Started Sep 11 06:47:45 PM UTC 24
Finished Sep 11 06:47:47 PM UTC 24
Peak memory 211452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887728522 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.887728522
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/30.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.93038108
Short name T1130
Test name
Test status
Simulation time 16766324 ps
CPU time 1.13 seconds
Started Sep 11 06:47:45 PM UTC 24
Finished Sep 11 06:47:47 PM UTC 24
Peak memory 211392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93038108 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.93038108
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/31.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.1747515577
Short name T1128
Test name
Test status
Simulation time 37730072 ps
CPU time 0.86 seconds
Started Sep 11 06:47:45 PM UTC 24
Finished Sep 11 06:47:47 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747515577 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.1747515577
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/32.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.1971637271
Short name T1132
Test name
Test status
Simulation time 16795305 ps
CPU time 0.84 seconds
Started Sep 11 06:47:46 PM UTC 24
Finished Sep 11 06:47:48 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971637271 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.1971637271
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/33.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.903213899
Short name T1124
Test name
Test status
Simulation time 54287073 ps
CPU time 0.72 seconds
Started Sep 11 06:47:46 PM UTC 24
Finished Sep 11 06:47:48 PM UTC 24
Peak memory 211392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903213899 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.903213899
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/34.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.3108526433
Short name T1131
Test name
Test status
Simulation time 50387701 ps
CPU time 0.78 seconds
Started Sep 11 06:47:46 PM UTC 24
Finished Sep 11 06:47:48 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108526433 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.3108526433
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/35.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.1109840036
Short name T1135
Test name
Test status
Simulation time 24914533 ps
CPU time 0.84 seconds
Started Sep 11 06:47:46 PM UTC 24
Finished Sep 11 06:47:48 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109840036 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.1109840036
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/36.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.4120221274
Short name T1133
Test name
Test status
Simulation time 16477204 ps
CPU time 0.89 seconds
Started Sep 11 06:47:46 PM UTC 24
Finished Sep 11 06:47:48 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120221274 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.4120221274
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/37.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.2771934427
Short name T1102
Test name
Test status
Simulation time 45561598 ps
CPU time 0.74 seconds
Started Sep 11 06:47:47 PM UTC 24
Finished Sep 11 06:47:48 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771934427 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.2771934427
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/38.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.3515266894
Short name T1139
Test name
Test status
Simulation time 14621467 ps
CPU time 0.86 seconds
Started Sep 11 06:47:47 PM UTC 24
Finished Sep 11 06:47:49 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515266894 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.3515266894
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/39.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.3213569297
Short name T152
Test name
Test status
Simulation time 3699968613 ps
CPU time 18.6 seconds
Started Sep 11 06:47:19 PM UTC 24
Finished Sep 11 06:47:39 PM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213569297 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.3213569297
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.318834344
Short name T1149
Test name
Test status
Simulation time 3681035391 ps
CPU time 33.65 seconds
Started Sep 11 06:47:18 PM UTC 24
Finished Sep 11 06:47:53 PM UTC 24
Peak memory 213888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318834344 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.318834344
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1407060205
Short name T103
Test name
Test status
Simulation time 57997502 ps
CPU time 1.42 seconds
Started Sep 11 06:47:18 PM UTC 24
Finished Sep 11 06:47:20 PM UTC 24
Peak memory 213304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407060205 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.1407060205
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3712756931
Short name T133
Test name
Test status
Simulation time 95281428 ps
CPU time 2.43 seconds
Started Sep 11 06:47:19 PM UTC 24
Finished Sep 11 06:47:23 PM UTC 24
Peak memory 224324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3712756931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.spi_device_csr_mem_rw_with_rand_reset.3712756931
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.4278626420
Short name T146
Test name
Test status
Simulation time 125094729 ps
CPU time 3.22 seconds
Started Sep 11 06:47:18 PM UTC 24
Finished Sep 11 06:47:22 PM UTC 24
Peak memory 224128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278626420 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4278626420
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.1271862101
Short name T1049
Test name
Test status
Simulation time 35379281 ps
CPU time 1.13 seconds
Started Sep 11 06:47:18 PM UTC 24
Finished Sep 11 06:47:20 PM UTC 24
Peak memory 211516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271862101 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1271862101
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.3375258861
Short name T1051
Test name
Test status
Simulation time 90611082 ps
CPU time 2.45 seconds
Started Sep 11 06:47:18 PM UTC 24
Finished Sep 11 06:47:21 PM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375258861 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.3375258861
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.4038453312
Short name T1048
Test name
Test status
Simulation time 16865440 ps
CPU time 1.02 seconds
Started Sep 11 06:47:18 PM UTC 24
Finished Sep 11 06:47:20 PM UTC 24
Peak memory 211444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038453312 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.4038453312
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1658591172
Short name T1053
Test name
Test status
Simulation time 240648603 ps
CPU time 2.21 seconds
Started Sep 11 06:47:19 PM UTC 24
Finished Sep 11 06:47:23 PM UTC 24
Peak memory 213816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658591172 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstanding.1658591172
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.2280424562
Short name T136
Test name
Test status
Simulation time 139166369 ps
CPU time 2.62 seconds
Started Sep 11 06:47:18 PM UTC 24
Finished Sep 11 06:47:21 PM UTC 24
Peak memory 226516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280424562 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2280424562
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.3474450572
Short name T194
Test name
Test status
Simulation time 304960359 ps
CPU time 21.04 seconds
Started Sep 11 06:47:18 PM UTC 24
Finished Sep 11 06:47:40 PM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474450572 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.3474450572
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.1497142646
Short name T1137
Test name
Test status
Simulation time 47186688 ps
CPU time 0.84 seconds
Started Sep 11 06:47:47 PM UTC 24
Finished Sep 11 06:47:49 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497142646 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.1497142646
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/40.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.1905639013
Short name T1134
Test name
Test status
Simulation time 12317016 ps
CPU time 0.7 seconds
Started Sep 11 06:47:47 PM UTC 24
Finished Sep 11 06:47:48 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905639013 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.1905639013
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/41.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.4256977723
Short name T1136
Test name
Test status
Simulation time 20188092 ps
CPU time 0.71 seconds
Started Sep 11 06:47:47 PM UTC 24
Finished Sep 11 06:47:48 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256977723 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.4256977723
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/42.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.1569107290
Short name T1138
Test name
Test status
Simulation time 34472361 ps
CPU time 0.76 seconds
Started Sep 11 06:47:47 PM UTC 24
Finished Sep 11 06:47:49 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569107290 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.1569107290
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/43.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.3497892737
Short name T1142
Test name
Test status
Simulation time 16499569 ps
CPU time 0.86 seconds
Started Sep 11 06:47:47 PM UTC 24
Finished Sep 11 06:47:49 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497892737 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.3497892737
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/44.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.2025543409
Short name T1141
Test name
Test status
Simulation time 50217238 ps
CPU time 0.75 seconds
Started Sep 11 06:47:47 PM UTC 24
Finished Sep 11 06:47:49 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025543409 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.2025543409
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/45.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.3867544085
Short name T1143
Test name
Test status
Simulation time 13063872 ps
CPU time 0.82 seconds
Started Sep 11 06:47:47 PM UTC 24
Finished Sep 11 06:47:49 PM UTC 24
Peak memory 211432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867544085 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.3867544085
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/46.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.512463594
Short name T1144
Test name
Test status
Simulation time 15222815 ps
CPU time 0.82 seconds
Started Sep 11 06:47:47 PM UTC 24
Finished Sep 11 06:47:49 PM UTC 24
Peak memory 211376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512463594 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.512463594
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/47.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.4015293604
Short name T1145
Test name
Test status
Simulation time 12930827 ps
CPU time 0.8 seconds
Started Sep 11 06:47:47 PM UTC 24
Finished Sep 11 06:47:49 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015293604 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.4015293604
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/48.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.3025765979
Short name T1147
Test name
Test status
Simulation time 51691358 ps
CPU time 0.71 seconds
Started Sep 11 06:47:48 PM UTC 24
Finished Sep 11 06:47:50 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025765979 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.3025765979
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/49.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1455674255
Short name T1056
Test name
Test status
Simulation time 47835553 ps
CPU time 2.01 seconds
Started Sep 11 06:47:22 PM UTC 24
Finished Sep 11 06:47:25 PM UTC 24
Peak memory 224360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1455674255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
5.spi_device_csr_mem_rw_with_rand_reset.1455674255
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.3994357695
Short name T1055
Test name
Test status
Simulation time 322098044 ps
CPU time 3.23 seconds
Started Sep 11 06:47:21 PM UTC 24
Finished Sep 11 06:47:25 PM UTC 24
Peak memory 224120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994357695 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3994357695
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.198767389
Short name T1052
Test name
Test status
Simulation time 70851480 ps
CPU time 1.05 seconds
Started Sep 11 06:47:21 PM UTC 24
Finished Sep 11 06:47:22 PM UTC 24
Peak memory 211392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198767389 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.198767389
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3047892012
Short name T1059
Test name
Test status
Simulation time 28276667 ps
CPU time 2.47 seconds
Started Sep 11 06:47:22 PM UTC 24
Finished Sep 11 06:47:25 PM UTC 24
Peak memory 224064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047892012 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstanding.3047892012
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.3133836828
Short name T127
Test name
Test status
Simulation time 122807228 ps
CPU time 4.27 seconds
Started Sep 11 06:47:19 PM UTC 24
Finished Sep 11 06:47:25 PM UTC 24
Peak memory 224256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133836828 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3133836828
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.1940960561
Short name T204
Test name
Test status
Simulation time 1777137481 ps
CPU time 22.17 seconds
Started Sep 11 06:47:20 PM UTC 24
Finished Sep 11 06:47:44 PM UTC 24
Peak memory 226112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940960561 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.1940960561
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1228840975
Short name T1061
Test name
Test status
Simulation time 73964452 ps
CPU time 3.21 seconds
Started Sep 11 06:47:23 PM UTC 24
Finished Sep 11 06:47:27 PM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1228840975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
6.spi_device_csr_mem_rw_with_rand_reset.1228840975
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.3762186820
Short name T148
Test name
Test status
Simulation time 152000352 ps
CPU time 3.25 seconds
Started Sep 11 06:47:23 PM UTC 24
Finished Sep 11 06:47:27 PM UTC 24
Peak memory 213832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762186820 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3762186820
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.2958534262
Short name T1057
Test name
Test status
Simulation time 57570164 ps
CPU time 1.11 seconds
Started Sep 11 06:47:23 PM UTC 24
Finished Sep 11 06:47:25 PM UTC 24
Peak memory 211516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958534262 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2958534262
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4005691674
Short name T165
Test name
Test status
Simulation time 753619535 ps
CPU time 3.8 seconds
Started Sep 11 06:47:23 PM UTC 24
Finished Sep 11 06:47:28 PM UTC 24
Peak memory 226380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005691674 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstanding.4005691674
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.2409107421
Short name T1058
Test name
Test status
Simulation time 77099421 ps
CPU time 2.21 seconds
Started Sep 11 06:47:22 PM UTC 24
Finished Sep 11 06:47:25 PM UTC 24
Peak memory 226260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409107421 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2409107421
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.931585772
Short name T1072
Test name
Test status
Simulation time 562274911 ps
CPU time 8.02 seconds
Started Sep 11 06:47:23 PM UTC 24
Finished Sep 11 06:47:32 PM UTC 24
Peak memory 224104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931585772 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.931585772
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3167190622
Short name T1065
Test name
Test status
Simulation time 89957333 ps
CPU time 3.47 seconds
Started Sep 11 06:47:26 PM UTC 24
Finished Sep 11 06:47:30 PM UTC 24
Peak memory 226240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3167190622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
7.spi_device_csr_mem_rw_with_rand_reset.3167190622
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.3601785512
Short name T1062
Test name
Test status
Simulation time 34838780 ps
CPU time 1.8 seconds
Started Sep 11 06:47:24 PM UTC 24
Finished Sep 11 06:47:27 PM UTC 24
Peak memory 213008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601785512 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3601785512
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.2607261861
Short name T1060
Test name
Test status
Simulation time 34252249 ps
CPU time 1.07 seconds
Started Sep 11 06:47:24 PM UTC 24
Finished Sep 11 06:47:27 PM UTC 24
Peak memory 211516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607261861 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2607261861
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2462870944
Short name T1066
Test name
Test status
Simulation time 229983848 ps
CPU time 4.92 seconds
Started Sep 11 06:47:24 PM UTC 24
Finished Sep 11 06:47:31 PM UTC 24
Peak memory 224032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462870944 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstanding.2462870944
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.3044286693
Short name T128
Test name
Test status
Simulation time 152553781 ps
CPU time 4.21 seconds
Started Sep 11 06:47:23 PM UTC 24
Finished Sep 11 06:47:28 PM UTC 24
Peak memory 226512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044286693 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3044286693
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.3935162350
Short name T195
Test name
Test status
Simulation time 280360031 ps
CPU time 15.17 seconds
Started Sep 11 06:47:24 PM UTC 24
Finished Sep 11 06:47:41 PM UTC 24
Peak memory 224152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935162350 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.3935162350
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2292451862
Short name T1068
Test name
Test status
Simulation time 179904959 ps
CPU time 3.11 seconds
Started Sep 11 06:47:27 PM UTC 24
Finished Sep 11 06:47:31 PM UTC 24
Peak memory 226256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2292451862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
8.spi_device_csr_mem_rw_with_rand_reset.2292451862
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.757825735
Short name T138
Test name
Test status
Simulation time 110153140 ps
CPU time 2.43 seconds
Started Sep 11 06:47:26 PM UTC 24
Finished Sep 11 06:47:30 PM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757825735 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.757825735
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.2307967968
Short name T1064
Test name
Test status
Simulation time 19935633 ps
CPU time 0.96 seconds
Started Sep 11 06:47:26 PM UTC 24
Finished Sep 11 06:47:28 PM UTC 24
Peak memory 211516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307967968 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2307967968
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.67572592
Short name T1044
Test name
Test status
Simulation time 217744875 ps
CPU time 3.17 seconds
Started Sep 11 06:47:26 PM UTC 24
Finished Sep 11 06:47:30 PM UTC 24
Peak memory 224304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67572592 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstanding.67572592
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.1600694767
Short name T126
Test name
Test status
Simulation time 1054075642 ps
CPU time 2.52 seconds
Started Sep 11 06:47:26 PM UTC 24
Finished Sep 11 06:47:29 PM UTC 24
Peak memory 224192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600694767 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1600694767
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.3643669355
Short name T202
Test name
Test status
Simulation time 3164153862 ps
CPU time 18.82 seconds
Started Sep 11 06:47:26 PM UTC 24
Finished Sep 11 06:47:46 PM UTC 24
Peak memory 224108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643669355 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.3643669355
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1874481094
Short name T1073
Test name
Test status
Simulation time 125943016 ps
CPU time 2.96 seconds
Started Sep 11 06:47:28 PM UTC 24
Finished Sep 11 06:47:33 PM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1874481094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
9.spi_device_csr_mem_rw_with_rand_reset.1874481094
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.2394233268
Short name T1069
Test name
Test status
Simulation time 99810631 ps
CPU time 3.42 seconds
Started Sep 11 06:47:28 PM UTC 24
Finished Sep 11 06:47:33 PM UTC 24
Peak memory 213880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394233268 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2394233268
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.4073983105
Short name T1035
Test name
Test status
Simulation time 32143349 ps
CPU time 0.9 seconds
Started Sep 11 06:47:28 PM UTC 24
Finished Sep 11 06:47:30 PM UTC 24
Peak memory 211516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073983105 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.4073983105
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2364152222
Short name T1067
Test name
Test status
Simulation time 26832368 ps
CPU time 1.76 seconds
Started Sep 11 06:47:28 PM UTC 24
Finished Sep 11 06:47:31 PM UTC 24
Peak memory 223192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364152222 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstanding.2364152222
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.3120114035
Short name T197
Test name
Test status
Simulation time 813635982 ps
CPU time 11.08 seconds
Started Sep 11 06:47:28 PM UTC 24
Finished Sep 11 06:47:40 PM UTC 24
Peak memory 226180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120114035 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.3120114035
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.3799146819
Short name T15
Test name
Test status
Simulation time 328196958 ps
CPU time 5.47 seconds
Started Sep 11 05:06:11 PM UTC 24
Finished Sep 11 05:06:18 PM UTC 24
Peak memory 245516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799146819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3799146819
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.975473235
Short name T3
Test name
Test status
Simulation time 17494305 ps
CPU time 0.94 seconds
Started Sep 11 05:06:10 PM UTC 24
Finished Sep 11 05:06:12 PM UTC 24
Peak memory 215652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975473235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.975473235
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.3026617757
Short name T26
Test name
Test status
Simulation time 1829397359 ps
CPU time 9.4 seconds
Started Sep 11 05:06:11 PM UTC 24
Finished Sep 11 05:06:22 PM UTC 24
Peak memory 245492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026617757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3026617757
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.1495283878
Short name T412
Test name
Test status
Simulation time 12700813036 ps
CPU time 60.55 seconds
Started Sep 11 05:06:10 PM UTC 24
Finished Sep 11 05:07:12 PM UTC 24
Peak memory 245624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495283878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1495283878
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.1132105769
Short name T13
Test name
Test status
Simulation time 1523113520 ps
CPU time 5.56 seconds
Started Sep 11 05:06:10 PM UTC 24
Finished Sep 11 05:06:17 PM UTC 24
Peak memory 245748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132105769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.1132105769
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.969611410
Short name T60
Test name
Test status
Simulation time 194776223247 ps
CPU time 48.03 seconds
Started Sep 11 05:06:10 PM UTC 24
Finished Sep 11 05:07:00 PM UTC 24
Peak memory 262036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969611410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.969611410
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3304514558
Short name T30
Test name
Test status
Simulation time 3785267240 ps
CPU time 17.12 seconds
Started Sep 11 05:06:10 PM UTC 24
Finished Sep 11 05:06:28 PM UTC 24
Peak memory 227844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304514558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3304514558
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.1921190914
Short name T4
Test name
Test status
Simulation time 18595040 ps
CPU time 1.01 seconds
Started Sep 11 05:06:10 PM UTC 24
Finished Sep 11 05:06:12 PM UTC 24
Peak memory 215976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921190914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1921190914
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.3583025426
Short name T2
Test name
Test status
Simulation time 35281655 ps
CPU time 0.77 seconds
Started Sep 11 05:06:10 PM UTC 24
Finished Sep 11 05:06:12 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583025426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3583025426
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.2975377561
Short name T24
Test name
Test status
Simulation time 3297220909 ps
CPU time 12.31 seconds
Started Sep 11 05:06:11 PM UTC 24
Finished Sep 11 05:06:25 PM UTC 24
Peak memory 251848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975377561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2975377561
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/0.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.323308165
Short name T42
Test name
Test status
Simulation time 14168907 ps
CPU time 1.07 seconds
Started Sep 11 05:06:18 PM UTC 24
Finished Sep 11 05:06:20 PM UTC 24
Peak memory 215280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323308165 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.323308165
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.595042813
Short name T41
Test name
Test status
Simulation time 99349059 ps
CPU time 3.08 seconds
Started Sep 11 05:06:14 PM UTC 24
Finished Sep 11 05:06:18 PM UTC 24
Peak memory 234896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595042813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.595042813
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.1170484079
Short name T8
Test name
Test status
Simulation time 29792252 ps
CPU time 1.08 seconds
Started Sep 11 05:06:11 PM UTC 24
Finished Sep 11 05:06:14 PM UTC 24
Peak memory 215788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170484079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1170484079
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.4050645245
Short name T48
Test name
Test status
Simulation time 9923846174 ps
CPU time 58.33 seconds
Started Sep 11 05:06:16 PM UTC 24
Finished Sep 11 05:07:16 PM UTC 24
Peak memory 266204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050645245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.4050645245
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.3406864779
Short name T23
Test name
Test status
Simulation time 158335288 ps
CPU time 6.86 seconds
Started Sep 11 05:06:15 PM UTC 24
Finished Sep 11 05:06:24 PM UTC 24
Peak memory 235524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406864779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3406864779
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.926890333
Short name T219
Test name
Test status
Simulation time 144355309709 ps
CPU time 288.7 seconds
Started Sep 11 05:06:15 PM UTC 24
Finished Sep 11 05:11:09 PM UTC 24
Peak memory 266468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926890333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.926890333
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.2637091269
Short name T253
Test name
Test status
Simulation time 43166233596 ps
CPU time 102.33 seconds
Started Sep 11 05:06:14 PM UTC 24
Finished Sep 11 05:07:59 PM UTC 24
Peak memory 245632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637091269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2637091269
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.2432201914
Short name T10
Test name
Test status
Simulation time 27686148 ps
CPU time 1.61 seconds
Started Sep 11 05:06:12 PM UTC 24
Finished Sep 11 05:06:14 PM UTC 24
Peak memory 229192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432201914 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_parity.2432201914
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.1675126315
Short name T40
Test name
Test status
Simulation time 282883095 ps
CPU time 3.21 seconds
Started Sep 11 05:06:14 PM UTC 24
Finished Sep 11 05:06:18 PM UTC 24
Peak memory 234504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675126315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.1675126315
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.4151264721
Short name T17
Test name
Test status
Simulation time 1150059091 ps
CPU time 4.04 seconds
Started Sep 11 05:06:14 PM UTC 24
Finished Sep 11 05:06:19 PM UTC 24
Peak memory 245572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151264721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4151264721
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.674264621
Short name T20
Test name
Test status
Simulation time 796888789 ps
CPU time 4.31 seconds
Started Sep 11 05:06:15 PM UTC 24
Finished Sep 11 05:06:21 PM UTC 24
Peak memory 231596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674264621 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.674264621
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.3483163707
Short name T19
Test name
Test status
Simulation time 153241336 ps
CPU time 1.86 seconds
Started Sep 11 05:06:18 PM UTC 24
Finished Sep 11 05:06:21 PM UTC 24
Peak memory 257540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483163707 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3483163707
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.3361747143
Short name T72
Test name
Test status
Simulation time 13162821570 ps
CPU time 52.24 seconds
Started Sep 11 05:06:12 PM UTC 24
Finished Sep 11 05:07:06 PM UTC 24
Peak memory 227876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361747143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3361747143
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.576200932
Short name T14
Test name
Test status
Simulation time 1429023196 ps
CPU time 4.45 seconds
Started Sep 11 05:06:12 PM UTC 24
Finished Sep 11 05:06:17 PM UTC 24
Peak memory 227912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576200932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.576200932
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.1999368945
Short name T11
Test name
Test status
Simulation time 69373737 ps
CPU time 1.95 seconds
Started Sep 11 05:06:13 PM UTC 24
Finished Sep 11 05:06:16 PM UTC 24
Peak memory 228068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999368945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1999368945
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.3896455181
Short name T21
Test name
Test status
Simulation time 391288098 ps
CPU time 5.9 seconds
Started Sep 11 05:06:14 PM UTC 24
Finished Sep 11 05:06:21 PM UTC 24
Peak memory 245528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896455181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3896455181
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/1.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.988575351
Short name T450
Test name
Test status
Simulation time 41969821 ps
CPU time 1.08 seconds
Started Sep 11 05:09:32 PM UTC 24
Finished Sep 11 05:09:34 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988575351 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.988575351
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.580702020
Short name T109
Test name
Test status
Simulation time 557525205 ps
CPU time 4.95 seconds
Started Sep 11 05:09:18 PM UTC 24
Finished Sep 11 05:09:24 PM UTC 24
Peak memory 235524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580702020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.580702020
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.1402317827
Short name T445
Test name
Test status
Simulation time 13528942 ps
CPU time 0.97 seconds
Started Sep 11 05:09:11 PM UTC 24
Finished Sep 11 05:09:14 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402317827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1402317827
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.162450663
Short name T182
Test name
Test status
Simulation time 18536908811 ps
CPU time 140.33 seconds
Started Sep 11 05:09:24 PM UTC 24
Finished Sep 11 05:11:47 PM UTC 24
Peak memory 262084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162450663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.162450663
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.2006236881
Short name T248
Test name
Test status
Simulation time 10544335378 ps
CPU time 91.87 seconds
Started Sep 11 05:09:26 PM UTC 24
Finished Sep 11 05:11:00 PM UTC 24
Peak memory 262164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006236881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2006236881
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.1011550939
Short name T455
Test name
Test status
Simulation time 2997240343 ps
CPU time 20.06 seconds
Started Sep 11 05:09:21 PM UTC 24
Finished Sep 11 05:09:43 PM UTC 24
Peak memory 235468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011550939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1011550939
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.3030337260
Short name T115
Test name
Test status
Simulation time 358420026 ps
CPU time 10.34 seconds
Started Sep 11 05:09:22 PM UTC 24
Finished Sep 11 05:09:34 PM UTC 24
Peak memory 247620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030337260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.3030337260
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.856548045
Short name T254
Test name
Test status
Simulation time 6644456725 ps
CPU time 34.87 seconds
Started Sep 11 05:09:17 PM UTC 24
Finished Sep 11 05:09:53 PM UTC 24
Peak memory 235400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856548045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.856548045
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.3123925620
Short name T252
Test name
Test status
Simulation time 5359953752 ps
CPU time 38.57 seconds
Started Sep 11 05:09:17 PM UTC 24
Finished Sep 11 05:09:57 PM UTC 24
Peak memory 245884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123925620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3123925620
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.167167263
Short name T446
Test name
Test status
Simulation time 34663638 ps
CPU time 1.47 seconds
Started Sep 11 05:09:13 PM UTC 24
Finished Sep 11 05:09:16 PM UTC 24
Peak memory 229200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167167263 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mem_parity.167167263
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.2710362712
Short name T328
Test name
Test status
Simulation time 23186580144 ps
CPU time 21.68 seconds
Started Sep 11 05:09:17 PM UTC 24
Finished Sep 11 05:09:40 PM UTC 24
Peak memory 235464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710362712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.2710362712
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.1160448337
Short name T343
Test name
Test status
Simulation time 181961139 ps
CPU time 3.06 seconds
Started Sep 11 05:09:17 PM UTC 24
Finished Sep 11 05:09:21 PM UTC 24
Peak memory 235248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160448337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1160448337
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.3674237979
Short name T453
Test name
Test status
Simulation time 1171613339 ps
CPU time 15.31 seconds
Started Sep 11 05:09:24 PM UTC 24
Finished Sep 11 05:09:40 PM UTC 24
Peak memory 233892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674237979 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.3674237979
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.1725626003
Short name T386
Test name
Test status
Simulation time 69742608538 ps
CPU time 62.31 seconds
Started Sep 11 05:09:14 PM UTC 24
Finished Sep 11 05:10:18 PM UTC 24
Peak memory 227884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725626003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1725626003
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.1694766242
Short name T447
Test name
Test status
Simulation time 1394294992 ps
CPU time 2.86 seconds
Started Sep 11 05:09:13 PM UTC 24
Finished Sep 11 05:09:17 PM UTC 24
Peak memory 227732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694766242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1694766242
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.2735876660
Short name T404
Test name
Test status
Simulation time 322172575 ps
CPU time 4.62 seconds
Started Sep 11 05:09:17 PM UTC 24
Finished Sep 11 05:09:23 PM UTC 24
Peak memory 227808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735876660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2735876660
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.648557813
Short name T448
Test name
Test status
Simulation time 139613093 ps
CPU time 1.25 seconds
Started Sep 11 05:09:15 PM UTC 24
Finished Sep 11 05:09:18 PM UTC 24
Peak memory 215912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648557813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.648557813
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.246054264
Short name T217
Test name
Test status
Simulation time 635038913 ps
CPU time 11.75 seconds
Started Sep 11 05:09:18 PM UTC 24
Finished Sep 11 05:09:31 PM UTC 24
Peak memory 245544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246054264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.246054264
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/10.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.2693841552
Short name T457
Test name
Test status
Simulation time 13851494 ps
CPU time 1.07 seconds
Started Sep 11 05:09:56 PM UTC 24
Finished Sep 11 05:09:58 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693841552 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.2693841552
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.3016518893
Short name T208
Test name
Test status
Simulation time 77755537 ps
CPU time 4.12 seconds
Started Sep 11 05:09:48 PM UTC 24
Finished Sep 11 05:09:53 PM UTC 24
Peak memory 245568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016518893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3016518893
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.3622381898
Short name T451
Test name
Test status
Simulation time 119744222 ps
CPU time 1.11 seconds
Started Sep 11 05:09:35 PM UTC 24
Finished Sep 11 05:09:37 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622381898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3622381898
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.3778780810
Short name T578
Test name
Test status
Simulation time 23969865950 ps
CPU time 223.32 seconds
Started Sep 11 05:09:55 PM UTC 24
Finished Sep 11 05:13:41 PM UTC 24
Peak memory 261576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778780810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3778780810
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.1021906581
Short name T210
Test name
Test status
Simulation time 30765840656 ps
CPU time 51.47 seconds
Started Sep 11 05:09:55 PM UTC 24
Finished Sep 11 05:10:48 PM UTC 24
Peak memory 261508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021906581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.1021906581
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.2000156823
Short name T377
Test name
Test status
Simulation time 3050848781 ps
CPU time 20.7 seconds
Started Sep 11 05:09:49 PM UTC 24
Finished Sep 11 05:10:11 PM UTC 24
Peak memory 247696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000156823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2000156823
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.3635845202
Short name T264
Test name
Test status
Simulation time 5590560342 ps
CPU time 57.6 seconds
Started Sep 11 05:09:51 PM UTC 24
Finished Sep 11 05:10:51 PM UTC 24
Peak memory 245696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635845202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.3635845202
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.1456744066
Short name T242
Test name
Test status
Simulation time 416867518 ps
CPU time 7.46 seconds
Started Sep 11 05:09:44 PM UTC 24
Finished Sep 11 05:09:52 PM UTC 24
Peak memory 245572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456744066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1456744066
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.3207383303
Short name T309
Test name
Test status
Simulation time 12318746196 ps
CPU time 83.94 seconds
Started Sep 11 05:09:44 PM UTC 24
Finished Sep 11 05:11:10 PM UTC 24
Peak memory 262044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207383303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3207383303
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.431381344
Short name T452
Test name
Test status
Simulation time 73035424 ps
CPU time 1.51 seconds
Started Sep 11 05:09:35 PM UTC 24
Finished Sep 11 05:09:38 PM UTC 24
Peak memory 229260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431381344 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mem_parity.431381344
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.1232857006
Short name T323
Test name
Test status
Simulation time 2518479234 ps
CPU time 11.98 seconds
Started Sep 11 05:09:42 PM UTC 24
Finished Sep 11 05:09:55 PM UTC 24
Peak memory 245924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232857006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.1232857006
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.1639480270
Short name T289
Test name
Test status
Simulation time 28117495063 ps
CPU time 32.12 seconds
Started Sep 11 05:09:42 PM UTC 24
Finished Sep 11 05:10:15 PM UTC 24
Peak memory 245896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639480270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1639480270
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.1702944427
Short name T462
Test name
Test status
Simulation time 524383511 ps
CPU time 9.83 seconds
Started Sep 11 05:09:51 PM UTC 24
Finished Sep 11 05:10:02 PM UTC 24
Peak memory 231784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702944427 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.1702944427
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.3931511429
Short name T387
Test name
Test status
Simulation time 4940487422 ps
CPU time 14.88 seconds
Started Sep 11 05:09:38 PM UTC 24
Finished Sep 11 05:09:54 PM UTC 24
Peak memory 228136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931511429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3931511429
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3847884910
Short name T456
Test name
Test status
Simulation time 5143991820 ps
CPU time 9.17 seconds
Started Sep 11 05:09:36 PM UTC 24
Finished Sep 11 05:09:47 PM UTC 24
Peak memory 227816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847884910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3847884910
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.2882451023
Short name T395
Test name
Test status
Simulation time 88002872 ps
CPU time 1.74 seconds
Started Sep 11 05:09:41 PM UTC 24
Finished Sep 11 05:09:43 PM UTC 24
Peak memory 216696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882451023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2882451023
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.1500382518
Short name T454
Test name
Test status
Simulation time 24572212 ps
CPU time 1.21 seconds
Started Sep 11 05:09:38 PM UTC 24
Finished Sep 11 05:09:41 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500382518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1500382518
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.3860073017
Short name T184
Test name
Test status
Simulation time 3609892076 ps
CPU time 7.14 seconds
Started Sep 11 05:09:46 PM UTC 24
Finished Sep 11 05:09:55 PM UTC 24
Peak memory 235644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860073017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3860073017
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/11.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.618721056
Short name T464
Test name
Test status
Simulation time 33369054 ps
CPU time 1.11 seconds
Started Sep 11 05:10:12 PM UTC 24
Finished Sep 11 05:10:15 PM UTC 24
Peak memory 215664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618721056 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.618721056
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.2125676902
Short name T303
Test name
Test status
Simulation time 4369744818 ps
CPU time 19.53 seconds
Started Sep 11 05:10:03 PM UTC 24
Finished Sep 11 05:10:24 PM UTC 24
Peak memory 235708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125676902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2125676902
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.1988154606
Short name T458
Test name
Test status
Simulation time 27833246 ps
CPU time 1.19 seconds
Started Sep 11 05:09:56 PM UTC 24
Finished Sep 11 05:09:58 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988154606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1988154606
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_all.1853483270
Short name T533
Test name
Test status
Simulation time 14164043619 ps
CPU time 126.18 seconds
Started Sep 11 05:10:08 PM UTC 24
Finished Sep 11 05:12:17 PM UTC 24
Peak memory 262084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853483270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1853483270
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.1378648120
Short name T597
Test name
Test status
Simulation time 27032753867 ps
CPU time 230.54 seconds
Started Sep 11 05:10:10 PM UTC 24
Finished Sep 11 05:14:05 PM UTC 24
Peak memory 266228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378648120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1378648120
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.1865363504
Short name T403
Test name
Test status
Simulation time 312337146 ps
CPU time 9.2 seconds
Started Sep 11 05:10:12 PM UTC 24
Finished Sep 11 05:10:23 PM UTC 24
Peak memory 245736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865363504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.1865363504
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.683376643
Short name T192
Test name
Test status
Simulation time 132655308 ps
CPU time 9.07 seconds
Started Sep 11 05:10:06 PM UTC 24
Finished Sep 11 05:10:16 PM UTC 24
Peak memory 247744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683376643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.683376643
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.93131934
Short name T498
Test name
Test status
Simulation time 186753902828 ps
CPU time 83.71 seconds
Started Sep 11 05:10:06 PM UTC 24
Finished Sep 11 05:11:31 PM UTC 24
Peak memory 249952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93131934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.93131934
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.730446682
Short name T299
Test name
Test status
Simulation time 7775042451 ps
CPU time 9.31 seconds
Started Sep 11 05:10:00 PM UTC 24
Finished Sep 11 05:10:10 PM UTC 24
Peak memory 235656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730446682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.730446682
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.2267667699
Short name T340
Test name
Test status
Simulation time 1239156748 ps
CPU time 9.84 seconds
Started Sep 11 05:10:01 PM UTC 24
Finished Sep 11 05:10:12 PM UTC 24
Peak memory 245592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267667699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2267667699
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.2005767599
Short name T459
Test name
Test status
Simulation time 128560919 ps
CPU time 1.39 seconds
Started Sep 11 05:09:56 PM UTC 24
Finished Sep 11 05:09:58 PM UTC 24
Peak memory 229196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005767599 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mem_parity.2005767599
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.3205625524
Short name T250
Test name
Test status
Simulation time 516844137 ps
CPU time 11.88 seconds
Started Sep 11 05:09:59 PM UTC 24
Finished Sep 11 05:10:12 PM UTC 24
Peak memory 245572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205625524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.3205625524
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1769789145
Short name T337
Test name
Test status
Simulation time 751978455 ps
CPU time 4.78 seconds
Started Sep 11 05:09:59 PM UTC 24
Finished Sep 11 05:10:05 PM UTC 24
Peak memory 235296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769789145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1769789145
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.3202014052
Short name T469
Test name
Test status
Simulation time 877909925 ps
CPU time 11.59 seconds
Started Sep 11 05:10:08 PM UTC 24
Finished Sep 11 05:10:21 PM UTC 24
Peak memory 233828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202014052 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.3202014052
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.2839179921
Short name T177
Test name
Test status
Simulation time 130565406971 ps
CPU time 78.49 seconds
Started Sep 11 05:10:12 PM UTC 24
Finished Sep 11 05:11:33 PM UTC 24
Peak memory 235744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839179921 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.2839179921
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.1724223421
Short name T394
Test name
Test status
Simulation time 2662415218 ps
CPU time 22.52 seconds
Started Sep 11 05:09:58 PM UTC 24
Finished Sep 11 05:10:22 PM UTC 24
Peak memory 228076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724223421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1724223421
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.4165162939
Short name T463
Test name
Test status
Simulation time 3796779529 ps
CPU time 8.24 seconds
Started Sep 11 05:09:56 PM UTC 24
Finished Sep 11 05:10:05 PM UTC 24
Peak memory 227888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165162939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.4165162939
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.2604984311
Short name T461
Test name
Test status
Simulation time 200902991 ps
CPU time 1.67 seconds
Started Sep 11 05:09:58 PM UTC 24
Finished Sep 11 05:10:01 PM UTC 24
Peak memory 216496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604984311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2604984311
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.2139112660
Short name T460
Test name
Test status
Simulation time 19981811 ps
CPU time 0.91 seconds
Started Sep 11 05:09:58 PM UTC 24
Finished Sep 11 05:10:00 PM UTC 24
Peak memory 215736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139112660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2139112660
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.3683340853
Short name T283
Test name
Test status
Simulation time 5687788156 ps
CPU time 8.07 seconds
Started Sep 11 05:10:02 PM UTC 24
Finished Sep 11 05:10:11 PM UTC 24
Peak memory 262300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683340853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3683340853
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/12.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_alert_test.123660727
Short name T471
Test name
Test status
Simulation time 35419888 ps
CPU time 1.11 seconds
Started Sep 11 05:10:31 PM UTC 24
Finished Sep 11 05:10:33 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123660727 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.123660727
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_cfg_cmd.3813527495
Short name T301
Test name
Test status
Simulation time 347862571 ps
CPU time 7.59 seconds
Started Sep 11 05:10:21 PM UTC 24
Finished Sep 11 05:10:30 PM UTC 24
Peak memory 235300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813527495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3813527495
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.1161752074
Short name T465
Test name
Test status
Simulation time 52997150 ps
CPU time 1.18 seconds
Started Sep 11 05:10:13 PM UTC 24
Finished Sep 11 05:10:15 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161752074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1161752074
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.2212182940
Short name T320
Test name
Test status
Simulation time 58728734643 ps
CPU time 464 seconds
Started Sep 11 05:10:25 PM UTC 24
Finished Sep 11 05:18:15 PM UTC 24
Peak memory 278720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212182940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2212182940
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.1785491834
Short name T590
Test name
Test status
Simulation time 30969427656 ps
CPU time 204.28 seconds
Started Sep 11 05:10:26 PM UTC 24
Finished Sep 11 05:13:53 PM UTC 24
Peak memory 268284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785491834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1785491834
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode.1045644111
Short name T381
Test name
Test status
Simulation time 12596149611 ps
CPU time 32.97 seconds
Started Sep 11 05:10:21 PM UTC 24
Finished Sep 11 05:10:56 PM UTC 24
Peak memory 247756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045644111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1045644111
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_intercept.2580907964
Short name T263
Test name
Test status
Simulation time 641826811 ps
CPU time 6.05 seconds
Started Sep 11 05:10:19 PM UTC 24
Finished Sep 11 05:10:26 PM UTC 24
Peak memory 244240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580907964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2580907964
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mailbox.1100982749
Short name T490
Test name
Test status
Simulation time 4428659519 ps
CPU time 55.76 seconds
Started Sep 11 05:10:19 PM UTC 24
Finished Sep 11 05:11:17 PM UTC 24
Peak memory 262044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100982749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1100982749
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.3984554840
Short name T466
Test name
Test status
Simulation time 236957880 ps
CPU time 1.56 seconds
Started Sep 11 05:10:14 PM UTC 24
Finished Sep 11 05:10:16 PM UTC 24
Peak memory 229196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984554840 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mem_parity.3984554840
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.2290229916
Short name T327
Test name
Test status
Simulation time 11430522460 ps
CPU time 15.71 seconds
Started Sep 11 05:10:17 PM UTC 24
Finished Sep 11 05:10:34 PM UTC 24
Peak memory 252064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290229916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.2290229916
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.4062883037
Short name T298
Test name
Test status
Simulation time 5242712150 ps
CPU time 16.76 seconds
Started Sep 11 05:10:17 PM UTC 24
Finished Sep 11 05:10:35 PM UTC 24
Peak memory 235348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062883037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.4062883037
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.2874675333
Short name T476
Test name
Test status
Simulation time 1120409888 ps
CPU time 15.53 seconds
Started Sep 11 05:10:24 PM UTC 24
Finished Sep 11 05:10:41 PM UTC 24
Peak memory 233920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874675333 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.2874675333
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_all.3524997458
Short name T396
Test name
Test status
Simulation time 3760242635 ps
CPU time 38.35 seconds
Started Sep 11 05:10:16 PM UTC 24
Finished Sep 11 05:10:56 PM UTC 24
Peak memory 227920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524997458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3524997458
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.560048227
Short name T468
Test name
Test status
Simulation time 486616077 ps
CPU time 5.83 seconds
Started Sep 11 05:10:14 PM UTC 24
Finished Sep 11 05:10:21 PM UTC 24
Peak memory 227772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560048227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.560048227
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.2622792198
Short name T470
Test name
Test status
Simulation time 204737186 ps
CPU time 8.04 seconds
Started Sep 11 05:10:16 PM UTC 24
Finished Sep 11 05:10:25 PM UTC 24
Peak memory 227724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622792198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2622792198
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.3283494604
Short name T467
Test name
Test status
Simulation time 10636732 ps
CPU time 1.09 seconds
Started Sep 11 05:10:16 PM UTC 24
Finished Sep 11 05:10:18 PM UTC 24
Peak memory 215736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283494604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3283494604
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_upload.4083016884
Short name T292
Test name
Test status
Simulation time 6595273646 ps
CPU time 14.79 seconds
Started Sep 11 05:10:21 PM UTC 24
Finished Sep 11 05:10:37 PM UTC 24
Peak memory 251828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083016884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.4083016884
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/13.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_alert_test.1111039512
Short name T480
Test name
Test status
Simulation time 15964008 ps
CPU time 1.06 seconds
Started Sep 11 05:10:54 PM UTC 24
Finished Sep 11 05:10:56 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111039512 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.1111039512
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_cfg_cmd.834010045
Short name T477
Test name
Test status
Simulation time 204450546 ps
CPU time 6.93 seconds
Started Sep 11 05:10:42 PM UTC 24
Finished Sep 11 05:10:50 PM UTC 24
Peak memory 235328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834010045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.834010045
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_csb_read.1471855511
Short name T472
Test name
Test status
Simulation time 16116991 ps
CPU time 1.18 seconds
Started Sep 11 05:10:34 PM UTC 24
Finished Sep 11 05:10:37 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471855511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1471855511
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_all.4123070672
Short name T87
Test name
Test status
Simulation time 91228652440 ps
CPU time 329.52 seconds
Started Sep 11 05:10:49 PM UTC 24
Finished Sep 11 05:16:23 PM UTC 24
Peak memory 266208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123070672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.4123070672
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.3620310394
Short name T621
Test name
Test status
Simulation time 82460656083 ps
CPU time 226.21 seconds
Started Sep 11 05:10:52 PM UTC 24
Finished Sep 11 05:14:42 PM UTC 24
Peak memory 268344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620310394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3620310394
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.1736632552
Short name T287
Test name
Test status
Simulation time 48514408199 ps
CPU time 342.28 seconds
Started Sep 11 05:10:52 PM UTC 24
Finished Sep 11 05:16:40 PM UTC 24
Peak memory 278528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736632552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.1736632552
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode.1392105014
Short name T378
Test name
Test status
Simulation time 4716437119 ps
CPU time 15.3 seconds
Started Sep 11 05:10:47 PM UTC 24
Finished Sep 11 05:11:04 PM UTC 24
Peak memory 245728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392105014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1392105014
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.472177348
Short name T206
Test name
Test status
Simulation time 2288643634 ps
CPU time 22.77 seconds
Started Sep 11 05:10:48 PM UTC 24
Finished Sep 11 05:11:12 PM UTC 24
Peak memory 249788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472177348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.472177348
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_intercept.3937824783
Short name T235
Test name
Test status
Simulation time 9602096582 ps
CPU time 12.91 seconds
Started Sep 11 05:10:41 PM UTC 24
Finished Sep 11 05:10:56 PM UTC 24
Peak memory 245724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937824783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3937824783
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mailbox.3720281844
Short name T293
Test name
Test status
Simulation time 4078240281 ps
CPU time 50.93 seconds
Started Sep 11 05:10:41 PM UTC 24
Finished Sep 11 05:11:34 PM UTC 24
Peak memory 251836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720281844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3720281844
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mem_parity.2125486710
Short name T473
Test name
Test status
Simulation time 34742641 ps
CPU time 1.59 seconds
Started Sep 11 05:10:35 PM UTC 24
Finished Sep 11 05:10:38 PM UTC 24
Peak memory 229196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125486710 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mem_parity.2125486710
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.1157343146
Short name T238
Test name
Test status
Simulation time 1564746352 ps
CPU time 11.39 seconds
Started Sep 11 05:10:39 PM UTC 24
Finished Sep 11 05:10:52 PM UTC 24
Peak memory 249760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157343146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.1157343146
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.238000892
Short name T305
Test name
Test status
Simulation time 7917097036 ps
CPU time 38.75 seconds
Started Sep 11 05:10:38 PM UTC 24
Finished Sep 11 05:11:18 PM UTC 24
Peak memory 235400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238000892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.238000892
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.3300118294
Short name T479
Test name
Test status
Simulation time 212469422 ps
CPU time 5.83 seconds
Started Sep 11 05:10:48 PM UTC 24
Finished Sep 11 05:10:54 PM UTC 24
Peak memory 229736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300118294 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.3300118294
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.1899477614
Short name T173
Test name
Test status
Simulation time 57138093262 ps
CPU time 277.26 seconds
Started Sep 11 05:10:53 PM UTC 24
Finished Sep 11 05:15:34 PM UTC 24
Peak memory 262348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899477614 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.1899477614
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_all.323838974
Short name T384
Test name
Test status
Simulation time 2377000336 ps
CPU time 27.26 seconds
Started Sep 11 05:10:37 PM UTC 24
Finished Sep 11 05:11:05 PM UTC 24
Peak memory 227944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323838974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.323838974
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.3436991379
Short name T478
Test name
Test status
Simulation time 4622024409 ps
CPU time 15.99 seconds
Started Sep 11 05:10:35 PM UTC 24
Finished Sep 11 05:10:53 PM UTC 24
Peak memory 228108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436991379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3436991379
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_rw.3164707043
Short name T474
Test name
Test status
Simulation time 57093989 ps
CPU time 1.35 seconds
Started Sep 11 05:10:38 PM UTC 24
Finished Sep 11 05:10:40 PM UTC 24
Peak memory 216496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164707043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3164707043
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.2403183647
Short name T475
Test name
Test status
Simulation time 15917373 ps
CPU time 1.15 seconds
Started Sep 11 05:10:38 PM UTC 24
Finished Sep 11 05:10:40 PM UTC 24
Peak memory 215772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403183647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2403183647
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_upload.3038254514
Short name T224
Test name
Test status
Simulation time 7497324354 ps
CPU time 27.93 seconds
Started Sep 11 05:10:41 PM UTC 24
Finished Sep 11 05:11:11 PM UTC 24
Peak memory 245884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038254514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3038254514
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/14.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_alert_test.1437345529
Short name T488
Test name
Test status
Simulation time 67858835 ps
CPU time 0.94 seconds
Started Sep 11 05:11:14 PM UTC 24
Finished Sep 11 05:11:16 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437345529 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.1437345529
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_cfg_cmd.2043158131
Short name T487
Test name
Test status
Simulation time 106724310 ps
CPU time 3.41 seconds
Started Sep 11 05:11:07 PM UTC 24
Finished Sep 11 05:11:11 PM UTC 24
Peak memory 235144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043158131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2043158131
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_csb_read.776643702
Short name T481
Test name
Test status
Simulation time 92794036 ps
CPU time 1.13 seconds
Started Sep 11 05:10:55 PM UTC 24
Finished Sep 11 05:10:58 PM UTC 24
Peak memory 215664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776643702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.776643702
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_all.712788193
Short name T257
Test name
Test status
Simulation time 28954670531 ps
CPU time 72.78 seconds
Started Sep 11 05:11:10 PM UTC 24
Finished Sep 11 05:12:25 PM UTC 24
Peak memory 262084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712788193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.712788193
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.4084398233
Short name T262
Test name
Test status
Simulation time 15893026429 ps
CPU time 112.4 seconds
Started Sep 11 05:11:11 PM UTC 24
Finished Sep 11 05:13:06 PM UTC 24
Peak memory 282560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084398233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.4084398233
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.1277430352
Short name T270
Test name
Test status
Simulation time 12842626065 ps
CPU time 152.33 seconds
Started Sep 11 05:11:13 PM UTC 24
Finished Sep 11 05:13:48 PM UTC 24
Peak memory 266232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277430352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.1277430352
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode.674149483
Short name T380
Test name
Test status
Simulation time 517866377 ps
CPU time 13.32 seconds
Started Sep 11 05:11:09 PM UTC 24
Finished Sep 11 05:11:24 PM UTC 24
Peak memory 235356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674149483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.674149483
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.2953188162
Short name T663
Test name
Test status
Simulation time 33779858758 ps
CPU time 265.85 seconds
Started Sep 11 05:11:09 PM UTC 24
Finished Sep 11 05:15:39 PM UTC 24
Peak memory 284612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953188162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.2953188162
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_intercept.2940114692
Short name T344
Test name
Test status
Simulation time 3649320095 ps
CPU time 36.82 seconds
Started Sep 11 05:11:02 PM UTC 24
Finished Sep 11 05:11:40 PM UTC 24
Peak memory 235680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940114692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2940114692
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mailbox.3885398794
Short name T342
Test name
Test status
Simulation time 12535237514 ps
CPU time 39.16 seconds
Started Sep 11 05:11:05 PM UTC 24
Finished Sep 11 05:11:46 PM UTC 24
Peak memory 249760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885398794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3885398794
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mem_parity.3787901582
Short name T482
Test name
Test status
Simulation time 17084473 ps
CPU time 1.48 seconds
Started Sep 11 05:10:56 PM UTC 24
Finished Sep 11 05:10:59 PM UTC 24
Peak memory 229196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787901582 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mem_parity.3787901582
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.2186639334
Short name T227
Test name
Test status
Simulation time 1784800766 ps
CPU time 7.34 seconds
Started Sep 11 05:11:01 PM UTC 24
Finished Sep 11 05:11:09 PM UTC 24
Peak memory 245572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186639334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.2186639334
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.2587838927
Short name T269
Test name
Test status
Simulation time 36773067032 ps
CPU time 31.33 seconds
Started Sep 11 05:11:00 PM UTC 24
Finished Sep 11 05:11:32 PM UTC 24
Peak memory 235720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587838927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2587838927
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.2552705838
Short name T494
Test name
Test status
Simulation time 2656245786 ps
CPU time 10.39 seconds
Started Sep 11 05:11:10 PM UTC 24
Finished Sep 11 05:11:22 PM UTC 24
Peak memory 231780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552705838 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.2552705838
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_all.675935612
Short name T486
Test name
Test status
Simulation time 116210726870 ps
CPU time 39.32 seconds
Started Sep 11 05:10:56 PM UTC 24
Finished Sep 11 05:11:37 PM UTC 24
Peak memory 227916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675935612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.675935612
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.1879282507
Short name T484
Test name
Test status
Simulation time 13836716190 ps
CPU time 9.26 seconds
Started Sep 11 05:10:56 PM UTC 24
Finished Sep 11 05:11:07 PM UTC 24
Peak memory 227832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879282507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1879282507
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_rw.1473526933
Short name T485
Test name
Test status
Simulation time 315071242 ps
CPU time 8.11 seconds
Started Sep 11 05:10:59 PM UTC 24
Finished Sep 11 05:11:08 PM UTC 24
Peak memory 227816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473526933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1473526933
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.2097154487
Short name T483
Test name
Test status
Simulation time 93216831 ps
CPU time 1.64 seconds
Started Sep 11 05:10:57 PM UTC 24
Finished Sep 11 05:11:00 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097154487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2097154487
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_upload.3470254277
Short name T495
Test name
Test status
Simulation time 2422461109 ps
CPU time 18.94 seconds
Started Sep 11 05:11:06 PM UTC 24
Finished Sep 11 05:11:26 PM UTC 24
Peak memory 251804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470254277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3470254277
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/15.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_alert_test.91657659
Short name T501
Test name
Test status
Simulation time 33118091 ps
CPU time 1.11 seconds
Started Sep 11 05:11:32 PM UTC 24
Finished Sep 11 05:11:34 PM UTC 24
Peak memory 215664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91657659 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.91657659
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_cfg_cmd.716220437
Short name T285
Test name
Test status
Simulation time 407565648 ps
CPU time 3.36 seconds
Started Sep 11 05:11:25 PM UTC 24
Finished Sep 11 05:11:29 PM UTC 24
Peak memory 235356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716220437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.716220437
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_csb_read.3780576846
Short name T489
Test name
Test status
Simulation time 15801365 ps
CPU time 1.14 seconds
Started Sep 11 05:11:14 PM UTC 24
Finished Sep 11 05:11:16 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780576846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3780576846
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_all.2016701883
Short name T525
Test name
Test status
Simulation time 34454725097 ps
CPU time 35.46 seconds
Started Sep 11 05:11:30 PM UTC 24
Finished Sep 11 05:12:07 PM UTC 24
Peak memory 245892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016701883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2016701883
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.902403831
Short name T214
Test name
Test status
Simulation time 53252757812 ps
CPU time 126.01 seconds
Started Sep 11 05:11:32 PM UTC 24
Finished Sep 11 05:13:40 PM UTC 24
Peak memory 268292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902403831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.902403831
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2962806414
Short name T391
Test name
Test status
Simulation time 7921380646 ps
CPU time 28.02 seconds
Started Sep 11 05:11:32 PM UTC 24
Finished Sep 11 05:12:01 PM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962806414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.2962806414
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode.501425215
Short name T513
Test name
Test status
Simulation time 2133290435 ps
CPU time 22.08 seconds
Started Sep 11 05:11:27 PM UTC 24
Finished Sep 11 05:11:50 PM UTC 24
Peak memory 255832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501425215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.501425215
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.31184663
Short name T537
Test name
Test status
Simulation time 88731351206 ps
CPU time 50.45 seconds
Started Sep 11 05:11:28 PM UTC 24
Finished Sep 11 05:12:20 PM UTC 24
Peak memory 252036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31184663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.31184663
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_intercept.2639611006
Short name T500
Test name
Test status
Simulation time 2129832961 ps
CPU time 10.39 seconds
Started Sep 11 05:11:21 PM UTC 24
Finished Sep 11 05:11:33 PM UTC 24
Peak memory 235360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639611006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2639611006
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mailbox.2013726104
Short name T230
Test name
Test status
Simulation time 530779674 ps
CPU time 3.4 seconds
Started Sep 11 05:11:22 PM UTC 24
Finished Sep 11 05:11:27 PM UTC 24
Peak memory 245532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013726104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2013726104
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mem_parity.983286316
Short name T491
Test name
Test status
Simulation time 16622629 ps
CPU time 1.37 seconds
Started Sep 11 05:11:16 PM UTC 24
Finished Sep 11 05:11:18 PM UTC 24
Peak memory 229200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983286316 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mem_parity.983286316
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.2487837974
Short name T247
Test name
Test status
Simulation time 4194377646 ps
CPU time 10.85 seconds
Started Sep 11 05:11:19 PM UTC 24
Finished Sep 11 05:11:31 PM UTC 24
Peak memory 262148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487837974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.2487837974
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.985252444
Short name T245
Test name
Test status
Simulation time 3495993225 ps
CPU time 22.95 seconds
Started Sep 11 05:11:19 PM UTC 24
Finished Sep 11 05:11:43 PM UTC 24
Peak memory 245720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985252444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.985252444
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.3460336518
Short name T499
Test name
Test status
Simulation time 160958650 ps
CPU time 3.76 seconds
Started Sep 11 05:11:28 PM UTC 24
Finished Sep 11 05:11:33 PM UTC 24
Peak memory 233640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460336518 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.3460336518
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.3059142065
Short name T812
Test name
Test status
Simulation time 163176072895 ps
CPU time 415.71 seconds
Started Sep 11 05:11:32 PM UTC 24
Finished Sep 11 05:18:33 PM UTC 24
Peak memory 266104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059142065 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.3059142065
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_all.2740910675
Short name T497
Test name
Test status
Simulation time 983052932 ps
CPU time 13.12 seconds
Started Sep 11 05:11:17 PM UTC 24
Finished Sep 11 05:11:31 PM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740910675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2740910675
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.1494828609
Short name T496
Test name
Test status
Simulation time 4081700190 ps
CPU time 8.66 seconds
Started Sep 11 05:11:17 PM UTC 24
Finished Sep 11 05:11:27 PM UTC 24
Peak memory 228020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494828609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1494828609
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_rw.2177330647
Short name T493
Test name
Test status
Simulation time 28120792 ps
CPU time 1.35 seconds
Started Sep 11 05:11:19 PM UTC 24
Finished Sep 11 05:11:21 PM UTC 24
Peak memory 215972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177330647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2177330647
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.3218990691
Short name T492
Test name
Test status
Simulation time 36349690 ps
CPU time 1.28 seconds
Started Sep 11 05:11:18 PM UTC 24
Finished Sep 11 05:11:20 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218990691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3218990691
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/16.spi_device_upload.999741328
Short name T232
Test name
Test status
Simulation time 1632612350 ps
CPU time 7.41 seconds
Started Sep 11 05:11:22 PM UTC 24
Finished Sep 11 05:11:31 PM UTC 24
Peak memory 245560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999741328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.999741328
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/16.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_alert_test.2930317418
Short name T510
Test name
Test status
Simulation time 10933932 ps
CPU time 0.86 seconds
Started Sep 11 05:11:46 PM UTC 24
Finished Sep 11 05:11:48 PM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930317418 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.2930317418
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_cfg_cmd.3673371269
Short name T507
Test name
Test status
Simulation time 31360320 ps
CPU time 2.84 seconds
Started Sep 11 05:11:40 PM UTC 24
Finished Sep 11 05:11:44 PM UTC 24
Peak memory 245276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673371269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3673371269
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_csb_read.1076999746
Short name T502
Test name
Test status
Simulation time 16570270 ps
CPU time 1.21 seconds
Started Sep 11 05:11:33 PM UTC 24
Finished Sep 11 05:11:35 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076999746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1076999746
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_all.712710238
Short name T267
Test name
Test status
Simulation time 8657769230 ps
CPU time 106.2 seconds
Started Sep 11 05:11:44 PM UTC 24
Finished Sep 11 05:13:33 PM UTC 24
Peak memory 268224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712710238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.712710238
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.3223007959
Short name T215
Test name
Test status
Simulation time 12246312566 ps
CPU time 126.27 seconds
Started Sep 11 05:11:45 PM UTC 24
Finished Sep 11 05:13:53 PM UTC 24
Peak memory 284888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223007959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3223007959
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.1843151868
Short name T322
Test name
Test status
Simulation time 200075133845 ps
CPU time 297.6 seconds
Started Sep 11 05:11:45 PM UTC 24
Finished Sep 11 05:16:46 PM UTC 24
Peak memory 268280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843151868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.1843151868
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode.1855286913
Short name T517
Test name
Test status
Simulation time 491748831 ps
CPU time 15.31 seconds
Started Sep 11 05:11:40 PM UTC 24
Finished Sep 11 05:11:57 PM UTC 24
Peak memory 262248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855286913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1855286913
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.3956399083
Short name T534
Test name
Test status
Simulation time 7499080224 ps
CPU time 36.14 seconds
Started Sep 11 05:11:41 PM UTC 24
Finished Sep 11 05:12:19 PM UTC 24
Peak memory 262084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956399083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.3956399083
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_intercept.2884635035
Short name T308
Test name
Test status
Simulation time 436747938 ps
CPU time 3.44 seconds
Started Sep 11 05:11:37 PM UTC 24
Finished Sep 11 05:11:41 PM UTC 24
Peak memory 245600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884635035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2884635035
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mailbox.1019624601
Short name T506
Test name
Test status
Simulation time 354581629 ps
CPU time 4.25 seconds
Started Sep 11 05:11:38 PM UTC 24
Finished Sep 11 05:11:43 PM UTC 24
Peak memory 245600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019624601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1019624601
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mem_parity.1210104498
Short name T503
Test name
Test status
Simulation time 28463766 ps
CPU time 1.61 seconds
Started Sep 11 05:11:33 PM UTC 24
Finished Sep 11 05:11:36 PM UTC 24
Peak memory 229196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210104498 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mem_parity.1210104498
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.1786959209
Short name T330
Test name
Test status
Simulation time 46894927711 ps
CPU time 37.83 seconds
Started Sep 11 05:11:37 PM UTC 24
Finished Sep 11 05:12:16 PM UTC 24
Peak memory 252068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786959209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.1786959209
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.3866658055
Short name T518
Test name
Test status
Simulation time 8476603150 ps
CPU time 19.77 seconds
Started Sep 11 05:11:37 PM UTC 24
Finished Sep 11 05:11:58 PM UTC 24
Peak memory 249800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866658055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3866658055
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.1695279509
Short name T512
Test name
Test status
Simulation time 417857093 ps
CPU time 5.62 seconds
Started Sep 11 05:11:42 PM UTC 24
Finished Sep 11 05:11:49 PM UTC 24
Peak memory 233956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695279509 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.1695279509
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_stress_all.4191501727
Short name T174
Test name
Test status
Simulation time 13221938541 ps
CPU time 256.46 seconds
Started Sep 11 05:11:46 PM UTC 24
Finished Sep 11 05:16:06 PM UTC 24
Peak memory 301048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191501727 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.4191501727
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_all.4060172901
Short name T402
Test name
Test status
Simulation time 18679309646 ps
CPU time 30.05 seconds
Started Sep 11 05:11:34 PM UTC 24
Finished Sep 11 05:12:06 PM UTC 24
Peak memory 227944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060172901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4060172901
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.2962547035
Short name T521
Test name
Test status
Simulation time 58407673764 ps
CPU time 30.25 seconds
Started Sep 11 05:11:33 PM UTC 24
Finished Sep 11 05:12:05 PM UTC 24
Peak memory 227888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962547035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2962547035
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_rw.779695706
Short name T504
Test name
Test status
Simulation time 26853453 ps
CPU time 1.11 seconds
Started Sep 11 05:11:36 PM UTC 24
Finished Sep 11 05:11:38 PM UTC 24
Peak memory 215976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779695706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.779695706
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.1694762195
Short name T505
Test name
Test status
Simulation time 208664845 ps
CPU time 1.37 seconds
Started Sep 11 05:11:36 PM UTC 24
Finished Sep 11 05:11:38 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694762195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1694762195
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/17.spi_device_upload.1498759625
Short name T508
Test name
Test status
Simulation time 40674058 ps
CPU time 3.33 seconds
Started Sep 11 05:11:40 PM UTC 24
Finished Sep 11 05:11:44 PM UTC 24
Peak memory 245244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498759625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1498759625
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/17.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_alert_test.2491645400
Short name T524
Test name
Test status
Simulation time 46042621 ps
CPU time 1.1 seconds
Started Sep 11 05:12:04 PM UTC 24
Finished Sep 11 05:12:07 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491645400 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.2491645400
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_cfg_cmd.2321357441
Short name T522
Test name
Test status
Simulation time 1019094602 ps
CPU time 6.31 seconds
Started Sep 11 05:11:58 PM UTC 24
Finished Sep 11 05:12:05 PM UTC 24
Peak memory 235324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321357441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2321357441
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_csb_read.199506828
Short name T511
Test name
Test status
Simulation time 29292890 ps
CPU time 1.2 seconds
Started Sep 11 05:11:47 PM UTC 24
Finished Sep 11 05:11:49 PM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199506828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.199506828
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_all.2881779320
Short name T297
Test name
Test status
Simulation time 7651170498 ps
CPU time 65.69 seconds
Started Sep 11 05:12:01 PM UTC 24
Finished Sep 11 05:13:08 PM UTC 24
Peak memory 245700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881779320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2881779320
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.3698655481
Short name T406
Test name
Test status
Simulation time 34356791906 ps
CPU time 84.48 seconds
Started Sep 11 05:12:02 PM UTC 24
Finished Sep 11 05:13:29 PM UTC 24
Peak memory 268280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698655481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3698655481
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.2139266195
Short name T538
Test name
Test status
Simulation time 997852275 ps
CPU time 16.16 seconds
Started Sep 11 05:12:02 PM UTC 24
Finished Sep 11 05:12:20 PM UTC 24
Peak memory 245760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139266195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.2139266195
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode.2750311195
Short name T379
Test name
Test status
Simulation time 6347681454 ps
CPU time 30.71 seconds
Started Sep 11 05:11:59 PM UTC 24
Finished Sep 11 05:12:31 PM UTC 24
Peak memory 235392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750311195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2750311195
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.1268059566
Short name T560
Test name
Test status
Simulation time 7504951292 ps
CPU time 53.59 seconds
Started Sep 11 05:11:59 PM UTC 24
Finished Sep 11 05:12:54 PM UTC 24
Peak memory 264080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268059566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.1268059566
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_intercept.2404148677
Short name T519
Test name
Test status
Simulation time 180538548 ps
CPU time 5.05 seconds
Started Sep 11 05:11:53 PM UTC 24
Finished Sep 11 05:12:00 PM UTC 24
Peak memory 235356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404148677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2404148677
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mailbox.1997231169
Short name T346
Test name
Test status
Simulation time 19351873349 ps
CPU time 53.73 seconds
Started Sep 11 05:11:53 PM UTC 24
Finished Sep 11 05:12:49 PM UTC 24
Peak memory 245824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997231169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1997231169
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mem_parity.3467329070
Short name T514
Test name
Test status
Simulation time 45950031 ps
CPU time 1.52 seconds
Started Sep 11 05:11:48 PM UTC 24
Finished Sep 11 05:11:50 PM UTC 24
Peak memory 229196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467329070 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mem_parity.3467329070
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.2271123296
Short name T329
Test name
Test status
Simulation time 340915438 ps
CPU time 8.29 seconds
Started Sep 11 05:11:51 PM UTC 24
Finished Sep 11 05:12:01 PM UTC 24
Peak memory 245540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271123296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.2271123296
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.4029553171
Short name T256
Test name
Test status
Simulation time 356657622 ps
CPU time 5.93 seconds
Started Sep 11 05:11:51 PM UTC 24
Finished Sep 11 05:11:58 PM UTC 24
Peak memory 251748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029553171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.4029553171
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.2695969682
Short name T523
Test name
Test status
Simulation time 125624557 ps
CPU time 4.2 seconds
Started Sep 11 05:12:01 PM UTC 24
Finished Sep 11 05:12:06 PM UTC 24
Peak memory 231912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695969682 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.2695969682
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_all.3439709963
Short name T547
Test name
Test status
Simulation time 3772395159 ps
CPU time 44.43 seconds
Started Sep 11 05:11:50 PM UTC 24
Finished Sep 11 05:12:36 PM UTC 24
Peak memory 232172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439709963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3439709963
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.2943772410
Short name T516
Test name
Test status
Simulation time 3887681222 ps
CPU time 6.61 seconds
Started Sep 11 05:11:49 PM UTC 24
Finished Sep 11 05:11:57 PM UTC 24
Peak memory 229868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943772410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2943772410
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_rw.1633427852
Short name T520
Test name
Test status
Simulation time 1337495213 ps
CPU time 7.41 seconds
Started Sep 11 05:11:51 PM UTC 24
Finished Sep 11 05:12:00 PM UTC 24
Peak memory 227752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633427852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1633427852
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.131735846
Short name T515
Test name
Test status
Simulation time 44259903 ps
CPU time 1.39 seconds
Started Sep 11 05:11:50 PM UTC 24
Finished Sep 11 05:11:52 PM UTC 24
Peak memory 215912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131735846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.131735846
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_upload.3693274452
Short name T349
Test name
Test status
Simulation time 23986820517 ps
CPU time 11.51 seconds
Started Sep 11 05:11:58 PM UTC 24
Finished Sep 11 05:12:10 PM UTC 24
Peak memory 235684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693274452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3693274452
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/18.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_alert_test.1000000416
Short name T540
Test name
Test status
Simulation time 58205279 ps
CPU time 1.14 seconds
Started Sep 11 05:12:21 PM UTC 24
Finished Sep 11 05:12:23 PM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000000416 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.1000000416
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_cfg_cmd.891736955
Short name T536
Test name
Test status
Simulation time 58312224 ps
CPU time 2.88 seconds
Started Sep 11 05:12:15 PM UTC 24
Finished Sep 11 05:12:19 PM UTC 24
Peak memory 234488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891736955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.891736955
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_csb_read.2114402730
Short name T526
Test name
Test status
Simulation time 14247373 ps
CPU time 1.08 seconds
Started Sep 11 05:12:05 PM UTC 24
Finished Sep 11 05:12:08 PM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114402730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2114402730
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_all.4080491678
Short name T588
Test name
Test status
Simulation time 16978674676 ps
CPU time 92.94 seconds
Started Sep 11 05:12:16 PM UTC 24
Finished Sep 11 05:13:52 PM UTC 24
Peak memory 251844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080491678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.4080491678
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.818769829
Short name T370
Test name
Test status
Simulation time 68432508723 ps
CPU time 563.68 seconds
Started Sep 11 05:12:18 PM UTC 24
Finished Sep 11 05:21:49 PM UTC 24
Peak memory 268288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818769829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.818769829
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.2892086054
Short name T154
Test name
Test status
Simulation time 67682797145 ps
CPU time 313.45 seconds
Started Sep 11 05:12:20 PM UTC 24
Finished Sep 11 05:17:38 PM UTC 24
Peak memory 266428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892086054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.2892086054
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode.174929812
Short name T539
Test name
Test status
Simulation time 123234489 ps
CPU time 4.24 seconds
Started Sep 11 05:12:16 PM UTC 24
Finished Sep 11 05:12:22 PM UTC 24
Peak memory 245596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174929812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.174929812
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_intercept.286997123
Short name T530
Test name
Test status
Simulation time 31953817 ps
CPU time 2.96 seconds
Started Sep 11 05:12:10 PM UTC 24
Finished Sep 11 05:12:14 PM UTC 24
Peak memory 233724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286997123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.286997123
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mailbox.3215639917
Short name T531
Test name
Test status
Simulation time 30734462 ps
CPU time 3.11 seconds
Started Sep 11 05:12:11 PM UTC 24
Finished Sep 11 05:12:15 PM UTC 24
Peak memory 245216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215639917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3215639917
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mem_parity.2203639013
Short name T527
Test name
Test status
Simulation time 79218545 ps
CPU time 1.53 seconds
Started Sep 11 05:12:06 PM UTC 24
Finished Sep 11 05:12:09 PM UTC 24
Peak memory 229196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203639013 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mem_parity.2203639013
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.4260289983
Short name T535
Test name
Test status
Simulation time 15369134863 ps
CPU time 8.22 seconds
Started Sep 11 05:12:10 PM UTC 24
Finished Sep 11 05:12:19 PM UTC 24
Peak memory 245644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260289983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.4260289983
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.1817556105
Short name T271
Test name
Test status
Simulation time 33302861347 ps
CPU time 79.21 seconds
Started Sep 11 05:12:09 PM UTC 24
Finished Sep 11 05:13:30 PM UTC 24
Peak memory 251848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817556105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1817556105
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.3894869388
Short name T546
Test name
Test status
Simulation time 1540569982 ps
CPU time 17.74 seconds
Started Sep 11 05:12:16 PM UTC 24
Finished Sep 11 05:12:35 PM UTC 24
Peak memory 234156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894869388 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.3894869388
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_all.3392005682
Short name T392
Test name
Test status
Simulation time 8089963187 ps
CPU time 26.42 seconds
Started Sep 11 05:12:08 PM UTC 24
Finished Sep 11 05:12:36 PM UTC 24
Peak memory 228076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392005682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3392005682
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.2231213699
Short name T528
Test name
Test status
Simulation time 146444023 ps
CPU time 1.84 seconds
Started Sep 11 05:12:06 PM UTC 24
Finished Sep 11 05:12:09 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231213699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2231213699
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_rw.1788787775
Short name T532
Test name
Test status
Simulation time 157936659 ps
CPU time 6.55 seconds
Started Sep 11 05:12:08 PM UTC 24
Finished Sep 11 05:12:15 PM UTC 24
Peak memory 227660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788787775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1788787775
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.2776516740
Short name T529
Test name
Test status
Simulation time 357670818 ps
CPU time 1.2 seconds
Started Sep 11 05:12:08 PM UTC 24
Finished Sep 11 05:12:10 PM UTC 24
Peak memory 215904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776516740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2776516740
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_upload.2077002606
Short name T291
Test name
Test status
Simulation time 4352789418 ps
CPU time 14.35 seconds
Started Sep 11 05:12:11 PM UTC 24
Finished Sep 11 05:12:27 PM UTC 24
Peak memory 235444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077002606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2077002606
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/19.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.479051847
Short name T95
Test name
Test status
Simulation time 41986611 ps
CPU time 1.1 seconds
Started Sep 11 05:06:29 PM UTC 24
Finished Sep 11 05:06:31 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479051847 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.479051847
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.2906047648
Short name T129
Test name
Test status
Simulation time 747818501 ps
CPU time 9.71 seconds
Started Sep 11 05:06:24 PM UTC 24
Finished Sep 11 05:06:35 PM UTC 24
Peak memory 235328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906047648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2906047648
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.178868003
Short name T18
Test name
Test status
Simulation time 65091011 ps
CPU time 1.21 seconds
Started Sep 11 05:06:18 PM UTC 24
Finished Sep 11 05:06:20 PM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178868003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.178868003
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.837996989
Short name T274
Test name
Test status
Simulation time 34268118451 ps
CPU time 333.57 seconds
Started Sep 11 05:06:25 PM UTC 24
Finished Sep 11 05:12:03 PM UTC 24
Peak memory 266372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837996989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.837996989
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.688162559
Short name T124
Test name
Test status
Simulation time 1589221069 ps
CPU time 7.13 seconds
Started Sep 11 05:06:24 PM UTC 24
Finished Sep 11 05:06:32 PM UTC 24
Peak memory 235464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688162559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.688162559
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.2181289781
Short name T52
Test name
Test status
Simulation time 10974667666 ps
CPU time 22.51 seconds
Started Sep 11 05:06:24 PM UTC 24
Finished Sep 11 05:06:48 PM UTC 24
Peak memory 235464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181289781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.2181289781
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.1970711318
Short name T178
Test name
Test status
Simulation time 1309478893 ps
CPU time 21.14 seconds
Started Sep 11 05:06:24 PM UTC 24
Finished Sep 11 05:06:46 PM UTC 24
Peak memory 235460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970711318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1970711318
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.1628211616
Short name T137
Test name
Test status
Simulation time 52722955444 ps
CPU time 29.61 seconds
Started Sep 11 05:06:24 PM UTC 24
Finished Sep 11 05:06:55 PM UTC 24
Peak memory 245660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628211616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1628211616
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.3691824394
Short name T44
Test name
Test status
Simulation time 109675636 ps
CPU time 1.65 seconds
Started Sep 11 05:06:20 PM UTC 24
Finished Sep 11 05:06:23 PM UTC 24
Peak memory 229140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691824394 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_parity.3691824394
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.3255750364
Short name T53
Test name
Test status
Simulation time 1319579333 ps
CPU time 8.72 seconds
Started Sep 11 05:06:22 PM UTC 24
Finished Sep 11 05:06:32 PM UTC 24
Peak memory 245580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255750364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.3255750364
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.2886928297
Short name T57
Test name
Test status
Simulation time 798267232 ps
CPU time 7.34 seconds
Started Sep 11 05:06:22 PM UTC 24
Finished Sep 11 05:06:31 PM UTC 24
Peak memory 245572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886928297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2886928297
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.3687307142
Short name T54
Test name
Test status
Simulation time 1037719411 ps
CPU time 11.36 seconds
Started Sep 11 05:06:24 PM UTC 24
Finished Sep 11 05:06:36 PM UTC 24
Peak memory 233904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687307142 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.3687307142
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.3907380497
Short name T33
Test name
Test status
Simulation time 146212158 ps
CPU time 1.73 seconds
Started Sep 11 05:06:29 PM UTC 24
Finished Sep 11 05:06:32 PM UTC 24
Peak memory 257728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907380497 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3907380497
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.109373698
Short name T25
Test name
Test status
Simulation time 122839286 ps
CPU time 1.68 seconds
Started Sep 11 05:06:26 PM UTC 24
Finished Sep 11 05:06:29 PM UTC 24
Peak memory 216632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109373698 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.109373698
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.2564410878
Short name T31
Test name
Test status
Simulation time 8583989594 ps
CPU time 12.09 seconds
Started Sep 11 05:06:20 PM UTC 24
Finished Sep 11 05:06:33 PM UTC 24
Peak memory 232008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564410878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2564410878
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.497428868
Short name T29
Test name
Test status
Simulation time 854465092 ps
CPU time 6.78 seconds
Started Sep 11 05:06:20 PM UTC 24
Finished Sep 11 05:06:28 PM UTC 24
Peak memory 227684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497428868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.497428868
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.4108191949
Short name T27
Test name
Test status
Simulation time 164139733 ps
CPU time 1.45 seconds
Started Sep 11 05:06:20 PM UTC 24
Finished Sep 11 05:06:23 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108191949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.4108191949
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.3932732625
Short name T55
Test name
Test status
Simulation time 50324872784 ps
CPU time 16.54 seconds
Started Sep 11 05:06:24 PM UTC 24
Finished Sep 11 05:06:41 PM UTC 24
Peak memory 235332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932732625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3932732625
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/2.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_alert_test.4021034642
Short name T550
Test name
Test status
Simulation time 47375578 ps
CPU time 1.15 seconds
Started Sep 11 05:12:40 PM UTC 24
Finished Sep 11 05:12:42 PM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021034642 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.4021034642
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/20.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_cfg_cmd.2905310653
Short name T548
Test name
Test status
Simulation time 1443394627 ps
CPU time 3.08 seconds
Started Sep 11 05:12:33 PM UTC 24
Finished Sep 11 05:12:37 PM UTC 24
Peak memory 235144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905310653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2905310653
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/20.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_csb_read.3635102748
Short name T541
Test name
Test status
Simulation time 15088499 ps
CPU time 1.16 seconds
Started Sep 11 05:12:21 PM UTC 24
Finished Sep 11 05:12:23 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635102748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3635102748
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/20.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_all.3098602410
Short name T239
Test name
Test status
Simulation time 6879754060 ps
CPU time 38.94 seconds
Started Sep 11 05:12:37 PM UTC 24
Finished Sep 11 05:13:17 PM UTC 24
Peak memory 247744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098602410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3098602410
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/20.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.4228881651
Short name T596
Test name
Test status
Simulation time 6275484875 ps
CPU time 82.52 seconds
Started Sep 11 05:12:38 PM UTC 24
Finished Sep 11 05:14:03 PM UTC 24
Peak memory 266240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228881651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.4228881651
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode.3820202623
Short name T552
Test name
Test status
Simulation time 1023731234 ps
CPU time 10.23 seconds
Started Sep 11 05:12:34 PM UTC 24
Finished Sep 11 05:12:45 PM UTC 24
Peak memory 247656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820202623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3820202623
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/20.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.1804714204
Short name T656
Test name
Test status
Simulation time 42763381479 ps
CPU time 171.78 seconds
Started Sep 11 05:12:36 PM UTC 24
Finished Sep 11 05:15:30 PM UTC 24
Peak memory 266176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804714204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.1804714204
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_intercept.2801349273
Short name T545
Test name
Test status
Simulation time 450854142 ps
CPU time 4.45 seconds
Started Sep 11 05:12:27 PM UTC 24
Finished Sep 11 05:12:33 PM UTC 24
Peak memory 235540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801349273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2801349273
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/20.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_mailbox.789251819
Short name T345
Test name
Test status
Simulation time 3305408291 ps
CPU time 7.52 seconds
Started Sep 11 05:12:29 PM UTC 24
Finished Sep 11 05:12:37 PM UTC 24
Peak memory 235588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789251819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.789251819
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/20.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.3168655977
Short name T244
Test name
Test status
Simulation time 1483640595 ps
CPU time 6.81 seconds
Started Sep 11 05:12:27 PM UTC 24
Finished Sep 11 05:12:35 PM UTC 24
Peak memory 245568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168655977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.3168655977
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/20.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.3637695552
Short name T347
Test name
Test status
Simulation time 29185920034 ps
CPU time 19.98 seconds
Started Sep 11 05:12:25 PM UTC 24
Finished Sep 11 05:12:46 PM UTC 24
Peak memory 235428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637695552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3637695552
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/20.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.3416966232
Short name T551
Test name
Test status
Simulation time 1416969926 ps
CPU time 8.08 seconds
Started Sep 11 05:12:36 PM UTC 24
Finished Sep 11 05:12:45 PM UTC 24
Peak memory 233892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416966232 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.3416966232
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/20.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_stress_all.4133126003
Short name T574
Test name
Test status
Simulation time 8114361363 ps
CPU time 58.62 seconds
Started Sep 11 05:12:38 PM UTC 24
Finished Sep 11 05:13:38 PM UTC 24
Peak memory 235748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133126003 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.4133126003
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/20.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_all.3778494398
Short name T543
Test name
Test status
Simulation time 578350245 ps
CPU time 3.39 seconds
Started Sep 11 05:12:23 PM UTC 24
Finished Sep 11 05:12:27 PM UTC 24
Peak memory 227792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778494398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3778494398
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/20.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.51253371
Short name T549
Test name
Test status
Simulation time 16127364667 ps
CPU time 17.16 seconds
Started Sep 11 05:12:21 PM UTC 24
Finished Sep 11 05:12:39 PM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51253371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.51253371
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/20.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_rw.423812227
Short name T544
Test name
Test status
Simulation time 85958002 ps
CPU time 5.64 seconds
Started Sep 11 05:12:24 PM UTC 24
Finished Sep 11 05:12:31 PM UTC 24
Peak memory 227844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423812227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.423812227
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/20.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.4179158289
Short name T542
Test name
Test status
Simulation time 37977000 ps
CPU time 1.11 seconds
Started Sep 11 05:12:24 PM UTC 24
Finished Sep 11 05:12:26 PM UTC 24
Peak memory 215916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179158289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.4179158289
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/20.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_upload.2328315540
Short name T559
Test name
Test status
Simulation time 1296799494 ps
CPU time 20.08 seconds
Started Sep 11 05:12:32 PM UTC 24
Finished Sep 11 05:12:53 PM UTC 24
Peak memory 262104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328315540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2328315540
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/20.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_alert_test.1624592226
Short name T564
Test name
Test status
Simulation time 11876240 ps
CPU time 1.09 seconds
Started Sep 11 05:13:03 PM UTC 24
Finished Sep 11 05:13:05 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624592226 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.1624592226
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/21.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_cfg_cmd.2483977156
Short name T315
Test name
Test status
Simulation time 1255422568 ps
CPU time 5.9 seconds
Started Sep 11 05:12:50 PM UTC 24
Finished Sep 11 05:12:57 PM UTC 24
Peak memory 245592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483977156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2483977156
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/21.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_csb_read.98411988
Short name T553
Test name
Test status
Simulation time 15656580 ps
CPU time 1.17 seconds
Started Sep 11 05:12:43 PM UTC 24
Finished Sep 11 05:12:45 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98411988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.98411988
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/21.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_all.738023863
Short name T584
Test name
Test status
Simulation time 6207607884 ps
CPU time 50.44 seconds
Started Sep 11 05:12:56 PM UTC 24
Finished Sep 11 05:13:48 PM UTC 24
Peak memory 268484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738023863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.738023863
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/21.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.1472394052
Short name T290
Test name
Test status
Simulation time 70292364461 ps
CPU time 160.8 seconds
Started Sep 11 05:12:58 PM UTC 24
Finished Sep 11 05:15:41 PM UTC 24
Peak memory 251828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472394052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1472394052
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode.1242228082
Short name T575
Test name
Test status
Simulation time 3684309198 ps
CPU time 44.88 seconds
Started Sep 11 05:12:52 PM UTC 24
Finished Sep 11 05:13:39 PM UTC 24
Peak memory 262284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242228082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1242228082
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/21.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.1984433525
Short name T266
Test name
Test status
Simulation time 9335255889 ps
CPU time 32.33 seconds
Started Sep 11 05:12:54 PM UTC 24
Finished Sep 11 05:13:27 PM UTC 24
Peak memory 262076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984433525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.1984433525
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_intercept.4230559084
Short name T568
Test name
Test status
Simulation time 13580307195 ps
CPU time 23.13 seconds
Started Sep 11 05:12:49 PM UTC 24
Finished Sep 11 05:13:13 PM UTC 24
Peak memory 235612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230559084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4230559084
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/21.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_mailbox.4212673094
Short name T255
Test name
Test status
Simulation time 258393823 ps
CPU time 10.76 seconds
Started Sep 11 05:12:50 PM UTC 24
Finished Sep 11 05:13:02 PM UTC 24
Peak memory 251380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212673094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.4212673094
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/21.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.3250481842
Short name T558
Test name
Test status
Simulation time 1007491747 ps
CPU time 2.95 seconds
Started Sep 11 05:12:48 PM UTC 24
Finished Sep 11 05:12:52 PM UTC 24
Peak memory 234996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250481842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.3250481842
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/21.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.2234017703
Short name T562
Test name
Test status
Simulation time 1493887208 ps
CPU time 13.23 seconds
Started Sep 11 05:12:48 PM UTC 24
Finished Sep 11 05:13:02 PM UTC 24
Peak memory 245708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234017703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2234017703
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/21.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.3757571424
Short name T561
Test name
Test status
Simulation time 1469338068 ps
CPU time 6.57 seconds
Started Sep 11 05:12:54 PM UTC 24
Finished Sep 11 05:13:01 PM UTC 24
Peak memory 233668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757571424 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.3757571424
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/21.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_stress_all.1290932240
Short name T790
Test name
Test status
Simulation time 68779487509 ps
CPU time 303.74 seconds
Started Sep 11 05:13:02 PM UTC 24
Finished Sep 11 05:18:10 PM UTC 24
Peak memory 262148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290932240 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.1290932240
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/21.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_all.874542028
Short name T555
Test name
Test status
Simulation time 15005155 ps
CPU time 1.11 seconds
Started Sep 11 05:12:45 PM UTC 24
Finished Sep 11 05:12:48 PM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874542028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.874542028
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/21.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.2408274197
Short name T554
Test name
Test status
Simulation time 704596374 ps
CPU time 2.3 seconds
Started Sep 11 05:12:43 PM UTC 24
Finished Sep 11 05:12:47 PM UTC 24
Peak memory 217236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408274197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2408274197
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/21.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_rw.1303916316
Short name T557
Test name
Test status
Simulation time 259141261 ps
CPU time 2 seconds
Started Sep 11 05:12:47 PM UTC 24
Finished Sep 11 05:12:50 PM UTC 24
Peak memory 226684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303916316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1303916316
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/21.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.1714076226
Short name T556
Test name
Test status
Simulation time 37668362 ps
CPU time 1.08 seconds
Started Sep 11 05:12:47 PM UTC 24
Finished Sep 11 05:12:49 PM UTC 24
Peak memory 215796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714076226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1714076226
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/21.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_upload.1386659487
Short name T284
Test name
Test status
Simulation time 1336795304 ps
CPU time 7.45 seconds
Started Sep 11 05:12:50 PM UTC 24
Finished Sep 11 05:12:59 PM UTC 24
Peak memory 245248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386659487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1386659487
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/21.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_alert_test.3847212719
Short name T570
Test name
Test status
Simulation time 14186968 ps
CPU time 1.12 seconds
Started Sep 11 05:13:34 PM UTC 24
Finished Sep 11 05:13:36 PM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847212719 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.3847212719
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/22.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_cfg_cmd.2707442380
Short name T281
Test name
Test status
Simulation time 33363975 ps
CPU time 2.99 seconds
Started Sep 11 05:13:18 PM UTC 24
Finished Sep 11 05:13:22 PM UTC 24
Peak memory 235348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707442380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2707442380
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/22.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_csb_read.184040802
Short name T563
Test name
Test status
Simulation time 36970129 ps
CPU time 1 seconds
Started Sep 11 05:13:03 PM UTC 24
Finished Sep 11 05:13:05 PM UTC 24
Peak memory 215664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184040802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.184040802
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/22.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_all.364676000
Short name T622
Test name
Test status
Simulation time 17616712096 ps
CPU time 72.28 seconds
Started Sep 11 05:13:28 PM UTC 24
Finished Sep 11 05:14:43 PM UTC 24
Peak memory 262108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364676000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.364676000
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/22.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.2731715770
Short name T353
Test name
Test status
Simulation time 38735277547 ps
CPU time 397.03 seconds
Started Sep 11 05:13:30 PM UTC 24
Finished Sep 11 05:20:13 PM UTC 24
Peak memory 278552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731715770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2731715770
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/22.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.951221796
Short name T75
Test name
Test status
Simulation time 154766940929 ps
CPU time 428.08 seconds
Started Sep 11 05:13:30 PM UTC 24
Finished Sep 11 05:20:45 PM UTC 24
Peak memory 261928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951221796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.951221796
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode.235689924
Short name T569
Test name
Test status
Simulation time 102337121 ps
CPU time 4.98 seconds
Started Sep 11 05:13:23 PM UTC 24
Finished Sep 11 05:13:29 PM UTC 24
Peak memory 245596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235689924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.235689924
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/22.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.3316083357
Short name T582
Test name
Test status
Simulation time 1775403039 ps
CPU time 17.72 seconds
Started Sep 11 05:13:26 PM UTC 24
Finished Sep 11 05:13:45 PM UTC 24
Peak memory 262172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316083357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.3316083357
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_intercept.1220024357
Short name T272
Test name
Test status
Simulation time 3043330669 ps
CPU time 16.32 seconds
Started Sep 11 05:13:10 PM UTC 24
Finished Sep 11 05:13:27 PM UTC 24
Peak memory 235648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220024357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1220024357
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/22.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_mailbox.637690144
Short name T572
Test name
Test status
Simulation time 2440621271 ps
CPU time 23.56 seconds
Started Sep 11 05:13:13 PM UTC 24
Finished Sep 11 05:13:38 PM UTC 24
Peak memory 245628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637690144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.637690144
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/22.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.2188111188
Short name T333
Test name
Test status
Simulation time 5885440091 ps
CPU time 23.73 seconds
Started Sep 11 05:13:10 PM UTC 24
Finished Sep 11 05:13:35 PM UTC 24
Peak memory 245704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188111188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.2188111188
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/22.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.629867209
Short name T282
Test name
Test status
Simulation time 13848681059 ps
CPU time 14.89 seconds
Started Sep 11 05:13:10 PM UTC 24
Finished Sep 11 05:13:26 PM UTC 24
Peak memory 245896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629867209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.629867209
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/22.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.3169461858
Short name T571
Test name
Test status
Simulation time 3439424961 ps
CPU time 7.35 seconds
Started Sep 11 05:13:28 PM UTC 24
Finished Sep 11 05:13:37 PM UTC 24
Peak memory 233988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169461858 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.3169461858
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/22.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.225508001
Short name T175
Test name
Test status
Simulation time 10724447401 ps
CPU time 156.65 seconds
Started Sep 11 05:13:31 PM UTC 24
Finished Sep 11 05:16:10 PM UTC 24
Peak memory 278516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225508001 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.225508001
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/22.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_all.2278525730
Short name T565
Test name
Test status
Simulation time 251302450 ps
CPU time 1.08 seconds
Started Sep 11 05:13:06 PM UTC 24
Finished Sep 11 05:13:08 PM UTC 24
Peak memory 215672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278525730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2278525730
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/22.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.441758379
Short name T580
Test name
Test status
Simulation time 25540278818 ps
CPU time 35.41 seconds
Started Sep 11 05:13:06 PM UTC 24
Finished Sep 11 05:13:43 PM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441758379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.441758379
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/22.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_rw.3925409068
Short name T567
Test name
Test status
Simulation time 375150236 ps
CPU time 2.16 seconds
Started Sep 11 05:13:09 PM UTC 24
Finished Sep 11 05:13:12 PM UTC 24
Peak memory 227732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925409068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3925409068
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/22.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.2322027531
Short name T566
Test name
Test status
Simulation time 11355795 ps
CPU time 1.1 seconds
Started Sep 11 05:13:07 PM UTC 24
Finished Sep 11 05:13:09 PM UTC 24
Peak memory 215796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322027531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2322027531
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/22.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/22.spi_device_upload.1444608735
Short name T350
Test name
Test status
Simulation time 17915783031 ps
CPU time 21.32 seconds
Started Sep 11 05:13:14 PM UTC 24
Finished Sep 11 05:13:36 PM UTC 24
Peak memory 235452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444608735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1444608735
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/22.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_alert_test.1017708326
Short name T585
Test name
Test status
Simulation time 43852508 ps
CPU time 1.13 seconds
Started Sep 11 05:13:48 PM UTC 24
Finished Sep 11 05:13:50 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017708326 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.1017708326
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/23.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_cfg_cmd.861092350
Short name T583
Test name
Test status
Simulation time 1001588027 ps
CPU time 3.31 seconds
Started Sep 11 05:13:43 PM UTC 24
Finished Sep 11 05:13:47 PM UTC 24
Peak memory 234732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861092350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.861092350
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/23.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_csb_read.738402938
Short name T573
Test name
Test status
Simulation time 63394160 ps
CPU time 1.21 seconds
Started Sep 11 05:13:36 PM UTC 24
Finished Sep 11 05:13:38 PM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738402938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.738402938
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/23.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_all.1390799482
Short name T295
Test name
Test status
Simulation time 3046493115 ps
CPU time 60.05 seconds
Started Sep 11 05:13:44 PM UTC 24
Finished Sep 11 05:14:46 PM UTC 24
Peak memory 268224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390799482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1390799482
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/23.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.2171848709
Short name T800
Test name
Test status
Simulation time 86821326624 ps
CPU time 270.9 seconds
Started Sep 11 05:13:45 PM UTC 24
Finished Sep 11 05:18:20 PM UTC 24
Peak memory 262360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171848709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2171848709
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.1583321271
Short name T1003
Test name
Test status
Simulation time 47747744939 ps
CPU time 506.45 seconds
Started Sep 11 05:13:46 PM UTC 24
Finished Sep 11 05:22:19 PM UTC 24
Peak memory 278556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583321271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.1583321271
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode.1667625845
Short name T601
Test name
Test status
Simulation time 2468467932 ps
CPU time 22.24 seconds
Started Sep 11 05:13:43 PM UTC 24
Finished Sep 11 05:14:06 PM UTC 24
Peak memory 251464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667625845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1667625845
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/23.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.3864609123
Short name T613
Test name
Test status
Simulation time 2746129259 ps
CPU time 39.28 seconds
Started Sep 11 05:13:43 PM UTC 24
Finished Sep 11 05:14:24 PM UTC 24
Peak memory 268444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864609123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.3864609123
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_intercept.750244653
Short name T581
Test name
Test status
Simulation time 239144776 ps
CPU time 3.06 seconds
Started Sep 11 05:13:39 PM UTC 24
Finished Sep 11 05:13:43 PM UTC 24
Peak memory 242128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750244653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.750244653
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/23.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_mailbox.4072650601
Short name T589
Test name
Test status
Simulation time 381607557 ps
CPU time 9.19 seconds
Started Sep 11 05:13:41 PM UTC 24
Finished Sep 11 05:13:52 PM UTC 24
Peak memory 235484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072650601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4072650601
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/23.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.3797012455
Short name T243
Test name
Test status
Simulation time 8331769197 ps
CPU time 24.17 seconds
Started Sep 11 05:13:39 PM UTC 24
Finished Sep 11 05:14:05 PM UTC 24
Peak memory 262084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797012455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.3797012455
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/23.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.969682797
Short name T579
Test name
Test status
Simulation time 33224287 ps
CPU time 2.38 seconds
Started Sep 11 05:13:39 PM UTC 24
Finished Sep 11 05:13:43 PM UTC 24
Peak memory 245408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969682797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.969682797
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/23.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.3001731627
Short name T586
Test name
Test status
Simulation time 91039957 ps
CPU time 1.42 seconds
Started Sep 11 05:13:48 PM UTC 24
Finished Sep 11 05:13:50 PM UTC 24
Peak memory 215676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001731627 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.3001731627
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/23.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_all.4044394579
Short name T598
Test name
Test status
Simulation time 1512702592 ps
CPU time 25.77 seconds
Started Sep 11 05:13:38 PM UTC 24
Finished Sep 11 05:14:05 PM UTC 24
Peak memory 228012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044394579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.4044394579
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/23.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.3305668510
Short name T603
Test name
Test status
Simulation time 160373652299 ps
CPU time 29.9 seconds
Started Sep 11 05:13:37 PM UTC 24
Finished Sep 11 05:14:08 PM UTC 24
Peak memory 227828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305668510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3305668510
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/23.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_rw.4256668917
Short name T577
Test name
Test status
Simulation time 13017299 ps
CPU time 1.04 seconds
Started Sep 11 05:13:39 PM UTC 24
Finished Sep 11 05:13:41 PM UTC 24
Peak memory 215788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256668917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.4256668917
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/23.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.1164935203
Short name T576
Test name
Test status
Simulation time 157293025 ps
CPU time 1.3 seconds
Started Sep 11 05:13:38 PM UTC 24
Finished Sep 11 05:13:40 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164935203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1164935203
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/23.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_upload.1871487735
Short name T351
Test name
Test status
Simulation time 1279450173 ps
CPU time 11.62 seconds
Started Sep 11 05:13:41 PM UTC 24
Finished Sep 11 05:13:54 PM UTC 24
Peak memory 245784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871487735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1871487735
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/23.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_alert_test.2331244930
Short name T600
Test name
Test status
Simulation time 19508830 ps
CPU time 0.83 seconds
Started Sep 11 05:14:04 PM UTC 24
Finished Sep 11 05:14:05 PM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331244930 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.2331244930
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/24.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_cfg_cmd.2446611060
Short name T595
Test name
Test status
Simulation time 208650140 ps
CPU time 4.52 seconds
Started Sep 11 05:13:56 PM UTC 24
Finished Sep 11 05:14:02 PM UTC 24
Peak memory 245312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446611060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2446611060
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/24.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_csb_read.3842720854
Short name T587
Test name
Test status
Simulation time 14074522 ps
CPU time 1.18 seconds
Started Sep 11 05:13:49 PM UTC 24
Finished Sep 11 05:13:51 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842720854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3842720854
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/24.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.3750974587
Short name T316
Test name
Test status
Simulation time 34453306157 ps
CPU time 151.97 seconds
Started Sep 11 05:14:00 PM UTC 24
Finished Sep 11 05:16:35 PM UTC 24
Peak memory 262148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750974587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3750974587
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/24.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.2271874810
Short name T1001
Test name
Test status
Simulation time 55403374228 ps
CPU time 490.05 seconds
Started Sep 11 05:14:01 PM UTC 24
Finished Sep 11 05:22:18 PM UTC 24
Peak memory 284604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271874810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2271874810
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.1671798442
Short name T625
Test name
Test status
Simulation time 5447478547 ps
CPU time 46.04 seconds
Started Sep 11 05:14:02 PM UTC 24
Finished Sep 11 05:14:50 PM UTC 24
Peak memory 264208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671798442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.1671798442
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.1632309346
Short name T638
Test name
Test status
Simulation time 24816870118 ps
CPU time 64.39 seconds
Started Sep 11 05:13:56 PM UTC 24
Finished Sep 11 05:15:02 PM UTC 24
Peak memory 261944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632309346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1632309346
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/24.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.2422068072
Short name T321
Test name
Test status
Simulation time 40272198313 ps
CPU time 163.51 seconds
Started Sep 11 05:13:56 PM UTC 24
Finished Sep 11 05:16:42 PM UTC 24
Peak memory 251836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422068072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.2422068072
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_intercept.3523276797
Short name T233
Test name
Test status
Simulation time 192310486 ps
CPU time 6.29 seconds
Started Sep 11 05:13:54 PM UTC 24
Finished Sep 11 05:14:01 PM UTC 24
Peak memory 235520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523276797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3523276797
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/24.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_mailbox.1462685019
Short name T268
Test name
Test status
Simulation time 6220884482 ps
CPU time 30.69 seconds
Started Sep 11 05:13:55 PM UTC 24
Finished Sep 11 05:14:27 PM UTC 24
Peak memory 245716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462685019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1462685019
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/24.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.28404581
Short name T317
Test name
Test status
Simulation time 985102275 ps
CPU time 4.33 seconds
Started Sep 11 05:13:54 PM UTC 24
Finished Sep 11 05:13:59 PM UTC 24
Peak memory 235264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28404581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.28404581
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/24.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.4224419362
Short name T611
Test name
Test status
Simulation time 33410103770 ps
CPU time 29.02 seconds
Started Sep 11 05:13:53 PM UTC 24
Finished Sep 11 05:14:23 PM UTC 24
Peak memory 235464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224419362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.4224419362
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/24.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.1422163232
Short name T605
Test name
Test status
Simulation time 978542604 ps
CPU time 12.23 seconds
Started Sep 11 05:14:00 PM UTC 24
Finished Sep 11 05:14:13 PM UTC 24
Peak memory 231844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422163232 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.1422163232
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/24.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_stress_all.3083561577
Short name T288
Test name
Test status
Simulation time 15132860566 ps
CPU time 200.99 seconds
Started Sep 11 05:14:03 PM UTC 24
Finished Sep 11 05:17:28 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083561577 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.3083561577
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/24.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_all.1081926940
Short name T599
Test name
Test status
Simulation time 1598654341 ps
CPU time 28.2 seconds
Started Sep 11 05:13:51 PM UTC 24
Finished Sep 11 05:14:21 PM UTC 24
Peak memory 231912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081926940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1081926940
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/24.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.3601887234
Short name T592
Test name
Test status
Simulation time 182494830 ps
CPU time 2.43 seconds
Started Sep 11 05:13:51 PM UTC 24
Finished Sep 11 05:13:55 PM UTC 24
Peak memory 217236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601887234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3601887234
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/24.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_rw.4204877178
Short name T593
Test name
Test status
Simulation time 38101590 ps
CPU time 1.91 seconds
Started Sep 11 05:13:52 PM UTC 24
Finished Sep 11 05:13:55 PM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204877178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.4204877178
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/24.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.1360780577
Short name T591
Test name
Test status
Simulation time 18430458 ps
CPU time 1.15 seconds
Started Sep 11 05:13:52 PM UTC 24
Finished Sep 11 05:13:55 PM UTC 24
Peak memory 215916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360780577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1360780577
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/24.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/24.spi_device_upload.3502759399
Short name T616
Test name
Test status
Simulation time 4557034326 ps
CPU time 31.71 seconds
Started Sep 11 05:13:55 PM UTC 24
Finished Sep 11 05:14:28 PM UTC 24
Peak memory 251836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502759399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3502759399
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/24.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_alert_test.2972452140
Short name T614
Test name
Test status
Simulation time 38937994 ps
CPU time 1.12 seconds
Started Sep 11 05:14:24 PM UTC 24
Finished Sep 11 05:14:26 PM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972452140 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.2972452140
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/25.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_cfg_cmd.4278319930
Short name T610
Test name
Test status
Simulation time 55741103 ps
CPU time 2.73 seconds
Started Sep 11 05:14:17 PM UTC 24
Finished Sep 11 05:14:21 PM UTC 24
Peak memory 234888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278319930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.4278319930
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/25.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_csb_read.3533490311
Short name T602
Test name
Test status
Simulation time 32839348 ps
CPU time 1.09 seconds
Started Sep 11 05:14:06 PM UTC 24
Finished Sep 11 05:14:08 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533490311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3533490311
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/25.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_all.3662233614
Short name T634
Test name
Test status
Simulation time 13895179420 ps
CPU time 32.88 seconds
Started Sep 11 05:14:22 PM UTC 24
Finished Sep 11 05:14:56 PM UTC 24
Peak memory 251840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662233614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3662233614
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/25.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.3908666156
Short name T335
Test name
Test status
Simulation time 36222789435 ps
CPU time 193.77 seconds
Started Sep 11 05:14:23 PM UTC 24
Finished Sep 11 05:17:39 PM UTC 24
Peak memory 274456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908666156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3908666156
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.4072097381
Short name T953
Test name
Test status
Simulation time 129022760592 ps
CPU time 428.32 seconds
Started Sep 11 05:14:24 PM UTC 24
Finished Sep 11 05:21:38 PM UTC 24
Peak memory 278528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072097381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.4072097381
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode.1091093378
Short name T612
Test name
Test status
Simulation time 153895040 ps
CPU time 4.6 seconds
Started Sep 11 05:14:17 PM UTC 24
Finished Sep 11 05:14:23 PM UTC 24
Peak memory 245608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091093378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1091093378
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/25.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.2334018404
Short name T357
Test name
Test status
Simulation time 133687982008 ps
CPU time 506.56 seconds
Started Sep 11 05:14:21 PM UTC 24
Finished Sep 11 05:22:54 PM UTC 24
Peak memory 278468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334018404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.2334018404
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_intercept.3216655501
Short name T259
Test name
Test status
Simulation time 4215583222 ps
CPU time 13.07 seconds
Started Sep 11 05:14:09 PM UTC 24
Finished Sep 11 05:14:23 PM UTC 24
Peak memory 245984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216655501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3216655501
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/25.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_mailbox.809921243
Short name T654
Test name
Test status
Simulation time 7745141337 ps
CPU time 69.05 seconds
Started Sep 11 05:14:14 PM UTC 24
Finished Sep 11 05:15:25 PM UTC 24
Peak memory 235436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809921243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.809921243
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/25.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.3691032884
Short name T334
Test name
Test status
Simulation time 14199265433 ps
CPU time 17.6 seconds
Started Sep 11 05:14:09 PM UTC 24
Finished Sep 11 05:14:28 PM UTC 24
Peak memory 245700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691032884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.3691032884
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/25.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.1426260879
Short name T609
Test name
Test status
Simulation time 3363945627 ps
CPU time 10.67 seconds
Started Sep 11 05:14:09 PM UTC 24
Finished Sep 11 05:14:21 PM UTC 24
Peak memory 235464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426260879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1426260879
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/25.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.682236187
Short name T619
Test name
Test status
Simulation time 1267763196 ps
CPU time 13 seconds
Started Sep 11 05:14:22 PM UTC 24
Finished Sep 11 05:14:36 PM UTC 24
Peak memory 233832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682236187 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.682236187
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/25.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.2047985020
Short name T373
Test name
Test status
Simulation time 47055906182 ps
CPU time 500.33 seconds
Started Sep 11 05:14:24 PM UTC 24
Finished Sep 11 05:22:50 PM UTC 24
Peak memory 284672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047985020 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.2047985020
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/25.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_all.2900719540
Short name T608
Test name
Test status
Simulation time 10759378811 ps
CPU time 10.15 seconds
Started Sep 11 05:14:06 PM UTC 24
Finished Sep 11 05:14:17 PM UTC 24
Peak memory 231980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900719540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2900719540
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/25.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.683334443
Short name T607
Test name
Test status
Simulation time 4527677854 ps
CPU time 9.41 seconds
Started Sep 11 05:14:06 PM UTC 24
Finished Sep 11 05:14:16 PM UTC 24
Peak memory 227992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683334443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.683334443
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/25.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_rw.11772001
Short name T606
Test name
Test status
Simulation time 183040976 ps
CPU time 5.59 seconds
Started Sep 11 05:14:07 PM UTC 24
Finished Sep 11 05:14:13 PM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11772001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_devi
ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.11772001
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/25.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.409088932
Short name T604
Test name
Test status
Simulation time 179607397 ps
CPU time 1.38 seconds
Started Sep 11 05:14:06 PM UTC 24
Finished Sep 11 05:14:08 PM UTC 24
Peak memory 215912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409088932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.409088932
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/25.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/25.spi_device_upload.2943879452
Short name T304
Test name
Test status
Simulation time 772780830 ps
CPU time 6.58 seconds
Started Sep 11 05:14:14 PM UTC 24
Finished Sep 11 05:14:22 PM UTC 24
Peak memory 235392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943879452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2943879452
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/25.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_alert_test.2368417012
Short name T627
Test name
Test status
Simulation time 21575742 ps
CPU time 1.11 seconds
Started Sep 11 05:14:48 PM UTC 24
Finished Sep 11 05:14:51 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368417012 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.2368417012
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/26.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_cfg_cmd.529178716
Short name T623
Test name
Test status
Simulation time 312535828 ps
CPU time 4.21 seconds
Started Sep 11 05:14:42 PM UTC 24
Finished Sep 11 05:14:47 PM UTC 24
Peak memory 245504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529178716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.529178716
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/26.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_csb_read.2900528501
Short name T615
Test name
Test status
Simulation time 15736090 ps
CPU time 1.19 seconds
Started Sep 11 05:14:25 PM UTC 24
Finished Sep 11 05:14:27 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900528501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2900528501
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/26.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.1101747910
Short name T715
Test name
Test status
Simulation time 14118696409 ps
CPU time 120.36 seconds
Started Sep 11 05:14:44 PM UTC 24
Finished Sep 11 05:16:47 PM UTC 24
Peak memory 252060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101747910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1101747910
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/26.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.2641664680
Short name T648
Test name
Test status
Simulation time 8409422309 ps
CPU time 24.95 seconds
Started Sep 11 05:14:45 PM UTC 24
Finished Sep 11 05:15:11 PM UTC 24
Peak memory 230088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641664680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2641664680
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode.1660721477
Short name T633
Test name
Test status
Simulation time 272240177 ps
CPU time 11.04 seconds
Started Sep 11 05:14:43 PM UTC 24
Finished Sep 11 05:14:55 PM UTC 24
Peak memory 245556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660721477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1660721477
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/26.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.83763204
Short name T352
Test name
Test status
Simulation time 137187239933 ps
CPU time 282.69 seconds
Started Sep 11 05:14:44 PM UTC 24
Finished Sep 11 05:19:30 PM UTC 24
Peak memory 284644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83763204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.83763204
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_intercept.168884488
Short name T260
Test name
Test status
Simulation time 1361727593 ps
CPU time 18.74 seconds
Started Sep 11 05:14:32 PM UTC 24
Finished Sep 11 05:14:52 PM UTC 24
Peak memory 235332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168884488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.168884488
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/26.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_mailbox.3522413535
Short name T650
Test name
Test status
Simulation time 9700221328 ps
CPU time 35.7 seconds
Started Sep 11 05:14:37 PM UTC 24
Finished Sep 11 05:15:14 PM UTC 24
Peak memory 235480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522413535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3522413535
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/26.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.2669789930
Short name T620
Test name
Test status
Simulation time 297880441 ps
CPU time 6.47 seconds
Started Sep 11 05:14:31 PM UTC 24
Finished Sep 11 05:14:39 PM UTC 24
Peak memory 235272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669789930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.2669789930
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/26.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.451089575
Short name T626
Test name
Test status
Simulation time 25374970829 ps
CPU time 19.64 seconds
Started Sep 11 05:14:29 PM UTC 24
Finished Sep 11 05:14:50 PM UTC 24
Peak memory 235464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451089575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.451089575
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/26.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.3402467984
Short name T624
Test name
Test status
Simulation time 299349337 ps
CPU time 3.91 seconds
Started Sep 11 05:14:44 PM UTC 24
Finished Sep 11 05:14:49 PM UTC 24
Peak memory 231784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402467984 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.3402467984
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/26.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_all.1428448445
Short name T630
Test name
Test status
Simulation time 5204376254 ps
CPU time 23.11 seconds
Started Sep 11 05:14:28 PM UTC 24
Finished Sep 11 05:14:52 PM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428448445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1428448445
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/26.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.3828919870
Short name T631
Test name
Test status
Simulation time 5362526192 ps
CPU time 24.55 seconds
Started Sep 11 05:14:27 PM UTC 24
Finished Sep 11 05:14:53 PM UTC 24
Peak memory 228052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828919870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3828919870
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/26.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_rw.528478486
Short name T618
Test name
Test status
Simulation time 104292924 ps
CPU time 1.58 seconds
Started Sep 11 05:14:29 PM UTC 24
Finished Sep 11 05:14:32 PM UTC 24
Peak memory 216504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528478486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.528478486
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/26.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.3234336728
Short name T617
Test name
Test status
Simulation time 159292748 ps
CPU time 1.52 seconds
Started Sep 11 05:14:28 PM UTC 24
Finished Sep 11 05:14:31 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234336728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3234336728
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/26.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_upload.3482958033
Short name T639
Test name
Test status
Simulation time 3104932284 ps
CPU time 22.43 seconds
Started Sep 11 05:14:40 PM UTC 24
Finished Sep 11 05:15:03 PM UTC 24
Peak memory 245632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482958033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3482958033
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/26.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_alert_test.2020951839
Short name T640
Test name
Test status
Simulation time 12541771 ps
CPU time 1.09 seconds
Started Sep 11 05:15:03 PM UTC 24
Finished Sep 11 05:15:05 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020951839 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.2020951839
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/27.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_cfg_cmd.1067150527
Short name T645
Test name
Test status
Simulation time 868724967 ps
CPU time 13.62 seconds
Started Sep 11 05:14:54 PM UTC 24
Finished Sep 11 05:15:09 PM UTC 24
Peak memory 245420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067150527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1067150527
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/27.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_csb_read.3656186754
Short name T628
Test name
Test status
Simulation time 17382599 ps
CPU time 1.17 seconds
Started Sep 11 05:14:48 PM UTC 24
Finished Sep 11 05:14:51 PM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656186754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3656186754
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/27.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.2636039348
Short name T637
Test name
Test status
Simulation time 23577812 ps
CPU time 1.17 seconds
Started Sep 11 05:14:59 PM UTC 24
Finished Sep 11 05:15:02 PM UTC 24
Peak memory 225724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636039348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2636039348
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/27.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.2458672198
Short name T677
Test name
Test status
Simulation time 5322582628 ps
CPU time 53.25 seconds
Started Sep 11 05:15:00 PM UTC 24
Finished Sep 11 05:15:54 PM UTC 24
Peak memory 262360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458672198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2458672198
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.1750129578
Short name T822
Test name
Test status
Simulation time 40556102965 ps
CPU time 222.04 seconds
Started Sep 11 05:15:02 PM UTC 24
Finished Sep 11 05:18:47 PM UTC 24
Peak memory 262140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750129578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.1750129578
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode.3940687972
Short name T684
Test name
Test status
Simulation time 3541416976 ps
CPU time 66.33 seconds
Started Sep 11 05:14:54 PM UTC 24
Finished Sep 11 05:16:03 PM UTC 24
Peak memory 262120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940687972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3940687972
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/27.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.4195694884
Short name T661
Test name
Test status
Simulation time 5470742352 ps
CPU time 37.88 seconds
Started Sep 11 05:14:55 PM UTC 24
Finished Sep 11 05:15:35 PM UTC 24
Peak memory 251936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195694884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.4195694884
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_intercept.205512131
Short name T636
Test name
Test status
Simulation time 156566072 ps
CPU time 6.11 seconds
Started Sep 11 05:14:53 PM UTC 24
Finished Sep 11 05:15:01 PM UTC 24
Peak memory 235616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205512131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.205512131
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/27.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_mailbox.2535950927
Short name T734
Test name
Test status
Simulation time 12397478249 ps
CPU time 125.21 seconds
Started Sep 11 05:14:53 PM UTC 24
Finished Sep 11 05:17:01 PM UTC 24
Peak memory 262240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535950927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2535950927
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/27.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.846364248
Short name T372
Test name
Test status
Simulation time 119920936 ps
CPU time 4.3 seconds
Started Sep 11 05:14:53 PM UTC 24
Finished Sep 11 05:14:59 PM UTC 24
Peak memory 235268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846364248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.846364248
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/27.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.2241658047
Short name T251
Test name
Test status
Simulation time 3181248041 ps
CPU time 23.5 seconds
Started Sep 11 05:14:53 PM UTC 24
Finished Sep 11 05:15:18 PM UTC 24
Peak memory 245688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241658047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2241658047
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/27.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.1391333856
Short name T642
Test name
Test status
Simulation time 580872398 ps
CPU time 9.33 seconds
Started Sep 11 05:14:56 PM UTC 24
Finished Sep 11 05:15:07 PM UTC 24
Peak memory 233812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391333856 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.1391333856
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/27.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_all.2430188256
Short name T643
Test name
Test status
Simulation time 11132013726 ps
CPU time 16.17 seconds
Started Sep 11 05:14:51 PM UTC 24
Finished Sep 11 05:15:08 PM UTC 24
Peak memory 227880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430188256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2430188256
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/27.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.3033972621
Short name T629
Test name
Test status
Simulation time 11022931 ps
CPU time 1.05 seconds
Started Sep 11 05:14:49 PM UTC 24
Finished Sep 11 05:14:52 PM UTC 24
Peak memory 215672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033972621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3033972621
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/27.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_rw.3120035502
Short name T635
Test name
Test status
Simulation time 133066258 ps
CPU time 4.37 seconds
Started Sep 11 05:14:53 PM UTC 24
Finished Sep 11 05:14:59 PM UTC 24
Peak memory 227732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120035502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3120035502
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/27.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.1889676708
Short name T632
Test name
Test status
Simulation time 21615038 ps
CPU time 1.23 seconds
Started Sep 11 05:14:51 PM UTC 24
Finished Sep 11 05:14:53 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889676708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1889676708
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/27.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_upload.2013010572
Short name T644
Test name
Test status
Simulation time 12735615051 ps
CPU time 12.8 seconds
Started Sep 11 05:14:54 PM UTC 24
Finished Sep 11 05:15:08 PM UTC 24
Peak memory 235392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013010572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2013010572
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/27.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_alert_test.3271843454
Short name T655
Test name
Test status
Simulation time 41670561 ps
CPU time 0.94 seconds
Started Sep 11 05:15:25 PM UTC 24
Finished Sep 11 05:15:27 PM UTC 24
Peak memory 215672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271843454 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.3271843454
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/28.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_cfg_cmd.1647171418
Short name T653
Test name
Test status
Simulation time 2199636310 ps
CPU time 9.36 seconds
Started Sep 11 05:15:13 PM UTC 24
Finished Sep 11 05:15:23 PM UTC 24
Peak memory 235452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647171418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1647171418
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/28.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_csb_read.687498010
Short name T641
Test name
Test status
Simulation time 35160577 ps
CPU time 1.14 seconds
Started Sep 11 05:15:04 PM UTC 24
Finished Sep 11 05:15:06 PM UTC 24
Peak memory 215664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687498010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.687498010
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/28.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_all.1205994601
Short name T364
Test name
Test status
Simulation time 99158164819 ps
CPU time 196.5 seconds
Started Sep 11 05:15:19 PM UTC 24
Finished Sep 11 05:18:38 PM UTC 24
Peak memory 264128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205994601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1205994601
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/28.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.74560261
Short name T702
Test name
Test status
Simulation time 8211538340 ps
CPU time 71.68 seconds
Started Sep 11 05:15:19 PM UTC 24
Finished Sep 11 05:16:32 PM UTC 24
Peak memory 266360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74560261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.74560261
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/28.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.4240936620
Short name T658
Test name
Test status
Simulation time 919904365 ps
CPU time 9.94 seconds
Started Sep 11 05:15:21 PM UTC 24
Finished Sep 11 05:15:32 PM UTC 24
Peak memory 234028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240936620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.4240936620
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode.3713390967
Short name T652
Test name
Test status
Simulation time 398143698 ps
CPU time 4.65 seconds
Started Sep 11 05:15:13 PM UTC 24
Finished Sep 11 05:15:18 PM UTC 24
Peak memory 235368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713390967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3713390967
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/28.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.1203091654
Short name T302
Test name
Test status
Simulation time 10424286997 ps
CPU time 75.53 seconds
Started Sep 11 05:15:15 PM UTC 24
Finished Sep 11 05:16:32 PM UTC 24
Peak memory 245760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203091654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.1203091654
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_intercept.1390386399
Short name T241
Test name
Test status
Simulation time 1258409334 ps
CPU time 20.32 seconds
Started Sep 11 05:15:10 PM UTC 24
Finished Sep 11 05:15:32 PM UTC 24
Peak memory 235328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390386399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1390386399
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/28.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_mailbox.1735596464
Short name T338
Test name
Test status
Simulation time 7684071053 ps
CPU time 76.2 seconds
Started Sep 11 05:15:10 PM UTC 24
Finished Sep 11 05:16:29 PM UTC 24
Peak memory 252028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735596464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1735596464
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/28.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.3564510631
Short name T325
Test name
Test status
Simulation time 279403874 ps
CPU time 9.35 seconds
Started Sep 11 05:15:09 PM UTC 24
Finished Sep 11 05:15:20 PM UTC 24
Peak memory 245828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564510631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.3564510631
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/28.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.2408275426
Short name T229
Test name
Test status
Simulation time 7431821373 ps
CPU time 33.27 seconds
Started Sep 11 05:15:09 PM UTC 24
Finished Sep 11 05:15:44 PM UTC 24
Peak memory 244320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408275426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2408275426
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/28.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.1133177259
Short name T659
Test name
Test status
Simulation time 5089981061 ps
CPU time 15.01 seconds
Started Sep 11 05:15:17 PM UTC 24
Finished Sep 11 05:15:33 PM UTC 24
Peak memory 231780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133177259 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.1133177259
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/28.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.447967809
Short name T756
Test name
Test status
Simulation time 21710592969 ps
CPU time 118.53 seconds
Started Sep 11 05:15:24 PM UTC 24
Finished Sep 11 05:17:25 PM UTC 24
Peak memory 278544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447967809 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.447967809
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/28.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_all.614556584
Short name T665
Test name
Test status
Simulation time 4399311855 ps
CPU time 33.04 seconds
Started Sep 11 05:15:06 PM UTC 24
Finished Sep 11 05:15:41 PM UTC 24
Peak memory 228104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614556584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.614556584
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/28.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.3491146372
Short name T649
Test name
Test status
Simulation time 1479596578 ps
CPU time 4.74 seconds
Started Sep 11 05:15:06 PM UTC 24
Finished Sep 11 05:15:12 PM UTC 24
Peak memory 227684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491146372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3491146372
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/28.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_rw.2567290353
Short name T647
Test name
Test status
Simulation time 16770624 ps
CPU time 1.17 seconds
Started Sep 11 05:15:08 PM UTC 24
Finished Sep 11 05:15:11 PM UTC 24
Peak memory 215972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567290353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2567290353
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/28.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.100126503
Short name T646
Test name
Test status
Simulation time 193096970 ps
CPU time 1.22 seconds
Started Sep 11 05:15:07 PM UTC 24
Finished Sep 11 05:15:09 PM UTC 24
Peak memory 215912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100126503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.100126503
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/28.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/28.spi_device_upload.291032235
Short name T651
Test name
Test status
Simulation time 41913880 ps
CPU time 3.25 seconds
Started Sep 11 05:15:11 PM UTC 24
Finished Sep 11 05:15:16 PM UTC 24
Peak memory 235228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291032235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.291032235
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/28.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_alert_test.1536650370
Short name T670
Test name
Test status
Simulation time 23418267 ps
CPU time 1.12 seconds
Started Sep 11 05:15:45 PM UTC 24
Finished Sep 11 05:15:47 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536650370 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.1536650370
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/29.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_cfg_cmd.1796745878
Short name T666
Test name
Test status
Simulation time 195819932 ps
CPU time 4.54 seconds
Started Sep 11 05:15:36 PM UTC 24
Finished Sep 11 05:15:42 PM UTC 24
Peak memory 245756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796745878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1796745878
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/29.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_csb_read.4035041219
Short name T657
Test name
Test status
Simulation time 52529307 ps
CPU time 1.19 seconds
Started Sep 11 05:15:28 PM UTC 24
Finished Sep 11 05:15:31 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035041219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.4035041219
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/29.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.634004308
Short name T669
Test name
Test status
Simulation time 111373167 ps
CPU time 1.35 seconds
Started Sep 11 05:15:41 PM UTC 24
Finished Sep 11 05:15:44 PM UTC 24
Peak memory 227760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634004308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.634004308
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/29.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.1879929122
Short name T79
Test name
Test status
Simulation time 7111613034 ps
CPU time 29.15 seconds
Started Sep 11 05:15:42 PM UTC 24
Finished Sep 11 05:16:13 PM UTC 24
Peak memory 262328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879929122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1879929122
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.1975210986
Short name T363
Test name
Test status
Simulation time 6111222723 ps
CPU time 90.4 seconds
Started Sep 11 05:15:42 PM UTC 24
Finished Sep 11 05:17:15 PM UTC 24
Peak memory 262140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975210986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.1975210986
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode.3782853181
Short name T673
Test name
Test status
Simulation time 875086754 ps
CPU time 7.8 seconds
Started Sep 11 05:15:40 PM UTC 24
Finished Sep 11 05:15:49 PM UTC 24
Peak memory 245608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782853181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3782853181
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/29.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.3208749974
Short name T692
Test name
Test status
Simulation time 2115126385 ps
CPU time 30.03 seconds
Started Sep 11 05:15:40 PM UTC 24
Finished Sep 11 05:16:12 PM UTC 24
Peak memory 251716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208749974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.3208749974
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_intercept.4185085253
Short name T682
Test name
Test status
Simulation time 4723423050 ps
CPU time 22.85 seconds
Started Sep 11 05:15:35 PM UTC 24
Finished Sep 11 05:15:59 PM UTC 24
Peak memory 245704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185085253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.4185085253
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/29.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_mailbox.1970312557
Short name T686
Test name
Test status
Simulation time 8426615536 ps
CPU time 29.36 seconds
Started Sep 11 05:15:35 PM UTC 24
Finished Sep 11 05:16:06 PM UTC 24
Peak memory 252060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970312557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1970312557
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/29.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.1677716237
Short name T336
Test name
Test status
Simulation time 236022407 ps
CPU time 3.98 seconds
Started Sep 11 05:15:34 PM UTC 24
Finished Sep 11 05:15:39 PM UTC 24
Peak memory 245572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677716237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.1677716237
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/29.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.1447562177
Short name T667
Test name
Test status
Simulation time 1260427857 ps
CPU time 9.19 seconds
Started Sep 11 05:15:33 PM UTC 24
Finished Sep 11 05:15:43 PM UTC 24
Peak memory 235336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447562177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1447562177
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/29.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.4078453120
Short name T681
Test name
Test status
Simulation time 1117298571 ps
CPU time 16.05 seconds
Started Sep 11 05:15:41 PM UTC 24
Finished Sep 11 05:15:59 PM UTC 24
Peak memory 231592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078453120 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.4078453120
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/29.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_all.1650802044
Short name T668
Test name
Test status
Simulation time 6721126375 ps
CPU time 11 seconds
Started Sep 11 05:15:31 PM UTC 24
Finished Sep 11 05:15:44 PM UTC 24
Peak memory 227972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650802044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1650802044
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/29.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.4141481794
Short name T672
Test name
Test status
Simulation time 74285663361 ps
CPU time 18.69 seconds
Started Sep 11 05:15:28 PM UTC 24
Finished Sep 11 05:15:48 PM UTC 24
Peak memory 228108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141481794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.4141481794
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/29.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_rw.450082115
Short name T662
Test name
Test status
Simulation time 210690191 ps
CPU time 1.53 seconds
Started Sep 11 05:15:33 PM UTC 24
Finished Sep 11 05:15:35 PM UTC 24
Peak memory 216972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450082115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.450082115
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/29.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.3402630649
Short name T660
Test name
Test status
Simulation time 118434515 ps
CPU time 1.12 seconds
Started Sep 11 05:15:31 PM UTC 24
Finished Sep 11 05:15:34 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402630649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3402630649
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/29.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_upload.2986496203
Short name T664
Test name
Test status
Simulation time 37433749 ps
CPU time 2.99 seconds
Started Sep 11 05:15:36 PM UTC 24
Finished Sep 11 05:15:40 PM UTC 24
Peak memory 235160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986496203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2986496203
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/29.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.340850216
Short name T408
Test name
Test status
Simulation time 33021248 ps
CPU time 1.09 seconds
Started Sep 11 05:06:49 PM UTC 24
Finished Sep 11 05:06:51 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340850216 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.340850216
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.1445636605
Short name T64
Test name
Test status
Simulation time 93610657 ps
CPU time 3.61 seconds
Started Sep 11 05:06:36 PM UTC 24
Finished Sep 11 05:06:41 PM UTC 24
Peak memory 245568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445636605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1445636605
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.269098485
Short name T176
Test name
Test status
Simulation time 18409840 ps
CPU time 1.27 seconds
Started Sep 11 05:06:29 PM UTC 24
Finished Sep 11 05:06:32 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269098485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.269098485
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.1576871590
Short name T96
Test name
Test status
Simulation time 27088683582 ps
CPU time 239.46 seconds
Started Sep 11 05:06:42 PM UTC 24
Finished Sep 11 05:10:45 PM UTC 24
Peak memory 268228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576871590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1576871590
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.2725144311
Short name T509
Test name
Test status
Simulation time 31262423891 ps
CPU time 296.72 seconds
Started Sep 11 05:06:43 PM UTC 24
Finished Sep 11 05:11:44 PM UTC 24
Peak memory 278784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725144311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2725144311
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.1886247462
Short name T221
Test name
Test status
Simulation time 23563746230 ps
CPU time 239.05 seconds
Started Sep 11 05:06:43 PM UTC 24
Finished Sep 11 05:10:46 PM UTC 24
Peak memory 268324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886247462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.1886247462
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.1755412160
Short name T92
Test name
Test status
Simulation time 81706289 ps
CPU time 4.06 seconds
Started Sep 11 05:06:37 PM UTC 24
Finished Sep 11 05:06:42 PM UTC 24
Peak memory 235332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755412160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1755412160
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.3873628493
Short name T88
Test name
Test status
Simulation time 2208267468 ps
CPU time 39.89 seconds
Started Sep 11 05:06:38 PM UTC 24
Finished Sep 11 05:07:20 PM UTC 24
Peak memory 262284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873628493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.3873628493
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.755427288
Short name T209
Test name
Test status
Simulation time 2415376260 ps
CPU time 22.93 seconds
Started Sep 11 05:06:35 PM UTC 24
Finished Sep 11 05:06:59 PM UTC 24
Peak memory 245668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755427288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.755427288
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.971721775
Short name T94
Test name
Test status
Simulation time 525242212 ps
CPU time 14.89 seconds
Started Sep 11 05:06:36 PM UTC 24
Finished Sep 11 05:06:52 PM UTC 24
Peak memory 245532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971721775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.971721775
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.4253395686
Short name T47
Test name
Test status
Simulation time 91277560 ps
CPU time 1.55 seconds
Started Sep 11 05:06:31 PM UTC 24
Finished Sep 11 05:06:34 PM UTC 24
Peak memory 229192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253395686 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_parity.4253395686
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.3398481892
Short name T61
Test name
Test status
Simulation time 4361752919 ps
CPU time 18.16 seconds
Started Sep 11 05:06:35 PM UTC 24
Finished Sep 11 05:06:54 PM UTC 24
Peak memory 245836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398481892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.3398481892
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.3722853839
Short name T179
Test name
Test status
Simulation time 7167796068 ps
CPU time 14.6 seconds
Started Sep 11 05:06:34 PM UTC 24
Finished Sep 11 05:06:50 PM UTC 24
Peak memory 245640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722853839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3722853839
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.478670141
Short name T93
Test name
Test status
Simulation time 1688633091 ps
CPU time 13.4 seconds
Started Sep 11 05:06:41 PM UTC 24
Finished Sep 11 05:06:56 PM UTC 24
Peak memory 231596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478670141 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.478670141
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.2013844694
Short name T34
Test name
Test status
Simulation time 310856294 ps
CPU time 1.96 seconds
Started Sep 11 05:06:47 PM UTC 24
Finished Sep 11 05:06:50 PM UTC 24
Peak memory 257728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013844694 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2013844694
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.781099209
Short name T170
Test name
Test status
Simulation time 42804158128 ps
CPU time 325.99 seconds
Started Sep 11 05:06:45 PM UTC 24
Finished Sep 11 05:12:15 PM UTC 24
Peak memory 284668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781099209 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.781099209
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.589770667
Short name T71
Test name
Test status
Simulation time 1413618304 ps
CPU time 28.39 seconds
Started Sep 11 05:06:33 PM UTC 24
Finished Sep 11 05:07:02 PM UTC 24
Peak memory 227748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589770667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.589770667
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.932144234
Short name T407
Test name
Test status
Simulation time 12447145 ps
CPU time 1.13 seconds
Started Sep 11 05:06:32 PM UTC 24
Finished Sep 11 05:06:35 PM UTC 24
Peak memory 215672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932144234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.932144234
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.3446201710
Short name T45
Test name
Test status
Simulation time 106231681 ps
CPU time 2.25 seconds
Started Sep 11 05:06:34 PM UTC 24
Finished Sep 11 05:06:37 PM UTC 24
Peak memory 227756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446201710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3446201710
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.243536020
Short name T32
Test name
Test status
Simulation time 289264080 ps
CPU time 1.52 seconds
Started Sep 11 05:06:33 PM UTC 24
Finished Sep 11 05:06:35 PM UTC 24
Peak memory 215912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243536020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.243536020
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.1754001323
Short name T62
Test name
Test status
Simulation time 5244106108 ps
CPU time 36.96 seconds
Started Sep 11 05:06:36 PM UTC 24
Finished Sep 11 05:07:14 PM UTC 24
Peak memory 251868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754001323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1754001323
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/3.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_alert_test.3374673457
Short name T688
Test name
Test status
Simulation time 14138409 ps
CPU time 1.12 seconds
Started Sep 11 05:16:05 PM UTC 24
Finished Sep 11 05:16:08 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374673457 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.3374673457
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/30.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_cfg_cmd.1629871480
Short name T84
Test name
Test status
Simulation time 2186523541 ps
CPU time 25.28 seconds
Started Sep 11 05:15:56 PM UTC 24
Finished Sep 11 05:16:22 PM UTC 24
Peak memory 245636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629871480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1629871480
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/30.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_csb_read.2307282089
Short name T671
Test name
Test status
Simulation time 28376020 ps
CPU time 1.13 seconds
Started Sep 11 05:15:45 PM UTC 24
Finished Sep 11 05:15:47 PM UTC 24
Peak memory 215664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307282089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2307282089
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/30.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_all.3301130447
Short name T687
Test name
Test status
Simulation time 287407912 ps
CPU time 5.67 seconds
Started Sep 11 05:15:59 PM UTC 24
Finished Sep 11 05:16:06 PM UTC 24
Peak memory 245632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301130447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3301130447
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/30.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.4178189372
Short name T714
Test name
Test status
Simulation time 1744331306 ps
CPU time 44.76 seconds
Started Sep 11 05:16:00 PM UTC 24
Finished Sep 11 05:16:46 PM UTC 24
Peak memory 262228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178189372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.4178189372
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/30.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.1928582118
Short name T738
Test name
Test status
Simulation time 28980129188 ps
CPU time 59.68 seconds
Started Sep 11 05:16:03 PM UTC 24
Finished Sep 11 05:17:04 PM UTC 24
Peak memory 234184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928582118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.1928582118
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode.1117535820
Short name T697
Test name
Test status
Simulation time 4571162731 ps
CPU time 31.16 seconds
Started Sep 11 05:15:56 PM UTC 24
Finished Sep 11 05:16:28 PM UTC 24
Peak memory 245704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117535820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1117535820
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/30.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_intercept.2973242116
Short name T680
Test name
Test status
Simulation time 230641432 ps
CPU time 2.83 seconds
Started Sep 11 05:15:51 PM UTC 24
Finished Sep 11 05:15:55 PM UTC 24
Peak memory 245572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973242116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2973242116
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/30.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_mailbox.211290943
Short name T782
Test name
Test status
Simulation time 52055744503 ps
CPU time 120.95 seconds
Started Sep 11 05:15:55 PM UTC 24
Finished Sep 11 05:17:58 PM UTC 24
Peak memory 245684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211290943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.211290943
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/30.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.1207717331
Short name T678
Test name
Test status
Simulation time 196355367 ps
CPU time 3.59 seconds
Started Sep 11 05:15:50 PM UTC 24
Finished Sep 11 05:15:55 PM UTC 24
Peak memory 245572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207717331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.1207717331
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/30.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.3667596028
Short name T675
Test name
Test status
Simulation time 31447286 ps
CPU time 2.8 seconds
Started Sep 11 05:15:50 PM UTC 24
Finished Sep 11 05:15:54 PM UTC 24
Peak memory 232656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667596028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3667596028
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/30.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.1887480972
Short name T685
Test name
Test status
Simulation time 543272275 ps
CPU time 6.44 seconds
Started Sep 11 05:15:56 PM UTC 24
Finished Sep 11 05:16:03 PM UTC 24
Peak memory 234212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887480972 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.1887480972
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/30.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.3013522502
Short name T318
Test name
Test status
Simulation time 58558010194 ps
CPU time 322.21 seconds
Started Sep 11 05:16:03 PM UTC 24
Finished Sep 11 05:21:30 PM UTC 24
Peak memory 284804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013522502 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.3013522502
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/30.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_all.3962382737
Short name T683
Test name
Test status
Simulation time 5272603938 ps
CPU time 12.88 seconds
Started Sep 11 05:15:48 PM UTC 24
Finished Sep 11 05:16:02 PM UTC 24
Peak memory 228072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962382737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3962382737
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/30.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.1572573416
Short name T676
Test name
Test status
Simulation time 4034999223 ps
CPU time 8.35 seconds
Started Sep 11 05:15:45 PM UTC 24
Finished Sep 11 05:15:54 PM UTC 24
Peak memory 228080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572573416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1572573416
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/30.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_rw.2993595812
Short name T679
Test name
Test status
Simulation time 297888698 ps
CPU time 3.98 seconds
Started Sep 11 05:15:50 PM UTC 24
Finished Sep 11 05:15:55 PM UTC 24
Peak memory 227752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993595812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2993595812
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/30.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.2789387236
Short name T674
Test name
Test status
Simulation time 39406768 ps
CPU time 1.4 seconds
Started Sep 11 05:15:48 PM UTC 24
Finished Sep 11 05:15:50 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789387236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2789387236
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/30.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_upload.420565582
Short name T691
Test name
Test status
Simulation time 2407024356 ps
CPU time 14.38 seconds
Started Sep 11 05:15:55 PM UTC 24
Finished Sep 11 05:16:10 PM UTC 24
Peak memory 235456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420565582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.420565582
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/30.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_alert_test.3936270609
Short name T694
Test name
Test status
Simulation time 10791135 ps
CPU time 1.1 seconds
Started Sep 11 05:16:24 PM UTC 24
Finished Sep 11 05:16:26 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936270609 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.3936270609
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/31.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_cfg_cmd.4049926205
Short name T80
Test name
Test status
Simulation time 36353246 ps
CPU time 3 seconds
Started Sep 11 05:16:12 PM UTC 24
Finished Sep 11 05:16:16 PM UTC 24
Peak memory 245728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049926205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4049926205
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/31.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_csb_read.3899215742
Short name T689
Test name
Test status
Simulation time 52080563 ps
CPU time 1.16 seconds
Started Sep 11 05:16:06 PM UTC 24
Finished Sep 11 05:16:08 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899215742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3899215742
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/31.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_all.213408872
Short name T86
Test name
Test status
Simulation time 60221174 ps
CPU time 1.6 seconds
Started Sep 11 05:16:20 PM UTC 24
Finished Sep 11 05:16:23 PM UTC 24
Peak memory 225720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213408872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.213408872
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/31.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.3023821543
Short name T704
Test name
Test status
Simulation time 3015601398 ps
CPU time 12.77 seconds
Started Sep 11 05:16:23 PM UTC 24
Finished Sep 11 05:16:37 PM UTC 24
Peak memory 232100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023821543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3023821543
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.2630266167
Short name T313
Test name
Test status
Simulation time 6105236136 ps
CPU time 123.75 seconds
Started Sep 11 05:16:23 PM UTC 24
Finished Sep 11 05:18:29 PM UTC 24
Peak memory 274652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630266167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.2630266167
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode.1622464360
Short name T769
Test name
Test status
Simulation time 48512206437 ps
CPU time 84.17 seconds
Started Sep 11 05:16:13 PM UTC 24
Finished Sep 11 05:17:40 PM UTC 24
Peak memory 250060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622464360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1622464360
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/31.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.2145860896
Short name T948
Test name
Test status
Simulation time 124830068705 ps
CPU time 312.33 seconds
Started Sep 11 05:16:13 PM UTC 24
Finished Sep 11 05:21:31 PM UTC 24
Peak memory 278464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145860896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.2145860896
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_intercept.2337089577
Short name T85
Test name
Test status
Simulation time 2750357883 ps
CPU time 10.43 seconds
Started Sep 11 05:16:11 PM UTC 24
Finished Sep 11 05:16:23 PM UTC 24
Peak memory 245856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337089577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2337089577
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/31.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_mailbox.372506588
Short name T83
Test name
Test status
Simulation time 376023953 ps
CPU time 9.81 seconds
Started Sep 11 05:16:11 PM UTC 24
Finished Sep 11 05:16:22 PM UTC 24
Peak memory 245564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372506588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.372506588
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/31.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.2393576435
Short name T81
Test name
Test status
Simulation time 244178127 ps
CPU time 7.58 seconds
Started Sep 11 05:16:10 PM UTC 24
Finished Sep 11 05:16:19 PM UTC 24
Peak memory 235268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393576435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.2393576435
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/31.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.2503948281
Short name T708
Test name
Test status
Simulation time 9635294042 ps
CPU time 30.63 seconds
Started Sep 11 05:16:09 PM UTC 24
Finished Sep 11 05:16:41 PM UTC 24
Peak memory 245564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503948281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2503948281
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/31.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.432095024
Short name T701
Test name
Test status
Simulation time 4442882863 ps
CPU time 12.35 seconds
Started Sep 11 05:16:17 PM UTC 24
Finished Sep 11 05:16:32 PM UTC 24
Peak memory 233992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432095024 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.432095024
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/31.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.167375590
Short name T696
Test name
Test status
Simulation time 53926098 ps
CPU time 1.48 seconds
Started Sep 11 05:16:24 PM UTC 24
Finished Sep 11 05:16:26 PM UTC 24
Peak memory 216256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167375590 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.167375590
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/31.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_all.3263276065
Short name T82
Test name
Test status
Simulation time 1845236515 ps
CPU time 14.12 seconds
Started Sep 11 05:16:07 PM UTC 24
Finished Sep 11 05:16:22 PM UTC 24
Peak memory 227784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263276065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3263276065
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/31.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.10875326
Short name T700
Test name
Test status
Simulation time 53067339030 ps
CPU time 23.1 seconds
Started Sep 11 05:16:07 PM UTC 24
Finished Sep 11 05:16:31 PM UTC 24
Peak memory 227824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10875326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.10875326
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/31.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_rw.4042157517
Short name T693
Test name
Test status
Simulation time 185379940 ps
CPU time 1.96 seconds
Started Sep 11 05:16:09 PM UTC 24
Finished Sep 11 05:16:12 PM UTC 24
Peak memory 227752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042157517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.4042157517
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/31.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.4098431845
Short name T690
Test name
Test status
Simulation time 173523844 ps
CPU time 1.24 seconds
Started Sep 11 05:16:07 PM UTC 24
Finished Sep 11 05:16:09 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098431845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.4098431845
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/31.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/31.spi_device_upload.2596189162
Short name T743
Test name
Test status
Simulation time 64911764871 ps
CPU time 54.48 seconds
Started Sep 11 05:16:12 PM UTC 24
Finished Sep 11 05:17:08 PM UTC 24
Peak memory 251804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596189162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2596189162
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/31.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_alert_test.3163111516
Short name T709
Test name
Test status
Simulation time 23572562 ps
CPU time 1.16 seconds
Started Sep 11 05:16:39 PM UTC 24
Finished Sep 11 05:16:42 PM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163111516 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.3163111516
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/32.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_cfg_cmd.2629384224
Short name T706
Test name
Test status
Simulation time 51270948 ps
CPU time 3.38 seconds
Started Sep 11 05:16:34 PM UTC 24
Finished Sep 11 05:16:39 PM UTC 24
Peak memory 245564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629384224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2629384224
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/32.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_csb_read.3677623590
Short name T695
Test name
Test status
Simulation time 19970015 ps
CPU time 1.11 seconds
Started Sep 11 05:16:24 PM UTC 24
Finished Sep 11 05:16:26 PM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677623590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3677623590
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/32.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_all.1741753078
Short name T860
Test name
Test status
Simulation time 21937645957 ps
CPU time 180.73 seconds
Started Sep 11 05:16:34 PM UTC 24
Finished Sep 11 05:19:38 PM UTC 24
Peak memory 268256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741753078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1741753078
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/32.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.1717326166
Short name T830
Test name
Test status
Simulation time 10462908340 ps
CPU time 136.54 seconds
Started Sep 11 05:16:36 PM UTC 24
Finished Sep 11 05:18:55 PM UTC 24
Peak memory 278548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717326166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1717326166
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.4108456284
Short name T779
Test name
Test status
Simulation time 24251632186 ps
CPU time 72.92 seconds
Started Sep 11 05:16:37 PM UTC 24
Finished Sep 11 05:17:52 PM UTC 24
Peak memory 262136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108456284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.4108456284
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode.1059520946
Short name T721
Test name
Test status
Simulation time 631770596 ps
CPU time 13.82 seconds
Started Sep 11 05:16:34 PM UTC 24
Finished Sep 11 05:16:49 PM UTC 24
Peak memory 235328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059520946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1059520946
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/32.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_intercept.1993423255
Short name T246
Test name
Test status
Simulation time 5475015762 ps
CPU time 15.44 seconds
Started Sep 11 05:16:30 PM UTC 24
Finished Sep 11 05:16:47 PM UTC 24
Peak memory 235588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993423255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1993423255
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/32.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_mailbox.1293591576
Short name T705
Test name
Test status
Simulation time 474640615 ps
CPU time 5.27 seconds
Started Sep 11 05:16:32 PM UTC 24
Finished Sep 11 05:16:38 PM UTC 24
Peak memory 235576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293591576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1293591576
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/32.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.3060548437
Short name T371
Test name
Test status
Simulation time 3573082152 ps
CPU time 15.66 seconds
Started Sep 11 05:16:29 PM UTC 24
Finished Sep 11 05:16:46 PM UTC 24
Peak memory 262304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060548437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.3060548437
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/32.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.4239646381
Short name T718
Test name
Test status
Simulation time 1373293668 ps
CPU time 16.92 seconds
Started Sep 11 05:16:29 PM UTC 24
Finished Sep 11 05:16:48 PM UTC 24
Peak memory 261960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239646381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.4239646381
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/32.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.1505891238
Short name T707
Test name
Test status
Simulation time 258820386 ps
CPU time 4.18 seconds
Started Sep 11 05:16:34 PM UTC 24
Finished Sep 11 05:16:39 PM UTC 24
Peak memory 231592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505891238 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.1505891238
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/32.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.3634656535
Short name T849
Test name
Test status
Simulation time 34597825589 ps
CPU time 160.14 seconds
Started Sep 11 05:16:39 PM UTC 24
Finished Sep 11 05:19:22 PM UTC 24
Peak memory 262272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634656535 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.3634656535
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/32.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_all.50551874
Short name T710
Test name
Test status
Simulation time 5625553167 ps
CPU time 14.11 seconds
Started Sep 11 05:16:27 PM UTC 24
Finished Sep 11 05:16:43 PM UTC 24
Peak memory 227888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50551874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.50551874
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/32.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.360438070
Short name T703
Test name
Test status
Simulation time 4391694293 ps
CPU time 8.18 seconds
Started Sep 11 05:16:24 PM UTC 24
Finished Sep 11 05:16:33 PM UTC 24
Peak memory 228076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360438070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.360438070
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/32.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_rw.1256629190
Short name T699
Test name
Test status
Simulation time 100289068 ps
CPU time 1.88 seconds
Started Sep 11 05:16:27 PM UTC 24
Finished Sep 11 05:16:30 PM UTC 24
Peak memory 228068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256629190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1256629190
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/32.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.3782475980
Short name T698
Test name
Test status
Simulation time 13471203 ps
CPU time 1.11 seconds
Started Sep 11 05:16:27 PM UTC 24
Finished Sep 11 05:16:29 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782475980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3782475980
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/32.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_upload.3618353204
Short name T712
Test name
Test status
Simulation time 2493797356 ps
CPU time 10.66 seconds
Started Sep 11 05:16:32 PM UTC 24
Finished Sep 11 05:16:44 PM UTC 24
Peak memory 245912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618353204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3618353204
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/32.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_alert_test.2076277980
Short name T723
Test name
Test status
Simulation time 13442909 ps
CPU time 1.1 seconds
Started Sep 11 05:16:49 PM UTC 24
Finished Sep 11 05:16:51 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076277980 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.2076277980
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/33.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_cfg_cmd.3426210209
Short name T724
Test name
Test status
Simulation time 156884932 ps
CPU time 3.72 seconds
Started Sep 11 05:16:47 PM UTC 24
Finished Sep 11 05:16:52 PM UTC 24
Peak memory 235592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426210209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3426210209
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/33.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_csb_read.3686457732
Short name T711
Test name
Test status
Simulation time 60195270 ps
CPU time 1.16 seconds
Started Sep 11 05:16:41 PM UTC 24
Finished Sep 11 05:16:43 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686457732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3686457732
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/33.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_all.2945292980
Short name T767
Test name
Test status
Simulation time 14265377990 ps
CPU time 48.8 seconds
Started Sep 11 05:16:49 PM UTC 24
Finished Sep 11 05:17:39 PM UTC 24
Peak memory 245680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945292980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2945292980
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/33.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.2915242346
Short name T722
Test name
Test status
Simulation time 72215144 ps
CPU time 1.26 seconds
Started Sep 11 05:16:49 PM UTC 24
Finished Sep 11 05:16:51 PM UTC 24
Peak memory 227832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915242346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2915242346
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.1858040306
Short name T731
Test name
Test status
Simulation time 1429723053 ps
CPU time 8.73 seconds
Started Sep 11 05:16:49 PM UTC 24
Finished Sep 11 05:16:58 PM UTC 24
Peak memory 232044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858040306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.1858040306
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode.2175423618
Short name T753
Test name
Test status
Simulation time 8801213808 ps
CPU time 31.75 seconds
Started Sep 11 05:16:47 PM UTC 24
Finished Sep 11 05:17:20 PM UTC 24
Peak memory 249812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175423618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2175423618
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/33.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.2543015043
Short name T766
Test name
Test status
Simulation time 6766796255 ps
CPU time 48.04 seconds
Started Sep 11 05:16:47 PM UTC 24
Finished Sep 11 05:17:37 PM UTC 24
Peak memory 249788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543015043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.2543015043
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_intercept.1741562361
Short name T732
Test name
Test status
Simulation time 3853331750 ps
CPU time 13.36 seconds
Started Sep 11 05:16:45 PM UTC 24
Finished Sep 11 05:16:59 PM UTC 24
Peak memory 235388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741562361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1741562361
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/33.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_mailbox.1160680301
Short name T339
Test name
Test status
Simulation time 872348313 ps
CPU time 9.52 seconds
Started Sep 11 05:16:46 PM UTC 24
Finished Sep 11 05:16:57 PM UTC 24
Peak memory 245724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160680301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1160680301
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/33.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.118715335
Short name T717
Test name
Test status
Simulation time 84765754 ps
CPU time 2.47 seconds
Started Sep 11 05:16:44 PM UTC 24
Finished Sep 11 05:16:47 PM UTC 24
Peak memory 235240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118715335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.118715335
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/33.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.3122035611
Short name T719
Test name
Test status
Simulation time 281841381 ps
CPU time 2.94 seconds
Started Sep 11 05:16:44 PM UTC 24
Finished Sep 11 05:16:48 PM UTC 24
Peak memory 234720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122035611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3122035611
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/33.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.3932382123
Short name T726
Test name
Test status
Simulation time 390340982 ps
CPU time 4.66 seconds
Started Sep 11 05:16:49 PM UTC 24
Finished Sep 11 05:16:54 PM UTC 24
Peak memory 231652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932382123 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.3932382123
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/33.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.791987101
Short name T1034
Test name
Test status
Simulation time 135088557925 ps
CPU time 783.15 seconds
Started Sep 11 05:16:49 PM UTC 24
Finished Sep 11 05:30:01 PM UTC 24
Peak memory 299024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791987101 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.791987101
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/33.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_all.1144739621
Short name T728
Test name
Test status
Simulation time 859804899 ps
CPU time 12.6 seconds
Started Sep 11 05:16:42 PM UTC 24
Finished Sep 11 05:16:55 PM UTC 24
Peak memory 231908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144739621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1144739621
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/33.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.1533464384
Short name T716
Test name
Test status
Simulation time 2503406496 ps
CPU time 5.37 seconds
Started Sep 11 05:16:41 PM UTC 24
Finished Sep 11 05:16:47 PM UTC 24
Peak memory 227908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533464384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1533464384
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/33.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_rw.2537972372
Short name T720
Test name
Test status
Simulation time 186333189 ps
CPU time 3.13 seconds
Started Sep 11 05:16:44 PM UTC 24
Finished Sep 11 05:16:48 PM UTC 24
Peak memory 217500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537972372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2537972372
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/33.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.806261465
Short name T713
Test name
Test status
Simulation time 82963002 ps
CPU time 1.49 seconds
Started Sep 11 05:16:43 PM UTC 24
Finished Sep 11 05:16:45 PM UTC 24
Peak memory 215912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806261465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.806261465
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/33.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/33.spi_device_upload.2088915582
Short name T747
Test name
Test status
Simulation time 7312540170 ps
CPU time 23.92 seconds
Started Sep 11 05:16:47 PM UTC 24
Finished Sep 11 05:17:12 PM UTC 24
Peak memory 251852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088915582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2088915582
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/33.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_alert_test.3069806646
Short name T742
Test name
Test status
Simulation time 32469008 ps
CPU time 1.07 seconds
Started Sep 11 05:17:05 PM UTC 24
Finished Sep 11 05:17:07 PM UTC 24
Peak memory 215672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069806646 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.3069806646
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/34.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_cfg_cmd.3835203630
Short name T739
Test name
Test status
Simulation time 272254917 ps
CPU time 6.49 seconds
Started Sep 11 05:16:59 PM UTC 24
Finished Sep 11 05:17:06 PM UTC 24
Peak memory 235516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835203630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3835203630
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/34.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_csb_read.3390038270
Short name T725
Test name
Test status
Simulation time 114517985 ps
CPU time 1.21 seconds
Started Sep 11 05:16:50 PM UTC 24
Finished Sep 11 05:16:52 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390038270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3390038270
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/34.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_all.197789935
Short name T801
Test name
Test status
Simulation time 60738981898 ps
CPU time 78.35 seconds
Started Sep 11 05:17:02 PM UTC 24
Finished Sep 11 05:18:22 PM UTC 24
Peak memory 262084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197789935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.197789935
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/34.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.2734405761
Short name T858
Test name
Test status
Simulation time 34175029072 ps
CPU time 150.74 seconds
Started Sep 11 05:17:03 PM UTC 24
Finished Sep 11 05:19:36 PM UTC 24
Peak memory 262360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734405761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2734405761
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/34.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.3994704492
Short name T369
Test name
Test status
Simulation time 38145148387 ps
CPU time 140.79 seconds
Started Sep 11 05:17:05 PM UTC 24
Finished Sep 11 05:19:28 PM UTC 24
Peak memory 270552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994704492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.3994704492
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode.2404306458
Short name T736
Test name
Test status
Simulation time 40821408 ps
CPU time 3.55 seconds
Started Sep 11 05:17:00 PM UTC 24
Finished Sep 11 05:17:04 PM UTC 24
Peak memory 245520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404306458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2404306458
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/34.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.3125329443
Short name T770
Test name
Test status
Simulation time 1328254218 ps
CPU time 42.32 seconds
Started Sep 11 05:17:01 PM UTC 24
Finished Sep 11 05:17:45 PM UTC 24
Peak memory 249860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125329443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.3125329443
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_intercept.2288506670
Short name T735
Test name
Test status
Simulation time 465630059 ps
CPU time 5.18 seconds
Started Sep 11 05:16:56 PM UTC 24
Finished Sep 11 05:17:03 PM UTC 24
Peak memory 235272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288506670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2288506670
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/34.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_mailbox.1868852788
Short name T740
Test name
Test status
Simulation time 2195131744 ps
CPU time 9.3 seconds
Started Sep 11 05:16:56 PM UTC 24
Finished Sep 11 05:17:07 PM UTC 24
Peak memory 251864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868852788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1868852788
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/34.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.1404969632
Short name T733
Test name
Test status
Simulation time 28426750 ps
CPU time 2.8 seconds
Started Sep 11 05:16:56 PM UTC 24
Finished Sep 11 05:17:00 PM UTC 24
Peak memory 234008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404969632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.1404969632
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/34.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.1760104673
Short name T741
Test name
Test status
Simulation time 1042451698 ps
CPU time 10.57 seconds
Started Sep 11 05:16:55 PM UTC 24
Finished Sep 11 05:17:07 PM UTC 24
Peak memory 245768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760104673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1760104673
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/34.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.3626311959
Short name T750
Test name
Test status
Simulation time 2654075993 ps
CPU time 16.95 seconds
Started Sep 11 05:17:01 PM UTC 24
Finished Sep 11 05:17:19 PM UTC 24
Peak memory 232036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626311959 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.3626311959
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/34.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.4175905579
Short name T1018
Test name
Test status
Simulation time 307919324214 ps
CPU time 377.3 seconds
Started Sep 11 05:17:05 PM UTC 24
Finished Sep 11 05:23:27 PM UTC 24
Peak memory 268480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175905579 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.4175905579
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/34.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_all.4148360648
Short name T737
Test name
Test status
Simulation time 8356557983 ps
CPU time 11.4 seconds
Started Sep 11 05:16:52 PM UTC 24
Finished Sep 11 05:17:04 PM UTC 24
Peak memory 232008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148360648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.4148360648
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/34.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.2172650996
Short name T730
Test name
Test status
Simulation time 1965313861 ps
CPU time 5.31 seconds
Started Sep 11 05:16:52 PM UTC 24
Finished Sep 11 05:16:58 PM UTC 24
Peak memory 227944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172650996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2172650996
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/34.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_rw.932685605
Short name T729
Test name
Test status
Simulation time 74228688 ps
CPU time 1.46 seconds
Started Sep 11 05:16:53 PM UTC 24
Finished Sep 11 05:16:56 PM UTC 24
Peak memory 216496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932685605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.932685605
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/34.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.538124971
Short name T727
Test name
Test status
Simulation time 72896140 ps
CPU time 1.26 seconds
Started Sep 11 05:16:53 PM UTC 24
Finished Sep 11 05:16:55 PM UTC 24
Peak memory 215912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538124971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.538124971
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/34.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/34.spi_device_upload.2315736592
Short name T348
Test name
Test status
Simulation time 71447568639 ps
CPU time 27.54 seconds
Started Sep 11 05:16:57 PM UTC 24
Finished Sep 11 05:17:26 PM UTC 24
Peak memory 235452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315736592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2315736592
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/34.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_alert_test.4064950900
Short name T757
Test name
Test status
Simulation time 53875060 ps
CPU time 1.13 seconds
Started Sep 11 05:17:26 PM UTC 24
Finished Sep 11 05:17:28 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064950900 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.4064950900
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/35.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_cfg_cmd.389424860
Short name T754
Test name
Test status
Simulation time 64533651 ps
CPU time 3.7 seconds
Started Sep 11 05:17:16 PM UTC 24
Finished Sep 11 05:17:21 PM UTC 24
Peak memory 245568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389424860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.389424860
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/35.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_csb_read.2028361559
Short name T744
Test name
Test status
Simulation time 65387471 ps
CPU time 1.14 seconds
Started Sep 11 05:17:07 PM UTC 24
Finished Sep 11 05:17:09 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028361559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2028361559
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/35.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.3481867093
Short name T361
Test name
Test status
Simulation time 2447817298 ps
CPU time 23.85 seconds
Started Sep 11 05:17:20 PM UTC 24
Finished Sep 11 05:17:45 PM UTC 24
Peak memory 251872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481867093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3481867093
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/35.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.1214527854
Short name T792
Test name
Test status
Simulation time 5354951956 ps
CPU time 48.38 seconds
Started Sep 11 05:17:21 PM UTC 24
Finished Sep 11 05:18:11 PM UTC 24
Peak memory 262164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214527854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1214527854
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.4282522334
Short name T836
Test name
Test status
Simulation time 10798643135 ps
CPU time 103.78 seconds
Started Sep 11 05:17:21 PM UTC 24
Finished Sep 11 05:19:07 PM UTC 24
Peak memory 235460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282522334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.4282522334
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode.367068509
Short name T813
Test name
Test status
Simulation time 5787891149 ps
CPU time 76.5 seconds
Started Sep 11 05:17:16 PM UTC 24
Finished Sep 11 05:18:34 PM UTC 24
Peak memory 245792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367068509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.367068509
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/35.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.2534999078
Short name T895
Test name
Test status
Simulation time 24591602618 ps
CPU time 184.42 seconds
Started Sep 11 05:17:19 PM UTC 24
Finished Sep 11 05:20:26 PM UTC 24
Peak memory 266372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534999078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.2534999078
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_intercept.852794347
Short name T752
Test name
Test status
Simulation time 420130236 ps
CPU time 7.54 seconds
Started Sep 11 05:17:12 PM UTC 24
Finished Sep 11 05:17:20 PM UTC 24
Peak memory 235272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852794347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.852794347
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/35.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_mailbox.3903903789
Short name T776
Test name
Test status
Simulation time 14105534199 ps
CPU time 37.39 seconds
Started Sep 11 05:17:13 PM UTC 24
Finished Sep 11 05:17:52 PM UTC 24
Peak memory 245660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903903789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3903903789
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/35.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.2307290599
Short name T749
Test name
Test status
Simulation time 623516107 ps
CPU time 3.98 seconds
Started Sep 11 05:17:11 PM UTC 24
Finished Sep 11 05:17:16 PM UTC 24
Peak memory 245764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307290599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.2307290599
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/35.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.2397412405
Short name T759
Test name
Test status
Simulation time 17870309219 ps
CPU time 17.27 seconds
Started Sep 11 05:17:11 PM UTC 24
Finished Sep 11 05:17:29 PM UTC 24
Peak memory 235464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397412405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2397412405
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/35.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.3586009457
Short name T763
Test name
Test status
Simulation time 868976140 ps
CPU time 11.86 seconds
Started Sep 11 05:17:20 PM UTC 24
Finished Sep 11 05:17:33 PM UTC 24
Peak memory 233640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586009457 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.3586009457
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/35.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.2502158217
Short name T354
Test name
Test status
Simulation time 34398077078 ps
CPU time 264.66 seconds
Started Sep 11 05:17:21 PM UTC 24
Finished Sep 11 05:21:50 PM UTC 24
Peak memory 301056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502158217 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.2502158217
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/35.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_all.55590106
Short name T745
Test name
Test status
Simulation time 26649645 ps
CPU time 1.14 seconds
Started Sep 11 05:17:07 PM UTC 24
Finished Sep 11 05:17:10 PM UTC 24
Peak memory 215676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55590106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.55590106
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/35.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.1256765128
Short name T748
Test name
Test status
Simulation time 524738768 ps
CPU time 5.85 seconds
Started Sep 11 05:17:07 PM UTC 24
Finished Sep 11 05:17:14 PM UTC 24
Peak memory 227748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256765128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1256765128
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/35.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_rw.2512650814
Short name T755
Test name
Test status
Simulation time 1215373720 ps
CPU time 14.29 seconds
Started Sep 11 05:17:10 PM UTC 24
Finished Sep 11 05:17:25 PM UTC 24
Peak memory 227752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512650814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2512650814
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/35.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.2802563319
Short name T746
Test name
Test status
Simulation time 38660515 ps
CPU time 1.25 seconds
Started Sep 11 05:17:08 PM UTC 24
Finished Sep 11 05:17:11 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802563319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2802563319
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/35.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/35.spi_device_upload.2637031253
Short name T751
Test name
Test status
Simulation time 172315491 ps
CPU time 3.03 seconds
Started Sep 11 05:17:15 PM UTC 24
Finished Sep 11 05:17:19 PM UTC 24
Peak memory 245212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637031253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2637031253
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/35.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_alert_test.3886608319
Short name T773
Test name
Test status
Simulation time 24219093 ps
CPU time 1.08 seconds
Started Sep 11 05:17:46 PM UTC 24
Finished Sep 11 05:17:48 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886608319 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.3886608319
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/36.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_cfg_cmd.4247597537
Short name T785
Test name
Test status
Simulation time 12724245754 ps
CPU time 20.01 seconds
Started Sep 11 05:17:37 PM UTC 24
Finished Sep 11 05:17:59 PM UTC 24
Peak memory 235456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247597537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.4247597537
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/36.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_csb_read.2929022993
Short name T758
Test name
Test status
Simulation time 43611937 ps
CPU time 1.15 seconds
Started Sep 11 05:17:26 PM UTC 24
Finished Sep 11 05:17:28 PM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929022993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2929022993
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/36.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_all.331466138
Short name T925
Test name
Test status
Simulation time 22362234005 ps
CPU time 204.19 seconds
Started Sep 11 05:17:40 PM UTC 24
Finished Sep 11 05:21:07 PM UTC 24
Peak memory 262084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331466138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.331466138
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/36.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.2355955021
Short name T794
Test name
Test status
Simulation time 18373679707 ps
CPU time 31.11 seconds
Started Sep 11 05:17:40 PM UTC 24
Finished Sep 11 05:18:12 PM UTC 24
Peak memory 262164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355955021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2355955021
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/36.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.2519290534
Short name T226
Test name
Test status
Simulation time 12457579460 ps
CPU time 190.64 seconds
Started Sep 11 05:17:41 PM UTC 24
Finished Sep 11 05:20:55 PM UTC 24
Peak memory 280784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519290534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.2519290534
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode.2413942351
Short name T781
Test name
Test status
Simulation time 1255319092 ps
CPU time 18.68 seconds
Started Sep 11 05:17:37 PM UTC 24
Finished Sep 11 05:17:58 PM UTC 24
Peak memory 262180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413942351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2413942351
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/36.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.1208665490
Short name T374
Test name
Test status
Simulation time 49968020718 ps
CPU time 199.69 seconds
Started Sep 11 05:17:37 PM UTC 24
Finished Sep 11 05:21:01 PM UTC 24
Peak memory 262112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208665490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.1208665490
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_intercept.3216214441
Short name T768
Test name
Test status
Simulation time 372755575 ps
CPU time 6.02 seconds
Started Sep 11 05:17:32 PM UTC 24
Finished Sep 11 05:17:39 PM UTC 24
Peak memory 245600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216214441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3216214441
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/36.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_mailbox.3980292440
Short name T795
Test name
Test status
Simulation time 3434929528 ps
CPU time 39.29 seconds
Started Sep 11 05:17:32 PM UTC 24
Finished Sep 11 05:18:13 PM UTC 24
Peak memory 245580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980292440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3980292440
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/36.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.2458924599
Short name T765
Test name
Test status
Simulation time 48034375 ps
CPU time 3.67 seconds
Started Sep 11 05:17:32 PM UTC 24
Finished Sep 11 05:17:37 PM UTC 24
Peak memory 245364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458924599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.2458924599
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/36.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.2240599777
Short name T786
Test name
Test status
Simulation time 5093101132 ps
CPU time 31.82 seconds
Started Sep 11 05:17:30 PM UTC 24
Finished Sep 11 05:18:03 PM UTC 24
Peak memory 251848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240599777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2240599777
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/36.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.1397070669
Short name T772
Test name
Test status
Simulation time 161042568 ps
CPU time 5.62 seconds
Started Sep 11 05:17:40 PM UTC 24
Finished Sep 11 05:17:46 PM UTC 24
Peak memory 231592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397070669 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.1397070669
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/36.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.4232642257
Short name T1028
Test name
Test status
Simulation time 113627948448 ps
CPU time 498.6 seconds
Started Sep 11 05:17:41 PM UTC 24
Finished Sep 11 05:26:07 PM UTC 24
Peak memory 284652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232642257 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.4232642257
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/36.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_all.2167175421
Short name T764
Test name
Test status
Simulation time 492272544 ps
CPU time 6.71 seconds
Started Sep 11 05:17:29 PM UTC 24
Finished Sep 11 05:17:37 PM UTC 24
Peak memory 227972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167175421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2167175421
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/36.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.1695166423
Short name T760
Test name
Test status
Simulation time 651778683 ps
CPU time 3.14 seconds
Started Sep 11 05:17:27 PM UTC 24
Finished Sep 11 05:17:31 PM UTC 24
Peak memory 217224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695166423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1695166423
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/36.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_rw.3803296821
Short name T761
Test name
Test status
Simulation time 11551299 ps
CPU time 1.09 seconds
Started Sep 11 05:17:29 PM UTC 24
Finished Sep 11 05:17:31 PM UTC 24
Peak memory 215788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803296821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3803296821
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/36.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.771336591
Short name T762
Test name
Test status
Simulation time 26533428 ps
CPU time 1.16 seconds
Started Sep 11 05:17:29 PM UTC 24
Finished Sep 11 05:17:31 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771336591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.771336591
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/36.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/36.spi_device_upload.767967255
Short name T771
Test name
Test status
Simulation time 5559512380 ps
CPU time 10.47 seconds
Started Sep 11 05:17:34 PM UTC 24
Finished Sep 11 05:17:46 PM UTC 24
Peak memory 235424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767967255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.767967255
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/36.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_alert_test.4128642887
Short name T791
Test name
Test status
Simulation time 21582550 ps
CPU time 1.05 seconds
Started Sep 11 05:18:08 PM UTC 24
Finished Sep 11 05:18:10 PM UTC 24
Peak memory 215672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128642887 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.4128642887
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/37.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_cfg_cmd.2894666509
Short name T312
Test name
Test status
Simulation time 1906067948 ps
CPU time 27.3 seconds
Started Sep 11 05:17:58 PM UTC 24
Finished Sep 11 05:18:26 PM UTC 24
Peak memory 245528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894666509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2894666509
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/37.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_csb_read.4292212233
Short name T774
Test name
Test status
Simulation time 59274566 ps
CPU time 1.17 seconds
Started Sep 11 05:17:46 PM UTC 24
Finished Sep 11 05:17:49 PM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292212233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.4292212233
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/37.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.1655435471
Short name T805
Test name
Test status
Simulation time 3439709981 ps
CPU time 26.13 seconds
Started Sep 11 05:18:00 PM UTC 24
Finished Sep 11 05:18:28 PM UTC 24
Peak memory 251776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655435471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1655435471
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/37.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.1705959409
Short name T360
Test name
Test status
Simulation time 17802878670 ps
CPU time 196.96 seconds
Started Sep 11 05:18:00 PM UTC 24
Finished Sep 11 05:21:20 PM UTC 24
Peak memory 280564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705959409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1705959409
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/37.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.3131349921
Short name T376
Test name
Test status
Simulation time 11872256770 ps
CPU time 106.75 seconds
Started Sep 11 05:18:04 PM UTC 24
Finished Sep 11 05:19:53 PM UTC 24
Peak memory 247872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131349921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.3131349921
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode.816056542
Short name T382
Test name
Test status
Simulation time 1285783490 ps
CPU time 17.13 seconds
Started Sep 11 05:17:59 PM UTC 24
Finished Sep 11 05:18:17 PM UTC 24
Peak memory 245568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816056542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.816056542
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/37.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.3123005557
Short name T1006
Test name
Test status
Simulation time 38796301558 ps
CPU time 263.12 seconds
Started Sep 11 05:17:59 PM UTC 24
Finished Sep 11 05:22:26 PM UTC 24
Peak memory 266368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123005557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.3123005557
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_intercept.450717403
Short name T783
Test name
Test status
Simulation time 317145174 ps
CPU time 4.36 seconds
Started Sep 11 05:17:52 PM UTC 24
Finished Sep 11 05:17:58 PM UTC 24
Peak memory 230064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450717403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.450717403
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/37.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_mailbox.2072780670
Short name T784
Test name
Test status
Simulation time 1132950377 ps
CPU time 5.18 seconds
Started Sep 11 05:17:52 PM UTC 24
Finished Sep 11 05:17:59 PM UTC 24
Peak memory 245728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072780670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2072780670
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/37.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.2032755466
Short name T787
Test name
Test status
Simulation time 1409590833 ps
CPU time 10.75 seconds
Started Sep 11 05:17:52 PM UTC 24
Finished Sep 11 05:18:04 PM UTC 24
Peak memory 251716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032755466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.2032755466
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/37.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.673576719
Short name T789
Test name
Test status
Simulation time 1987200810 ps
CPU time 14.79 seconds
Started Sep 11 05:17:52 PM UTC 24
Finished Sep 11 05:18:08 PM UTC 24
Peak memory 262244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673576719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.673576719
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/37.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.681468396
Short name T788
Test name
Test status
Simulation time 613615972 ps
CPU time 6.75 seconds
Started Sep 11 05:17:59 PM UTC 24
Finished Sep 11 05:18:07 PM UTC 24
Peak memory 231912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681468396 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.681468396
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/37.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.672583720
Short name T212
Test name
Test status
Simulation time 10236719100 ps
CPU time 236.41 seconds
Started Sep 11 05:18:05 PM UTC 24
Finished Sep 11 05:22:05 PM UTC 24
Peak memory 295120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672583720 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.672583720
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/37.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_all.3364500785
Short name T780
Test name
Test status
Simulation time 6568073964 ps
CPU time 9 seconds
Started Sep 11 05:17:47 PM UTC 24
Finished Sep 11 05:17:57 PM UTC 24
Peak memory 227912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364500785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3364500785
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/37.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.2201601887
Short name T778
Test name
Test status
Simulation time 233742021 ps
CPU time 3.73 seconds
Started Sep 11 05:17:47 PM UTC 24
Finished Sep 11 05:17:52 PM UTC 24
Peak memory 227756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201601887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2201601887
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/37.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_rw.4000304664
Short name T777
Test name
Test status
Simulation time 41214923 ps
CPU time 1.7 seconds
Started Sep 11 05:17:49 PM UTC 24
Finished Sep 11 05:17:52 PM UTC 24
Peak memory 216496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000304664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.4000304664
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/37.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.2244208424
Short name T775
Test name
Test status
Simulation time 31820031 ps
CPU time 1.23 seconds
Started Sep 11 05:17:49 PM UTC 24
Finished Sep 11 05:17:51 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244208424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2244208424
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/37.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/37.spi_device_upload.2063186231
Short name T799
Test name
Test status
Simulation time 3253451241 ps
CPU time 23.07 seconds
Started Sep 11 05:17:54 PM UTC 24
Finished Sep 11 05:18:18 PM UTC 24
Peak memory 252032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063186231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2063186231
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/37.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_alert_test.223473166
Short name T807
Test name
Test status
Simulation time 45853874 ps
CPU time 1.11 seconds
Started Sep 11 05:18:28 PM UTC 24
Finished Sep 11 05:18:30 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223473166 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.223473166
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/38.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_cfg_cmd.2731570481
Short name T112
Test name
Test status
Simulation time 222324523 ps
CPU time 5.47 seconds
Started Sep 11 05:18:18 PM UTC 24
Finished Sep 11 05:18:25 PM UTC 24
Peak memory 245448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731570481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2731570481
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/38.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_csb_read.2207739739
Short name T793
Test name
Test status
Simulation time 30395344 ps
CPU time 1.15 seconds
Started Sep 11 05:18:09 PM UTC 24
Finished Sep 11 05:18:11 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207739739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2207739739
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/38.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_all.750506138
Short name T913
Test name
Test status
Simulation time 12196913857 ps
CPU time 151.4 seconds
Started Sep 11 05:18:23 PM UTC 24
Finished Sep 11 05:20:58 PM UTC 24
Peak memory 266180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750506138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.750506138
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/38.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.3628354968
Short name T818
Test name
Test status
Simulation time 6045717390 ps
CPU time 18.08 seconds
Started Sep 11 05:18:23 PM UTC 24
Finished Sep 11 05:18:43 PM UTC 24
Peak memory 230248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628354968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3628354968
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/38.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.3983331827
Short name T1013
Test name
Test status
Simulation time 22340854979 ps
CPU time 273.35 seconds
Started Sep 11 05:18:27 PM UTC 24
Finished Sep 11 05:23:05 PM UTC 24
Peak memory 284892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983331827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.3983331827
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode.4076478620
Short name T850
Test name
Test status
Simulation time 7402157018 ps
CPU time 62.67 seconds
Started Sep 11 05:18:18 PM UTC 24
Finished Sep 11 05:19:22 PM UTC 24
Peak memory 261996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076478620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.4076478620
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/38.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.3453840132
Short name T365
Test name
Test status
Simulation time 8406999220 ps
CPU time 30.69 seconds
Started Sep 11 05:18:19 PM UTC 24
Finished Sep 11 05:18:51 PM UTC 24
Peak memory 262272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453840132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.3453840132
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_intercept.2070768843
Short name T804
Test name
Test status
Simulation time 4595540687 ps
CPU time 10.5 seconds
Started Sep 11 05:18:16 PM UTC 24
Finished Sep 11 05:18:28 PM UTC 24
Peak memory 245668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070768843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2070768843
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/38.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_mailbox.2727953080
Short name T881
Test name
Test status
Simulation time 24413543317 ps
CPU time 110.1 seconds
Started Sep 11 05:18:16 PM UTC 24
Finished Sep 11 05:20:08 PM UTC 24
Peak memory 261852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727953080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2727953080
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/38.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.1555017604
Short name T816
Test name
Test status
Simulation time 3760332904 ps
CPU time 22.79 seconds
Started Sep 11 05:18:14 PM UTC 24
Finished Sep 11 05:18:38 PM UTC 24
Peak memory 249824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555017604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.1555017604
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/38.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.3657076097
Short name T798
Test name
Test status
Simulation time 675841228 ps
CPU time 2.91 seconds
Started Sep 11 05:18:13 PM UTC 24
Finished Sep 11 05:18:17 PM UTC 24
Peak memory 235316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657076097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3657076097
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/38.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.1986940511
Short name T809
Test name
Test status
Simulation time 1513208976 ps
CPU time 9.54 seconds
Started Sep 11 05:18:21 PM UTC 24
Finished Sep 11 05:18:32 PM UTC 24
Peak memory 231592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986940511 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.1986940511
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/38.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.3053018527
Short name T982
Test name
Test status
Simulation time 72195380491 ps
CPU time 208.11 seconds
Started Sep 11 05:18:27 PM UTC 24
Finished Sep 11 05:21:59 PM UTC 24
Peak memory 262428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053018527 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.3053018527
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/38.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_all.1121057433
Short name T802
Test name
Test status
Simulation time 1186956505 ps
CPU time 9.8 seconds
Started Sep 11 05:18:11 PM UTC 24
Finished Sep 11 05:18:22 PM UTC 24
Peak memory 227856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121057433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1121057433
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/38.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.3317371050
Short name T803
Test name
Test status
Simulation time 18476990090 ps
CPU time 11.93 seconds
Started Sep 11 05:18:10 PM UTC 24
Finished Sep 11 05:18:23 PM UTC 24
Peak memory 229936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317371050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3317371050
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/38.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_rw.3472199773
Short name T797
Test name
Test status
Simulation time 83142698 ps
CPU time 1.14 seconds
Started Sep 11 05:18:13 PM UTC 24
Finished Sep 11 05:18:15 PM UTC 24
Peak memory 215972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472199773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3472199773
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/38.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.3532220059
Short name T796
Test name
Test status
Simulation time 40180431 ps
CPU time 1.09 seconds
Started Sep 11 05:18:13 PM UTC 24
Finished Sep 11 05:18:15 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532220059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3532220059
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/38.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/38.spi_device_upload.1000351198
Short name T806
Test name
Test status
Simulation time 427228823 ps
CPU time 12.85 seconds
Started Sep 11 05:18:16 PM UTC 24
Finished Sep 11 05:18:30 PM UTC 24
Peak memory 235292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000351198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1000351198
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/38.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_alert_test.1655709968
Short name T823
Test name
Test status
Simulation time 14121201 ps
CPU time 1 seconds
Started Sep 11 05:18:46 PM UTC 24
Finished Sep 11 05:18:48 PM UTC 24
Peak memory 215732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655709968 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.1655709968
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/39.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_cfg_cmd.2378659038
Short name T817
Test name
Test status
Simulation time 891928088 ps
CPU time 3.71 seconds
Started Sep 11 05:18:35 PM UTC 24
Finished Sep 11 05:18:40 PM UTC 24
Peak memory 235324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378659038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2378659038
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/39.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_csb_read.1143414799
Short name T808
Test name
Test status
Simulation time 31941798 ps
CPU time 1.19 seconds
Started Sep 11 05:18:28 PM UTC 24
Finished Sep 11 05:18:31 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143414799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1143414799
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/39.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.1120433940
Short name T870
Test name
Test status
Simulation time 19566827969 ps
CPU time 74.23 seconds
Started Sep 11 05:18:39 PM UTC 24
Finished Sep 11 05:19:55 PM UTC 24
Peak memory 268228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120433940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1120433940
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/39.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.1543771780
Short name T988
Test name
Test status
Simulation time 39183942390 ps
CPU time 200.69 seconds
Started Sep 11 05:18:41 PM UTC 24
Finished Sep 11 05:22:05 PM UTC 24
Peak memory 268280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543771780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1543771780
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/39.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.3565676390
Short name T837
Test name
Test status
Simulation time 3711200724 ps
CPU time 23.51 seconds
Started Sep 11 05:18:44 PM UTC 24
Finished Sep 11 05:19:08 PM UTC 24
Peak memory 249848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565676390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.3565676390
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.1944157863
Short name T819
Test name
Test status
Simulation time 990094578 ps
CPU time 6.25 seconds
Started Sep 11 05:18:37 PM UTC 24
Finished Sep 11 05:18:45 PM UTC 24
Peak memory 245608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944157863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1944157863
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/39.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.1440344868
Short name T366
Test name
Test status
Simulation time 10045162978 ps
CPU time 121.31 seconds
Started Sep 11 05:18:39 PM UTC 24
Finished Sep 11 05:20:43 PM UTC 24
Peak memory 278752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440344868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.1440344868
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_intercept.1919911908
Short name T820
Test name
Test status
Simulation time 754227346 ps
CPU time 10.88 seconds
Started Sep 11 05:18:33 PM UTC 24
Finished Sep 11 05:18:45 PM UTC 24
Peak memory 245560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919911908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1919911908
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/39.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_mailbox.4234950404
Short name T832
Test name
Test status
Simulation time 1006107980 ps
CPU time 21.28 seconds
Started Sep 11 05:18:35 PM UTC 24
Finished Sep 11 05:18:58 PM UTC 24
Peak memory 245760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234950404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4234950404
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/39.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.3580613727
Short name T825
Test name
Test status
Simulation time 13895248728 ps
CPU time 14.97 seconds
Started Sep 11 05:18:33 PM UTC 24
Finished Sep 11 05:18:49 PM UTC 24
Peak memory 244496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580613727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.3580613727
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/39.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.3575984201
Short name T815
Test name
Test status
Simulation time 77329599 ps
CPU time 2.91 seconds
Started Sep 11 05:18:33 PM UTC 24
Finished Sep 11 05:18:37 PM UTC 24
Peak memory 244580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575984201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3575984201
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/39.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.3016924963
Short name T821
Test name
Test status
Simulation time 332058754 ps
CPU time 5.05 seconds
Started Sep 11 05:18:39 PM UTC 24
Finished Sep 11 05:18:45 PM UTC 24
Peak memory 234076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016924963 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.3016924963
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/39.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.541016359
Short name T824
Test name
Test status
Simulation time 460090357 ps
CPU time 1.43 seconds
Started Sep 11 05:18:46 PM UTC 24
Finished Sep 11 05:18:48 PM UTC 24
Peak memory 215616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541016359 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.541016359
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/39.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.1722566027
Short name T829
Test name
Test status
Simulation time 18071253425 ps
CPU time 20.88 seconds
Started Sep 11 05:18:31 PM UTC 24
Finished Sep 11 05:18:53 PM UTC 24
Peak memory 228164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722566027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1722566027
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/39.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.1092434370
Short name T810
Test name
Test status
Simulation time 243295602 ps
CPU time 2.63 seconds
Started Sep 11 05:18:28 PM UTC 24
Finished Sep 11 05:18:32 PM UTC 24
Peak memory 217212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092434370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1092434370
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/39.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_rw.1207718832
Short name T814
Test name
Test status
Simulation time 99201025 ps
CPU time 2.37 seconds
Started Sep 11 05:18:33 PM UTC 24
Finished Sep 11 05:18:36 PM UTC 24
Peak memory 227812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207718832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1207718832
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/39.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.2885078758
Short name T811
Test name
Test status
Simulation time 108106289 ps
CPU time 1.06 seconds
Started Sep 11 05:18:31 PM UTC 24
Finished Sep 11 05:18:33 PM UTC 24
Peak memory 215736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885078758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2885078758
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/39.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/39.spi_device_upload.1865072233
Short name T831
Test name
Test status
Simulation time 667222414 ps
CPU time 20.46 seconds
Started Sep 11 05:18:35 PM UTC 24
Finished Sep 11 05:18:57 PM UTC 24
Peak memory 244588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865072233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1865072233
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/39.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.3947503889
Short name T413
Test name
Test status
Simulation time 21489565 ps
CPU time 1.12 seconds
Started Sep 11 05:07:13 PM UTC 24
Finished Sep 11 05:07:15 PM UTC 24
Peak memory 215732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947503889 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3947503889
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.1734328735
Short name T207
Test name
Test status
Simulation time 1417678934 ps
CPU time 21.92 seconds
Started Sep 11 05:06:58 PM UTC 24
Finished Sep 11 05:07:21 PM UTC 24
Peak memory 235268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734328735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1734328735
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.1256549880
Short name T409
Test name
Test status
Simulation time 18140651 ps
CPU time 1.22 seconds
Started Sep 11 05:06:51 PM UTC 24
Finished Sep 11 05:06:53 PM UTC 24
Peak memory 215732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256549880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1256549880
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.1890436474
Short name T49
Test name
Test status
Simulation time 80771612291 ps
CPU time 194.27 seconds
Started Sep 11 05:07:03 PM UTC 24
Finished Sep 11 05:10:20 PM UTC 24
Peak memory 262076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890436474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1890436474
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.3749543698
Short name T594
Test name
Test status
Simulation time 35976365298 ps
CPU time 407.14 seconds
Started Sep 11 05:07:06 PM UTC 24
Finished Sep 11 05:13:59 PM UTC 24
Peak memory 264192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749543698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3749543698
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.1880004523
Short name T188
Test name
Test status
Simulation time 13368063412 ps
CPU time 89.76 seconds
Started Sep 11 05:07:06 PM UTC 24
Finished Sep 11 05:08:38 PM UTC 24
Peak memory 262340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880004523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.1880004523
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.2472972213
Short name T164
Test name
Test status
Simulation time 5435572015 ps
CPU time 82.26 seconds
Started Sep 11 05:06:59 PM UTC 24
Finished Sep 11 05:08:23 PM UTC 24
Peak memory 247744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472972213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2472972213
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.2622537944
Short name T106
Test name
Test status
Simulation time 4478118871 ps
CPU time 33.81 seconds
Started Sep 11 05:07:00 PM UTC 24
Finished Sep 11 05:07:35 PM UTC 24
Peak memory 249796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622537944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.2622537944
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.2097453046
Short name T114
Test name
Test status
Simulation time 1236087697 ps
CPU time 11.4 seconds
Started Sep 11 05:06:56 PM UTC 24
Finished Sep 11 05:07:09 PM UTC 24
Peak memory 235468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097453046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2097453046
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.3863781947
Short name T125
Test name
Test status
Simulation time 2788377357 ps
CPU time 19.1 seconds
Started Sep 11 05:06:58 PM UTC 24
Finished Sep 11 05:07:18 PM UTC 24
Peak memory 251868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863781947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3863781947
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.1905136199
Short name T410
Test name
Test status
Simulation time 35304152 ps
CPU time 1.68 seconds
Started Sep 11 05:06:51 PM UTC 24
Finished Sep 11 05:06:54 PM UTC 24
Peak memory 229192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905136199 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_parity.1905136199
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.3948661472
Short name T63
Test name
Test status
Simulation time 12738109282 ps
CPU time 20.64 seconds
Started Sep 11 05:06:55 PM UTC 24
Finished Sep 11 05:07:17 PM UTC 24
Peak memory 251820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948661472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.3948661472
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.121685260
Short name T306
Test name
Test status
Simulation time 28473353071 ps
CPU time 25.25 seconds
Started Sep 11 05:06:55 PM UTC 24
Finished Sep 11 05:07:22 PM UTC 24
Peak memory 235624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121685260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.121685260
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.2894000807
Short name T159
Test name
Test status
Simulation time 353531184 ps
CPU time 10.69 seconds
Started Sep 11 05:07:01 PM UTC 24
Finished Sep 11 05:07:13 PM UTC 24
Peak memory 233880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894000807 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.2894000807
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.971064754
Short name T36
Test name
Test status
Simulation time 315068278 ps
CPU time 1.81 seconds
Started Sep 11 05:07:11 PM UTC 24
Finished Sep 11 05:07:14 PM UTC 24
Peak memory 257728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971064754 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.971064754
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.2472758647
Short name T73
Test name
Test status
Simulation time 13167111249 ps
CPU time 22.07 seconds
Started Sep 11 05:06:53 PM UTC 24
Finished Sep 11 05:07:16 PM UTC 24
Peak memory 227884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472758647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2472758647
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2214014597
Short name T411
Test name
Test status
Simulation time 776064220 ps
CPU time 4.64 seconds
Started Sep 11 05:06:52 PM UTC 24
Finished Sep 11 05:06:58 PM UTC 24
Peak memory 227688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214014597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2214014597
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.3142964023
Short name T70
Test name
Test status
Simulation time 48649422 ps
CPU time 1.75 seconds
Started Sep 11 05:06:54 PM UTC 24
Finished Sep 11 05:06:57 PM UTC 24
Peak memory 216588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142964023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3142964023
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.1222047443
Short name T105
Test name
Test status
Simulation time 209901866 ps
CPU time 1.4 seconds
Started Sep 11 05:06:54 PM UTC 24
Finished Sep 11 05:06:57 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222047443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1222047443
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.1401283328
Short name T216
Test name
Test status
Simulation time 1300244768 ps
CPU time 7.03 seconds
Started Sep 11 05:06:58 PM UTC 24
Finished Sep 11 05:07:06 PM UTC 24
Peak memory 249552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401283328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1401283328
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/4.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.3537032565
Short name T840
Test name
Test status
Simulation time 23485041 ps
CPU time 1.09 seconds
Started Sep 11 05:19:09 PM UTC 24
Finished Sep 11 05:19:11 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537032565 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.3537032565
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/40.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_cfg_cmd.2253946668
Short name T842
Test name
Test status
Simulation time 6411561220 ps
CPU time 17.23 seconds
Started Sep 11 05:18:54 PM UTC 24
Finished Sep 11 05:19:13 PM UTC 24
Peak memory 245856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253946668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2253946668
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/40.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_csb_read.816321250
Short name T826
Test name
Test status
Simulation time 80634388 ps
CPU time 1.06 seconds
Started Sep 11 05:18:48 PM UTC 24
Finished Sep 11 05:18:50 PM UTC 24
Peak memory 215664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816321250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.816321250
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/40.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.1021611837
Short name T937
Test name
Test status
Simulation time 31508243979 ps
CPU time 130.51 seconds
Started Sep 11 05:19:05 PM UTC 24
Finished Sep 11 05:21:18 PM UTC 24
Peak memory 268420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021611837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1021611837
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/40.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.1226008555
Short name T356
Test name
Test status
Simulation time 31212832069 ps
CPU time 157.45 seconds
Started Sep 11 05:19:05 PM UTC 24
Finished Sep 11 05:21:45 PM UTC 24
Peak memory 266264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226008555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1226008555
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.2899558576
Short name T902
Test name
Test status
Simulation time 21153399186 ps
CPU time 93.12 seconds
Started Sep 11 05:19:05 PM UTC 24
Finished Sep 11 05:20:40 PM UTC 24
Peak memory 268308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899558576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.2899558576
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.1882259368
Short name T833
Test name
Test status
Simulation time 184609307 ps
CPU time 5.02 seconds
Started Sep 11 05:18:57 PM UTC 24
Finished Sep 11 05:19:03 PM UTC 24
Peak memory 235316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882259368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1882259368
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/40.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.1277482505
Short name T855
Test name
Test status
Simulation time 4301631666 ps
CPU time 33.72 seconds
Started Sep 11 05:18:59 PM UTC 24
Finished Sep 11 05:19:34 PM UTC 24
Peak memory 235456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277482505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.1277482505
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_intercept.3420945326
Short name T835
Test name
Test status
Simulation time 1667592668 ps
CPU time 9.02 seconds
Started Sep 11 05:18:54 PM UTC 24
Finished Sep 11 05:19:04 PM UTC 24
Peak memory 235548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420945326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3420945326
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/40.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.2882165057
Short name T932
Test name
Test status
Simulation time 215034457690 ps
CPU time 136.7 seconds
Started Sep 11 05:18:54 PM UTC 24
Finished Sep 11 05:21:13 PM UTC 24
Peak memory 245724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882165057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2882165057
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/40.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.638543463
Short name T838
Test name
Test status
Simulation time 7453217181 ps
CPU time 15.74 seconds
Started Sep 11 05:18:52 PM UTC 24
Finished Sep 11 05:19:09 PM UTC 24
Peak memory 245664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638543463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.638543463
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/40.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.4004568289
Short name T839
Test name
Test status
Simulation time 8154902664 ps
CPU time 16.86 seconds
Started Sep 11 05:18:52 PM UTC 24
Finished Sep 11 05:19:10 PM UTC 24
Peak memory 235228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004568289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4004568289
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/40.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.107458253
Short name T841
Test name
Test status
Simulation time 3014421015 ps
CPU time 12.3 seconds
Started Sep 11 05:18:59 PM UTC 24
Finished Sep 11 05:19:12 PM UTC 24
Peak memory 234184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107458253 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.107458253
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/40.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.1586572444
Short name T1022
Test name
Test status
Simulation time 28447221381 ps
CPU time 316.04 seconds
Started Sep 11 05:19:09 PM UTC 24
Finished Sep 11 05:24:30 PM UTC 24
Peak memory 266496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586572444 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.1586572444
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/40.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.4252471895
Short name T851
Test name
Test status
Simulation time 41813463425 ps
CPU time 33.82 seconds
Started Sep 11 05:18:50 PM UTC 24
Finished Sep 11 05:19:25 PM UTC 24
Peak memory 228052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252471895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.4252471895
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/40.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.2553758133
Short name T834
Test name
Test status
Simulation time 14328791568 ps
CPU time 15.24 seconds
Started Sep 11 05:18:48 PM UTC 24
Finished Sep 11 05:19:04 PM UTC 24
Peak memory 227828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553758133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2553758133
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/40.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_rw.2835519677
Short name T828
Test name
Test status
Simulation time 21378192 ps
CPU time 1.32 seconds
Started Sep 11 05:18:50 PM UTC 24
Finished Sep 11 05:18:52 PM UTC 24
Peak memory 215972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835519677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2835519677
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/40.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.3523570041
Short name T827
Test name
Test status
Simulation time 375352407 ps
CPU time 1.24 seconds
Started Sep 11 05:18:50 PM UTC 24
Finished Sep 11 05:18:52 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523570041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3523570041
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/40.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.2814889356
Short name T844
Test name
Test status
Simulation time 2897176109 ps
CPU time 18.04 seconds
Started Sep 11 05:18:54 PM UTC 24
Finished Sep 11 05:19:14 PM UTC 24
Peak memory 245632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814889356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2814889356
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/40.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.4154404417
Short name T856
Test name
Test status
Simulation time 25221341 ps
CPU time 1.13 seconds
Started Sep 11 05:19:33 PM UTC 24
Finished Sep 11 05:19:35 PM UTC 24
Peak memory 215732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154404417 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.4154404417
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/41.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.851118787
Short name T862
Test name
Test status
Simulation time 3134595096 ps
CPU time 14.91 seconds
Started Sep 11 05:19:23 PM UTC 24
Finished Sep 11 05:19:39 PM UTC 24
Peak memory 245384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851118787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.851118787
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/41.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.1377458905
Short name T843
Test name
Test status
Simulation time 33794022 ps
CPU time 1.14 seconds
Started Sep 11 05:19:11 PM UTC 24
Finished Sep 11 05:19:13 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377458905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1377458905
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/41.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.2318182928
Short name T1031
Test name
Test status
Simulation time 95826655576 ps
CPU time 491.18 seconds
Started Sep 11 05:19:27 PM UTC 24
Finished Sep 11 05:27:45 PM UTC 24
Peak memory 262272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318182928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2318182928
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/41.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.2662047593
Short name T1023
Test name
Test status
Simulation time 358029378560 ps
CPU time 327.72 seconds
Started Sep 11 05:19:29 PM UTC 24
Finished Sep 11 05:25:02 PM UTC 24
Peak memory 268220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662047593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2662047593
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.3980099894
Short name T1027
Test name
Test status
Simulation time 31923502704 ps
CPU time 370.56 seconds
Started Sep 11 05:19:31 PM UTC 24
Finished Sep 11 05:25:47 PM UTC 24
Peak memory 284668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980099894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.3980099894
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.1484192721
Short name T996
Test name
Test status
Simulation time 17545574692 ps
CPU time 165.27 seconds
Started Sep 11 05:19:23 PM UTC 24
Finished Sep 11 05:22:12 PM UTC 24
Peak memory 262084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484192721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.1484192721
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.230618735
Short name T853
Test name
Test status
Simulation time 3329755134 ps
CPU time 12.15 seconds
Started Sep 11 05:19:18 PM UTC 24
Finished Sep 11 05:19:31 PM UTC 24
Peak memory 242292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230618735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.230618735
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/41.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.3220682472
Short name T854
Test name
Test status
Simulation time 12264291853 ps
CPU time 14.25 seconds
Started Sep 11 05:19:18 PM UTC 24
Finished Sep 11 05:19:33 PM UTC 24
Peak memory 245660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220682472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3220682472
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/41.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.3417905631
Short name T847
Test name
Test status
Simulation time 30333155 ps
CPU time 3.18 seconds
Started Sep 11 05:19:16 PM UTC 24
Finished Sep 11 05:19:20 PM UTC 24
Peak memory 245572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417905631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.3417905631
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/41.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.2634936468
Short name T852
Test name
Test status
Simulation time 316100076 ps
CPU time 9.77 seconds
Started Sep 11 05:19:15 PM UTC 24
Finished Sep 11 05:19:26 PM UTC 24
Peak memory 251876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634936468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2634936468
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/41.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.2426447482
Short name T861
Test name
Test status
Simulation time 3185742658 ps
CPU time 9.6 seconds
Started Sep 11 05:19:27 PM UTC 24
Finished Sep 11 05:19:38 PM UTC 24
Peak memory 231912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426447482 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.2426447482
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/41.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.430869765
Short name T972
Test name
Test status
Simulation time 11869781508 ps
CPU time 140.95 seconds
Started Sep 11 05:19:31 PM UTC 24
Finished Sep 11 05:21:55 PM UTC 24
Peak memory 268220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430869765 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.430869765
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/41.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.760385521
Short name T879
Test name
Test status
Simulation time 39956827547 ps
CPU time 46.81 seconds
Started Sep 11 05:19:13 PM UTC 24
Finished Sep 11 05:20:02 PM UTC 24
Peak memory 228076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760385521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.760385521
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/41.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.3353787841
Short name T848
Test name
Test status
Simulation time 3821063814 ps
CPU time 9.86 seconds
Started Sep 11 05:19:11 PM UTC 24
Finished Sep 11 05:19:22 PM UTC 24
Peak memory 228016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353787841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3353787841
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/41.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.902839513
Short name T846
Test name
Test status
Simulation time 37113598 ps
CPU time 1.54 seconds
Started Sep 11 05:19:13 PM UTC 24
Finished Sep 11 05:19:16 PM UTC 24
Peak memory 215624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902839513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.902839513
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/41.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.3587943181
Short name T845
Test name
Test status
Simulation time 24294903 ps
CPU time 1.18 seconds
Started Sep 11 05:19:13 PM UTC 24
Finished Sep 11 05:19:16 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587943181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3587943181
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/41.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.1725532730
Short name T863
Test name
Test status
Simulation time 5722330829 ps
CPU time 19.36 seconds
Started Sep 11 05:19:21 PM UTC 24
Finished Sep 11 05:19:42 PM UTC 24
Peak memory 245720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725532730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1725532730
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/41.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.3012971150
Short name T874
Test name
Test status
Simulation time 14726681 ps
CPU time 1.14 seconds
Started Sep 11 05:19:55 PM UTC 24
Finished Sep 11 05:19:57 PM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012971150 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.3012971150
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/42.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3159273264
Short name T113
Test name
Test status
Simulation time 588900068 ps
CPU time 6.06 seconds
Started Sep 11 05:19:42 PM UTC 24
Finished Sep 11 05:19:49 PM UTC 24
Peak memory 235324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159273264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3159273264
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/42.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.4020145602
Short name T857
Test name
Test status
Simulation time 72850528 ps
CPU time 1.12 seconds
Started Sep 11 05:19:34 PM UTC 24
Finished Sep 11 05:19:36 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020145602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.4020145602
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/42.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.3006689934
Short name T915
Test name
Test status
Simulation time 11146884796 ps
CPU time 65.54 seconds
Started Sep 11 05:19:52 PM UTC 24
Finished Sep 11 05:20:59 PM UTC 24
Peak memory 262084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006689934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3006689934
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/42.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.1978434481
Short name T76
Test name
Test status
Simulation time 29672372797 ps
CPU time 146.85 seconds
Started Sep 11 05:19:52 PM UTC 24
Finished Sep 11 05:22:21 PM UTC 24
Peak memory 284860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978434481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1978434481
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.490841896
Short name T965
Test name
Test status
Simulation time 10754506404 ps
CPU time 114.15 seconds
Started Sep 11 05:19:53 PM UTC 24
Finished Sep 11 05:21:49 PM UTC 24
Peak memory 278652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490841896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.490841896
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.1817546561
Short name T869
Test name
Test status
Simulation time 318889494 ps
CPU time 9.15 seconds
Started Sep 11 05:19:43 PM UTC 24
Finished Sep 11 05:19:54 PM UTC 24
Peak memory 244216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817546561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1817546561
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/42.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.2078566438
Short name T912
Test name
Test status
Simulation time 16395487115 ps
CPU time 64.91 seconds
Started Sep 11 05:19:46 PM UTC 24
Finished Sep 11 05:20:53 PM UTC 24
Peak memory 262108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078566438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.2078566438
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.1225647189
Short name T866
Test name
Test status
Simulation time 800901156 ps
CPU time 10.3 seconds
Started Sep 11 05:19:39 PM UTC 24
Finished Sep 11 05:19:50 PM UTC 24
Peak memory 245568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225647189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1225647189
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/42.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.3211142779
Short name T884
Test name
Test status
Simulation time 12429024077 ps
CPU time 29.51 seconds
Started Sep 11 05:19:39 PM UTC 24
Finished Sep 11 05:20:10 PM UTC 24
Peak memory 235452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211142779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3211142779
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/42.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.3590269373
Short name T882
Test name
Test status
Simulation time 31186181402 ps
CPU time 28.98 seconds
Started Sep 11 05:19:39 PM UTC 24
Finished Sep 11 05:20:09 PM UTC 24
Peak memory 235588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590269373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.3590269373
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/42.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.1959689004
Short name T868
Test name
Test status
Simulation time 835474901 ps
CPU time 13.38 seconds
Started Sep 11 05:19:37 PM UTC 24
Finished Sep 11 05:19:51 PM UTC 24
Peak memory 245516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959689004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1959689004
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/42.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2468514194
Short name T873
Test name
Test status
Simulation time 231118115 ps
CPU time 4.83 seconds
Started Sep 11 05:19:51 PM UTC 24
Finished Sep 11 05:19:56 PM UTC 24
Peak memory 233668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468514194 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.2468514194
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/42.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.620519307
Short name T872
Test name
Test status
Simulation time 188590841 ps
CPU time 1.49 seconds
Started Sep 11 05:19:54 PM UTC 24
Finished Sep 11 05:19:56 PM UTC 24
Peak memory 216136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620519307 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.620519307
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/42.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.3766374051
Short name T871
Test name
Test status
Simulation time 4207906258 ps
CPU time 18.78 seconds
Started Sep 11 05:19:36 PM UTC 24
Finished Sep 11 05:19:56 PM UTC 24
Peak memory 227948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766374051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3766374051
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/42.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.3008453698
Short name T876
Test name
Test status
Simulation time 6072171467 ps
CPU time 23.14 seconds
Started Sep 11 05:19:35 PM UTC 24
Finished Sep 11 05:19:59 PM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008453698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3008453698
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/42.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.1271406069
Short name T864
Test name
Test status
Simulation time 351487672 ps
CPU time 5.01 seconds
Started Sep 11 05:19:37 PM UTC 24
Finished Sep 11 05:19:43 PM UTC 24
Peak memory 228004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271406069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1271406069
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/42.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.1433852952
Short name T859
Test name
Test status
Simulation time 362263496 ps
CPU time 1.4 seconds
Started Sep 11 05:19:36 PM UTC 24
Finished Sep 11 05:19:38 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433852952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1433852952
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/42.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.12868109
Short name T867
Test name
Test status
Simulation time 1682979732 ps
CPU time 9.94 seconds
Started Sep 11 05:19:40 PM UTC 24
Finished Sep 11 05:19:51 PM UTC 24
Peak memory 235356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12868109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_devi
ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.12868109
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/42.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.2775088534
Short name T888
Test name
Test status
Simulation time 11372336 ps
CPU time 1.11 seconds
Started Sep 11 05:20:14 PM UTC 24
Finished Sep 11 05:20:16 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775088534 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.2775088534
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/43.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.2341916890
Short name T883
Test name
Test status
Simulation time 400969583 ps
CPU time 5.92 seconds
Started Sep 11 05:20:03 PM UTC 24
Finished Sep 11 05:20:10 PM UTC 24
Peak memory 235460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341916890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2341916890
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/43.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.669665363
Short name T875
Test name
Test status
Simulation time 98671572 ps
CPU time 1.13 seconds
Started Sep 11 05:19:55 PM UTC 24
Finished Sep 11 05:19:57 PM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669665363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.669665363
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/43.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.2587764513
Short name T898
Test name
Test status
Simulation time 14534499906 ps
CPU time 25.31 seconds
Started Sep 11 05:20:11 PM UTC 24
Finished Sep 11 05:20:38 PM UTC 24
Peak memory 230056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587764513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2587764513
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.882527402
Short name T358
Test name
Test status
Simulation time 3206951134 ps
CPU time 53.21 seconds
Started Sep 11 05:20:11 PM UTC 24
Finished Sep 11 05:21:06 PM UTC 24
Peak memory 249872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882527402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.882527402
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.621566501
Short name T904
Test name
Test status
Simulation time 11423759794 ps
CPU time 38.01 seconds
Started Sep 11 05:20:07 PM UTC 24
Finished Sep 11 05:20:46 PM UTC 24
Peak memory 245700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621566501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.621566501
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/43.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.800668295
Short name T1015
Test name
Test status
Simulation time 70607400742 ps
CPU time 183.12 seconds
Started Sep 11 05:20:09 PM UTC 24
Finished Sep 11 05:23:15 PM UTC 24
Peak memory 284608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800668295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.800668295
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.3344705371
Short name T892
Test name
Test status
Simulation time 1682587883 ps
CPU time 18.26 seconds
Started Sep 11 05:20:00 PM UTC 24
Finished Sep 11 05:20:19 PM UTC 24
Peak memory 245664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344705371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3344705371
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/43.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.232796409
Short name T887
Test name
Test status
Simulation time 1496243695 ps
CPU time 11.68 seconds
Started Sep 11 05:20:01 PM UTC 24
Finished Sep 11 05:20:14 PM UTC 24
Peak memory 245596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232796409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.232796409
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/43.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.3655048656
Short name T885
Test name
Test status
Simulation time 2441903148 ps
CPU time 11.19 seconds
Started Sep 11 05:19:59 PM UTC 24
Finished Sep 11 05:20:11 PM UTC 24
Peak memory 235460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655048656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.3655048656
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/43.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.2224509303
Short name T890
Test name
Test status
Simulation time 5489047105 ps
CPU time 18.17 seconds
Started Sep 11 05:19:59 PM UTC 24
Finished Sep 11 05:20:18 PM UTC 24
Peak memory 235532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224509303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2224509303
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/43.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.3151606443
Short name T893
Test name
Test status
Simulation time 1624313651 ps
CPU time 8.52 seconds
Started Sep 11 05:20:10 PM UTC 24
Finished Sep 11 05:20:20 PM UTC 24
Peak memory 233696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151606443 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.3151606443
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/43.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.4153779725
Short name T935
Test name
Test status
Simulation time 2960501795 ps
CPU time 62.84 seconds
Started Sep 11 05:20:12 PM UTC 24
Finished Sep 11 05:21:17 PM UTC 24
Peak memory 262148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153779725 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.4153779725
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/43.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.249665246
Short name T886
Test name
Test status
Simulation time 7044198290 ps
CPU time 15.29 seconds
Started Sep 11 05:19:56 PM UTC 24
Finished Sep 11 05:20:13 PM UTC 24
Peak memory 227884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249665246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.249665246
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/43.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.3066121920
Short name T880
Test name
Test status
Simulation time 3674300765 ps
CPU time 9.04 seconds
Started Sep 11 05:19:56 PM UTC 24
Finished Sep 11 05:20:06 PM UTC 24
Peak memory 228012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066121920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3066121920
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/43.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.3193881041
Short name T878
Test name
Test status
Simulation time 96548655 ps
CPU time 1.55 seconds
Started Sep 11 05:19:57 PM UTC 24
Finished Sep 11 05:20:00 PM UTC 24
Peak memory 216528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193881041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3193881041
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/43.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.1995149891
Short name T877
Test name
Test status
Simulation time 33727153 ps
CPU time 1.26 seconds
Started Sep 11 05:19:57 PM UTC 24
Finished Sep 11 05:20:00 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995149891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1995149891
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/43.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.3929577761
Short name T894
Test name
Test status
Simulation time 4079933196 ps
CPU time 19.33 seconds
Started Sep 11 05:20:01 PM UTC 24
Finished Sep 11 05:20:21 PM UTC 24
Peak memory 251772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929577761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3929577761
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/43.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.2784001888
Short name T906
Test name
Test status
Simulation time 13803237 ps
CPU time 1.14 seconds
Started Sep 11 05:20:46 PM UTC 24
Finished Sep 11 05:20:48 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784001888 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.2784001888
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/44.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.2943603328
Short name T900
Test name
Test status
Simulation time 482564377 ps
CPU time 8.89 seconds
Started Sep 11 05:20:28 PM UTC 24
Finished Sep 11 05:20:38 PM UTC 24
Peak memory 245508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943603328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2943603328
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/44.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.3053518069
Short name T889
Test name
Test status
Simulation time 18695993 ps
CPU time 1.13 seconds
Started Sep 11 05:20:14 PM UTC 24
Finished Sep 11 05:20:16 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053518069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3053518069
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/44.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.3549748760
Short name T941
Test name
Test status
Simulation time 9184859298 ps
CPU time 42.26 seconds
Started Sep 11 05:20:40 PM UTC 24
Finished Sep 11 05:21:24 PM UTC 24
Peak memory 266180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549748760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3549748760
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/44.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1497654823
Short name T1016
Test name
Test status
Simulation time 9078718765 ps
CPU time 152.73 seconds
Started Sep 11 05:20:40 PM UTC 24
Finished Sep 11 05:23:15 PM UTC 24
Peak memory 284696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497654823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1497654823
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.148288618
Short name T1012
Test name
Test status
Simulation time 8681446259 ps
CPU time 136.36 seconds
Started Sep 11 05:20:41 PM UTC 24
Finished Sep 11 05:23:00 PM UTC 24
Peak memory 266388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148288618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.148288618
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.29457608
Short name T901
Test name
Test status
Simulation time 198065122 ps
CPU time 8.39 seconds
Started Sep 11 05:20:29 PM UTC 24
Finished Sep 11 05:20:39 PM UTC 24
Peak memory 245580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29457608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.29457608
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/44.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.2844455972
Short name T1008
Test name
Test status
Simulation time 61740899750 ps
CPU time 117.77 seconds
Started Sep 11 05:20:39 PM UTC 24
Finished Sep 11 05:22:39 PM UTC 24
Peak memory 262112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844455972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.2844455972
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.2097107331
Short name T896
Test name
Test status
Simulation time 559831931 ps
CPU time 4.94 seconds
Started Sep 11 05:20:21 PM UTC 24
Finished Sep 11 05:20:27 PM UTC 24
Peak memory 245600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097107331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2097107331
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/44.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.3420838807
Short name T951
Test name
Test status
Simulation time 15380505238 ps
CPU time 72.43 seconds
Started Sep 11 05:20:22 PM UTC 24
Finished Sep 11 05:21:36 PM UTC 24
Peak memory 251808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420838807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3420838807
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/44.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.347450715
Short name T899
Test name
Test status
Simulation time 6912879401 ps
CPU time 16.89 seconds
Started Sep 11 05:20:20 PM UTC 24
Finished Sep 11 05:20:38 PM UTC 24
Peak memory 245664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347450715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.347450715
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/44.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.1020948567
Short name T908
Test name
Test status
Simulation time 26434191055 ps
CPU time 28.99 seconds
Started Sep 11 05:20:20 PM UTC 24
Finished Sep 11 05:20:50 PM UTC 24
Peak memory 245644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020948567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1020948567
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/44.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.234724363
Short name T903
Test name
Test status
Simulation time 198749796 ps
CPU time 5.24 seconds
Started Sep 11 05:20:39 PM UTC 24
Finished Sep 11 05:20:45 PM UTC 24
Peak memory 233984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234724363 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.234724363
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/44.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.1313387501
Short name T1025
Test name
Test status
Simulation time 135496954840 ps
CPU time 280.21 seconds
Started Sep 11 05:20:44 PM UTC 24
Finished Sep 11 05:25:28 PM UTC 24
Peak memory 268512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313387501 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.1313387501
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/44.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.349751193
Short name T909
Test name
Test status
Simulation time 4977552547 ps
CPU time 33.32 seconds
Started Sep 11 05:20:17 PM UTC 24
Finished Sep 11 05:20:51 PM UTC 24
Peak memory 227944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349751193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.349751193
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/44.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.1157022588
Short name T905
Test name
Test status
Simulation time 28674832276 ps
CPU time 32.4 seconds
Started Sep 11 05:20:15 PM UTC 24
Finished Sep 11 05:20:48 PM UTC 24
Peak memory 228084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157022588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1157022588
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/44.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.932323284
Short name T897
Test name
Test status
Simulation time 184879424 ps
CPU time 8.18 seconds
Started Sep 11 05:20:19 PM UTC 24
Finished Sep 11 05:20:28 PM UTC 24
Peak memory 227748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932323284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.932323284
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/44.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.3007124770
Short name T891
Test name
Test status
Simulation time 65727242 ps
CPU time 1.16 seconds
Started Sep 11 05:20:17 PM UTC 24
Finished Sep 11 05:20:19 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007124770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3007124770
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/44.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.3952289460
Short name T914
Test name
Test status
Simulation time 26645002598 ps
CPU time 29.69 seconds
Started Sep 11 05:20:27 PM UTC 24
Finished Sep 11 05:20:58 PM UTC 24
Peak memory 245660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952289460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3952289460
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/44.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.648260201
Short name T922
Test name
Test status
Simulation time 37382726 ps
CPU time 1.11 seconds
Started Sep 11 05:21:04 PM UTC 24
Finished Sep 11 05:21:06 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648260201 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.648260201
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/45.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.777159976
Short name T927
Test name
Test status
Simulation time 1259233495 ps
CPU time 11.48 seconds
Started Sep 11 05:20:56 PM UTC 24
Finished Sep 11 05:21:09 PM UTC 24
Peak memory 235328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777159976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.777159976
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/45.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.2207597465
Short name T907
Test name
Test status
Simulation time 18044893 ps
CPU time 1.18 seconds
Started Sep 11 05:20:46 PM UTC 24
Finished Sep 11 05:20:48 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207597465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2207597465
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/45.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.2703063299
Short name T1019
Test name
Test status
Simulation time 22364629337 ps
CPU time 146.15 seconds
Started Sep 11 05:21:00 PM UTC 24
Finished Sep 11 05:23:29 PM UTC 24
Peak memory 262084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703063299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2703063299
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/45.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.64716909
Short name T1011
Test name
Test status
Simulation time 41007518135 ps
CPU time 115.55 seconds
Started Sep 11 05:21:01 PM UTC 24
Finished Sep 11 05:22:59 PM UTC 24
Peak memory 263972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64716909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.64716909
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.3838739417
Short name T942
Test name
Test status
Simulation time 5855286531 ps
CPU time 21.32 seconds
Started Sep 11 05:21:01 PM UTC 24
Finished Sep 11 05:21:24 PM UTC 24
Peak memory 262076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838739417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.3838739417
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.1703321795
Short name T958
Test name
Test status
Simulation time 2839345364 ps
CPU time 41.87 seconds
Started Sep 11 05:20:59 PM UTC 24
Finished Sep 11 05:21:42 PM UTC 24
Peak memory 245696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703321795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1703321795
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/45.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.402199860
Short name T368
Test name
Test status
Simulation time 17409725381 ps
CPU time 89.33 seconds
Started Sep 11 05:20:59 PM UTC 24
Finished Sep 11 05:22:30 PM UTC 24
Peak memory 249792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402199860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.402199860
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.2927099866
Short name T917
Test name
Test status
Simulation time 131726010 ps
CPU time 5.79 seconds
Started Sep 11 05:20:53 PM UTC 24
Finished Sep 11 05:21:00 PM UTC 24
Peak memory 245536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927099866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2927099866
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/45.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.3648388183
Short name T919
Test name
Test status
Simulation time 1578323418 ps
CPU time 7.39 seconds
Started Sep 11 05:20:54 PM UTC 24
Finished Sep 11 05:21:03 PM UTC 24
Peak memory 235260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648388183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3648388183
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/45.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.3627314515
Short name T921
Test name
Test status
Simulation time 2850571570 ps
CPU time 10.6 seconds
Started Sep 11 05:20:53 PM UTC 24
Finished Sep 11 05:21:05 PM UTC 24
Peak memory 229944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627314515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.3627314515
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/45.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.2939117541
Short name T955
Test name
Test status
Simulation time 40921067235 ps
CPU time 46.67 seconds
Started Sep 11 05:20:51 PM UTC 24
Finished Sep 11 05:21:40 PM UTC 24
Peak memory 264136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939117541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2939117541
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/45.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.4000908759
Short name T926
Test name
Test status
Simulation time 1341160130 ps
CPU time 7.02 seconds
Started Sep 11 05:21:00 PM UTC 24
Finished Sep 11 05:21:08 PM UTC 24
Peak memory 233668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000908759 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.4000908759
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/45.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.3186089483
Short name T923
Test name
Test status
Simulation time 343809835 ps
CPU time 1.87 seconds
Started Sep 11 05:21:04 PM UTC 24
Finished Sep 11 05:21:06 PM UTC 24
Peak memory 215872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186089483 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.3186089483
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/45.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.3406328423
Short name T920
Test name
Test status
Simulation time 2274356024 ps
CPU time 13.73 seconds
Started Sep 11 05:20:49 PM UTC 24
Finished Sep 11 05:21:04 PM UTC 24
Peak memory 227520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406328423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3406328423
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/45.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.1841987429
Short name T918
Test name
Test status
Simulation time 2114974309 ps
CPU time 14.04 seconds
Started Sep 11 05:20:47 PM UTC 24
Finished Sep 11 05:21:02 PM UTC 24
Peak memory 227780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841987429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1841987429
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/45.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.730653019
Short name T911
Test name
Test status
Simulation time 50395231 ps
CPU time 2.2 seconds
Started Sep 11 05:20:49 PM UTC 24
Finished Sep 11 05:20:53 PM UTC 24
Peak memory 227788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730653019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.730653019
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/45.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.1823105292
Short name T910
Test name
Test status
Simulation time 224050931 ps
CPU time 1.32 seconds
Started Sep 11 05:20:49 PM UTC 24
Finished Sep 11 05:20:52 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823105292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1823105292
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/45.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.3582583429
Short name T916
Test name
Test status
Simulation time 368008323 ps
CPU time 4.29 seconds
Started Sep 11 05:20:54 PM UTC 24
Finished Sep 11 05:20:59 PM UTC 24
Peak memory 245756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582583429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3582583429
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/45.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.3992729223
Short name T939
Test name
Test status
Simulation time 21100904 ps
CPU time 1.15 seconds
Started Sep 11 05:21:21 PM UTC 24
Finished Sep 11 05:21:23 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992729223 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.3992729223
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/46.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.204776469
Short name T934
Test name
Test status
Simulation time 435622758 ps
CPU time 3.77 seconds
Started Sep 11 05:21:10 PM UTC 24
Finished Sep 11 05:21:15 PM UTC 24
Peak memory 235524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204776469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.204776469
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/46.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.1310101570
Short name T924
Test name
Test status
Simulation time 12585221 ps
CPU time 1.14 seconds
Started Sep 11 05:21:05 PM UTC 24
Finished Sep 11 05:21:07 PM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310101570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1310101570
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/46.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.890349089
Short name T1004
Test name
Test status
Simulation time 5687510566 ps
CPU time 63.77 seconds
Started Sep 11 05:21:16 PM UTC 24
Finished Sep 11 05:22:21 PM UTC 24
Peak memory 262108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890349089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.890349089
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/46.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.1567805768
Short name T999
Test name
Test status
Simulation time 2550530139 ps
CPU time 57.96 seconds
Started Sep 11 05:21:16 PM UTC 24
Finished Sep 11 05:22:15 PM UTC 24
Peak memory 266260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567805768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1567805768
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/46.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.2534093793
Short name T1002
Test name
Test status
Simulation time 15775088020 ps
CPU time 58.92 seconds
Started Sep 11 05:21:18 PM UTC 24
Finished Sep 11 05:22:18 PM UTC 24
Peak memory 266240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534093793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.2534093793
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.2598787056
Short name T1007
Test name
Test status
Simulation time 35017086230 ps
CPU time 79.21 seconds
Started Sep 11 05:21:12 PM UTC 24
Finished Sep 11 05:22:34 PM UTC 24
Peak memory 251820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598787056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2598787056
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/46.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.3050280701
Short name T984
Test name
Test status
Simulation time 11818827805 ps
CPU time 46.57 seconds
Started Sep 11 05:21:13 PM UTC 24
Finished Sep 11 05:22:01 PM UTC 24
Peak memory 262112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050280701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.3050280701
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.991613309
Short name T945
Test name
Test status
Simulation time 2001806423 ps
CPU time 18.26 seconds
Started Sep 11 05:21:09 PM UTC 24
Finished Sep 11 05:21:29 PM UTC 24
Peak memory 235268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991613309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.991613309
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/46.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.3444512226
Short name T960
Test name
Test status
Simulation time 1940825905 ps
CPU time 34.58 seconds
Started Sep 11 05:21:09 PM UTC 24
Finished Sep 11 05:21:45 PM UTC 24
Peak memory 245720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444512226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3444512226
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/46.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.3873982609
Short name T931
Test name
Test status
Simulation time 96225884 ps
CPU time 2.97 seconds
Started Sep 11 05:21:08 PM UTC 24
Finished Sep 11 05:21:12 PM UTC 24
Peak memory 234676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873982609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.3873982609
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/46.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.1755670034
Short name T930
Test name
Test status
Simulation time 146330101 ps
CPU time 2.92 seconds
Started Sep 11 05:21:08 PM UTC 24
Finished Sep 11 05:21:12 PM UTC 24
Peak memory 235152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755670034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1755670034
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/46.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.2701616084
Short name T938
Test name
Test status
Simulation time 271848860 ps
CPU time 5.04 seconds
Started Sep 11 05:21:15 PM UTC 24
Finished Sep 11 05:21:21 PM UTC 24
Peak memory 234028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701616084 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.2701616084
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/46.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.2528434805
Short name T991
Test name
Test status
Simulation time 11878976232 ps
CPU time 46.85 seconds
Started Sep 11 05:21:19 PM UTC 24
Finished Sep 11 05:22:07 PM UTC 24
Peak memory 262144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528434805 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.2528434805
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/46.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.355108530
Short name T933
Test name
Test status
Simulation time 1131658739 ps
CPU time 6.64 seconds
Started Sep 11 05:21:07 PM UTC 24
Finished Sep 11 05:21:15 PM UTC 24
Peak memory 228008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355108530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.355108530
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/46.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.1647059548
Short name T946
Test name
Test status
Simulation time 17089205913 ps
CPU time 22.14 seconds
Started Sep 11 05:21:06 PM UTC 24
Finished Sep 11 05:21:29 PM UTC 24
Peak memory 227916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647059548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1647059548
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/46.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.1262464657
Short name T928
Test name
Test status
Simulation time 216356833 ps
CPU time 1.43 seconds
Started Sep 11 05:21:07 PM UTC 24
Finished Sep 11 05:21:09 PM UTC 24
Peak memory 215972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262464657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1262464657
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/46.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.2785039284
Short name T929
Test name
Test status
Simulation time 355945850 ps
CPU time 1.71 seconds
Started Sep 11 05:21:07 PM UTC 24
Finished Sep 11 05:21:10 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785039284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2785039284
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/46.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.3688722670
Short name T992
Test name
Test status
Simulation time 43657764124 ps
CPU time 56.83 seconds
Started Sep 11 05:21:10 PM UTC 24
Finished Sep 11 05:22:09 PM UTC 24
Peak memory 245624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688722670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3688722670
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/46.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.2388793307
Short name T957
Test name
Test status
Simulation time 42922105 ps
CPU time 0.94 seconds
Started Sep 11 05:21:39 PM UTC 24
Finished Sep 11 05:21:41 PM UTC 24
Peak memory 215672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388793307 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.2388793307
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/47.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.1191129353
Short name T950
Test name
Test status
Simulation time 844504808 ps
CPU time 4.41 seconds
Started Sep 11 05:21:31 PM UTC 24
Finished Sep 11 05:21:36 PM UTC 24
Peak memory 245572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191129353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1191129353
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/47.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.2838169845
Short name T940
Test name
Test status
Simulation time 21578202 ps
CPU time 1.21 seconds
Started Sep 11 05:21:21 PM UTC 24
Finished Sep 11 05:21:23 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838169845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2838169845
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/47.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.3464608890
Short name T998
Test name
Test status
Simulation time 12527098958 ps
CPU time 36.55 seconds
Started Sep 11 05:21:37 PM UTC 24
Finished Sep 11 05:22:15 PM UTC 24
Peak memory 252036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464608890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3464608890
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/47.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3364862324
Short name T1029
Test name
Test status
Simulation time 241965520283 ps
CPU time 332.53 seconds
Started Sep 11 05:21:37 PM UTC 24
Finished Sep 11 05:27:14 PM UTC 24
Peak memory 278552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364862324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3364862324
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.1697265617
Short name T1020
Test name
Test status
Simulation time 60851271048 ps
CPU time 142.11 seconds
Started Sep 11 05:21:39 PM UTC 24
Finished Sep 11 05:24:04 PM UTC 24
Peak memory 262328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697265617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.1697265617
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.4255354449
Short name T967
Test name
Test status
Simulation time 2856958950 ps
CPU time 18.31 seconds
Started Sep 11 05:21:31 PM UTC 24
Finished Sep 11 05:21:50 PM UTC 24
Peak memory 245736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255354449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.4255354449
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/47.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.4123661035
Short name T1024
Test name
Test status
Simulation time 90583073002 ps
CPU time 206.39 seconds
Started Sep 11 05:21:32 PM UTC 24
Finished Sep 11 05:25:02 PM UTC 24
Peak memory 262112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123661035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.4123661035
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.623776146
Short name T956
Test name
Test status
Simulation time 699979664 ps
CPU time 10.25 seconds
Started Sep 11 05:21:29 PM UTC 24
Finished Sep 11 05:21:40 PM UTC 24
Peak memory 245760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623776146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.623776146
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/47.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.3698781358
Short name T1009
Test name
Test status
Simulation time 8326998480 ps
CPU time 74.65 seconds
Started Sep 11 05:21:30 PM UTC 24
Finished Sep 11 05:22:46 PM UTC 24
Peak memory 262296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698781358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3698781358
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/47.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.4157388706
Short name T954
Test name
Test status
Simulation time 4415516609 ps
CPU time 10.15 seconds
Started Sep 11 05:21:27 PM UTC 24
Finished Sep 11 05:21:39 PM UTC 24
Peak memory 235460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157388706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.4157388706
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/47.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.2837955390
Short name T947
Test name
Test status
Simulation time 248634552 ps
CPU time 3.64 seconds
Started Sep 11 05:21:25 PM UTC 24
Finished Sep 11 05:21:30 PM UTC 24
Peak memory 245604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837955390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2837955390
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/47.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.1374358541
Short name T963
Test name
Test status
Simulation time 3763557454 ps
CPU time 11.84 seconds
Started Sep 11 05:21:34 PM UTC 24
Finished Sep 11 05:21:47 PM UTC 24
Peak memory 233828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374358541 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.1374358541
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/47.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.3646127640
Short name T1026
Test name
Test status
Simulation time 40873127506 ps
CPU time 230.73 seconds
Started Sep 11 05:21:39 PM UTC 24
Finished Sep 11 05:25:33 PM UTC 24
Peak memory 278720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646127640 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.3646127640
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/47.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.4272545223
Short name T964
Test name
Test status
Simulation time 4359617165 ps
CPU time 21.57 seconds
Started Sep 11 05:21:24 PM UTC 24
Finished Sep 11 05:21:47 PM UTC 24
Peak memory 228104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272545223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.4272545223
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/47.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.2533094090
Short name T952
Test name
Test status
Simulation time 26398088124 ps
CPU time 12.63 seconds
Started Sep 11 05:21:24 PM UTC 24
Finished Sep 11 05:21:38 PM UTC 24
Peak memory 229876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533094090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2533094090
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/47.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.3370087000
Short name T944
Test name
Test status
Simulation time 200214469 ps
CPU time 2.1 seconds
Started Sep 11 05:21:24 PM UTC 24
Finished Sep 11 05:21:27 PM UTC 24
Peak memory 217500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370087000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3370087000
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/47.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.1165630636
Short name T943
Test name
Test status
Simulation time 83918163 ps
CPU time 1.2 seconds
Started Sep 11 05:21:24 PM UTC 24
Finished Sep 11 05:21:26 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165630636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1165630636
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/47.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.1699481286
Short name T949
Test name
Test status
Simulation time 50863323 ps
CPU time 2.68 seconds
Started Sep 11 05:21:30 PM UTC 24
Finished Sep 11 05:21:34 PM UTC 24
Peak memory 245560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699481286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1699481286
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/47.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.375895678
Short name T974
Test name
Test status
Simulation time 11703824 ps
CPU time 1.05 seconds
Started Sep 11 05:21:54 PM UTC 24
Finished Sep 11 05:21:56 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375895678 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.375895678
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/48.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.2434109774
Short name T975
Test name
Test status
Simulation time 1810472482 ps
CPU time 6.94 seconds
Started Sep 11 05:21:48 PM UTC 24
Finished Sep 11 05:21:56 PM UTC 24
Peak memory 235264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434109774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2434109774
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/48.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.1543961057
Short name T959
Test name
Test status
Simulation time 14767305 ps
CPU time 1.19 seconds
Started Sep 11 05:21:40 PM UTC 24
Finished Sep 11 05:21:43 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543961057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1543961057
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/48.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.1671225958
Short name T1032
Test name
Test status
Simulation time 209827731388 ps
CPU time 375.2 seconds
Started Sep 11 05:21:50 PM UTC 24
Finished Sep 11 05:28:10 PM UTC 24
Peak memory 278492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671225958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1671225958
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/48.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.3664121055
Short name T1033
Test name
Test status
Simulation time 40562634015 ps
CPU time 480.11 seconds
Started Sep 11 05:21:50 PM UTC 24
Finished Sep 11 05:29:57 PM UTC 24
Peak memory 262140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664121055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3664121055
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.590508075
Short name T1017
Test name
Test status
Simulation time 6892847246 ps
CPU time 84.23 seconds
Started Sep 11 05:21:52 PM UTC 24
Finished Sep 11 05:23:18 PM UTC 24
Peak memory 268156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590508075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.590508075
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.2375437546
Short name T995
Test name
Test status
Simulation time 14505681725 ps
CPU time 20.95 seconds
Started Sep 11 05:21:49 PM UTC 24
Finished Sep 11 05:22:11 PM UTC 24
Peak memory 235400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375437546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2375437546
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/48.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.4080314409
Short name T968
Test name
Test status
Simulation time 78662535 ps
CPU time 2.88 seconds
Started Sep 11 05:21:47 PM UTC 24
Finished Sep 11 05:21:51 PM UTC 24
Peak memory 234132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080314409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.4080314409
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/48.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.1165083642
Short name T983
Test name
Test status
Simulation time 577561088 ps
CPU time 11.78 seconds
Started Sep 11 05:21:47 PM UTC 24
Finished Sep 11 05:22:00 PM UTC 24
Peak memory 251676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165083642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1165083642
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/48.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.2650716270
Short name T966
Test name
Test status
Simulation time 126870529 ps
CPU time 2.68 seconds
Started Sep 11 05:21:46 PM UTC 24
Finished Sep 11 05:21:50 PM UTC 24
Peak memory 245572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650716270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.2650716270
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/48.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.431307446
Short name T970
Test name
Test status
Simulation time 268485131 ps
CPU time 6.44 seconds
Started Sep 11 05:21:46 PM UTC 24
Finished Sep 11 05:21:54 PM UTC 24
Peak memory 251712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431307446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.431307446
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/48.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2542018159
Short name T973
Test name
Test status
Simulation time 252132758 ps
CPU time 4.28 seconds
Started Sep 11 05:21:50 PM UTC 24
Finished Sep 11 05:21:56 PM UTC 24
Peak memory 234012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542018159 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.2542018159
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/48.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.2175162175
Short name T971
Test name
Test status
Simulation time 202225840 ps
CPU time 1.75 seconds
Started Sep 11 05:21:52 PM UTC 24
Finished Sep 11 05:21:54 PM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175162175 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.2175162175
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/48.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.3426312533
Short name T986
Test name
Test status
Simulation time 4409500937 ps
CPU time 17.92 seconds
Started Sep 11 05:21:43 PM UTC 24
Finished Sep 11 05:22:02 PM UTC 24
Peak memory 227948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426312533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3426312533
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/48.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.27365205
Short name T977
Test name
Test status
Simulation time 10399409393 ps
CPU time 14.98 seconds
Started Sep 11 05:21:41 PM UTC 24
Finished Sep 11 05:21:57 PM UTC 24
Peak memory 228044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27365205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.27365205
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/48.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.845686543
Short name T962
Test name
Test status
Simulation time 16133786 ps
CPU time 1.14 seconds
Started Sep 11 05:21:44 PM UTC 24
Finished Sep 11 05:21:46 PM UTC 24
Peak memory 215976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845686543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.845686543
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/48.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.1468436695
Short name T961
Test name
Test status
Simulation time 25748593 ps
CPU time 1.09 seconds
Started Sep 11 05:21:44 PM UTC 24
Finished Sep 11 05:21:46 PM UTC 24
Peak memory 215752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468436695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1468436695
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/48.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.251399796
Short name T969
Test name
Test status
Simulation time 80970937 ps
CPU time 4.32 seconds
Started Sep 11 05:21:48 PM UTC 24
Finished Sep 11 05:21:53 PM UTC 24
Peak memory 245728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251399796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.251399796
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/48.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.3319860533
Short name T989
Test name
Test status
Simulation time 16240095 ps
CPU time 1.15 seconds
Started Sep 11 05:22:04 PM UTC 24
Finished Sep 11 05:22:06 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319860533 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.3319860533
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/49.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.19874299
Short name T936
Test name
Test status
Simulation time 842631378 ps
CPU time 4.24 seconds
Started Sep 11 05:21:59 PM UTC 24
Finished Sep 11 05:22:05 PM UTC 24
Peak memory 235192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19874299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.19874299
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/49.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.4212963946
Short name T976
Test name
Test status
Simulation time 14831626 ps
CPU time 0.92 seconds
Started Sep 11 05:21:55 PM UTC 24
Finished Sep 11 05:21:57 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212963946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.4212963946
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/49.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.796321827
Short name T1021
Test name
Test status
Simulation time 69384251176 ps
CPU time 144.88 seconds
Started Sep 11 05:22:01 PM UTC 24
Finished Sep 11 05:24:28 PM UTC 24
Peak memory 249988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796321827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.796321827
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/49.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.324649494
Short name T1000
Test name
Test status
Simulation time 885149392 ps
CPU time 13.3 seconds
Started Sep 11 05:22:02 PM UTC 24
Finished Sep 11 05:22:16 PM UTC 24
Peak memory 235396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324649494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.324649494
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.1399854270
Short name T1014
Test name
Test status
Simulation time 36404067193 ps
CPU time 68.65 seconds
Started Sep 11 05:22:02 PM UTC 24
Finished Sep 11 05:23:12 PM UTC 24
Peak memory 266240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399854270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.1399854270
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.2522840133
Short name T993
Test name
Test status
Simulation time 294272694 ps
CPU time 9.19 seconds
Started Sep 11 05:22:00 PM UTC 24
Finished Sep 11 05:22:10 PM UTC 24
Peak memory 235512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522840133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2522840133
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/49.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.1293510279
Short name T1005
Test name
Test status
Simulation time 933711650 ps
CPU time 20.88 seconds
Started Sep 11 05:22:00 PM UTC 24
Finished Sep 11 05:22:22 PM UTC 24
Peak memory 262176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293510279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.1293510279
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.17489595
Short name T987
Test name
Test status
Simulation time 783846329 ps
CPU time 4.59 seconds
Started Sep 11 05:21:57 PM UTC 24
Finished Sep 11 05:22:03 PM UTC 24
Peak memory 235396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17489595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.17489595
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/49.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.3089073351
Short name T1010
Test name
Test status
Simulation time 7107563822 ps
CPU time 56.49 seconds
Started Sep 11 05:21:57 PM UTC 24
Finished Sep 11 05:22:55 PM UTC 24
Peak memory 245660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089073351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3089073351
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/49.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.362437200
Short name T985
Test name
Test status
Simulation time 1313368226 ps
CPU time 3.05 seconds
Started Sep 11 05:21:57 PM UTC 24
Finished Sep 11 05:22:01 PM UTC 24
Peak memory 235520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362437200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.362437200
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/49.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.1795927857
Short name T994
Test name
Test status
Simulation time 2985827301 ps
CPU time 12.24 seconds
Started Sep 11 05:21:57 PM UTC 24
Finished Sep 11 05:22:11 PM UTC 24
Peak memory 245684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795927857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1795927857
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/49.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.523594198
Short name T997
Test name
Test status
Simulation time 5108861799 ps
CPU time 11.92 seconds
Started Sep 11 05:22:00 PM UTC 24
Finished Sep 11 05:22:13 PM UTC 24
Peak memory 231724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523594198 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.523594198
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/49.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.1315733001
Short name T1030
Test name
Test status
Simulation time 29086219088 ps
CPU time 317.39 seconds
Started Sep 11 05:22:03 PM UTC 24
Finished Sep 11 05:27:25 PM UTC 24
Peak memory 278748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315733001 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.1315733001
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/49.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.3583698429
Short name T978
Test name
Test status
Simulation time 45406719 ps
CPU time 1.08 seconds
Started Sep 11 05:21:55 PM UTC 24
Finished Sep 11 05:21:58 PM UTC 24
Peak memory 215672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583698429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3583698429
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/49.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.1764898244
Short name T980
Test name
Test status
Simulation time 75145007 ps
CPU time 2.67 seconds
Started Sep 11 05:21:55 PM UTC 24
Finished Sep 11 05:21:59 PM UTC 24
Peak memory 216772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764898244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1764898244
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/49.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.1042011261
Short name T979
Test name
Test status
Simulation time 12697826 ps
CPU time 1.08 seconds
Started Sep 11 05:21:56 PM UTC 24
Finished Sep 11 05:21:58 PM UTC 24
Peak memory 215788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042011261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1042011261
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/49.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.3376784478
Short name T981
Test name
Test status
Simulation time 415214613 ps
CPU time 1.6 seconds
Started Sep 11 05:21:56 PM UTC 24
Finished Sep 11 05:21:59 PM UTC 24
Peak memory 215796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376784478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3376784478
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/49.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.3820465552
Short name T990
Test name
Test status
Simulation time 1141566734 ps
CPU time 7.59 seconds
Started Sep 11 05:21:58 PM UTC 24
Finished Sep 11 05:22:07 PM UTC 24
Peak memory 235348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820465552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3820465552
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/49.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.4117438489
Short name T418
Test name
Test status
Simulation time 14723911 ps
CPU time 1.11 seconds
Started Sep 11 05:07:25 PM UTC 24
Finished Sep 11 05:07:28 PM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117438489 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.4117438489
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.1332407405
Short name T275
Test name
Test status
Simulation time 423719409 ps
CPU time 3.25 seconds
Started Sep 11 05:07:20 PM UTC 24
Finished Sep 11 05:07:25 PM UTC 24
Peak memory 235524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332407405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1332407405
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.277414388
Short name T414
Test name
Test status
Simulation time 17101032 ps
CPU time 1.19 seconds
Started Sep 11 05:07:13 PM UTC 24
Finished Sep 11 05:07:16 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277414388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.277414388
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.2320516832
Short name T107
Test name
Test status
Simulation time 20635145683 ps
CPU time 34.03 seconds
Started Sep 11 05:07:23 PM UTC 24
Finished Sep 11 05:07:59 PM UTC 24
Peak memory 262024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320516832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2320516832
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.315406490
Short name T69
Test name
Test status
Simulation time 19394054324 ps
CPU time 166.09 seconds
Started Sep 11 05:07:23 PM UTC 24
Finished Sep 11 05:10:12 PM UTC 24
Peak memory 280800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315406490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.315406490
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2935857802
Short name T220
Test name
Test status
Simulation time 16170677283 ps
CPU time 180.5 seconds
Started Sep 11 05:07:23 PM UTC 24
Finished Sep 11 05:10:27 PM UTC 24
Peak memory 264196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935857802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.2935857802
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.3278517467
Short name T160
Test name
Test status
Simulation time 1038912540 ps
CPU time 15.11 seconds
Started Sep 11 05:07:21 PM UTC 24
Finished Sep 11 05:07:38 PM UTC 24
Peak memory 235488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278517467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3278517467
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.4231388286
Short name T185
Test name
Test status
Simulation time 2350973146 ps
CPU time 30.82 seconds
Started Sep 11 05:07:22 PM UTC 24
Finished Sep 11 05:07:54 PM UTC 24
Peak memory 245708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231388286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.4231388286
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.430302755
Short name T417
Test name
Test status
Simulation time 589651677 ps
CPU time 5.62 seconds
Started Sep 11 05:07:18 PM UTC 24
Finished Sep 11 05:07:25 PM UTC 24
Peak memory 235352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430302755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.430302755
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.1279524766
Short name T426
Test name
Test status
Simulation time 6428220782 ps
CPU time 25.06 seconds
Started Sep 11 05:07:19 PM UTC 24
Finished Sep 11 05:07:46 PM UTC 24
Peak memory 245220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279524766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1279524766
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.4021344026
Short name T415
Test name
Test status
Simulation time 44637287 ps
CPU time 1.51 seconds
Started Sep 11 05:07:15 PM UTC 24
Finished Sep 11 05:07:17 PM UTC 24
Peak memory 229192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021344026 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mem_parity.4021344026
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.3744139318
Short name T279
Test name
Test status
Simulation time 12786053341 ps
CPU time 16.16 seconds
Started Sep 11 05:07:18 PM UTC 24
Finished Sep 11 05:07:35 PM UTC 24
Peak memory 245640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744139318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.3744139318
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.2354828406
Short name T183
Test name
Test status
Simulation time 1605563328 ps
CPU time 12.14 seconds
Started Sep 11 05:07:17 PM UTC 24
Finished Sep 11 05:07:30 PM UTC 24
Peak memory 245600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354828406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2354828406
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.1974382714
Short name T108
Test name
Test status
Simulation time 1039190917 ps
CPU time 9.39 seconds
Started Sep 11 05:07:22 PM UTC 24
Finished Sep 11 05:07:32 PM UTC 24
Peak memory 231664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974382714 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.1974382714
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.3786796534
Short name T228
Test name
Test status
Simulation time 49763370650 ps
CPU time 432.18 seconds
Started Sep 11 05:07:25 PM UTC 24
Finished Sep 11 05:14:43 PM UTC 24
Peak memory 280664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786796534 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.3786796534
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.1626884340
Short name T385
Test name
Test status
Simulation time 5021052021 ps
CPU time 14.24 seconds
Started Sep 11 05:07:17 PM UTC 24
Finished Sep 11 05:07:32 PM UTC 24
Peak memory 232008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626884340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1626884340
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2920577932
Short name T422
Test name
Test status
Simulation time 17157382909 ps
CPU time 21.1 seconds
Started Sep 11 05:07:16 PM UTC 24
Finished Sep 11 05:07:38 PM UTC 24
Peak memory 227820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920577932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2920577932
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.3450129435
Short name T104
Test name
Test status
Simulation time 347737824 ps
CPU time 2.22 seconds
Started Sep 11 05:07:17 PM UTC 24
Finished Sep 11 05:07:20 PM UTC 24
Peak memory 227804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450129435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3450129435
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.3754658318
Short name T416
Test name
Test status
Simulation time 22223062 ps
CPU time 1.19 seconds
Started Sep 11 05:07:17 PM UTC 24
Finished Sep 11 05:07:19 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754658318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3754658318
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.2753223870
Short name T300
Test name
Test status
Simulation time 2310207193 ps
CPU time 10.39 seconds
Started Sep 11 05:07:20 PM UTC 24
Finished Sep 11 05:07:32 PM UTC 24
Peak memory 235648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753223870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2753223870
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/5.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.1055854823
Short name T425
Test name
Test status
Simulation time 22668565 ps
CPU time 1.04 seconds
Started Sep 11 05:07:43 PM UTC 24
Finished Sep 11 05:07:45 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055854823 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1055854823
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.1270219870
Short name T424
Test name
Test status
Simulation time 4342641318 ps
CPU time 7.52 seconds
Started Sep 11 05:07:36 PM UTC 24
Finished Sep 11 05:07:45 PM UTC 24
Peak memory 245692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270219870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1270219870
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.3591975512
Short name T419
Test name
Test status
Simulation time 40932415 ps
CPU time 1.24 seconds
Started Sep 11 05:07:26 PM UTC 24
Finished Sep 11 05:07:28 PM UTC 24
Peak memory 215792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591975512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3591975512
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.1338379842
Short name T99
Test name
Test status
Simulation time 4979464019 ps
CPU time 82.23 seconds
Started Sep 11 05:07:39 PM UTC 24
Finished Sep 11 05:09:04 PM UTC 24
Peak memory 268416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338379842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1338379842
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.1364020101
Short name T186
Test name
Test status
Simulation time 9298705267 ps
CPU time 75.49 seconds
Started Sep 11 05:07:39 PM UTC 24
Finished Sep 11 05:08:57 PM UTC 24
Peak memory 268268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364020101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1364020101
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.2904105806
Short name T398
Test name
Test status
Simulation time 31882660581 ps
CPU time 297.24 seconds
Started Sep 11 05:07:40 PM UTC 24
Finished Sep 11 05:12:42 PM UTC 24
Peak memory 262148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904105806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.2904105806
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.772849322
Short name T161
Test name
Test status
Simulation time 465079601 ps
CPU time 4.08 seconds
Started Sep 11 05:07:37 PM UTC 24
Finished Sep 11 05:07:42 PM UTC 24
Peak memory 245580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772849322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.772849322
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.1693719276
Short name T90
Test name
Test status
Simulation time 502822324 ps
CPU time 9.51 seconds
Started Sep 11 05:07:33 PM UTC 24
Finished Sep 11 05:07:44 PM UTC 24
Peak memory 245792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693719276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1693719276
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.2709804344
Short name T280
Test name
Test status
Simulation time 9878534757 ps
CPU time 69.53 seconds
Started Sep 11 05:07:34 PM UTC 24
Finished Sep 11 05:08:46 PM UTC 24
Peak memory 245656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709804344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2709804344
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.923782715
Short name T420
Test name
Test status
Simulation time 46020696 ps
CPU time 1.54 seconds
Started Sep 11 05:07:28 PM UTC 24
Finished Sep 11 05:07:30 PM UTC 24
Peak memory 229192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923782715 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mem_parity.923782715
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.98196899
Short name T59
Test name
Test status
Simulation time 1386323044 ps
CPU time 5.07 seconds
Started Sep 11 05:07:33 PM UTC 24
Finished Sep 11 05:07:39 PM UTC 24
Peak memory 245576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98196899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.98196899
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.2604654886
Short name T311
Test name
Test status
Simulation time 1871943316 ps
CPU time 7.6 seconds
Started Sep 11 05:07:32 PM UTC 24
Finished Sep 11 05:07:41 PM UTC 24
Peak memory 245512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604654886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2604654886
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.1891563788
Short name T162
Test name
Test status
Simulation time 220271111 ps
CPU time 7.94 seconds
Started Sep 11 05:07:39 PM UTC 24
Finished Sep 11 05:07:49 PM UTC 24
Peak memory 234040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891563788 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.1891563788
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.1870113388
Short name T388
Test name
Test status
Simulation time 6452220592 ps
CPU time 26.42 seconds
Started Sep 11 05:07:29 PM UTC 24
Finished Sep 11 05:07:57 PM UTC 24
Peak memory 228200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870113388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1870113388
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.784391325
Short name T423
Test name
Test status
Simulation time 5179576678 ps
CPU time 8.02 seconds
Started Sep 11 05:07:29 PM UTC 24
Finished Sep 11 05:07:38 PM UTC 24
Peak memory 228076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784391325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.784391325
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.3848487527
Short name T405
Test name
Test status
Simulation time 28134261 ps
CPU time 1.19 seconds
Started Sep 11 05:07:31 PM UTC 24
Finished Sep 11 05:07:33 PM UTC 24
Peak memory 215976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848487527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3848487527
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.2464713121
Short name T421
Test name
Test status
Simulation time 84192469 ps
CPU time 1.48 seconds
Started Sep 11 05:07:31 PM UTC 24
Finished Sep 11 05:07:33 PM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464713121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2464713121
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.1472764498
Short name T180
Test name
Test status
Simulation time 4244524036 ps
CPU time 11 seconds
Started Sep 11 05:07:34 PM UTC 24
Finished Sep 11 05:07:47 PM UTC 24
Peak memory 252060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472764498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1472764498
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/6.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.2621846779
Short name T432
Test name
Test status
Simulation time 13456533 ps
CPU time 1.17 seconds
Started Sep 11 05:08:08 PM UTC 24
Finished Sep 11 05:08:10 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621846779 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2621846779
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.1788060634
Short name T286
Test name
Test status
Simulation time 34795991531 ps
CPU time 30.5 seconds
Started Sep 11 05:07:57 PM UTC 24
Finished Sep 11 05:08:29 PM UTC 24
Peak memory 235432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788060634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1788060634
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.3464502172
Short name T427
Test name
Test status
Simulation time 52512536 ps
CPU time 1.14 seconds
Started Sep 11 05:07:44 PM UTC 24
Finished Sep 11 05:07:47 PM UTC 24
Peak memory 215732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464502172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3464502172
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.3980503487
Short name T189
Test name
Test status
Simulation time 8187923269 ps
CPU time 51.94 seconds
Started Sep 11 05:08:01 PM UTC 24
Finished Sep 11 05:08:54 PM UTC 24
Peak memory 262080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980503487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3980503487
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.2609530263
Short name T91
Test name
Test status
Simulation time 6118218550 ps
CPU time 17.54 seconds
Started Sep 11 05:07:51 PM UTC 24
Finished Sep 11 05:08:10 PM UTC 24
Peak memory 245724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609530263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2609530263
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.3072168611
Short name T341
Test name
Test status
Simulation time 345238028 ps
CPU time 6.88 seconds
Started Sep 11 05:07:52 PM UTC 24
Finished Sep 11 05:08:00 PM UTC 24
Peak memory 235204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072168611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3072168611
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.1623654809
Short name T429
Test name
Test status
Simulation time 229307052 ps
CPU time 1.53 seconds
Started Sep 11 05:07:45 PM UTC 24
Finished Sep 11 05:07:48 PM UTC 24
Peak memory 229192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623654809 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mem_parity.1623654809
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3771525351
Short name T231
Test name
Test status
Simulation time 972991165 ps
CPU time 8.79 seconds
Started Sep 11 05:07:50 PM UTC 24
Finished Sep 11 05:08:00 PM UTC 24
Peak memory 251692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771525351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.3771525351
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3858291850
Short name T190
Test name
Test status
Simulation time 8114089987 ps
CPU time 32.66 seconds
Started Sep 11 05:07:49 PM UTC 24
Finished Sep 11 05:08:23 PM UTC 24
Peak memory 251844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858291850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3858291850
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.1947024724
Short name T163
Test name
Test status
Simulation time 687394234 ps
CPU time 9.84 seconds
Started Sep 11 05:08:00 PM UTC 24
Finished Sep 11 05:08:11 PM UTC 24
Peak memory 233776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947024724 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.1947024724
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.1254679948
Short name T39
Test name
Test status
Simulation time 6900666423 ps
CPU time 108.02 seconds
Started Sep 11 05:08:05 PM UTC 24
Finished Sep 11 05:09:55 PM UTC 24
Peak memory 262088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254679948 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.1254679948
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.4011024766
Short name T431
Test name
Test status
Simulation time 4184560721 ps
CPU time 11.83 seconds
Started Sep 11 05:07:47 PM UTC 24
Finished Sep 11 05:07:59 PM UTC 24
Peak memory 227880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011024766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.4011024766
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.3105264708
Short name T400
Test name
Test status
Simulation time 166261133 ps
CPU time 2.12 seconds
Started Sep 11 05:07:48 PM UTC 24
Finished Sep 11 05:07:51 PM UTC 24
Peak memory 227792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105264708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3105264708
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.3188049519
Short name T430
Test name
Test status
Simulation time 53172261 ps
CPU time 1.21 seconds
Started Sep 11 05:07:48 PM UTC 24
Finished Sep 11 05:07:50 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188049519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3188049519
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.556335089
Short name T314
Test name
Test status
Simulation time 2002489262 ps
CPU time 11.83 seconds
Started Sep 11 05:07:54 PM UTC 24
Finished Sep 11 05:08:07 PM UTC 24
Peak memory 235328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556335089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.556335089
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/7.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.3017968267
Short name T437
Test name
Test status
Simulation time 44915040 ps
CPU time 1.09 seconds
Started Sep 11 05:08:38 PM UTC 24
Finished Sep 11 05:08:41 PM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017968267 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3017968267
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.3857946563
Short name T296
Test name
Test status
Simulation time 694261122 ps
CPU time 4.87 seconds
Started Sep 11 05:08:25 PM UTC 24
Finished Sep 11 05:08:31 PM UTC 24
Peak memory 235328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857946563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3857946563
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.1079177031
Short name T433
Test name
Test status
Simulation time 16228021 ps
CPU time 1 seconds
Started Sep 11 05:08:11 PM UTC 24
Finished Sep 11 05:08:13 PM UTC 24
Peak memory 215732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079177031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1079177031
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.4056997015
Short name T273
Test name
Test status
Simulation time 4871232913 ps
CPU time 26.51 seconds
Started Sep 11 05:08:31 PM UTC 24
Finished Sep 11 05:08:59 PM UTC 24
Peak memory 251844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056997015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.4056997015
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.2540091791
Short name T265
Test name
Test status
Simulation time 4053917522 ps
CPU time 43.46 seconds
Started Sep 11 05:08:31 PM UTC 24
Finished Sep 11 05:09:16 PM UTC 24
Peak memory 266376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540091791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2540091791
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.608083122
Short name T237
Test name
Test status
Simulation time 18880590321 ps
CPU time 125.24 seconds
Started Sep 11 05:08:32 PM UTC 24
Finished Sep 11 05:10:40 PM UTC 24
Peak memory 274408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608083122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.608083122
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.1806836843
Short name T258
Test name
Test status
Simulation time 127491394 ps
CPU time 5.36 seconds
Started Sep 11 05:08:25 PM UTC 24
Finished Sep 11 05:08:31 PM UTC 24
Peak memory 235328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806836843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1806836843
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.1656805822
Short name T191
Test name
Test status
Simulation time 1494600494 ps
CPU time 29.15 seconds
Started Sep 11 05:08:24 PM UTC 24
Finished Sep 11 05:08:54 PM UTC 24
Peak memory 235524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656805822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1656805822
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.494395841
Short name T240
Test name
Test status
Simulation time 2708447199 ps
CPU time 32.72 seconds
Started Sep 11 05:08:24 PM UTC 24
Finished Sep 11 05:08:58 PM UTC 24
Peak memory 249816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494395841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.494395841
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.3268260957
Short name T434
Test name
Test status
Simulation time 100876332 ps
CPU time 1.66 seconds
Started Sep 11 05:08:11 PM UTC 24
Finished Sep 11 05:08:14 PM UTC 24
Peak memory 229192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268260957 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mem_parity.3268260957
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.360678182
Short name T332
Test name
Test status
Simulation time 4494340200 ps
CPU time 13.74 seconds
Started Sep 11 05:08:21 PM UTC 24
Finished Sep 11 05:08:36 PM UTC 24
Peak memory 245768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360678182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.360678182
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.1804092074
Short name T310
Test name
Test status
Simulation time 227411714 ps
CPU time 6.01 seconds
Started Sep 11 05:08:17 PM UTC 24
Finished Sep 11 05:08:24 PM UTC 24
Peak memory 235520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804092074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1804092074
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.3893226873
Short name T440
Test name
Test status
Simulation time 1372009498 ps
CPU time 18.91 seconds
Started Sep 11 05:08:30 PM UTC 24
Finished Sep 11 05:08:50 PM UTC 24
Peak memory 231476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893226873 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.3893226873
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.3439216146
Short name T390
Test name
Test status
Simulation time 479707339 ps
CPU time 8.03 seconds
Started Sep 11 05:08:14 PM UTC 24
Finished Sep 11 05:08:23 PM UTC 24
Peak memory 227948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439216146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3439216146
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.3928652748
Short name T436
Test name
Test status
Simulation time 3907121633 ps
CPU time 16.24 seconds
Started Sep 11 05:08:12 PM UTC 24
Finished Sep 11 05:08:30 PM UTC 24
Peak memory 227880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928652748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3928652748
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.1385134659
Short name T401
Test name
Test status
Simulation time 23371782 ps
CPU time 1.83 seconds
Started Sep 11 05:08:17 PM UTC 24
Finished Sep 11 05:08:20 PM UTC 24
Peak memory 227972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385134659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1385134659
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3245962977
Short name T435
Test name
Test status
Simulation time 103263929 ps
CPU time 1.21 seconds
Started Sep 11 05:08:14 PM UTC 24
Finished Sep 11 05:08:16 PM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245962977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3245962977
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.1744513574
Short name T307
Test name
Test status
Simulation time 1328978807 ps
CPU time 5.38 seconds
Started Sep 11 05:08:24 PM UTC 24
Finished Sep 11 05:08:30 PM UTC 24
Peak memory 245564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744513574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1744513574
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/8.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.2211757565
Short name T443
Test name
Test status
Simulation time 23150542 ps
CPU time 1.1 seconds
Started Sep 11 05:09:08 PM UTC 24
Finished Sep 11 05:09:10 PM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211757565 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2211757565
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1044488558
Short name T110
Test name
Test status
Simulation time 2130839464 ps
CPU time 25.21 seconds
Started Sep 11 05:08:59 PM UTC 24
Finished Sep 11 05:09:25 PM UTC 24
Peak memory 245728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044488558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1044488558
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.1197297643
Short name T438
Test name
Test status
Simulation time 61883241 ps
CPU time 1.17 seconds
Started Sep 11 05:08:42 PM UTC 24
Finished Sep 11 05:08:44 PM UTC 24
Peak memory 215732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197297643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1197297643
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.488243670
Short name T278
Test name
Test status
Simulation time 9885787622 ps
CPU time 133.7 seconds
Started Sep 11 05:09:02 PM UTC 24
Finished Sep 11 05:11:18 PM UTC 24
Peak memory 268292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488243670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.488243670
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.3575652373
Short name T98
Test name
Test status
Simulation time 14756651633 ps
CPU time 172.97 seconds
Started Sep 11 05:09:05 PM UTC 24
Finished Sep 11 05:12:01 PM UTC 24
Peak memory 266232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575652373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3575652373
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2836264474
Short name T276
Test name
Test status
Simulation time 16831633147 ps
CPU time 161.54 seconds
Started Sep 11 05:09:06 PM UTC 24
Finished Sep 11 05:11:50 PM UTC 24
Peak memory 262152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836264474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.2836264474
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.3222310296
Short name T444
Test name
Test status
Simulation time 1417361002 ps
CPU time 11.46 seconds
Started Sep 11 05:09:00 PM UTC 24
Finished Sep 11 05:09:12 PM UTC 24
Peak memory 245596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222310296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3222310296
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.2556454330
Short name T234
Test name
Test status
Simulation time 19294897587 ps
CPU time 66.29 seconds
Started Sep 11 05:09:00 PM UTC 24
Finished Sep 11 05:10:08 PM UTC 24
Peak memory 262116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556454330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.2556454330
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.3598944390
Short name T294
Test name
Test status
Simulation time 2348967398 ps
CPU time 7.25 seconds
Started Sep 11 05:08:56 PM UTC 24
Finished Sep 11 05:09:05 PM UTC 24
Peak memory 245856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598944390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3598944390
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.4085701651
Short name T213
Test name
Test status
Simulation time 29866836087 ps
CPU time 67.77 seconds
Started Sep 11 05:08:57 PM UTC 24
Finished Sep 11 05:10:07 PM UTC 24
Peak memory 249816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085701651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4085701651
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.2594071650
Short name T439
Test name
Test status
Simulation time 31977689 ps
CPU time 1.61 seconds
Started Sep 11 05:08:45 PM UTC 24
Finished Sep 11 05:08:47 PM UTC 24
Peak memory 229192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594071650 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mem_parity.2594071650
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.896014592
Short name T236
Test name
Test status
Simulation time 7412592267 ps
CPU time 9.86 seconds
Started Sep 11 05:08:55 PM UTC 24
Finished Sep 11 05:09:06 PM UTC 24
Peak memory 245708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896014592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.896014592
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.1144778823
Short name T222
Test name
Test status
Simulation time 2435745420 ps
CPU time 10.6 seconds
Started Sep 11 05:08:55 PM UTC 24
Finished Sep 11 05:09:07 PM UTC 24
Peak memory 235396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144778823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1144778823
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.3088549264
Short name T449
Test name
Test status
Simulation time 1281934817 ps
CPU time 19.62 seconds
Started Sep 11 05:09:01 PM UTC 24
Finished Sep 11 05:09:22 PM UTC 24
Peak memory 231596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088549264 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.3088549264
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.2943602047
Short name T383
Test name
Test status
Simulation time 3727770778 ps
CPU time 11.5 seconds
Started Sep 11 05:08:48 PM UTC 24
Finished Sep 11 05:09:00 PM UTC 24
Peak memory 231980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943602047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2943602047
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.765482867
Short name T442
Test name
Test status
Simulation time 15667603986 ps
CPU time 11.05 seconds
Started Sep 11 05:08:47 PM UTC 24
Finished Sep 11 05:08:59 PM UTC 24
Peak memory 228016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765482867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.765482867
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.823471721
Short name T441
Test name
Test status
Simulation time 59649879 ps
CPU time 1.41 seconds
Started Sep 11 05:08:54 PM UTC 24
Finished Sep 11 05:08:56 PM UTC 24
Peak memory 227072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823471721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.823471721
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.246778290
Short name T428
Test name
Test status
Simulation time 80194561 ps
CPU time 1.2 seconds
Started Sep 11 05:08:51 PM UTC 24
Finished Sep 11 05:08:53 PM UTC 24
Peak memory 215912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246778290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.246778290
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.827440062
Short name T277
Test name
Test status
Simulation time 24064888348 ps
CPU time 50.95 seconds
Started Sep 11 05:08:57 PM UTC 24
Finished Sep 11 05:09:50 PM UTC 24
Peak memory 264264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827440062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.827440062
Directory /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%