| T478 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mailbox.2141879006 |
|
|
Sep 18 09:06:47 PM UTC 24 |
Sep 18 09:07:05 PM UTC 24 |
3493290602 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mem_parity.1112456312 |
|
|
Sep 18 09:07:03 PM UTC 24 |
Sep 18 09:07:06 PM UTC 24 |
16275045 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode.505227654 |
|
|
Sep 18 09:06:51 PM UTC 24 |
Sep 18 09:07:08 PM UTC 24 |
746241865 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.2769478563 |
|
|
Sep 18 09:07:06 PM UTC 24 |
Sep 18 09:07:08 PM UTC 24 |
44256061 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_rw.3981981282 |
|
|
Sep 18 09:07:07 PM UTC 24 |
Sep 18 09:07:11 PM UTC 24 |
324927832 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mailbox.1828452896 |
|
|
Sep 18 09:07:11 PM UTC 24 |
Sep 18 09:07:15 PM UTC 24 |
28550600 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.741818907 |
|
|
Sep 18 09:07:09 PM UTC 24 |
Sep 18 09:07:16 PM UTC 24 |
582479945 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1144941381 |
|
|
Sep 18 09:04:50 PM UTC 24 |
Sep 18 09:07:17 PM UTC 24 |
10414916350 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_intercept.579398254 |
|
|
Sep 18 09:07:09 PM UTC 24 |
Sep 18 09:07:17 PM UTC 24 |
177469494 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.3750581052 |
|
|
Sep 18 09:05:34 PM UTC 24 |
Sep 18 09:07:18 PM UTC 24 |
17952983061 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.2084038989 |
|
|
Sep 18 09:07:03 PM UTC 24 |
Sep 18 09:07:18 PM UTC 24 |
1108194048 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.593587008 |
|
|
Sep 18 09:06:43 PM UTC 24 |
Sep 18 09:07:19 PM UTC 24 |
11046775466 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.1742522379 |
|
|
Sep 18 09:07:08 PM UTC 24 |
Sep 18 09:07:20 PM UTC 24 |
1069032568 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.688673921 |
|
|
Sep 18 09:05:37 PM UTC 24 |
Sep 18 09:07:20 PM UTC 24 |
10232542196 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.3985431083 |
|
|
Sep 18 09:04:05 PM UTC 24 |
Sep 18 09:07:21 PM UTC 24 |
91142520575 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_cfg_cmd.127949068 |
|
|
Sep 18 09:07:17 PM UTC 24 |
Sep 18 09:07:22 PM UTC 24 |
188798707 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_upload.3670328934 |
|
|
Sep 18 09:06:47 PM UTC 24 |
Sep 18 09:07:22 PM UTC 24 |
27777660263 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.3591576223 |
|
|
Sep 18 09:05:19 PM UTC 24 |
Sep 18 09:07:23 PM UTC 24 |
37958327427 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_alert_test.754668675 |
|
|
Sep 18 09:07:22 PM UTC 24 |
Sep 18 09:07:24 PM UTC 24 |
26020774 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_csb_read.477478756 |
|
|
Sep 18 09:07:23 PM UTC 24 |
Sep 18 09:07:25 PM UTC 24 |
287186309 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mem_parity.2259159678 |
|
|
Sep 18 09:07:23 PM UTC 24 |
Sep 18 09:07:26 PM UTC 24 |
25983520 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.3412713999 |
|
|
Sep 18 09:07:18 PM UTC 24 |
Sep 18 09:07:26 PM UTC 24 |
404174474 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_all.762903717 |
|
|
Sep 18 09:07:25 PM UTC 24 |
Sep 18 09:07:28 PM UTC 24 |
35411960 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.2753703822 |
|
|
Sep 18 09:07:25 PM UTC 24 |
Sep 18 09:07:28 PM UTC 24 |
21341263 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_rw.3472187074 |
|
|
Sep 18 09:07:26 PM UTC 24 |
Sep 18 09:07:29 PM UTC 24 |
94191851 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_all.2216773643 |
|
|
Sep 18 09:07:05 PM UTC 24 |
Sep 18 09:07:30 PM UTC 24 |
6336089205 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.3060811240 |
|
|
Sep 18 09:02:42 PM UTC 24 |
Sep 18 09:07:30 PM UTC 24 |
48991868838 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_upload.3938774224 |
|
|
Sep 18 09:07:16 PM UTC 24 |
Sep 18 09:07:32 PM UTC 24 |
2846136642 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_intercept.4207570478 |
|
|
Sep 18 09:07:28 PM UTC 24 |
Sep 18 09:07:32 PM UTC 24 |
32357982 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.3718200076 |
|
|
Sep 18 09:06:14 PM UTC 24 |
Sep 18 09:07:33 PM UTC 24 |
3401192055 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_all.3834044948 |
|
|
Sep 18 09:06:31 PM UTC 24 |
Sep 18 09:07:33 PM UTC 24 |
3405132939 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode.1386775200 |
|
|
Sep 18 09:07:18 PM UTC 24 |
Sep 18 09:07:33 PM UTC 24 |
955066420 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.875102813 |
|
|
Sep 18 09:05:14 PM UTC 24 |
Sep 18 09:07:35 PM UTC 24 |
68627198226 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_cfg_cmd.236025871 |
|
|
Sep 18 09:07:31 PM UTC 24 |
Sep 18 09:07:35 PM UTC 24 |
535544658 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_upload.2457945885 |
|
|
Sep 18 09:07:31 PM UTC 24 |
Sep 18 09:07:37 PM UTC 24 |
248654979 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_alert_test.3722516295 |
|
|
Sep 18 09:07:35 PM UTC 24 |
Sep 18 09:07:38 PM UTC 24 |
12805902 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.1774614521 |
|
|
Sep 18 09:07:27 PM UTC 24 |
Sep 18 09:07:38 PM UTC 24 |
1242786809 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.632463828 |
|
|
Sep 18 09:06:32 PM UTC 24 |
Sep 18 09:07:38 PM UTC 24 |
29173948840 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mailbox.987805026 |
|
|
Sep 18 09:07:29 PM UTC 24 |
Sep 18 09:07:39 PM UTC 24 |
861502189 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.1819518240 |
|
|
Sep 18 09:07:26 PM UTC 24 |
Sep 18 09:07:40 PM UTC 24 |
431119133 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_csb_read.3499416369 |
|
|
Sep 18 09:07:38 PM UTC 24 |
Sep 18 09:07:40 PM UTC 24 |
25444891 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mem_parity.1073643913 |
|
|
Sep 18 09:07:38 PM UTC 24 |
Sep 18 09:07:40 PM UTC 24 |
100954898 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.4240742869 |
|
|
Sep 18 09:07:33 PM UTC 24 |
Sep 18 09:07:41 PM UTC 24 |
972968988 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.3082216945 |
|
|
Sep 18 09:07:39 PM UTC 24 |
Sep 18 09:07:41 PM UTC 24 |
123448079 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_rw.2321519799 |
|
|
Sep 18 09:07:40 PM UTC 24 |
Sep 18 09:07:44 PM UTC 24 |
52725943 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_cfg_cmd.1902401976 |
|
|
Sep 18 09:07:44 PM UTC 24 |
Sep 18 09:07:49 PM UTC 24 |
411596369 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_intercept.589107672 |
|
|
Sep 18 09:07:41 PM UTC 24 |
Sep 18 09:07:49 PM UTC 24 |
590837946 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.3361740116 |
|
|
Sep 18 09:07:24 PM UTC 24 |
Sep 18 09:07:50 PM UTC 24 |
20198767477 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.3381806416 |
|
|
Sep 18 09:07:39 PM UTC 24 |
Sep 18 09:07:50 PM UTC 24 |
3867394910 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.1033273906 |
|
|
Sep 18 09:07:33 PM UTC 24 |
Sep 18 09:07:51 PM UTC 24 |
17778501323 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.105700764 |
|
|
Sep 18 09:02:59 PM UTC 24 |
Sep 18 09:07:51 PM UTC 24 |
140899601865 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode.3870806029 |
|
|
Sep 18 09:07:31 PM UTC 24 |
Sep 18 09:07:52 PM UTC 24 |
1398184590 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_upload.3057706084 |
|
|
Sep 18 09:07:42 PM UTC 24 |
Sep 18 09:07:53 PM UTC 24 |
1319994373 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.2793915496 |
|
|
Sep 18 09:02:57 PM UTC 24 |
Sep 18 09:07:54 PM UTC 24 |
135866290346 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.3309604552 |
|
|
Sep 18 09:07:41 PM UTC 24 |
Sep 18 09:07:54 PM UTC 24 |
6421253810 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_alert_test.1975073366 |
|
|
Sep 18 09:07:53 PM UTC 24 |
Sep 18 09:07:55 PM UTC 24 |
37879187 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_csb_read.692036023 |
|
|
Sep 18 09:07:53 PM UTC 24 |
Sep 18 09:07:56 PM UTC 24 |
107228575 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.2831412948 |
|
|
Sep 18 09:07:51 PM UTC 24 |
Sep 18 09:07:57 PM UTC 24 |
779473831 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mem_parity.1843374037 |
|
|
Sep 18 09:07:55 PM UTC 24 |
Sep 18 09:07:57 PM UTC 24 |
26054295 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.355288843 |
|
|
Sep 18 09:07:57 PM UTC 24 |
Sep 18 09:07:59 PM UTC 24 |
104698998 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.1095103618 |
|
|
Sep 18 09:07:41 PM UTC 24 |
Sep 18 09:07:58 PM UTC 24 |
2057933518 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.965157872 |
|
|
Sep 18 09:06:09 PM UTC 24 |
Sep 18 09:07:58 PM UTC 24 |
6167525094 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_rw.1817534366 |
|
|
Sep 18 09:07:58 PM UTC 24 |
Sep 18 09:08:00 PM UTC 24 |
41442188 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.4207888761 |
|
|
Sep 18 09:06:57 PM UTC 24 |
Sep 18 09:08:01 PM UTC 24 |
10750349578 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.1895532918 |
|
|
Sep 18 09:07:55 PM UTC 24 |
Sep 18 09:08:02 PM UTC 24 |
1154638644 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode.3238295742 |
|
|
Sep 18 09:07:50 PM UTC 24 |
Sep 18 09:08:03 PM UTC 24 |
2877566559 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_intercept.2511638480 |
|
|
Sep 18 09:07:59 PM UTC 24 |
Sep 18 09:08:03 PM UTC 24 |
94840963 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.3672088757 |
|
|
Sep 18 09:07:34 PM UTC 24 |
Sep 18 09:08:07 PM UTC 24 |
5247530706 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mailbox.3671230108 |
|
|
Sep 18 09:07:42 PM UTC 24 |
Sep 18 09:08:10 PM UTC 24 |
11915610231 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_all.876111877 |
|
|
Sep 18 09:07:34 PM UTC 24 |
Sep 18 09:08:15 PM UTC 24 |
2019417841 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_cfg_cmd.2358922409 |
|
|
Sep 18 09:08:02 PM UTC 24 |
Sep 18 09:08:17 PM UTC 24 |
2439321803 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.474641157 |
|
|
Sep 18 09:03:40 PM UTC 24 |
Sep 18 09:08:17 PM UTC 24 |
26300464706 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_all.2407359492 |
|
|
Sep 18 09:07:57 PM UTC 24 |
Sep 18 09:08:18 PM UTC 24 |
1908931381 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.2125034444 |
|
|
Sep 18 09:07:59 PM UTC 24 |
Sep 18 09:08:18 PM UTC 24 |
11515156998 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_all.724068580 |
|
|
Sep 18 09:07:39 PM UTC 24 |
Sep 18 09:08:20 PM UTC 24 |
15638347694 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_alert_test.3562414557 |
|
|
Sep 18 09:08:18 PM UTC 24 |
Sep 18 09:08:20 PM UTC 24 |
12802544 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_csb_read.1807105997 |
|
|
Sep 18 09:08:18 PM UTC 24 |
Sep 18 09:08:20 PM UTC 24 |
71385942 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_upload.758152014 |
|
|
Sep 18 09:08:01 PM UTC 24 |
Sep 18 09:08:21 PM UTC 24 |
8434819523 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mem_parity.1370460409 |
|
|
Sep 18 09:08:19 PM UTC 24 |
Sep 18 09:08:22 PM UTC 24 |
40680318 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mailbox.405796354 |
|
|
Sep 18 09:08:00 PM UTC 24 |
Sep 18 09:08:23 PM UTC 24 |
833448582 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.1980215894 |
|
|
Sep 18 09:08:22 PM UTC 24 |
Sep 18 09:08:24 PM UTC 24 |
92920914 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_rw.2565707167 |
|
|
Sep 18 09:08:22 PM UTC 24 |
Sep 18 09:08:25 PM UTC 24 |
132494362 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.108020254 |
|
|
Sep 18 09:08:20 PM UTC 24 |
Sep 18 09:08:26 PM UTC 24 |
527810348 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.660141141 |
|
|
Sep 18 09:08:04 PM UTC 24 |
Sep 18 09:08:26 PM UTC 24 |
3366314151 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_alert_test.705653855 |
|
|
Sep 18 09:09:26 PM UTC 24 |
Sep 18 09:09:28 PM UTC 24 |
185072353 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.1737737479 |
|
|
Sep 18 09:05:37 PM UTC 24 |
Sep 18 09:08:26 PM UTC 24 |
38503516796 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.1534439509 |
|
|
Sep 18 09:04:50 PM UTC 24 |
Sep 18 09:08:29 PM UTC 24 |
19516692727 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_all.1819611973 |
|
|
Sep 18 09:08:22 PM UTC 24 |
Sep 18 09:08:29 PM UTC 24 |
1889079892 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_upload.2144989857 |
|
|
Sep 18 09:08:26 PM UTC 24 |
Sep 18 09:08:31 PM UTC 24 |
193582810 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_intercept.18580165 |
|
|
Sep 18 09:08:25 PM UTC 24 |
Sep 18 09:08:31 PM UTC 24 |
421997850 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_cfg_cmd.1957275982 |
|
|
Sep 18 09:08:26 PM UTC 24 |
Sep 18 09:08:32 PM UTC 24 |
495707040 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.3264233734 |
|
|
Sep 18 09:08:24 PM UTC 24 |
Sep 18 09:08:34 PM UTC 24 |
2335729981 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_all.1424569873 |
|
|
Sep 18 09:08:08 PM UTC 24 |
Sep 18 09:08:35 PM UTC 24 |
15535400492 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.2589988459 |
|
|
Sep 18 09:07:22 PM UTC 24 |
Sep 18 09:08:37 PM UTC 24 |
8580112639 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_upload.467699854 |
|
|
Sep 18 09:09:11 PM UTC 24 |
Sep 18 09:09:28 PM UTC 24 |
9645217341 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.3612200748 |
|
|
Sep 18 09:08:35 PM UTC 24 |
Sep 18 09:08:38 PM UTC 24 |
86577930 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_alert_test.1841954741 |
|
|
Sep 18 09:08:36 PM UTC 24 |
Sep 18 09:08:38 PM UTC 24 |
40969714 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.1258393531 |
|
|
Sep 18 09:08:30 PM UTC 24 |
Sep 18 09:08:38 PM UTC 24 |
1127977622 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_csb_read.2716606309 |
|
|
Sep 18 09:08:38 PM UTC 24 |
Sep 18 09:08:40 PM UTC 24 |
20904783 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mem_parity.2591029267 |
|
|
Sep 18 09:08:38 PM UTC 24 |
Sep 18 09:08:41 PM UTC 24 |
46659743 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.570738595 |
|
|
Sep 18 09:07:52 PM UTC 24 |
Sep 18 09:08:42 PM UTC 24 |
8274309093 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode.2244368787 |
|
|
Sep 18 09:09:12 PM UTC 24 |
Sep 18 09:09:31 PM UTC 24 |
870453200 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mailbox.3535923042 |
|
|
Sep 18 09:08:26 PM UTC 24 |
Sep 18 09:08:43 PM UTC 24 |
2029786298 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.3379865292 |
|
|
Sep 18 09:08:41 PM UTC 24 |
Sep 18 09:08:44 PM UTC 24 |
42211182 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_rw.2862198930 |
|
|
Sep 18 09:08:42 PM UTC 24 |
Sep 18 09:08:44 PM UTC 24 |
26479582 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode.2819128618 |
|
|
Sep 18 09:08:27 PM UTC 24 |
Sep 18 09:08:45 PM UTC 24 |
4769480269 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.3516325958 |
|
|
Sep 18 09:07:58 PM UTC 24 |
Sep 18 09:08:46 PM UTC 24 |
153779963681 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.3433881894 |
|
|
Sep 18 09:08:30 PM UTC 24 |
Sep 18 09:08:47 PM UTC 24 |
6792118859 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.3411676981 |
|
|
Sep 18 09:08:39 PM UTC 24 |
Sep 18 09:08:47 PM UTC 24 |
4350254918 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.1263950177 |
|
|
Sep 18 09:08:43 PM UTC 24 |
Sep 18 09:08:49 PM UTC 24 |
2130891098 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_cfg_cmd.343737702 |
|
|
Sep 18 09:08:46 PM UTC 24 |
Sep 18 09:08:53 PM UTC 24 |
410537704 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mailbox.4286471951 |
|
|
Sep 18 09:08:45 PM UTC 24 |
Sep 18 09:08:54 PM UTC 24 |
449420463 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_upload.260842063 |
|
|
Sep 18 09:08:46 PM UTC 24 |
Sep 18 09:08:57 PM UTC 24 |
331626600 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.1069453265 |
|
|
Sep 18 09:08:44 PM UTC 24 |
Sep 18 09:09:02 PM UTC 24 |
6020810191 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.1573735181 |
|
|
Sep 18 09:08:23 PM UTC 24 |
Sep 18 09:09:03 PM UTC 24 |
6249017543 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.187014894 |
|
|
Sep 18 09:05:38 PM UTC 24 |
Sep 18 09:09:03 PM UTC 24 |
19137209665 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_all.3486652702 |
|
|
Sep 18 09:07:52 PM UTC 24 |
Sep 18 09:09:04 PM UTC 24 |
47415992133 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.606781449 |
|
|
Sep 18 09:05:55 PM UTC 24 |
Sep 18 09:09:06 PM UTC 24 |
81695004897 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.2079830054 |
|
|
Sep 18 09:07:50 PM UTC 24 |
Sep 18 09:09:06 PM UTC 24 |
2230765825 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_csb_read.4130487428 |
|
|
Sep 18 09:09:04 PM UTC 24 |
Sep 18 09:09:06 PM UTC 24 |
13433139 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_alert_test.3581180048 |
|
|
Sep 18 09:09:04 PM UTC 24 |
Sep 18 09:09:06 PM UTC 24 |
83140097 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode.2774963333 |
|
|
Sep 18 09:08:04 PM UTC 24 |
Sep 18 09:09:06 PM UTC 24 |
2683742076 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.2413926 |
|
|
Sep 18 09:08:50 PM UTC 24 |
Sep 18 09:09:08 PM UTC 24 |
2403817985 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.1806860885 |
|
|
Sep 18 09:08:58 PM UTC 24 |
Sep 18 09:09:08 PM UTC 24 |
1345527510 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.2680732338 |
|
|
Sep 18 09:09:07 PM UTC 24 |
Sep 18 09:09:10 PM UTC 24 |
158789395 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.3267574769 |
|
|
Sep 18 09:09:05 PM UTC 24 |
Sep 18 09:09:11 PM UTC 24 |
1087010761 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_intercept.2227986164 |
|
|
Sep 18 09:08:45 PM UTC 24 |
Sep 18 09:09:11 PM UTC 24 |
2726509443 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode.4129103305 |
|
|
Sep 18 09:08:48 PM UTC 24 |
Sep 18 09:09:14 PM UTC 24 |
6710881267 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_cfg_cmd.1694099924 |
|
|
Sep 18 09:09:12 PM UTC 24 |
Sep 18 09:09:16 PM UTC 24 |
137027664 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_rw.3750412752 |
|
|
Sep 18 09:09:07 PM UTC 24 |
Sep 18 09:09:17 PM UTC 24 |
422829047 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_all.4272542358 |
|
|
Sep 18 09:08:39 PM UTC 24 |
Sep 18 09:09:20 PM UTC 24 |
34556245218 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_all.3251856561 |
|
|
Sep 18 09:08:32 PM UTC 24 |
Sep 18 09:09:21 PM UTC 24 |
12094495919 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.2675145735 |
|
|
Sep 18 09:09:17 PM UTC 24 |
Sep 18 09:09:23 PM UTC 24 |
654878889 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_intercept.2201773415 |
|
|
Sep 18 09:09:09 PM UTC 24 |
Sep 18 09:09:25 PM UTC 24 |
1021645462 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.3066325237 |
|
|
Sep 18 09:08:16 PM UTC 24 |
Sep 18 09:09:26 PM UTC 24 |
10889312959 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.511490497 |
|
|
Sep 18 09:05:15 PM UTC 24 |
Sep 18 09:09:26 PM UTC 24 |
92632477366 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_csb_read.334455291 |
|
|
Sep 18 09:09:28 PM UTC 24 |
Sep 18 09:09:30 PM UTC 24 |
26321203 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.1387192063 |
|
|
Sep 18 09:09:28 PM UTC 24 |
Sep 18 09:09:31 PM UTC 24 |
92630317 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.565960831 |
|
|
Sep 18 09:09:29 PM UTC 24 |
Sep 18 09:09:32 PM UTC 24 |
24235491 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.343071720 |
|
|
Sep 18 09:09:07 PM UTC 24 |
Sep 18 09:09:33 PM UTC 24 |
4164489749 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_all.565151005 |
|
|
Sep 18 09:09:06 PM UTC 24 |
Sep 18 09:09:34 PM UTC 24 |
17983081835 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.3816700075 |
|
|
Sep 18 09:06:58 PM UTC 24 |
Sep 18 09:09:36 PM UTC 24 |
93539640069 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_rw.573093890 |
|
|
Sep 18 09:09:31 PM UTC 24 |
Sep 18 09:09:36 PM UTC 24 |
101480067 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_all.2215744818 |
|
|
Sep 18 09:07:20 PM UTC 24 |
Sep 18 09:09:38 PM UTC 24 |
9614858812 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_intercept.1558366415 |
|
|
Sep 18 09:09:33 PM UTC 24 |
Sep 18 09:09:39 PM UTC 24 |
190873583 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_all.3499039046 |
|
|
Sep 18 09:09:29 PM UTC 24 |
Sep 18 09:09:40 PM UTC 24 |
2414571338 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.4246103487 |
|
|
Sep 18 09:06:15 PM UTC 24 |
Sep 18 09:09:41 PM UTC 24 |
15126100935 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.3297136462 |
|
|
Sep 18 09:06:59 PM UTC 24 |
Sep 18 09:09:41 PM UTC 24 |
19337298546 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_cfg_cmd.1131982750 |
|
|
Sep 18 09:09:37 PM UTC 24 |
Sep 18 09:09:42 PM UTC 24 |
753569561 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode.2747813000 |
|
|
Sep 18 09:09:38 PM UTC 24 |
Sep 18 09:09:43 PM UTC 24 |
714863558 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_mailbox.792443281 |
|
|
Sep 18 09:09:34 PM UTC 24 |
Sep 18 09:09:43 PM UTC 24 |
1350430253 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_upload.3547041640 |
|
|
Sep 18 09:09:35 PM UTC 24 |
Sep 18 09:09:43 PM UTC 24 |
267666202 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_all.4201657391 |
|
|
Sep 18 09:09:41 PM UTC 24 |
Sep 18 09:09:43 PM UTC 24 |
12865324 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.2279274794 |
|
|
Sep 18 09:09:32 PM UTC 24 |
Sep 18 09:09:44 PM UTC 24 |
665345720 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_stress_all.2397264865 |
|
|
Sep 18 09:09:42 PM UTC 24 |
Sep 18 09:09:45 PM UTC 24 |
96257101 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_all.1040641687 |
|
|
Sep 18 09:08:54 PM UTC 24 |
Sep 18 09:09:46 PM UTC 24 |
3264327700 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_alert_test.3546030612 |
|
|
Sep 18 09:09:43 PM UTC 24 |
Sep 18 09:09:46 PM UTC 24 |
39462610 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.231772104 |
|
|
Sep 18 09:07:18 PM UTC 24 |
Sep 18 09:09:46 PM UTC 24 |
137640126343 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_csb_read.1098746260 |
|
|
Sep 18 09:09:45 PM UTC 24 |
Sep 18 09:09:47 PM UTC 24 |
20174680 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.4219143535 |
|
|
Sep 18 09:09:07 PM UTC 24 |
Sep 18 09:09:48 PM UTC 24 |
30723280956 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.1635978675 |
|
|
Sep 18 09:09:46 PM UTC 24 |
Sep 18 09:09:48 PM UTC 24 |
59712416 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_rw.2775052053 |
|
|
Sep 18 09:09:46 PM UTC 24 |
Sep 18 09:09:48 PM UTC 24 |
34842990 ps |
| T42 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.2847776465 |
|
|
Sep 18 09:02:47 PM UTC 24 |
Sep 18 09:09:51 PM UTC 24 |
160551521543 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_mailbox.3487670151 |
|
|
Sep 18 09:09:10 PM UTC 24 |
Sep 18 09:09:51 PM UTC 24 |
2690772903 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_intercept.3772315555 |
|
|
Sep 18 09:09:47 PM UTC 24 |
Sep 18 09:09:52 PM UTC 24 |
120980738 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_cfg_cmd.876726582 |
|
|
Sep 18 09:09:49 PM UTC 24 |
Sep 18 09:09:54 PM UTC 24 |
265949942 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.1485157895 |
|
|
Sep 18 09:09:52 PM UTC 24 |
Sep 18 09:09:56 PM UTC 24 |
1342264208 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.3084644553 |
|
|
Sep 18 09:09:40 PM UTC 24 |
Sep 18 09:09:58 PM UTC 24 |
1257937772 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.748155427 |
|
|
Sep 18 09:09:47 PM UTC 24 |
Sep 18 09:09:59 PM UTC 24 |
641739888 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.3963872709 |
|
|
Sep 18 09:09:47 PM UTC 24 |
Sep 18 09:10:00 PM UTC 24 |
1596580753 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.1380518704 |
|
|
Sep 18 09:09:32 PM UTC 24 |
Sep 18 09:10:00 PM UTC 24 |
19659824196 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.1800920872 |
|
|
Sep 18 09:09:21 PM UTC 24 |
Sep 18 09:10:01 PM UTC 24 |
8990252016 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_alert_test.478679495 |
|
|
Sep 18 09:10:01 PM UTC 24 |
Sep 18 09:10:03 PM UTC 24 |
48462783 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_csb_read.279403541 |
|
|
Sep 18 09:10:01 PM UTC 24 |
Sep 18 09:10:03 PM UTC 24 |
53789068 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.718420277 |
|
|
Sep 18 09:10:03 PM UTC 24 |
Sep 18 09:10:05 PM UTC 24 |
33844471 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_mailbox.458697318 |
|
|
Sep 18 09:09:48 PM UTC 24 |
Sep 18 09:10:06 PM UTC 24 |
1054236671 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_stress_all.2566472424 |
|
|
Sep 18 09:08:18 PM UTC 24 |
Sep 18 09:10:06 PM UTC 24 |
53700313405 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_rw.3105736375 |
|
|
Sep 18 09:10:04 PM UTC 24 |
Sep 18 09:10:08 PM UTC 24 |
83771489 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.2987717639 |
|
|
Sep 18 09:09:45 PM UTC 24 |
Sep 18 09:10:09 PM UTC 24 |
32136249680 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.577743117 |
|
|
Sep 18 09:08:33 PM UTC 24 |
Sep 18 09:10:10 PM UTC 24 |
65127027298 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.590081242 |
|
|
Sep 18 09:08:54 PM UTC 24 |
Sep 18 09:10:10 PM UTC 24 |
21940424417 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.3303160458 |
|
|
Sep 18 09:09:41 PM UTC 24 |
Sep 18 09:10:12 PM UTC 24 |
6651860367 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.468981222 |
|
|
Sep 18 09:10:07 PM UTC 24 |
Sep 18 09:10:14 PM UTC 24 |
1298900679 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.1905218276 |
|
|
Sep 18 09:07:34 PM UTC 24 |
Sep 18 09:10:15 PM UTC 24 |
30040508565 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_alert_test.4038378165 |
|
|
Sep 18 09:10:33 PM UTC 24 |
Sep 18 09:10:35 PM UTC 24 |
37806601 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_upload.3769532054 |
|
|
Sep 18 09:09:48 PM UTC 24 |
Sep 18 09:10:15 PM UTC 24 |
5173802358 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.23812309 |
|
|
Sep 18 09:10:07 PM UTC 24 |
Sep 18 09:10:16 PM UTC 24 |
490826090 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_all.2246589109 |
|
|
Sep 18 09:09:45 PM UTC 24 |
Sep 18 09:10:17 PM UTC 24 |
52151650750 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_intercept.1785224739 |
|
|
Sep 18 09:10:07 PM UTC 24 |
Sep 18 09:10:18 PM UTC 24 |
725241849 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.1634567074 |
|
|
Sep 18 09:09:39 PM UTC 24 |
Sep 18 09:10:19 PM UTC 24 |
3984662235 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.2113654247 |
|
|
Sep 18 09:06:12 PM UTC 24 |
Sep 18 09:10:20 PM UTC 24 |
124788509933 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode.3462834117 |
|
|
Sep 18 09:10:11 PM UTC 24 |
Sep 18 09:10:20 PM UTC 24 |
289872457 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.166595895 |
|
|
Sep 18 09:10:18 PM UTC 24 |
Sep 18 09:10:20 PM UTC 24 |
37485801 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.2791389565 |
|
|
Sep 18 09:08:48 PM UTC 24 |
Sep 18 09:10:21 PM UTC 24 |
12074965887 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_alert_test.4258256391 |
|
|
Sep 18 09:10:19 PM UTC 24 |
Sep 18 09:10:22 PM UTC 24 |
14884573 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_cfg_cmd.1671460433 |
|
|
Sep 18 09:10:11 PM UTC 24 |
Sep 18 09:10:22 PM UTC 24 |
3559141000 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_csb_read.1340895154 |
|
|
Sep 18 09:10:21 PM UTC 24 |
Sep 18 09:10:23 PM UTC 24 |
20545604 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.2633485536 |
|
|
Sep 18 09:10:15 PM UTC 24 |
Sep 18 09:10:23 PM UTC 24 |
480977657 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.2049959370 |
|
|
Sep 18 09:10:22 PM UTC 24 |
Sep 18 09:10:25 PM UTC 24 |
114343216 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_upload.485222875 |
|
|
Sep 18 09:10:10 PM UTC 24 |
Sep 18 09:10:25 PM UTC 24 |
3090088680 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.629023285 |
|
|
Sep 18 09:06:36 PM UTC 24 |
Sep 18 09:10:26 PM UTC 24 |
18371970503 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.2473754370 |
|
|
Sep 18 09:10:22 PM UTC 24 |
Sep 18 09:10:27 PM UTC 24 |
109693853 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.3332766990 |
|
|
Sep 18 09:10:01 PM UTC 24 |
Sep 18 09:10:27 PM UTC 24 |
12704813026 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_all.3843630165 |
|
|
Sep 18 09:10:22 PM UTC 24 |
Sep 18 09:10:28 PM UTC 24 |
303214713 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.2403180208 |
|
|
Sep 18 09:10:21 PM UTC 24 |
Sep 18 09:10:29 PM UTC 24 |
777408611 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode.2030765273 |
|
|
Sep 18 09:09:49 PM UTC 24 |
Sep 18 09:10:31 PM UTC 24 |
18938371780 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_rw.2004631456 |
|
|
Sep 18 09:10:22 PM UTC 24 |
Sep 18 09:10:32 PM UTC 24 |
535717239 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_cfg_cmd.4061395062 |
|
|
Sep 18 09:10:26 PM UTC 24 |
Sep 18 09:10:33 PM UTC 24 |
189799753 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_all.567314372 |
|
|
Sep 18 09:10:02 PM UTC 24 |
Sep 18 09:10:33 PM UTC 24 |
4992813645 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.4089989024 |
|
|
Sep 18 09:04:05 PM UTC 24 |
Sep 18 09:10:33 PM UTC 24 |
199301576141 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.3414121908 |
|
|
Sep 18 09:10:27 PM UTC 24 |
Sep 18 09:10:33 PM UTC 24 |
162590148 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.931721560 |
|
|
Sep 18 09:10:23 PM UTC 24 |
Sep 18 09:10:34 PM UTC 24 |
1278997901 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_upload.3556406714 |
|
|
Sep 18 09:10:26 PM UTC 24 |
Sep 18 09:10:37 PM UTC 24 |
8180756995 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_csb_read.3640317767 |
|
|
Sep 18 09:10:35 PM UTC 24 |
Sep 18 09:10:37 PM UTC 24 |
15497475 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.2205508655 |
|
|
Sep 18 09:10:35 PM UTC 24 |
Sep 18 09:10:37 PM UTC 24 |
160729887 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.1052314881 |
|
|
Sep 18 09:10:35 PM UTC 24 |
Sep 18 09:10:38 PM UTC 24 |
233633635 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_rw.3340756601 |
|
|
Sep 18 09:10:36 PM UTC 24 |
Sep 18 09:10:40 PM UTC 24 |
353614146 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_mailbox.2697911813 |
|
|
Sep 18 09:10:09 PM UTC 24 |
Sep 18 09:10:41 PM UTC 24 |
14922890263 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.2716768265 |
|
|
Sep 18 09:10:29 PM UTC 24 |
Sep 18 09:10:41 PM UTC 24 |
1718013011 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.2268125821 |
|
|
Sep 18 09:10:38 PM UTC 24 |
Sep 18 09:10:42 PM UTC 24 |
94766589 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_intercept.1221171542 |
|
|
Sep 18 09:10:38 PM UTC 24 |
Sep 18 09:10:44 PM UTC 24 |
237647305 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.1865664165 |
|
|
Sep 18 09:10:38 PM UTC 24 |
Sep 18 09:10:44 PM UTC 24 |
178075467 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.2950552720 |
|
|
Sep 18 09:10:43 PM UTC 24 |
Sep 18 09:10:45 PM UTC 24 |
11301903 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_intercept.3377060008 |
|
|
Sep 18 09:10:25 PM UTC 24 |
Sep 18 09:10:45 PM UTC 24 |
1416847823 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.1874349457 |
|
|
Sep 18 09:07:20 PM UTC 24 |
Sep 18 09:10:49 PM UTC 24 |
23274936086 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_alert_test.2983106528 |
|
|
Sep 18 09:10:50 PM UTC 24 |
Sep 18 09:10:52 PM UTC 24 |
40463882 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_all.284238750 |
|
|
Sep 18 09:10:35 PM UTC 24 |
Sep 18 09:10:53 PM UTC 24 |
13657387760 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.3591215996 |
|
|
Sep 18 09:09:52 PM UTC 24 |
Sep 18 09:10:53 PM UTC 24 |
4257437570 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode.2395131521 |
|
|
Sep 18 09:10:43 PM UTC 24 |
Sep 18 09:10:53 PM UTC 24 |
984923846 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_csb_read.2195917030 |
|
|
Sep 18 09:10:53 PM UTC 24 |
Sep 18 09:10:55 PM UTC 24 |
23869552 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_cfg_cmd.4210102601 |
|
|
Sep 18 09:10:43 PM UTC 24 |
Sep 18 09:10:56 PM UTC 24 |
976146845 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.3935641356 |
|
|
Sep 18 09:10:55 PM UTC 24 |
Sep 18 09:10:57 PM UTC 24 |
43630133 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_rw.2383201698 |
|
|
Sep 18 09:10:56 PM UTC 24 |
Sep 18 09:10:58 PM UTC 24 |
13149387 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.478489323 |
|
|
Sep 18 09:08:32 PM UTC 24 |
Sep 18 09:11:01 PM UTC 24 |
50551049667 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.3414375037 |
|
|
Sep 18 09:10:27 PM UTC 24 |
Sep 18 09:11:01 PM UTC 24 |
7550808741 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.1651821908 |
|
|
Sep 18 09:10:57 PM UTC 24 |
Sep 18 09:11:01 PM UTC 24 |
51598122 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_all.4156378445 |
|
|
Sep 18 09:09:53 PM UTC 24 |
Sep 18 09:11:02 PM UTC 24 |
5181157317 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.837428618 |
|
|
Sep 18 09:10:58 PM UTC 24 |
Sep 18 09:11:03 PM UTC 24 |
745914662 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_all.1555880028 |
|
|
Sep 18 09:10:54 PM UTC 24 |
Sep 18 09:11:03 PM UTC 24 |
788898278 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.3929339324 |
|
|
Sep 18 09:10:45 PM UTC 24 |
Sep 18 09:11:03 PM UTC 24 |
1965391901 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.3707749543 |
|
|
Sep 18 09:06:58 PM UTC 24 |
Sep 18 09:11:04 PM UTC 24 |
161940916028 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.3843224715 |
|
|
Sep 18 09:09:41 PM UTC 24 |
Sep 18 09:11:06 PM UTC 24 |
4460778471 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_cfg_cmd.3780173798 |
|
|
Sep 18 09:11:02 PM UTC 24 |
Sep 18 09:11:06 PM UTC 24 |
443428696 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.3120440751 |
|
|
Sep 18 09:10:47 PM UTC 24 |
Sep 18 09:11:07 PM UTC 24 |
2635180292 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_upload.327499418 |
|
|
Sep 18 09:10:41 PM UTC 24 |
Sep 18 09:11:07 PM UTC 24 |
11420364103 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_alert_test.3374691301 |
|
|
Sep 18 09:11:07 PM UTC 24 |
Sep 18 09:11:10 PM UTC 24 |
37299606 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.4018769425 |
|
|
Sep 18 09:09:15 PM UTC 24 |
Sep 18 09:11:10 PM UTC 24 |
51612073791 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_csb_read.2587265442 |
|
|
Sep 18 09:11:09 PM UTC 24 |
Sep 18 09:11:11 PM UTC 24 |
17918120 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_mailbox.1614051253 |
|
|
Sep 18 09:11:02 PM UTC 24 |
Sep 18 09:11:11 PM UTC 24 |
657338414 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.784007088 |
|
|
Sep 18 09:11:05 PM UTC 24 |
Sep 18 09:11:12 PM UTC 24 |
1475121524 ps |