| T369 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.744987422 |
|
|
Sep 18 09:14:54 PM UTC 24 |
Sep 18 09:16:35 PM UTC 24 |
12394426862 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.1155576436 |
|
|
Sep 18 09:16:26 PM UTC 24 |
Sep 18 09:16:36 PM UTC 24 |
1388978767 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.1597097244 |
|
|
Sep 18 09:16:31 PM UTC 24 |
Sep 18 09:16:38 PM UTC 24 |
1246351524 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.3314657156 |
|
|
Sep 18 09:14:57 PM UTC 24 |
Sep 18 09:16:39 PM UTC 24 |
11235918082 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_cfg_cmd.1860880130 |
|
|
Sep 18 09:16:35 PM UTC 24 |
Sep 18 09:16:39 PM UTC 24 |
108908416 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.2727356857 |
|
|
Sep 18 09:16:31 PM UTC 24 |
Sep 18 09:16:51 PM UTC 24 |
20938247696 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.4191585491 |
|
|
Sep 18 09:11:05 PM UTC 24 |
Sep 18 09:16:40 PM UTC 24 |
42828813821 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.59732378 |
|
|
Sep 18 09:15:36 PM UTC 24 |
Sep 18 09:16:40 PM UTC 24 |
22130257037 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.2746978180 |
|
|
Sep 18 09:16:32 PM UTC 24 |
Sep 18 09:16:41 PM UTC 24 |
288003672 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.1893403123 |
|
|
Sep 18 09:16:39 PM UTC 24 |
Sep 18 09:16:42 PM UTC 24 |
219551063 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.4155033449 |
|
|
Sep 18 09:16:42 PM UTC 24 |
Sep 18 09:16:44 PM UTC 24 |
14734327 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.2382966613 |
|
|
Sep 18 09:16:42 PM UTC 24 |
Sep 18 09:16:45 PM UTC 24 |
88337236 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.18264737 |
|
|
Sep 18 09:16:43 PM UTC 24 |
Sep 18 09:16:46 PM UTC 24 |
19854748 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.1900349758 |
|
|
Sep 18 09:16:34 PM UTC 24 |
Sep 18 09:16:47 PM UTC 24 |
10614337097 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.2455940188 |
|
|
Sep 18 09:16:09 PM UTC 24 |
Sep 18 09:16:48 PM UTC 24 |
8244223143 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.63265835 |
|
|
Sep 18 09:16:46 PM UTC 24 |
Sep 18 09:16:48 PM UTC 24 |
87541840 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.1161876391 |
|
|
Sep 18 09:16:36 PM UTC 24 |
Sep 18 09:16:49 PM UTC 24 |
542901434 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.2774490582 |
|
|
Sep 18 09:15:12 PM UTC 24 |
Sep 18 09:16:50 PM UTC 24 |
3233935815 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_intercept.495840837 |
|
|
Sep 18 09:16:31 PM UTC 24 |
Sep 18 09:16:50 PM UTC 24 |
4248470714 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.3190690631 |
|
|
Sep 18 09:16:46 PM UTC 24 |
Sep 18 09:16:51 PM UTC 24 |
79713994 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.3201248534 |
|
|
Sep 18 09:05:57 PM UTC 24 |
Sep 18 09:16:53 PM UTC 24 |
268877007825 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.2195005208 |
|
|
Sep 18 09:16:44 PM UTC 24 |
Sep 18 09:16:54 PM UTC 24 |
1029513371 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.1284131710 |
|
|
Sep 18 09:16:49 PM UTC 24 |
Sep 18 09:16:54 PM UTC 24 |
668389975 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.236314571 |
|
|
Sep 18 09:15:14 PM UTC 24 |
Sep 18 09:16:54 PM UTC 24 |
79280429558 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.751975021 |
|
|
Sep 18 09:16:50 PM UTC 24 |
Sep 18 09:16:54 PM UTC 24 |
343729628 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.3033838012 |
|
|
Sep 18 09:16:38 PM UTC 24 |
Sep 18 09:16:55 PM UTC 24 |
2687211066 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.149502734 |
|
|
Sep 18 09:16:51 PM UTC 24 |
Sep 18 09:16:56 PM UTC 24 |
119538000 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.1661162742 |
|
|
Sep 18 09:16:47 PM UTC 24 |
Sep 18 09:16:57 PM UTC 24 |
2674240750 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.1228099299 |
|
|
Sep 18 09:16:56 PM UTC 24 |
Sep 18 09:16:58 PM UTC 24 |
14981559 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.3329809382 |
|
|
Sep 18 09:16:56 PM UTC 24 |
Sep 18 09:16:58 PM UTC 24 |
49775032 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.2178247080 |
|
|
Sep 18 09:16:56 PM UTC 24 |
Sep 18 09:16:58 PM UTC 24 |
70790914 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.2562243546 |
|
|
Sep 18 09:16:51 PM UTC 24 |
Sep 18 09:16:59 PM UTC 24 |
420026635 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3892974375 |
|
|
Sep 18 09:16:53 PM UTC 24 |
Sep 18 09:17:00 PM UTC 24 |
919816504 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.3955899088 |
|
|
Sep 18 09:16:59 PM UTC 24 |
Sep 18 09:17:01 PM UTC 24 |
103091309 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.550206386 |
|
|
Sep 18 09:16:59 PM UTC 24 |
Sep 18 09:17:02 PM UTC 24 |
45880148 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.2498681916 |
|
|
Sep 18 09:16:50 PM UTC 24 |
Sep 18 09:17:05 PM UTC 24 |
2234000029 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.1525726748 |
|
|
Sep 18 09:17:00 PM UTC 24 |
Sep 18 09:17:06 PM UTC 24 |
1184040253 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.299336457 |
|
|
Sep 18 09:16:26 PM UTC 24 |
Sep 18 09:17:06 PM UTC 24 |
2692841547 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.1577036739 |
|
|
Sep 18 09:17:00 PM UTC 24 |
Sep 18 09:17:06 PM UTC 24 |
2014524696 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.2828332093 |
|
|
Sep 18 09:17:00 PM UTC 24 |
Sep 18 09:17:08 PM UTC 24 |
793193314 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.3274599517 |
|
|
Sep 18 09:16:57 PM UTC 24 |
Sep 18 09:17:09 PM UTC 24 |
991242640 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.2362473516 |
|
|
Sep 18 09:17:49 PM UTC 24 |
Sep 18 09:17:54 PM UTC 24 |
528368117 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.4079752226 |
|
|
Sep 18 09:14:43 PM UTC 24 |
Sep 18 09:17:09 PM UTC 24 |
41088774102 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.2506207291 |
|
|
Sep 18 09:17:03 PM UTC 24 |
Sep 18 09:17:11 PM UTC 24 |
382449541 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.3855993714 |
|
|
Sep 18 09:17:02 PM UTC 24 |
Sep 18 09:17:11 PM UTC 24 |
277889505 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.1006883869 |
|
|
Sep 18 09:14:10 PM UTC 24 |
Sep 18 09:17:13 PM UTC 24 |
12938755556 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_all.343543110 |
|
|
Sep 18 09:10:16 PM UTC 24 |
Sep 18 09:17:13 PM UTC 24 |
568623245157 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.1279015988 |
|
|
Sep 18 09:17:13 PM UTC 24 |
Sep 18 09:17:15 PM UTC 24 |
44076913 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.3699575088 |
|
|
Sep 18 09:16:54 PM UTC 24 |
Sep 18 09:17:15 PM UTC 24 |
11619804316 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.2160512900 |
|
|
Sep 18 09:12:02 PM UTC 24 |
Sep 18 09:17:15 PM UTC 24 |
106305257940 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.4271028860 |
|
|
Sep 18 09:16:14 PM UTC 24 |
Sep 18 09:17:15 PM UTC 24 |
2193849927 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.980305407 |
|
|
Sep 18 09:17:14 PM UTC 24 |
Sep 18 09:17:16 PM UTC 24 |
121736533 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2922188864 |
|
|
Sep 18 09:17:08 PM UTC 24 |
Sep 18 09:17:16 PM UTC 24 |
1119010912 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.762075850 |
|
|
Sep 18 09:17:07 PM UTC 24 |
Sep 18 09:17:16 PM UTC 24 |
187174818 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.3450577544 |
|
|
Sep 18 09:17:17 PM UTC 24 |
Sep 18 09:17:19 PM UTC 24 |
27070022 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.2949920130 |
|
|
Sep 18 09:17:17 PM UTC 24 |
Sep 18 09:17:19 PM UTC 24 |
16179909 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.1471532591 |
|
|
Sep 18 09:17:18 PM UTC 24 |
Sep 18 09:17:22 PM UTC 24 |
30953210 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.1326334071 |
|
|
Sep 18 09:11:23 PM UTC 24 |
Sep 18 09:17:23 PM UTC 24 |
139961458249 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.3760715360 |
|
|
Sep 18 09:17:15 PM UTC 24 |
Sep 18 09:17:24 PM UTC 24 |
781346365 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.1878733968 |
|
|
Sep 18 09:17:06 PM UTC 24 |
Sep 18 09:17:25 PM UTC 24 |
5238923894 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.2757118256 |
|
|
Sep 18 09:17:21 PM UTC 24 |
Sep 18 09:17:25 PM UTC 24 |
64469665 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.150643048 |
|
|
Sep 18 09:17:15 PM UTC 24 |
Sep 18 09:17:25 PM UTC 24 |
3075169772 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.3547640901 |
|
|
Sep 18 09:17:19 PM UTC 24 |
Sep 18 09:17:27 PM UTC 24 |
1758615808 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.806354600 |
|
|
Sep 18 09:17:23 PM UTC 24 |
Sep 18 09:17:28 PM UTC 24 |
103672223 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.3142920399 |
|
|
Sep 18 09:17:28 PM UTC 24 |
Sep 18 09:17:30 PM UTC 24 |
64631911 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.3895439305 |
|
|
Sep 18 09:17:17 PM UTC 24 |
Sep 18 09:17:31 PM UTC 24 |
1299526414 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.1302718296 |
|
|
Sep 18 09:10:32 PM UTC 24 |
Sep 18 09:17:32 PM UTC 24 |
40603393461 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.1311362288 |
|
|
Sep 18 09:17:29 PM UTC 24 |
Sep 18 09:17:32 PM UTC 24 |
62273611 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.1502501571 |
|
|
Sep 18 09:17:29 PM UTC 24 |
Sep 18 09:17:32 PM UTC 24 |
14658961 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.1933094727 |
|
|
Sep 18 09:17:17 PM UTC 24 |
Sep 18 09:17:33 PM UTC 24 |
6524766148 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.2349805091 |
|
|
Sep 18 09:14:57 PM UTC 24 |
Sep 18 09:17:34 PM UTC 24 |
28452827688 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.1765883643 |
|
|
Sep 18 09:16:53 PM UTC 24 |
Sep 18 09:17:36 PM UTC 24 |
21269849135 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.2543948198 |
|
|
Sep 18 09:17:35 PM UTC 24 |
Sep 18 09:17:55 PM UTC 24 |
1570758886 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.3156821032 |
|
|
Sep 18 09:17:33 PM UTC 24 |
Sep 18 09:17:36 PM UTC 24 |
98355656 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.586250402 |
|
|
Sep 18 09:17:33 PM UTC 24 |
Sep 18 09:17:36 PM UTC 24 |
170610398 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.4163797542 |
|
|
Sep 18 09:16:51 PM UTC 24 |
Sep 18 09:17:37 PM UTC 24 |
141734256061 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.3453474757 |
|
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Sep 18 09:16:59 PM UTC 24 |
Sep 18 09:17:37 PM UTC 24 |
26541710133 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.2210524527 |
|
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Sep 18 09:17:33 PM UTC 24 |
Sep 18 09:17:38 PM UTC 24 |
253656523 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.133591120 |
|
|
Sep 18 09:17:32 PM UTC 24 |
Sep 18 09:17:39 PM UTC 24 |
4436718620 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.708297076 |
|
|
Sep 18 09:17:39 PM UTC 24 |
Sep 18 09:17:41 PM UTC 24 |
158576387 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.2194250560 |
|
|
Sep 18 09:17:26 PM UTC 24 |
Sep 18 09:17:42 PM UTC 24 |
1133229691 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.982839882 |
|
|
Sep 18 09:17:37 PM UTC 24 |
Sep 18 09:17:42 PM UTC 24 |
296699302 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.3918832170 |
|
|
Sep 18 09:17:26 PM UTC 24 |
Sep 18 09:17:42 PM UTC 24 |
3397193391 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.3883535188 |
|
|
Sep 18 09:17:35 PM UTC 24 |
Sep 18 09:17:44 PM UTC 24 |
1038817184 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.56877235 |
|
|
Sep 18 09:14:09 PM UTC 24 |
Sep 18 09:17:44 PM UTC 24 |
39780871283 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.2289637661 |
|
|
Sep 18 09:17:39 PM UTC 24 |
Sep 18 09:17:45 PM UTC 24 |
253912340 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.3505553966 |
|
|
Sep 18 09:05:36 PM UTC 24 |
Sep 18 09:17:45 PM UTC 24 |
89732876820 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.2344245282 |
|
|
Sep 18 09:17:44 PM UTC 24 |
Sep 18 09:17:46 PM UTC 24 |
13677048 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.1122372314 |
|
|
Sep 18 09:17:37 PM UTC 24 |
Sep 18 09:17:46 PM UTC 24 |
261860226 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.3367275415 |
|
|
Sep 18 09:17:45 PM UTC 24 |
Sep 18 09:17:47 PM UTC 24 |
59332325 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.189342496 |
|
|
Sep 18 09:17:37 PM UTC 24 |
Sep 18 09:17:48 PM UTC 24 |
775400279 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.1570435243 |
|
|
Sep 18 09:17:47 PM UTC 24 |
Sep 18 09:17:49 PM UTC 24 |
108514956 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.2981451208 |
|
|
Sep 18 09:17:48 PM UTC 24 |
Sep 18 09:17:52 PM UTC 24 |
197620408 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.424749391 |
|
|
Sep 18 09:12:50 PM UTC 24 |
Sep 18 09:17:54 PM UTC 24 |
109673823798 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.1907393477 |
|
|
Sep 18 09:17:47 PM UTC 24 |
Sep 18 09:17:54 PM UTC 24 |
1058010374 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.2293119488 |
|
|
Sep 18 09:17:50 PM UTC 24 |
Sep 18 09:17:55 PM UTC 24 |
73567039 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.3614230834 |
|
|
Sep 18 09:17:45 PM UTC 24 |
Sep 18 09:17:58 PM UTC 24 |
3127846211 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.3890046007 |
|
|
Sep 18 09:17:32 PM UTC 24 |
Sep 18 09:17:59 PM UTC 24 |
3775133743 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.2847831440 |
|
|
Sep 18 09:17:54 PM UTC 24 |
Sep 18 09:18:00 PM UTC 24 |
378486286 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.3070687799 |
|
|
Sep 18 09:17:56 PM UTC 24 |
Sep 18 09:18:00 PM UTC 24 |
206405183 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.1168057715 |
|
|
Sep 18 09:17:55 PM UTC 24 |
Sep 18 09:18:01 PM UTC 24 |
73911825 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.351387589 |
|
|
Sep 18 09:18:01 PM UTC 24 |
Sep 18 09:18:03 PM UTC 24 |
15056830 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.788905514 |
|
|
Sep 18 09:18:01 PM UTC 24 |
Sep 18 09:18:03 PM UTC 24 |
13435337 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.2233259971 |
|
|
Sep 18 09:15:36 PM UTC 24 |
Sep 18 09:18:03 PM UTC 24 |
17841464283 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.3182515485 |
|
|
Sep 18 09:17:07 PM UTC 24 |
Sep 18 09:18:04 PM UTC 24 |
4354251914 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.4188583443 |
|
|
Sep 18 09:17:48 PM UTC 24 |
Sep 18 09:18:04 PM UTC 24 |
8335922454 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.2626417505 |
|
|
Sep 18 09:14:57 PM UTC 24 |
Sep 18 09:18:07 PM UTC 24 |
26862215259 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.3732073480 |
|
|
Sep 18 09:18:05 PM UTC 24 |
Sep 18 09:18:07 PM UTC 24 |
73441827 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.1946261445 |
|
|
Sep 18 09:16:10 PM UTC 24 |
Sep 18 09:18:08 PM UTC 24 |
66926554216 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.1779241849 |
|
|
Sep 18 09:18:05 PM UTC 24 |
Sep 18 09:18:08 PM UTC 24 |
72927609 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.422875431 |
|
|
Sep 18 09:17:17 PM UTC 24 |
Sep 18 09:18:08 PM UTC 24 |
42152519556 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.2305646057 |
|
|
Sep 18 09:17:39 PM UTC 24 |
Sep 18 09:18:10 PM UTC 24 |
22016846455 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.489442465 |
|
|
Sep 18 09:17:26 PM UTC 24 |
Sep 18 09:18:12 PM UTC 24 |
19248284910 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.2599519993 |
|
|
Sep 18 09:17:56 PM UTC 24 |
Sep 18 09:18:13 PM UTC 24 |
2146964715 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.2420667641 |
|
|
Sep 18 09:18:08 PM UTC 24 |
Sep 18 09:18:13 PM UTC 24 |
350180419 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.976328135 |
|
|
Sep 18 09:18:09 PM UTC 24 |
Sep 18 09:18:16 PM UTC 24 |
852777607 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.1091198904 |
|
|
Sep 18 09:18:05 PM UTC 24 |
Sep 18 09:18:17 PM UTC 24 |
1734336435 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_mailbox.397417378 |
|
|
Sep 18 09:15:05 PM UTC 24 |
Sep 18 09:18:17 PM UTC 24 |
50386153775 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.673056591 |
|
|
Sep 18 09:16:19 PM UTC 24 |
Sep 18 09:18:18 PM UTC 24 |
7039156325 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.1363432654 |
|
|
Sep 18 09:18:18 PM UTC 24 |
Sep 18 09:18:20 PM UTC 24 |
56933895 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.2089916934 |
|
|
Sep 18 09:18:09 PM UTC 24 |
Sep 18 09:18:20 PM UTC 24 |
3465458717 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.4058222698 |
|
|
Sep 18 09:18:05 PM UTC 24 |
Sep 18 09:18:21 PM UTC 24 |
11393907816 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.241038846 |
|
|
Sep 18 09:18:19 PM UTC 24 |
Sep 18 09:18:22 PM UTC 24 |
30528341 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.1017183311 |
|
|
Sep 18 09:18:05 PM UTC 24 |
Sep 18 09:18:22 PM UTC 24 |
7879259123 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.882784487 |
|
|
Sep 18 09:17:56 PM UTC 24 |
Sep 18 09:18:23 PM UTC 24 |
5080942469 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.2545259047 |
|
|
Sep 18 09:18:02 PM UTC 24 |
Sep 18 09:18:24 PM UTC 24 |
25121167656 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.960712706 |
|
|
Sep 18 09:18:22 PM UTC 24 |
Sep 18 09:18:24 PM UTC 24 |
24773743 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.3260393744 |
|
|
Sep 18 09:11:05 PM UTC 24 |
Sep 18 09:18:24 PM UTC 24 |
174706255030 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.2704830093 |
|
|
Sep 18 09:18:22 PM UTC 24 |
Sep 18 09:18:24 PM UTC 24 |
211266054 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.1927900920 |
|
|
Sep 18 09:18:14 PM UTC 24 |
Sep 18 09:18:25 PM UTC 24 |
1706433758 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.953600280 |
|
|
Sep 18 09:18:24 PM UTC 24 |
Sep 18 09:18:28 PM UTC 24 |
80527242 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.3125868779 |
|
|
Sep 18 09:18:22 PM UTC 24 |
Sep 18 09:18:28 PM UTC 24 |
106118400 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.267285122 |
|
|
Sep 18 09:18:25 PM UTC 24 |
Sep 18 09:18:31 PM UTC 24 |
90772200 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.1962273394 |
|
|
Sep 18 09:18:22 PM UTC 24 |
Sep 18 09:18:33 PM UTC 24 |
8625042271 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.1788882414 |
|
|
Sep 18 09:18:10 PM UTC 24 |
Sep 18 09:18:33 PM UTC 24 |
3607633371 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.2321460735 |
|
|
Sep 18 09:18:25 PM UTC 24 |
Sep 18 09:18:33 PM UTC 24 |
170584911 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.3351585000 |
|
|
Sep 18 09:17:42 PM UTC 24 |
Sep 18 09:18:34 PM UTC 24 |
3224726303 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.494729964 |
|
|
Sep 18 09:18:13 PM UTC 24 |
Sep 18 09:18:34 PM UTC 24 |
3771739613 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.528416779 |
|
|
Sep 18 09:18:25 PM UTC 24 |
Sep 18 09:18:35 PM UTC 24 |
3351923630 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.3639684699 |
|
|
Sep 18 09:17:56 PM UTC 24 |
Sep 18 09:18:36 PM UTC 24 |
8298644122 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.1988469985 |
|
|
Sep 18 09:18:29 PM UTC 24 |
Sep 18 09:18:37 PM UTC 24 |
652079515 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.864879288 |
|
|
Sep 18 09:18:35 PM UTC 24 |
Sep 18 09:18:37 PM UTC 24 |
50584791 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.566552524 |
|
|
Sep 18 09:15:11 PM UTC 24 |
Sep 18 09:18:37 PM UTC 24 |
142784511715 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.356356120 |
|
|
Sep 18 09:18:35 PM UTC 24 |
Sep 18 09:18:37 PM UTC 24 |
20425820 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.3580902221 |
|
|
Sep 18 09:17:47 PM UTC 24 |
Sep 18 09:18:38 PM UTC 24 |
30835349928 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.11134810 |
|
|
Sep 18 09:18:24 PM UTC 24 |
Sep 18 09:18:38 PM UTC 24 |
5573688753 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.3108044415 |
|
|
Sep 18 09:18:09 PM UTC 24 |
Sep 18 09:18:40 PM UTC 24 |
4466979731 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.3322800851 |
|
|
Sep 18 09:18:38 PM UTC 24 |
Sep 18 09:18:40 PM UTC 24 |
18849831 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.618751490 |
|
|
Sep 18 09:17:10 PM UTC 24 |
Sep 18 09:18:42 PM UTC 24 |
4801274957 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.1905870711 |
|
|
Sep 18 09:18:38 PM UTC 24 |
Sep 18 09:18:42 PM UTC 24 |
69724808 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.3042102344 |
|
|
Sep 18 09:18:38 PM UTC 24 |
Sep 18 09:18:43 PM UTC 24 |
272005139 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.2173363515 |
|
|
Sep 18 09:18:25 PM UTC 24 |
Sep 18 09:18:44 PM UTC 24 |
8433853808 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.1831749963 |
|
|
Sep 18 09:18:40 PM UTC 24 |
Sep 18 09:18:44 PM UTC 24 |
56964777 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.4271185234 |
|
|
Sep 18 09:18:40 PM UTC 24 |
Sep 18 09:18:44 PM UTC 24 |
61740773 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.2776134927 |
|
|
Sep 18 09:18:41 PM UTC 24 |
Sep 18 09:18:46 PM UTC 24 |
352568054 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.751051564 |
|
|
Sep 18 09:09:22 PM UTC 24 |
Sep 18 09:18:50 PM UTC 24 |
87183138074 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.4154561193 |
|
|
Sep 18 09:17:59 PM UTC 24 |
Sep 18 09:18:50 PM UTC 24 |
2784716303 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.3145132257 |
|
|
Sep 18 09:09:55 PM UTC 24 |
Sep 18 09:18:53 PM UTC 24 |
388317636771 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.1803059602 |
|
|
Sep 18 09:18:51 PM UTC 24 |
Sep 18 09:18:53 PM UTC 24 |
46716128 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.3915770268 |
|
|
Sep 18 09:18:51 PM UTC 24 |
Sep 18 09:18:53 PM UTC 24 |
331978255 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.3277066291 |
|
|
Sep 18 09:17:42 PM UTC 24 |
Sep 18 09:18:54 PM UTC 24 |
2820640734 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.2029287677 |
|
|
Sep 18 09:15:11 PM UTC 24 |
Sep 18 09:18:54 PM UTC 24 |
53091220441 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.616073529 |
|
|
Sep 18 09:18:27 PM UTC 24 |
Sep 18 09:18:55 PM UTC 24 |
3849946681 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2142538431 |
|
|
Sep 18 09:18:44 PM UTC 24 |
Sep 18 09:18:55 PM UTC 24 |
849009270 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.4278878271 |
|
|
Sep 18 09:18:43 PM UTC 24 |
Sep 18 09:18:56 PM UTC 24 |
493233150 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.1541566328 |
|
|
Sep 18 09:18:55 PM UTC 24 |
Sep 18 09:18:57 PM UTC 24 |
84121019 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.3956213674 |
|
|
Sep 18 09:17:26 PM UTC 24 |
Sep 18 09:18:57 PM UTC 24 |
10004357056 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.316630692 |
|
|
Sep 18 09:18:37 PM UTC 24 |
Sep 18 09:18:57 PM UTC 24 |
15770417056 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.2470746515 |
|
|
Sep 18 09:18:56 PM UTC 24 |
Sep 18 09:18:58 PM UTC 24 |
32424905 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.4115388185 |
|
|
Sep 18 09:18:29 PM UTC 24 |
Sep 18 09:19:02 PM UTC 24 |
10989270037 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2452339505 |
|
|
Sep 18 09:18:38 PM UTC 24 |
Sep 18 09:19:02 PM UTC 24 |
3056901020 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.2351237300 |
|
|
Sep 18 09:18:58 PM UTC 24 |
Sep 18 09:19:03 PM UTC 24 |
109428341 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.2285454057 |
|
|
Sep 18 09:18:56 PM UTC 24 |
Sep 18 09:19:06 PM UTC 24 |
512505549 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.3838896014 |
|
|
Sep 18 09:19:00 PM UTC 24 |
Sep 18 09:19:06 PM UTC 24 |
143185920 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.2874223910 |
|
|
Sep 18 09:18:56 PM UTC 24 |
Sep 18 09:19:08 PM UTC 24 |
2970154472 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.3983226267 |
|
|
Sep 18 09:18:58 PM UTC 24 |
Sep 18 09:19:10 PM UTC 24 |
763635819 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.2656027945 |
|
|
Sep 18 09:19:08 PM UTC 24 |
Sep 18 09:19:10 PM UTC 24 |
11456159 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.1996024498 |
|
|
Sep 18 09:18:58 PM UTC 24 |
Sep 18 09:19:12 PM UTC 24 |
1444557055 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.3935154030 |
|
|
Sep 18 09:18:56 PM UTC 24 |
Sep 18 09:19:12 PM UTC 24 |
8440215900 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.768925270 |
|
|
Sep 18 09:18:45 PM UTC 24 |
Sep 18 09:19:17 PM UTC 24 |
25100047901 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.1748104515 |
|
|
Sep 18 09:18:45 PM UTC 24 |
Sep 18 09:19:18 PM UTC 24 |
2734168864 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.801872045 |
|
|
Sep 18 09:17:40 PM UTC 24 |
Sep 18 09:19:19 PM UTC 24 |
31983609675 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.521433317 |
|
|
Sep 18 09:18:58 PM UTC 24 |
Sep 18 09:19:20 PM UTC 24 |
3573778489 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.2198445334 |
|
|
Sep 18 09:05:55 PM UTC 24 |
Sep 18 09:19:21 PM UTC 24 |
306911120832 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.116427242 |
|
|
Sep 18 09:18:55 PM UTC 24 |
Sep 18 09:19:24 PM UTC 24 |
5851053465 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.160652529 |
|
|
Sep 18 09:18:55 PM UTC 24 |
Sep 18 09:19:25 PM UTC 24 |
7635221979 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.703673656 |
|
|
Sep 18 09:18:58 PM UTC 24 |
Sep 18 09:19:26 PM UTC 24 |
1572854615 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.3488489876 |
|
|
Sep 18 09:18:18 PM UTC 24 |
Sep 18 09:19:27 PM UTC 24 |
22330617351 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_all.1237119413 |
|
|
Sep 18 09:15:33 PM UTC 24 |
Sep 18 09:19:29 PM UTC 24 |
451946587502 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.3803461804 |
|
|
Sep 18 09:18:41 PM UTC 24 |
Sep 18 09:19:30 PM UTC 24 |
21639728888 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.348057272 |
|
|
Sep 18 09:17:12 PM UTC 24 |
Sep 18 09:19:33 PM UTC 24 |
8669771989 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.3635505034 |
|
|
Sep 18 09:18:11 PM UTC 24 |
Sep 18 09:19:38 PM UTC 24 |
11823942578 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.3089839238 |
|
|
Sep 18 09:18:37 PM UTC 24 |
Sep 18 09:19:48 PM UTC 24 |
10544264699 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.3517391108 |
|
|
Sep 18 09:17:44 PM UTC 24 |
Sep 18 09:19:51 PM UTC 24 |
53169010008 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.2994056514 |
|
|
Sep 18 09:18:17 PM UTC 24 |
Sep 18 09:19:59 PM UTC 24 |
51564215906 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.1156136193 |
|
|
Sep 18 09:14:45 PM UTC 24 |
Sep 18 09:20:06 PM UTC 24 |
37652709131 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.3297673791 |
|
|
Sep 18 09:18:32 PM UTC 24 |
Sep 18 09:20:18 PM UTC 24 |
21517529505 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.3491720829 |
|
|
Sep 18 09:16:37 PM UTC 24 |
Sep 18 09:20:24 PM UTC 24 |
17670828662 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.1393027627 |
|
|
Sep 18 09:16:54 PM UTC 24 |
Sep 18 09:20:28 PM UTC 24 |
19884131662 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.2781837644 |
|
|
Sep 18 09:18:43 PM UTC 24 |
Sep 18 09:20:31 PM UTC 24 |
7874524533 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.1673467110 |
|
|
Sep 18 09:13:42 PM UTC 24 |
Sep 18 09:20:33 PM UTC 24 |
87886040738 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.4021231489 |
|
|
Sep 18 09:06:15 PM UTC 24 |
Sep 18 09:20:52 PM UTC 24 |
92447038947 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.1686171120 |
|
|
Sep 18 09:18:47 PM UTC 24 |
Sep 18 09:20:53 PM UTC 24 |
10406131135 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.243050479 |
|
|
Sep 18 09:16:40 PM UTC 24 |
Sep 18 09:20:57 PM UTC 24 |
25535425421 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.3665887219 |
|
|
Sep 18 09:17:10 PM UTC 24 |
Sep 18 09:21:22 PM UTC 24 |
88267538978 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_all.4226326639 |
|
|
Sep 18 09:14:57 PM UTC 24 |
Sep 18 09:21:38 PM UTC 24 |
38757765843 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.2648581508 |
|
|
Sep 18 09:18:14 PM UTC 24 |
Sep 18 09:22:16 PM UTC 24 |
170550110967 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.3438081174 |
|
|
Sep 18 09:16:18 PM UTC 24 |
Sep 18 09:22:26 PM UTC 24 |
173585353539 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.2332016461 |
|
|
Sep 18 09:12:31 PM UTC 24 |
Sep 18 09:22:29 PM UTC 24 |
548687767428 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.1272389056 |
|
|
Sep 18 09:19:03 PM UTC 24 |
Sep 18 09:22:38 PM UTC 24 |
128616508865 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.2781145610 |
|
|
Sep 18 09:15:36 PM UTC 24 |
Sep 18 09:22:40 PM UTC 24 |
32837924321 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.3885131364 |
|
|
Sep 18 09:19:04 PM UTC 24 |
Sep 18 09:22:45 PM UTC 24 |
81136158740 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.3557127601 |
|
|
Sep 18 09:17:24 PM UTC 24 |
Sep 18 09:22:48 PM UTC 24 |
43109874777 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.20043064 |
|
|
Sep 18 09:17:09 PM UTC 24 |
Sep 18 09:23:02 PM UTC 24 |
152729738299 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.1741569961 |
|
|
Sep 18 09:19:06 PM UTC 24 |
Sep 18 09:23:10 PM UTC 24 |
23456652856 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.895907526 |
|
|
Sep 18 09:19:03 PM UTC 24 |
Sep 18 09:24:36 PM UTC 24 |
173826463459 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.1189885491 |
|
|
Sep 18 09:18:01 PM UTC 24 |
Sep 18 09:25:03 PM UTC 24 |
40663348927 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3281520855 |
|
|
Sep 18 09:18:34 PM UTC 24 |
Sep 18 09:25:17 PM UTC 24 |
87000815068 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.1717341495 |
|
|
Sep 18 09:09:58 PM UTC 24 |
Sep 18 09:25:56 PM UTC 24 |
96356939711 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.3933582767 |
|
|
Sep 18 09:18:35 PM UTC 24 |
Sep 18 09:26:02 PM UTC 24 |
141590340774 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.3842687795 |
|
|
Sep 18 09:16:41 PM UTC 24 |
Sep 18 09:26:53 PM UTC 24 |
607585838604 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.340535069 |
|
|
Sep 18 09:18:45 PM UTC 24 |
Sep 18 09:27:03 PM UTC 24 |
127946127748 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.2848954402 |
|
|
Sep 18 09:17:57 PM UTC 24 |
Sep 18 09:27:38 PM UTC 24 |
63964775406 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.3236214673 |
|
|
Sep 18 09:16:56 PM UTC 24 |
Sep 18 09:28:02 PM UTC 24 |
71211781140 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_stress_all.2382240681 |
|
|
Sep 18 09:09:03 PM UTC 24 |
Sep 18 09:28:15 PM UTC 24 |
229830607870 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.862370500 |
|
|
Sep 18 09:18:34 PM UTC 24 |
Sep 18 09:30:19 PM UTC 24 |
400494132073 ps |
| T1038 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2611737575 |
|
|
Sep 18 08:56:56 PM UTC 24 |
Sep 18 08:56:59 PM UTC 24 |
20874858 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.820043697 |
|
|
Sep 18 08:56:56 PM UTC 24 |
Sep 18 08:57:00 PM UTC 24 |
273541908 ps |
| T1039 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.1047233641 |
|
|
Sep 18 08:56:57 PM UTC 24 |
Sep 18 08:57:00 PM UTC 24 |
11890390 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.967490054 |
|
|
Sep 18 08:56:58 PM UTC 24 |
Sep 18 08:57:01 PM UTC 24 |
81283164 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.983687087 |
|
|
Sep 18 08:56:58 PM UTC 24 |
Sep 18 08:57:01 PM UTC 24 |
54384930 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1803843241 |
|
|
Sep 18 08:56:57 PM UTC 24 |
Sep 18 08:57:01 PM UTC 24 |
134625103 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.242306827 |
|
|
Sep 18 08:57:07 PM UTC 24 |
Sep 18 08:57:31 PM UTC 24 |
1815476526 ps |
| T1040 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.1981455436 |
|
|
Sep 18 08:56:59 PM UTC 24 |
Sep 18 08:57:02 PM UTC 24 |
17935610 ps |
| T1041 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.935606161 |
|
|
Sep 18 08:56:59 PM UTC 24 |
Sep 18 08:57:02 PM UTC 24 |
12480049 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.1035863104 |
|
|
Sep 18 08:56:58 PM UTC 24 |
Sep 18 08:57:02 PM UTC 24 |
424651691 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3193503418 |
|
|
Sep 18 08:56:58 PM UTC 24 |
Sep 18 08:57:02 PM UTC 24 |
102788847 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.4041014503 |
|
|
Sep 18 08:56:59 PM UTC 24 |
Sep 18 08:57:02 PM UTC 24 |
32916654 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.875776019 |
|
|
Sep 18 08:56:59 PM UTC 24 |
Sep 18 08:57:02 PM UTC 24 |
40082743 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.57967234 |
|
|
Sep 18 08:57:00 PM UTC 24 |
Sep 18 08:57:02 PM UTC 24 |
524112944 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1101640065 |
|
|
Sep 18 08:56:58 PM UTC 24 |
Sep 18 08:57:03 PM UTC 24 |
2957484110 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3736570565 |
|
|
Sep 18 08:57:00 PM UTC 24 |
Sep 18 08:57:03 PM UTC 24 |
24661771 ps |
| T1042 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.3796468574 |
|
|
Sep 18 08:57:02 PM UTC 24 |
Sep 18 08:57:04 PM UTC 24 |
31265879 ps |
| T1043 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.3664525572 |
|
|
Sep 18 08:57:02 PM UTC 24 |
Sep 18 08:57:05 PM UTC 24 |
18622240 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.55421747 |
|
|
Sep 18 08:56:56 PM UTC 24 |
Sep 18 08:57:05 PM UTC 24 |
477863748 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.373206126 |
|
|
Sep 18 08:57:03 PM UTC 24 |
Sep 18 08:57:06 PM UTC 24 |
73806244 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.2491069547 |
|
|
Sep 18 08:57:02 PM UTC 24 |
Sep 18 08:57:06 PM UTC 24 |
69507135 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2198579310 |
|
|
Sep 18 08:57:00 PM UTC 24 |
Sep 18 08:57:06 PM UTC 24 |
365971080 ps |
| T1044 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.2831612823 |
|
|
Sep 18 08:57:05 PM UTC 24 |
Sep 18 08:57:07 PM UTC 24 |
70826406 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.183253098 |
|
|
Sep 18 08:57:03 PM UTC 24 |
Sep 18 08:57:07 PM UTC 24 |
54543503 ps |