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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.08 98.45 94.10 98.62 89.36 97.29 95.56 99.21


Total test records in report: 1151
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T128 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.4102869920 Sep 18 08:56:59 PM UTC 24 Sep 18 08:57:07 PM UTC 24 283114211 ps
T1045 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.4129794165 Sep 18 08:57:06 PM UTC 24 Sep 18 08:57:08 PM UTC 24 58725495 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.2208509454 Sep 18 08:57:03 PM UTC 24 Sep 18 08:57:08 PM UTC 24 92951280 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.1621340491 Sep 18 08:57:01 PM UTC 24 Sep 18 08:57:08 PM UTC 24 341976761 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3545837559 Sep 18 08:57:01 PM UTC 24 Sep 18 08:57:09 PM UTC 24 1440316228 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2280924913 Sep 18 08:57:00 PM UTC 24 Sep 18 08:57:09 PM UTC 24 1336558195 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1824279665 Sep 18 08:57:03 PM UTC 24 Sep 18 08:57:10 PM UTC 24 315127232 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.527774355 Sep 18 08:57:03 PM UTC 24 Sep 18 08:57:10 PM UTC 24 137173836 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2348365680 Sep 18 08:57:07 PM UTC 24 Sep 18 08:57:10 PM UTC 24 42195909 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.3688945848 Sep 18 08:57:06 PM UTC 24 Sep 18 08:57:10 PM UTC 24 219242910 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.222361814 Sep 18 08:57:07 PM UTC 24 Sep 18 08:57:11 PM UTC 24 228817190 ps
T1046 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.3863160145 Sep 18 08:57:09 PM UTC 24 Sep 18 08:57:12 PM UTC 24 12830933 ps
T1047 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.401345893 Sep 18 08:57:09 PM UTC 24 Sep 18 08:57:12 PM UTC 24 40891089 ps
T1048 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.67785757 Sep 18 08:57:08 PM UTC 24 Sep 18 08:57:12 PM UTC 24 315320627 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.281235654 Sep 18 08:57:08 PM UTC 24 Sep 18 08:57:13 PM UTC 24 49652972 ps
T1049 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.583992441 Sep 18 08:57:10 PM UTC 24 Sep 18 08:57:13 PM UTC 24 20482009 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.222211347 Sep 18 08:57:10 PM UTC 24 Sep 18 08:57:14 PM UTC 24 34361198 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.2994725235 Sep 18 08:57:04 PM UTC 24 Sep 18 08:57:14 PM UTC 24 270794243 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3871399057 Sep 18 08:57:08 PM UTC 24 Sep 18 08:57:14 PM UTC 24 102403462 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.2646840024 Sep 18 08:57:11 PM UTC 24 Sep 18 08:57:15 PM UTC 24 68951206 ps
T1050 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.240023129 Sep 18 08:57:13 PM UTC 24 Sep 18 08:57:16 PM UTC 24 48063883 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2218112898 Sep 18 08:57:12 PM UTC 24 Sep 18 08:57:16 PM UTC 24 1042617016 ps
T1051 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.871939157 Sep 18 08:57:11 PM UTC 24 Sep 18 08:57:17 PM UTC 24 112916749 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.2066826599 Sep 18 08:57:14 PM UTC 24 Sep 18 08:57:17 PM UTC 24 141547169 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.1377992812 Sep 18 08:57:13 PM UTC 24 Sep 18 08:57:17 PM UTC 24 40875554 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.1899857565 Sep 18 08:57:09 PM UTC 24 Sep 18 08:57:18 PM UTC 24 288166673 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.232477239 Sep 18 08:57:03 PM UTC 24 Sep 18 08:57:18 PM UTC 24 222025235 ps
T1052 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.3334413334 Sep 18 08:57:16 PM UTC 24 Sep 18 08:57:19 PM UTC 24 35253652 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2438114051 Sep 18 08:57:14 PM UTC 24 Sep 18 08:57:20 PM UTC 24 198888837 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3594497020 Sep 18 08:57:14 PM UTC 24 Sep 18 08:57:20 PM UTC 24 563934096 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.2224851434 Sep 18 08:57:16 PM UTC 24 Sep 18 08:57:20 PM UTC 24 98409938 ps
T1053 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.1420533840 Sep 18 08:57:19 PM UTC 24 Sep 18 08:57:21 PM UTC 24 21044196 ps
T1054 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.1190531113 Sep 18 08:57:19 PM UTC 24 Sep 18 08:57:22 PM UTC 24 68144713 ps
T1055 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1376295880 Sep 18 08:57:17 PM UTC 24 Sep 18 08:57:22 PM UTC 24 204126790 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.3891738269 Sep 18 08:57:15 PM UTC 24 Sep 18 08:57:22 PM UTC 24 716563794 ps
T1056 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.2918720553 Sep 18 08:57:22 PM UTC 24 Sep 18 08:57:24 PM UTC 24 15153280 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3466964975 Sep 18 08:57:17 PM UTC 24 Sep 18 08:57:24 PM UTC 24 1523377805 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.574213651 Sep 18 08:57:22 PM UTC 24 Sep 18 08:57:25 PM UTC 24 62489586 ps
T1057 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.805997311 Sep 18 08:57:20 PM UTC 24 Sep 18 08:57:26 PM UTC 24 150279931 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4063618027 Sep 18 08:57:21 PM UTC 24 Sep 18 08:57:27 PM UTC 24 911172172 ps
T1058 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1800699118 Sep 18 08:57:23 PM UTC 24 Sep 18 08:57:27 PM UTC 24 110227015 ps
T1059 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.1321129342 Sep 18 08:57:25 PM UTC 24 Sep 18 08:57:28 PM UTC 24 34701890 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2759868633 Sep 18 08:57:23 PM UTC 24 Sep 18 08:57:28 PM UTC 24 100493810 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.3986290646 Sep 18 08:57:11 PM UTC 24 Sep 18 08:57:28 PM UTC 24 3792594013 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.59618479 Sep 18 08:57:19 PM UTC 24 Sep 18 08:57:28 PM UTC 24 1391572049 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.715035471 Sep 18 08:56:58 PM UTC 24 Sep 18 08:57:28 PM UTC 24 965833062 ps
T1060 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3357436323 Sep 18 08:57:00 PM UTC 24 Sep 18 08:57:28 PM UTC 24 1261564619 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.3356425664 Sep 18 08:57:15 PM UTC 24 Sep 18 08:57:29 PM UTC 24 767114824 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.1053387677 Sep 18 08:57:21 PM UTC 24 Sep 18 08:57:29 PM UTC 24 190285384 ps
T1061 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3273012784 Sep 18 08:57:11 PM UTC 24 Sep 18 08:57:29 PM UTC 24 1026761294 ps
T1062 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.3249456039 Sep 18 08:57:26 PM UTC 24 Sep 18 08:57:30 PM UTC 24 424049800 ps
T1063 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2807039407 Sep 18 08:57:28 PM UTC 24 Sep 18 08:57:31 PM UTC 24 54563900 ps
T1064 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.3287800680 Sep 18 08:57:29 PM UTC 24 Sep 18 08:57:31 PM UTC 24 10385805 ps
T1065 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.1478277945 Sep 18 08:57:29 PM UTC 24 Sep 18 08:57:32 PM UTC 24 36614945 ps
T1066 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.2093710555 Sep 18 08:57:29 PM UTC 24 Sep 18 08:57:32 PM UTC 24 32904970 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.992784548 Sep 18 08:57:25 PM UTC 24 Sep 18 08:57:32 PM UTC 24 1093406622 ps
T1067 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.55283629 Sep 18 08:57:29 PM UTC 24 Sep 18 08:57:32 PM UTC 24 33627091 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.2526937973 Sep 18 08:57:13 PM UTC 24 Sep 18 08:57:33 PM UTC 24 2822159941 ps
T1068 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3132906657 Sep 18 08:57:29 PM UTC 24 Sep 18 08:57:33 PM UTC 24 167761092 ps
T1069 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3315137718 Sep 18 08:57:28 PM UTC 24 Sep 18 08:57:33 PM UTC 24 115602736 ps
T1070 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1601744235 Sep 18 08:57:29 PM UTC 24 Sep 18 08:57:33 PM UTC 24 370951807 ps
T1071 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.3556977898 Sep 18 08:57:31 PM UTC 24 Sep 18 08:57:34 PM UTC 24 41040331 ps
T1072 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.3653485351 Sep 18 08:57:28 PM UTC 24 Sep 18 08:57:34 PM UTC 24 556228298 ps
T1073 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2491141484 Sep 18 08:57:31 PM UTC 24 Sep 18 08:57:34 PM UTC 24 46438950 ps
T1074 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.3678510709 Sep 18 08:57:32 PM UTC 24 Sep 18 08:57:34 PM UTC 24 26140134 ps
T1075 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3861506606 Sep 18 08:56:58 PM UTC 24 Sep 18 08:57:35 PM UTC 24 3771974271 ps
T1076 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.3204051271 Sep 18 08:57:33 PM UTC 24 Sep 18 08:57:35 PM UTC 24 15647270 ps
T1077 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.2897747726 Sep 18 08:57:33 PM UTC 24 Sep 18 08:57:37 PM UTC 24 33640037 ps
T1078 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.3650486847 Sep 18 08:57:33 PM UTC 24 Sep 18 08:57:37 PM UTC 24 375822467 ps
T1079 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4268171908 Sep 18 08:57:33 PM UTC 24 Sep 18 08:57:37 PM UTC 24 84481925 ps
T1080 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.657802356 Sep 18 08:57:31 PM UTC 24 Sep 18 08:57:37 PM UTC 24 410427620 ps
T1081 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.4036872291 Sep 18 08:57:32 PM UTC 24 Sep 18 08:57:37 PM UTC 24 488701420 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.186711515 Sep 18 08:57:21 PM UTC 24 Sep 18 08:57:38 PM UTC 24 2130024708 ps
T1082 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.962624514 Sep 18 08:57:36 PM UTC 24 Sep 18 08:57:38 PM UTC 24 20834582 ps
T1083 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.3612214704 Sep 18 08:57:34 PM UTC 24 Sep 18 08:57:38 PM UTC 24 28853350 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.2357564994 Sep 18 08:57:29 PM UTC 24 Sep 18 08:57:38 PM UTC 24 293688975 ps
T1084 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.759254368 Sep 18 08:57:33 PM UTC 24 Sep 18 08:57:38 PM UTC 24 358337842 ps
T1085 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.1070093023 Sep 18 08:57:36 PM UTC 24 Sep 18 08:57:38 PM UTC 24 80800955 ps
T1086 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.159358055 Sep 18 08:57:34 PM UTC 24 Sep 18 08:57:39 PM UTC 24 353001230 ps
T1087 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.3973971607 Sep 18 08:57:34 PM UTC 24 Sep 18 08:57:40 PM UTC 24 188851044 ps
T1088 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.576413680 Sep 18 08:57:48 PM UTC 24 Sep 18 08:57:50 PM UTC 24 11270999 ps
T1089 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.1909379482 Sep 18 08:57:38 PM UTC 24 Sep 18 08:57:40 PM UTC 24 209780691 ps
T1090 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2419884176 Sep 18 08:57:34 PM UTC 24 Sep 18 08:57:41 PM UTC 24 736560842 ps
T1091 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.2572547916 Sep 18 08:57:38 PM UTC 24 Sep 18 08:57:41 PM UTC 24 42999120 ps
T1092 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.1565704881 Sep 18 08:57:39 PM UTC 24 Sep 18 08:57:41 PM UTC 24 12551268 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.3025791277 Sep 18 08:57:19 PM UTC 24 Sep 18 08:57:42 PM UTC 24 899524592 ps
T1093 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3298534897 Sep 18 08:57:37 PM UTC 24 Sep 18 08:57:42 PM UTC 24 111321816 ps
T1094 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.2097367852 Sep 18 08:57:48 PM UTC 24 Sep 18 08:57:50 PM UTC 24 14176839 ps
T1095 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.1621327866 Sep 18 08:57:33 PM UTC 24 Sep 18 08:57:42 PM UTC 24 416372421 ps
T1096 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2423601688 Sep 18 08:57:38 PM UTC 24 Sep 18 08:57:43 PM UTC 24 212928180 ps
T1097 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3726296159 Sep 18 08:57:03 PM UTC 24 Sep 18 08:57:43 PM UTC 24 6011119292 ps
T1098 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1015509683 Sep 18 08:57:38 PM UTC 24 Sep 18 08:57:43 PM UTC 24 403951275 ps
T1099 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3503321389 Sep 18 08:57:37 PM UTC 24 Sep 18 08:57:43 PM UTC 24 58106310 ps
T1100 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.3800259769 Sep 18 08:57:39 PM UTC 24 Sep 18 08:57:43 PM UTC 24 43038706 ps
T1101 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.87744189 Sep 18 08:57:40 PM UTC 24 Sep 18 08:57:44 PM UTC 24 44332636 ps
T1102 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.1940745783 Sep 18 08:57:38 PM UTC 24 Sep 18 08:57:44 PM UTC 24 135639747 ps
T1103 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.378461758 Sep 18 08:57:42 PM UTC 24 Sep 18 08:57:44 PM UTC 24 12340015 ps
T1104 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.100740102 Sep 18 08:57:07 PM UTC 24 Sep 18 08:57:44 PM UTC 24 691609686 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.3604096371 Sep 18 08:57:36 PM UTC 24 Sep 18 08:57:45 PM UTC 24 1107972785 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.4255174543 Sep 18 08:57:41 PM UTC 24 Sep 18 08:57:45 PM UTC 24 105449831 ps
T1105 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3248447638 Sep 18 08:57:40 PM UTC 24 Sep 18 08:57:45 PM UTC 24 116397242 ps
T1106 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3451867938 Sep 18 08:57:42 PM UTC 24 Sep 18 08:57:46 PM UTC 24 78275010 ps
T1107 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.2939397970 Sep 18 08:57:42 PM UTC 24 Sep 18 08:57:46 PM UTC 24 111846996 ps
T1108 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3649344584 Sep 18 08:57:43 PM UTC 24 Sep 18 08:57:46 PM UTC 24 170143700 ps
T1109 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.1365712168 Sep 18 08:57:49 PM UTC 24 Sep 18 08:57:51 PM UTC 24 47350068 ps
T1110 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.1487051582 Sep 18 08:57:38 PM UTC 24 Sep 18 08:57:46 PM UTC 24 75151602 ps
T1111 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.1896517581 Sep 18 08:57:44 PM UTC 24 Sep 18 08:57:46 PM UTC 24 35552938 ps
T1112 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.1906853401 Sep 18 08:57:45 PM UTC 24 Sep 18 08:57:46 PM UTC 24 29914644 ps
T1113 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.3797076856 Sep 18 08:57:43 PM UTC 24 Sep 18 08:57:47 PM UTC 24 316447223 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.787578634 Sep 18 08:57:38 PM UTC 24 Sep 18 08:57:47 PM UTC 24 364792452 ps
T1114 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2727069699 Sep 18 08:57:44 PM UTC 24 Sep 18 08:57:48 PM UTC 24 79860733 ps
T1115 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.377459432 Sep 18 08:57:46 PM UTC 24 Sep 18 08:57:48 PM UTC 24 11929676 ps
T1116 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.1861765967 Sep 18 08:57:32 PM UTC 24 Sep 18 08:57:48 PM UTC 24 5821895817 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.2561729842 Sep 18 08:57:25 PM UTC 24 Sep 18 08:57:48 PM UTC 24 3333590778 ps
T1117 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.3877976384 Sep 18 08:57:44 PM UTC 24 Sep 18 08:57:48 PM UTC 24 155391775 ps
T1118 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.1895360704 Sep 18 08:57:46 PM UTC 24 Sep 18 08:57:49 PM UTC 24 99062646 ps
T1119 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1612878439 Sep 18 08:57:46 PM UTC 24 Sep 18 08:57:49 PM UTC 24 97596461 ps
T1120 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.1443009977 Sep 18 08:57:47 PM UTC 24 Sep 18 08:57:49 PM UTC 24 105706141 ps
T1121 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.2349702078 Sep 18 08:57:47 PM UTC 24 Sep 18 08:57:49 PM UTC 24 68284923 ps
T1122 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.2760070516 Sep 18 08:57:44 PM UTC 24 Sep 18 08:57:49 PM UTC 24 185954154 ps
T1123 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1819038862 Sep 18 08:57:47 PM UTC 24 Sep 18 08:57:49 PM UTC 24 80348254 ps
T1124 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.3544647403 Sep 18 08:57:47 PM UTC 24 Sep 18 08:57:49 PM UTC 24 100174399 ps
T1125 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.3365603789 Sep 18 08:57:47 PM UTC 24 Sep 18 08:57:49 PM UTC 24 14869617 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.2875780697 Sep 18 08:57:29 PM UTC 24 Sep 18 08:57:49 PM UTC 24 1178419143 ps
T1126 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.1907338752 Sep 18 08:57:47 PM UTC 24 Sep 18 08:57:49 PM UTC 24 275129579 ps
T1127 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.299017013 Sep 18 08:57:44 PM UTC 24 Sep 18 08:57:49 PM UTC 24 126630191 ps
T1128 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.1931687926 Sep 18 08:57:47 PM UTC 24 Sep 18 08:57:49 PM UTC 24 125060216 ps
T1129 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4215972016 Sep 18 08:57:46 PM UTC 24 Sep 18 08:57:50 PM UTC 24 87487833 ps
T1130 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.2657853762 Sep 18 08:57:48 PM UTC 24 Sep 18 08:57:50 PM UTC 24 25115925 ps
T1131 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.3076540780 Sep 18 08:57:48 PM UTC 24 Sep 18 08:57:50 PM UTC 24 26862549 ps
T1132 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.1868834040 Sep 18 08:57:50 PM UTC 24 Sep 18 08:57:52 PM UTC 24 38464780 ps
T1133 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.374250620 Sep 18 08:57:50 PM UTC 24 Sep 18 08:57:52 PM UTC 24 29330813 ps
T1134 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.789836534 Sep 18 08:57:50 PM UTC 24 Sep 18 08:57:52 PM UTC 24 12556624 ps
T1135 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.2778250235 Sep 18 08:57:50 PM UTC 24 Sep 18 08:57:52 PM UTC 24 12397933 ps
T1136 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.3074521447 Sep 18 08:57:50 PM UTC 24 Sep 18 08:57:52 PM UTC 24 16428826 ps
T1137 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.2294657069 Sep 18 08:57:50 PM UTC 24 Sep 18 08:57:52 PM UTC 24 49586417 ps
T1138 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.2585828103 Sep 18 08:57:50 PM UTC 24 Sep 18 08:57:52 PM UTC 24 12458931 ps
T1139 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.2606723534 Sep 18 08:57:50 PM UTC 24 Sep 18 08:57:52 PM UTC 24 55278400 ps
T1140 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.3446771889 Sep 18 08:57:50 PM UTC 24 Sep 18 08:57:52 PM UTC 24 57959064 ps
T1141 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.3515056422 Sep 18 08:57:50 PM UTC 24 Sep 18 08:57:52 PM UTC 24 37409536 ps
T1142 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.224767497 Sep 18 08:57:50 PM UTC 24 Sep 18 08:57:52 PM UTC 24 18191721 ps
T1143 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.2894973139 Sep 18 08:57:50 PM UTC 24 Sep 18 08:57:52 PM UTC 24 13460275 ps
T1144 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.304145921 Sep 18 08:57:50 PM UTC 24 Sep 18 08:57:52 PM UTC 24 46337503 ps
T1145 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.4243004411 Sep 18 08:57:50 PM UTC 24 Sep 18 08:57:52 PM UTC 24 43166769 ps
T1146 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.487874779 Sep 18 08:57:51 PM UTC 24 Sep 18 08:57:53 PM UTC 24 122044201 ps
T1147 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.810285727 Sep 18 08:57:51 PM UTC 24 Sep 18 08:57:53 PM UTC 24 43094057 ps
T1148 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.3307184823 Sep 18 08:57:51 PM UTC 24 Sep 18 08:57:53 PM UTC 24 29585271 ps
T1149 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.2010556868 Sep 18 08:57:43 PM UTC 24 Sep 18 08:57:57 PM UTC 24 222393682 ps
T1150 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.2710696981 Sep 18 08:57:38 PM UTC 24 Sep 18 08:57:58 PM UTC 24 295902900 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.1731392581 Sep 18 08:57:41 PM UTC 24 Sep 18 08:57:59 PM UTC 24 296245585 ps
T1151 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.134265240 Sep 18 08:57:44 PM UTC 24 Sep 18 08:58:05 PM UTC 24 927420450 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.4121356149
Short name T6
Test name
Test status
Simulation time 587201055 ps
CPU time 2.91 seconds
Started Sep 18 09:02:38 PM UTC 24
Finished Sep 18 09:02:43 PM UTC 24
Peak memory 227692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121356149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.4121356149
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.3705353501
Short name T24
Test name
Test status
Simulation time 8427601585 ps
CPU time 11.05 seconds
Started Sep 18 09:02:46 PM UTC 24
Finished Sep 18 09:02:58 PM UTC 24
Peak memory 245608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705353501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3705353501
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.1887592235
Short name T37
Test name
Test status
Simulation time 6757067515 ps
CPU time 53.48 seconds
Started Sep 18 09:03:17 PM UTC 24
Finished Sep 18 09:04:12 PM UTC 24
Peak memory 262048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887592235 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.1887592235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.3344535477
Short name T17
Test name
Test status
Simulation time 312453946 ps
CPU time 5.64 seconds
Started Sep 18 09:02:42 PM UTC 24
Finished Sep 18 09:02:50 PM UTC 24
Peak memory 245424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344535477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3344535477
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.96006768
Short name T51
Test name
Test status
Simulation time 5957151205 ps
CPU time 61 seconds
Started Sep 18 09:03:00 PM UTC 24
Finished Sep 18 09:04:02 PM UTC 24
Peak memory 263984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96006768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.96006768
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.3060811240
Short name T235
Test name
Test status
Simulation time 48991868838 ps
CPU time 283.63 seconds
Started Sep 18 09:02:42 PM UTC 24
Finished Sep 18 09:07:30 PM UTC 24
Peak memory 251684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060811240 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.3060811240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1824279665
Short name T139
Test name
Test status
Simulation time 315127232 ps
CPU time 5.16 seconds
Started Sep 18 08:57:03 PM UTC 24
Finished Sep 18 08:57:10 PM UTC 24
Peak memory 229184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1824279665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.spi_device_csr_mem_rw_with_rand_reset.1824279665
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.1146998247
Short name T68
Test name
Test status
Simulation time 4626633486 ps
CPU time 100.57 seconds
Started Sep 18 09:02:41 PM UTC 24
Finished Sep 18 09:04:24 PM UTC 24
Peak memory 278304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146998247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1146998247
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.2639378477
Short name T391
Test name
Test status
Simulation time 7936370949 ps
CPU time 38.84 seconds
Started Sep 18 09:03:46 PM UTC 24
Finished Sep 18 09:04:27 PM UTC 24
Peak memory 227944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639378477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2639378477
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.105700764
Short name T231
Test name
Test status
Simulation time 140899601865 ps
CPU time 288.72 seconds
Started Sep 18 09:02:59 PM UTC 24
Finished Sep 18 09:07:51 PM UTC 24
Peak memory 284532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105700764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.105700764
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.4225793900
Short name T3
Test name
Test status
Simulation time 16340148 ps
CPU time 0.92 seconds
Started Sep 18 09:02:38 PM UTC 24
Finished Sep 18 09:02:41 PM UTC 24
Peak memory 226268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225793900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.4225793900
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.1188656693
Short name T14
Test name
Test status
Simulation time 514858942 ps
CPU time 4.49 seconds
Started Sep 18 09:02:40 PM UTC 24
Finished Sep 18 09:02:46 PM UTC 24
Peak memory 229616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188656693 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.1188656693
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.3103834046
Short name T72
Test name
Test status
Simulation time 35154450234 ps
CPU time 168.43 seconds
Started Sep 18 09:02:47 PM UTC 24
Finished Sep 18 09:05:38 PM UTC 24
Peak memory 284240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103834046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3103834046
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.2574822025
Short name T12
Test name
Test status
Simulation time 317197747 ps
CPU time 1.89 seconds
Started Sep 18 09:02:42 PM UTC 24
Finished Sep 18 09:02:45 PM UTC 24
Peak memory 257652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574822025 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2574822025
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.1737737479
Short name T285
Test name
Test status
Simulation time 38503516796 ps
CPU time 166.08 seconds
Started Sep 18 09:05:37 PM UTC 24
Finished Sep 18 09:08:26 PM UTC 24
Peak memory 284452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737737479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1737737479
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.4246103487
Short name T256
Test name
Test status
Simulation time 15126100935 ps
CPU time 202.75 seconds
Started Sep 18 09:06:15 PM UTC 24
Finished Sep 18 09:09:41 PM UTC 24
Peak memory 280364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246103487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.4246103487
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.2422154273
Short name T84
Test name
Test status
Simulation time 80770599532 ps
CPU time 148.8 seconds
Started Sep 18 09:02:47 PM UTC 24
Finished Sep 18 09:05:19 PM UTC 24
Peak memory 262068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422154273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.2422154273
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.3597707813
Short name T122
Test name
Test status
Simulation time 46072129094 ps
CPU time 239.92 seconds
Started Sep 18 09:02:40 PM UTC 24
Finished Sep 18 09:06:44 PM UTC 24
Peak memory 263928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597707813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.3597707813
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.3976247008
Short name T29
Test name
Test status
Simulation time 11500524673 ps
CPU time 14.32 seconds
Started Sep 18 09:02:42 PM UTC 24
Finished Sep 18 09:02:58 PM UTC 24
Peak memory 227832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976247008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3976247008
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.3025791277
Short name T213
Test name
Test status
Simulation time 899524592 ps
CPU time 21.52 seconds
Started Sep 18 08:57:19 PM UTC 24
Finished Sep 18 08:57:42 PM UTC 24
Peak memory 227300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025791277 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.3025791277
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.231772104
Short name T225
Test name
Test status
Simulation time 137640126343 ps
CPU time 145.57 seconds
Started Sep 18 09:07:18 PM UTC 24
Finished Sep 18 09:09:46 PM UTC 24
Peak memory 263916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231772104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.231772104
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.59618479
Short name T136
Test name
Test status
Simulation time 1391572049 ps
CPU time 8.29 seconds
Started Sep 18 08:57:19 PM UTC 24
Finished Sep 18 08:57:28 PM UTC 24
Peak memory 225212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59618479 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.59618479
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.242306827
Short name T145
Test name
Test status
Simulation time 1815476526 ps
CPU time 23.06 seconds
Started Sep 18 08:57:07 PM UTC 24
Finished Sep 18 08:57:31 PM UTC 24
Peak memory 225136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242306827 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.242306827
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.3982214454
Short name T109
Test name
Test status
Simulation time 8229003252 ps
CPU time 52.54 seconds
Started Sep 18 09:04:01 PM UTC 24
Finished Sep 18 09:04:56 PM UTC 24
Peak memory 278256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982214454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.3982214454
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.2561873980
Short name T172
Test name
Test status
Simulation time 11464571279 ps
CPU time 213.07 seconds
Started Sep 18 09:11:07 PM UTC 24
Finished Sep 18 09:14:44 PM UTC 24
Peak memory 284464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561873980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.2561873980
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.790839642
Short name T4
Test name
Test status
Simulation time 47684587 ps
CPU time 1.16 seconds
Started Sep 18 09:02:38 PM UTC 24
Finished Sep 18 09:02:41 PM UTC 24
Peak memory 228264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790839642 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_parity.790839642
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.3343307130
Short name T105
Test name
Test status
Simulation time 24049993168 ps
CPU time 29.35 seconds
Started Sep 18 09:02:40 PM UTC 24
Finished Sep 18 09:03:11 PM UTC 24
Peak memory 245480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343307130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3343307130
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.2450142174
Short name T194
Test name
Test status
Simulation time 31060497047 ps
CPU time 113.14 seconds
Started Sep 18 09:11:07 PM UTC 24
Finished Sep 18 09:13:03 PM UTC 24
Peak memory 268132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450142174 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.2450142174
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/26.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.1534439509
Short name T246
Test name
Test status
Simulation time 19516692727 ps
CPU time 215.97 seconds
Started Sep 18 09:04:50 PM UTC 24
Finished Sep 18 09:08:29 PM UTC 24
Peak memory 268140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534439509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1534439509
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.3201248534
Short name T86
Test name
Test status
Simulation time 268877007825 ps
CPU time 648.11 seconds
Started Sep 18 09:05:57 PM UTC 24
Finished Sep 18 09:16:53 PM UTC 24
Peak memory 311068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201248534 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.3201248534
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.30074983
Short name T365
Test name
Test status
Simulation time 4579883091 ps
CPU time 112.79 seconds
Started Sep 18 09:13:18 PM UTC 24
Finished Sep 18 09:15:13 PM UTC 24
Peak memory 284348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30074983 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.30074983
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/32.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.3146808311
Short name T184
Test name
Test status
Simulation time 433189763 ps
CPU time 13.58 seconds
Started Sep 18 09:04:46 PM UTC 24
Finished Sep 18 09:05:02 PM UTC 24
Peak memory 261808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146808311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3146808311
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.3505553966
Short name T115
Test name
Test status
Simulation time 89732876820 ps
CPU time 720.27 seconds
Started Sep 18 09:05:36 PM UTC 24
Finished Sep 18 09:17:45 PM UTC 24
Peak memory 284440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505553966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3505553966
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.3309193861
Short name T9
Test name
Test status
Simulation time 37988776 ps
CPU time 1.03 seconds
Started Sep 18 09:02:42 PM UTC 24
Finished Sep 18 09:02:44 PM UTC 24
Peak memory 213048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309193861 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3309193861
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1101640065
Short name T126
Test name
Test status
Simulation time 2957484110 ps
CPU time 3.23 seconds
Started Sep 18 08:56:58 PM UTC 24
Finished Sep 18 08:57:03 PM UTC 24
Peak memory 225204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101640065 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1101640065
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.3297136462
Short name T228
Test name
Test status
Simulation time 19337298546 ps
CPU time 158.94 seconds
Started Sep 18 09:06:59 PM UTC 24
Finished Sep 18 09:09:41 PM UTC 24
Peak memory 284516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297136462 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.3297136462
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.688673921
Short name T289
Test name
Test status
Simulation time 10232542196 ps
CPU time 101.31 seconds
Started Sep 18 09:05:37 PM UTC 24
Finished Sep 18 09:07:20 PM UTC 24
Peak memory 245464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688673921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.688673921
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.3991029057
Short name T108
Test name
Test status
Simulation time 2617470664 ps
CPU time 88.67 seconds
Started Sep 18 09:02:46 PM UTC 24
Finished Sep 18 09:04:17 PM UTC 24
Peak memory 259208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991029057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.3991029057
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.2349805091
Short name T339
Test name
Test status
Simulation time 28452827688 ps
CPU time 154.49 seconds
Started Sep 18 09:14:57 PM UTC 24
Finished Sep 18 09:17:34 PM UTC 24
Peak memory 263908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349805091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2349805091
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/36.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.3184170033
Short name T34
Test name
Test status
Simulation time 16809079042 ps
CPU time 43.01 seconds
Started Sep 18 09:03:01 PM UTC 24
Finished Sep 18 09:03:45 PM UTC 24
Peak memory 235236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184170033 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.3184170033
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.3707749543
Short name T326
Test name
Test status
Simulation time 161940916028 ps
CPU time 242.22 seconds
Started Sep 18 09:06:58 PM UTC 24
Finished Sep 18 09:11:04 PM UTC 24
Peak memory 278376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707749543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.3707749543
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.1189885491
Short name T385
Test name
Test status
Simulation time 40663348927 ps
CPU time 416.61 seconds
Started Sep 18 09:18:01 PM UTC 24
Finished Sep 18 09:25:03 PM UTC 24
Peak memory 266084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189885491 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.1189885491
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/45.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.2357564994
Short name T211
Test name
Test status
Simulation time 293688975 ps
CPU time 7.39 seconds
Started Sep 18 08:57:29 PM UTC 24
Finished Sep 18 08:57:38 PM UTC 24
Peak memory 226956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357564994 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.2357564994
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.665226369
Short name T207
Test name
Test status
Simulation time 11201002136 ps
CPU time 122.66 seconds
Started Sep 18 09:02:46 PM UTC 24
Finished Sep 18 09:04:51 PM UTC 24
Peak memory 261924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665226369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.665226369
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.2198445334
Short name T377
Test name
Test status
Simulation time 306911120832 ps
CPU time 796.39 seconds
Started Sep 18 09:05:55 PM UTC 24
Finished Sep 18 09:19:21 PM UTC 24
Peak memory 278384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198445334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2198445334
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode.2819128618
Short name T279
Test name
Test status
Simulation time 4769480269 ps
CPU time 16.31 seconds
Started Sep 18 09:08:27 PM UTC 24
Finished Sep 18 09:08:45 PM UTC 24
Peak memory 251756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819128618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2819128618
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.3843414745
Short name T242
Test name
Test status
Simulation time 276413948704 ps
CPU time 211.19 seconds
Started Sep 18 09:03:16 PM UTC 24
Finished Sep 18 09:06:51 PM UTC 24
Peak memory 249652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843414745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.3843414745
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.1156136193
Short name T372
Test name
Test status
Simulation time 37652709131 ps
CPU time 316.92 seconds
Started Sep 18 09:14:45 PM UTC 24
Finished Sep 18 09:20:06 PM UTC 24
Peak memory 261924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156136193 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.1156136193
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/35.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.4102869920
Short name T128
Test name
Test status
Simulation time 283114211 ps
CPU time 6.64 seconds
Started Sep 18 08:56:59 PM UTC 24
Finished Sep 18 08:57:07 PM UTC 24
Peak memory 227312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102869920 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.4102869920
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.1466125813
Short name T58
Test name
Test status
Simulation time 2438555798 ps
CPU time 6.68 seconds
Started Sep 18 09:03:07 PM UTC 24
Finished Sep 18 09:03:15 PM UTC 24
Peak memory 245484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466125813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1466125813
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.1731392581
Short name T212
Test name
Test status
Simulation time 296245585 ps
CPU time 17.33 seconds
Started Sep 18 08:57:41 PM UTC 24
Finished Sep 18 08:57:59 PM UTC 24
Peak memory 224988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731392581 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.1731392581
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_upload.3670328934
Short name T316
Test name
Test status
Simulation time 27777660263 ps
CPU time 33.77 seconds
Started Sep 18 09:06:47 PM UTC 24
Finished Sep 18 09:07:22 PM UTC 24
Peak memory 245472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670328934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3670328934
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.758579976
Short name T276
Test name
Test status
Simulation time 72040926863 ps
CPU time 181.09 seconds
Started Sep 18 09:08:11 PM UTC 24
Finished Sep 18 09:11:15 PM UTC 24
Peak memory 268076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758579976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.758579976
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.3264233734
Short name T342
Test name
Test status
Simulation time 2335729981 ps
CPU time 8.61 seconds
Started Sep 18 09:08:24 PM UTC 24
Finished Sep 18 09:08:34 PM UTC 24
Peak memory 235156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264233734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.3264233734
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.3314657156
Short name T269
Test name
Test status
Simulation time 11235918082 ps
CPU time 99.57 seconds
Started Sep 18 09:14:57 PM UTC 24
Finished Sep 18 09:16:39 PM UTC 24
Peak memory 268076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314657156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.3314657156
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.3236214673
Short name T367
Test name
Test status
Simulation time 71211781140 ps
CPU time 657.7 seconds
Started Sep 18 09:16:56 PM UTC 24
Finished Sep 18 09:28:02 PM UTC 24
Peak memory 294700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236214673 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.3236214673
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/41.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.967490054
Short name T112
Test name
Test status
Simulation time 81283164 ps
CPU time 1.82 seconds
Started Sep 18 08:56:58 PM UTC 24
Finished Sep 18 08:57:01 PM UTC 24
Peak memory 226348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967490054 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.967490054
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.715035471
Short name T160
Test name
Test status
Simulation time 965833062 ps
CPU time 28.59 seconds
Started Sep 18 08:56:58 PM UTC 24
Finished Sep 18 08:57:28 PM UTC 24
Peak memory 225220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715035471 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.715035471
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3861506606
Short name T1075
Test name
Test status
Simulation time 3771974271 ps
CPU time 35.25 seconds
Started Sep 18 08:56:58 PM UTC 24
Finished Sep 18 08:57:35 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861506606 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.3861506606
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.983687087
Short name T125
Test name
Test status
Simulation time 54384930 ps
CPU time 1.85 seconds
Started Sep 18 08:56:58 PM UTC 24
Finished Sep 18 08:57:01 PM UTC 24
Peak memory 226028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=983687087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.spi_device_csr_mem_rw_with_rand_reset.983687087
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.1035863104
Short name T174
Test name
Test status
Simulation time 424651691 ps
CPU time 2.46 seconds
Started Sep 18 08:56:58 PM UTC 24
Finished Sep 18 08:57:02 PM UTC 24
Peak memory 224988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035863104 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1035863104
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2611737575
Short name T1038
Test name
Test status
Simulation time 20874858 ps
CPU time 0.84 seconds
Started Sep 18 08:56:56 PM UTC 24
Finished Sep 18 08:56:59 PM UTC 24
Peak memory 212624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611737575 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2611737575
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1803843241
Short name T144
Test name
Test status
Simulation time 134625103 ps
CPU time 2.32 seconds
Started Sep 18 08:56:57 PM UTC 24
Finished Sep 18 08:57:01 PM UTC 24
Peak memory 225284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803843241 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.1803843241
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.1047233641
Short name T1039
Test name
Test status
Simulation time 11890390 ps
CPU time 1.01 seconds
Started Sep 18 08:56:57 PM UTC 24
Finished Sep 18 08:57:00 PM UTC 24
Peak memory 211568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047233641 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.1047233641
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3193503418
Short name T175
Test name
Test status
Simulation time 102788847 ps
CPU time 2.35 seconds
Started Sep 18 08:56:58 PM UTC 24
Finished Sep 18 08:57:02 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193503418 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstanding.3193503418
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.820043697
Short name T124
Test name
Test status
Simulation time 273541908 ps
CPU time 1.88 seconds
Started Sep 18 08:56:56 PM UTC 24
Finished Sep 18 08:57:00 PM UTC 24
Peak memory 224108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820043697 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.820043697
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.55421747
Short name T127
Test name
Test status
Simulation time 477863748 ps
CPU time 7.61 seconds
Started Sep 18 08:56:56 PM UTC 24
Finished Sep 18 08:57:05 PM UTC 24
Peak memory 224944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55421747 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.55421747
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2280924913
Short name T150
Test name
Test status
Simulation time 1336558195 ps
CPU time 7.96 seconds
Started Sep 18 08:57:00 PM UTC 24
Finished Sep 18 08:57:09 PM UTC 24
Peak memory 225000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280924913 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.2280924913
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3357436323
Short name T1060
Test name
Test status
Simulation time 1261564619 ps
CPU time 27.21 seconds
Started Sep 18 08:57:00 PM UTC 24
Finished Sep 18 08:57:28 PM UTC 24
Peak memory 224828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357436323 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.3357436323
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.875776019
Short name T113
Test name
Test status
Simulation time 40082743 ps
CPU time 1.5 seconds
Started Sep 18 08:56:59 PM UTC 24
Finished Sep 18 08:57:02 PM UTC 24
Peak memory 226116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875776019 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.875776019
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3736570565
Short name T138
Test name
Test status
Simulation time 24661771 ps
CPU time 2.27 seconds
Started Sep 18 08:57:00 PM UTC 24
Finished Sep 18 08:57:03 PM UTC 24
Peak memory 227136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3736570565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.spi_device_csr_mem_rw_with_rand_reset.3736570565
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.57967234
Short name T176
Test name
Test status
Simulation time 524112944 ps
CPU time 1.67 seconds
Started Sep 18 08:57:00 PM UTC 24
Finished Sep 18 08:57:02 PM UTC 24
Peak memory 223792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57967234 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.57967234
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.1981455436
Short name T1040
Test name
Test status
Simulation time 17935610 ps
CPU time 0.95 seconds
Started Sep 18 08:56:59 PM UTC 24
Finished Sep 18 08:57:02 PM UTC 24
Peak memory 211576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981455436 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1981455436
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.4041014503
Short name T146
Test name
Test status
Simulation time 32916654 ps
CPU time 1.45 seconds
Started Sep 18 08:56:59 PM UTC 24
Finished Sep 18 08:57:02 PM UTC 24
Peak memory 223884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041014503 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.4041014503
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.935606161
Short name T1041
Test name
Test status
Simulation time 12480049 ps
CPU time 0.99 seconds
Started Sep 18 08:56:59 PM UTC 24
Finished Sep 18 08:57:02 PM UTC 24
Peak memory 211568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935606161 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.935606161
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2198579310
Short name T177
Test name
Test status
Simulation time 365971080 ps
CPU time 5.36 seconds
Started Sep 18 08:57:00 PM UTC 24
Finished Sep 18 08:57:06 PM UTC 24
Peak memory 224940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198579310 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstanding.2198579310
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1601744235
Short name T1070
Test name
Test status
Simulation time 370951807 ps
CPU time 2.93 seconds
Started Sep 18 08:57:29 PM UTC 24
Finished Sep 18 08:57:33 PM UTC 24
Peak memory 227128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1601744235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
10.spi_device_csr_mem_rw_with_rand_reset.1601744235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.2093710555
Short name T1066
Test name
Test status
Simulation time 32904970 ps
CPU time 1.76 seconds
Started Sep 18 08:57:29 PM UTC 24
Finished Sep 18 08:57:32 PM UTC 24
Peak memory 213604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093710555 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.2093710555
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.3287800680
Short name T1064
Test name
Test status
Simulation time 10385805 ps
CPU time 1.07 seconds
Started Sep 18 08:57:29 PM UTC 24
Finished Sep 18 08:57:31 PM UTC 24
Peak memory 211304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287800680 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.3287800680
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.55283629
Short name T1067
Test name
Test status
Simulation time 33627091 ps
CPU time 1.91 seconds
Started Sep 18 08:57:29 PM UTC 24
Finished Sep 18 08:57:32 PM UTC 24
Peak memory 214208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55283629 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstanding.55283629
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.3653485351
Short name T1072
Test name
Test status
Simulation time 556228298 ps
CPU time 4.9 seconds
Started Sep 18 08:57:28 PM UTC 24
Finished Sep 18 08:57:34 PM UTC 24
Peak memory 227124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653485351 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.3653485351
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2491141484
Short name T1073
Test name
Test status
Simulation time 46438950 ps
CPU time 2.2 seconds
Started Sep 18 08:57:31 PM UTC 24
Finished Sep 18 08:57:34 PM UTC 24
Peak memory 227128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2491141484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
11.spi_device_csr_mem_rw_with_rand_reset.2491141484
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.3556977898
Short name T1071
Test name
Test status
Simulation time 41040331 ps
CPU time 1.93 seconds
Started Sep 18 08:57:31 PM UTC 24
Finished Sep 18 08:57:34 PM UTC 24
Peak memory 213556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556977898 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.3556977898
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.1478277945
Short name T1065
Test name
Test status
Simulation time 36614945 ps
CPU time 1.07 seconds
Started Sep 18 08:57:29 PM UTC 24
Finished Sep 18 08:57:32 PM UTC 24
Peak memory 211576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478277945 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.1478277945
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.657802356
Short name T1080
Test name
Test status
Simulation time 410427620 ps
CPU time 5.42 seconds
Started Sep 18 08:57:31 PM UTC 24
Finished Sep 18 08:57:37 PM UTC 24
Peak memory 225012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657802356 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstanding.657802356
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3132906657
Short name T1068
Test name
Test status
Simulation time 167761092 ps
CPU time 2.14 seconds
Started Sep 18 08:57:29 PM UTC 24
Finished Sep 18 08:57:33 PM UTC 24
Peak memory 225192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132906657 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.3132906657
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.2875780697
Short name T216
Test name
Test status
Simulation time 1178419143 ps
CPU time 18.45 seconds
Started Sep 18 08:57:29 PM UTC 24
Finished Sep 18 08:57:49 PM UTC 24
Peak memory 227160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875780697 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.2875780697
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.759254368
Short name T1084
Test name
Test status
Simulation time 358337842 ps
CPU time 3.5 seconds
Started Sep 18 08:57:33 PM UTC 24
Finished Sep 18 08:57:38 PM UTC 24
Peak memory 227372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=759254368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
12.spi_device_csr_mem_rw_with_rand_reset.759254368
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.3650486847
Short name T1078
Test name
Test status
Simulation time 375822467 ps
CPU time 2.82 seconds
Started Sep 18 08:57:33 PM UTC 24
Finished Sep 18 08:57:37 PM UTC 24
Peak memory 214820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650486847 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.3650486847
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.3678510709
Short name T1074
Test name
Test status
Simulation time 26140134 ps
CPU time 1.06 seconds
Started Sep 18 08:57:32 PM UTC 24
Finished Sep 18 08:57:34 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678510709 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.3678510709
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4268171908
Short name T1079
Test name
Test status
Simulation time 84481925 ps
CPU time 2.85 seconds
Started Sep 18 08:57:33 PM UTC 24
Finished Sep 18 08:57:37 PM UTC 24
Peak memory 225244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268171908 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstanding.4268171908
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.4036872291
Short name T1081
Test name
Test status
Simulation time 488701420 ps
CPU time 4.24 seconds
Started Sep 18 08:57:32 PM UTC 24
Finished Sep 18 08:57:37 PM UTC 24
Peak memory 227176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036872291 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.4036872291
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.1861765967
Short name T1116
Test name
Test status
Simulation time 5821895817 ps
CPU time 14.84 seconds
Started Sep 18 08:57:32 PM UTC 24
Finished Sep 18 08:57:48 PM UTC 24
Peak memory 227192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861765967 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.1861765967
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.159358055
Short name T1086
Test name
Test status
Simulation time 353001230 ps
CPU time 3.14 seconds
Started Sep 18 08:57:34 PM UTC 24
Finished Sep 18 08:57:39 PM UTC 24
Peak memory 229184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=159358055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
13.spi_device_csr_mem_rw_with_rand_reset.159358055
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.3612214704
Short name T1083
Test name
Test status
Simulation time 28853350 ps
CPU time 2.27 seconds
Started Sep 18 08:57:34 PM UTC 24
Finished Sep 18 08:57:38 PM UTC 24
Peak memory 227260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612214704 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.3612214704
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.3204051271
Short name T1076
Test name
Test status
Simulation time 15647270 ps
CPU time 1.12 seconds
Started Sep 18 08:57:33 PM UTC 24
Finished Sep 18 08:57:35 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204051271 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.3204051271
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2419884176
Short name T1090
Test name
Test status
Simulation time 736560842 ps
CPU time 5.35 seconds
Started Sep 18 08:57:34 PM UTC 24
Finished Sep 18 08:57:41 PM UTC 24
Peak memory 224832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419884176 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstanding.2419884176
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.2897747726
Short name T1077
Test name
Test status
Simulation time 33640037 ps
CPU time 2.39 seconds
Started Sep 18 08:57:33 PM UTC 24
Finished Sep 18 08:57:37 PM UTC 24
Peak memory 227172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897747726 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.2897747726
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.1621327866
Short name T1095
Test name
Test status
Simulation time 416372421 ps
CPU time 8.07 seconds
Started Sep 18 08:57:33 PM UTC 24
Finished Sep 18 08:57:42 PM UTC 24
Peak memory 224924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621327866 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.1621327866
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3503321389
Short name T1099
Test name
Test status
Simulation time 58106310 ps
CPU time 4.92 seconds
Started Sep 18 08:57:37 PM UTC 24
Finished Sep 18 08:57:43 PM UTC 24
Peak memory 229376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3503321389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
14.spi_device_csr_mem_rw_with_rand_reset.3503321389
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.1070093023
Short name T1085
Test name
Test status
Simulation time 80800955 ps
CPU time 1.77 seconds
Started Sep 18 08:57:36 PM UTC 24
Finished Sep 18 08:57:38 PM UTC 24
Peak memory 213604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070093023 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.1070093023
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.962624514
Short name T1082
Test name
Test status
Simulation time 20834582 ps
CPU time 1.06 seconds
Started Sep 18 08:57:36 PM UTC 24
Finished Sep 18 08:57:38 PM UTC 24
Peak memory 211580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962624514 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.962624514
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3298534897
Short name T1093
Test name
Test status
Simulation time 111321816 ps
CPU time 4.48 seconds
Started Sep 18 08:57:37 PM UTC 24
Finished Sep 18 08:57:42 PM UTC 24
Peak memory 224972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298534897 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstanding.3298534897
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.3973971607
Short name T1087
Test name
Test status
Simulation time 188851044 ps
CPU time 4.54 seconds
Started Sep 18 08:57:34 PM UTC 24
Finished Sep 18 08:57:40 PM UTC 24
Peak memory 225132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973971607 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.3973971607
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.3604096371
Short name T217
Test name
Test status
Simulation time 1107972785 ps
CPU time 8.22 seconds
Started Sep 18 08:57:36 PM UTC 24
Finished Sep 18 08:57:45 PM UTC 24
Peak memory 227368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604096371 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.3604096371
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2423601688
Short name T1096
Test name
Test status
Simulation time 212928180 ps
CPU time 3.41 seconds
Started Sep 18 08:57:38 PM UTC 24
Finished Sep 18 08:57:43 PM UTC 24
Peak memory 227260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2423601688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
15.spi_device_csr_mem_rw_with_rand_reset.2423601688
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.2572547916
Short name T1091
Test name
Test status
Simulation time 42999120 ps
CPU time 1.95 seconds
Started Sep 18 08:57:38 PM UTC 24
Finished Sep 18 08:57:41 PM UTC 24
Peak memory 223840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572547916 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.2572547916
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.1909379482
Short name T1089
Test name
Test status
Simulation time 209780691 ps
CPU time 1.14 seconds
Started Sep 18 08:57:38 PM UTC 24
Finished Sep 18 08:57:40 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909379482 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.1909379482
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1015509683
Short name T1098
Test name
Test status
Simulation time 403951275 ps
CPU time 3.69 seconds
Started Sep 18 08:57:38 PM UTC 24
Finished Sep 18 08:57:43 PM UTC 24
Peak memory 227136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015509683 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstanding.1015509683
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.1940745783
Short name T1102
Test name
Test status
Simulation time 135639747 ps
CPU time 4.69 seconds
Started Sep 18 08:57:38 PM UTC 24
Finished Sep 18 08:57:44 PM UTC 24
Peak memory 225148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940745783 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.1940745783
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.2710696981
Short name T1150
Test name
Test status
Simulation time 295902900 ps
CPU time 18.9 seconds
Started Sep 18 08:57:38 PM UTC 24
Finished Sep 18 08:57:58 PM UTC 24
Peak memory 225216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710696981 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.2710696981
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3248447638
Short name T1105
Test name
Test status
Simulation time 116397242 ps
CPU time 4.68 seconds
Started Sep 18 08:57:40 PM UTC 24
Finished Sep 18 08:57:45 PM UTC 24
Peak memory 227132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3248447638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.spi_device_csr_mem_rw_with_rand_reset.3248447638
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.3800259769
Short name T1100
Test name
Test status
Simulation time 43038706 ps
CPU time 3.01 seconds
Started Sep 18 08:57:39 PM UTC 24
Finished Sep 18 08:57:43 PM UTC 24
Peak memory 224936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800259769 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.3800259769
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.1565704881
Short name T1092
Test name
Test status
Simulation time 12551268 ps
CPU time 1.03 seconds
Started Sep 18 08:57:39 PM UTC 24
Finished Sep 18 08:57:41 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565704881 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.1565704881
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.87744189
Short name T1101
Test name
Test status
Simulation time 44332636 ps
CPU time 3.15 seconds
Started Sep 18 08:57:40 PM UTC 24
Finished Sep 18 08:57:44 PM UTC 24
Peak memory 225188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87744189 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstanding.87744189
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.1487051582
Short name T1110
Test name
Test status
Simulation time 75151602 ps
CPU time 6.63 seconds
Started Sep 18 08:57:38 PM UTC 24
Finished Sep 18 08:57:46 PM UTC 24
Peak memory 227176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487051582 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.1487051582
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.787578634
Short name T218
Test name
Test status
Simulation time 364792452 ps
CPU time 7.97 seconds
Started Sep 18 08:57:38 PM UTC 24
Finished Sep 18 08:57:47 PM UTC 24
Peak memory 227184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787578634 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.787578634
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3649344584
Short name T1108
Test name
Test status
Simulation time 170143700 ps
CPU time 1.85 seconds
Started Sep 18 08:57:43 PM UTC 24
Finished Sep 18 08:57:46 PM UTC 24
Peak memory 223956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3649344584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
17.spi_device_csr_mem_rw_with_rand_reset.3649344584
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.2939397970
Short name T1107
Test name
Test status
Simulation time 111846996 ps
CPU time 2.64 seconds
Started Sep 18 08:57:42 PM UTC 24
Finished Sep 18 08:57:46 PM UTC 24
Peak memory 224944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939397970 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.2939397970
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.378461758
Short name T1103
Test name
Test status
Simulation time 12340015 ps
CPU time 1.08 seconds
Started Sep 18 08:57:42 PM UTC 24
Finished Sep 18 08:57:44 PM UTC 24
Peak memory 211580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378461758 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.378461758
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3451867938
Short name T1106
Test name
Test status
Simulation time 78275010 ps
CPU time 2.63 seconds
Started Sep 18 08:57:42 PM UTC 24
Finished Sep 18 08:57:46 PM UTC 24
Peak memory 224940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451867938 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstanding.3451867938
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.4255174543
Short name T209
Test name
Test status
Simulation time 105449831 ps
CPU time 3.5 seconds
Started Sep 18 08:57:41 PM UTC 24
Finished Sep 18 08:57:45 PM UTC 24
Peak memory 227208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255174543 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.4255174543
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.299017013
Short name T1127
Test name
Test status
Simulation time 126630191 ps
CPU time 3.74 seconds
Started Sep 18 08:57:44 PM UTC 24
Finished Sep 18 08:57:49 PM UTC 24
Peak memory 227188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=299017013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
18.spi_device_csr_mem_rw_with_rand_reset.299017013
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.3877976384
Short name T1117
Test name
Test status
Simulation time 155391775 ps
CPU time 3 seconds
Started Sep 18 08:57:44 PM UTC 24
Finished Sep 18 08:57:48 PM UTC 24
Peak memory 225012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877976384 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.3877976384
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.1896517581
Short name T1111
Test name
Test status
Simulation time 35552938 ps
CPU time 0.96 seconds
Started Sep 18 08:57:44 PM UTC 24
Finished Sep 18 08:57:46 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896517581 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.1896517581
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2727069699
Short name T1114
Test name
Test status
Simulation time 79860733 ps
CPU time 2.28 seconds
Started Sep 18 08:57:44 PM UTC 24
Finished Sep 18 08:57:48 PM UTC 24
Peak memory 214828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727069699 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstanding.2727069699
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.3797076856
Short name T1113
Test name
Test status
Simulation time 316447223 ps
CPU time 3.02 seconds
Started Sep 18 08:57:43 PM UTC 24
Finished Sep 18 08:57:47 PM UTC 24
Peak memory 227388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797076856 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.3797076856
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.2010556868
Short name T1149
Test name
Test status
Simulation time 222393682 ps
CPU time 12.6 seconds
Started Sep 18 08:57:43 PM UTC 24
Finished Sep 18 08:57:57 PM UTC 24
Peak memory 225016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010556868 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.2010556868
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1612878439
Short name T1119
Test name
Test status
Simulation time 97596461 ps
CPU time 2.09 seconds
Started Sep 18 08:57:46 PM UTC 24
Finished Sep 18 08:57:49 PM UTC 24
Peak memory 227308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1612878439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
19.spi_device_csr_mem_rw_with_rand_reset.1612878439
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.1895360704
Short name T1118
Test name
Test status
Simulation time 99062646 ps
CPU time 2.22 seconds
Started Sep 18 08:57:46 PM UTC 24
Finished Sep 18 08:57:49 PM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895360704 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.1895360704
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.1906853401
Short name T1112
Test name
Test status
Simulation time 29914644 ps
CPU time 0.93 seconds
Started Sep 18 08:57:45 PM UTC 24
Finished Sep 18 08:57:46 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906853401 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.1906853401
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4215972016
Short name T1129
Test name
Test status
Simulation time 87487833 ps
CPU time 3 seconds
Started Sep 18 08:57:46 PM UTC 24
Finished Sep 18 08:57:50 PM UTC 24
Peak memory 224932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215972016 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstanding.4215972016
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.2760070516
Short name T1122
Test name
Test status
Simulation time 185954154 ps
CPU time 3.55 seconds
Started Sep 18 08:57:44 PM UTC 24
Finished Sep 18 08:57:49 PM UTC 24
Peak memory 225464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760070516 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.2760070516
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.134265240
Short name T1151
Test name
Test status
Simulation time 927420450 ps
CPU time 19.08 seconds
Started Sep 18 08:57:44 PM UTC 24
Finished Sep 18 08:58:05 PM UTC 24
Peak memory 227128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134265240 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.134265240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.232477239
Short name T156
Test name
Test status
Simulation time 222025235 ps
CPU time 13.24 seconds
Started Sep 18 08:57:03 PM UTC 24
Finished Sep 18 08:57:18 PM UTC 24
Peak memory 225016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232477239 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.232477239
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3726296159
Short name T1097
Test name
Test status
Simulation time 6011119292 ps
CPU time 38.12 seconds
Started Sep 18 08:57:03 PM UTC 24
Finished Sep 18 08:57:43 PM UTC 24
Peak memory 225016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726296159 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.3726296159
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.373206126
Short name T147
Test name
Test status
Simulation time 73806244 ps
CPU time 1.45 seconds
Started Sep 18 08:57:03 PM UTC 24
Finished Sep 18 08:57:06 PM UTC 24
Peak memory 214020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373206126 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.373206126
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.2208509454
Short name T149
Test name
Test status
Simulation time 92951280 ps
CPU time 3.53 seconds
Started Sep 18 08:57:03 PM UTC 24
Finished Sep 18 08:57:08 PM UTC 24
Peak memory 225004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208509454 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2208509454
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.3664525572
Short name T1043
Test name
Test status
Simulation time 18622240 ps
CPU time 1.16 seconds
Started Sep 18 08:57:02 PM UTC 24
Finished Sep 18 08:57:05 PM UTC 24
Peak memory 211576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664525572 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3664525572
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.2491069547
Short name T148
Test name
Test status
Simulation time 69507135 ps
CPU time 2.6 seconds
Started Sep 18 08:57:02 PM UTC 24
Finished Sep 18 08:57:06 PM UTC 24
Peak memory 225216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491069547 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.2491069547
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.3796468574
Short name T1042
Test name
Test status
Simulation time 31265879 ps
CPU time 1.05 seconds
Started Sep 18 08:57:02 PM UTC 24
Finished Sep 18 08:57:04 PM UTC 24
Peak memory 211568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796468574 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.3796468574
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.183253098
Short name T178
Test name
Test status
Simulation time 54543503 ps
CPU time 2.73 seconds
Started Sep 18 08:57:03 PM UTC 24
Finished Sep 18 08:57:07 PM UTC 24
Peak memory 224940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183253098 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstanding.183253098
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3545837559
Short name T130
Test name
Test status
Simulation time 1440316228 ps
CPU time 6.51 seconds
Started Sep 18 08:57:01 PM UTC 24
Finished Sep 18 08:57:09 PM UTC 24
Peak memory 225392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545837559 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3545837559
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.1621340491
Short name T129
Test name
Test status
Simulation time 341976761 ps
CPU time 6.11 seconds
Started Sep 18 08:57:01 PM UTC 24
Finished Sep 18 08:57:08 PM UTC 24
Peak memory 227176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621340491 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.1621340491
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.377459432
Short name T1115
Test name
Test status
Simulation time 11929676 ps
CPU time 0.99 seconds
Started Sep 18 08:57:46 PM UTC 24
Finished Sep 18 08:57:48 PM UTC 24
Peak memory 211580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377459432 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.377459432
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/20.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.2349702078
Short name T1121
Test name
Test status
Simulation time 68284923 ps
CPU time 1.02 seconds
Started Sep 18 08:57:47 PM UTC 24
Finished Sep 18 08:57:49 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349702078 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.2349702078
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/21.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.1443009977
Short name T1120
Test name
Test status
Simulation time 105706141 ps
CPU time 1.07 seconds
Started Sep 18 08:57:47 PM UTC 24
Finished Sep 18 08:57:49 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443009977 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.1443009977
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/22.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1819038862
Short name T1123
Test name
Test status
Simulation time 80348254 ps
CPU time 1 seconds
Started Sep 18 08:57:47 PM UTC 24
Finished Sep 18 08:57:49 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819038862 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.1819038862
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/23.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.3365603789
Short name T1125
Test name
Test status
Simulation time 14869617 ps
CPU time 1.09 seconds
Started Sep 18 08:57:47 PM UTC 24
Finished Sep 18 08:57:49 PM UTC 24
Peak memory 211364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365603789 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.3365603789
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/24.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.3544647403
Short name T1124
Test name
Test status
Simulation time 100174399 ps
CPU time 0.99 seconds
Started Sep 18 08:57:47 PM UTC 24
Finished Sep 18 08:57:49 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544647403 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.3544647403
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/25.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.1931687926
Short name T1128
Test name
Test status
Simulation time 125060216 ps
CPU time 1.11 seconds
Started Sep 18 08:57:47 PM UTC 24
Finished Sep 18 08:57:49 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931687926 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.1931687926
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/26.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.1907338752
Short name T1126
Test name
Test status
Simulation time 275129579 ps
CPU time 0.97 seconds
Started Sep 18 08:57:47 PM UTC 24
Finished Sep 18 08:57:49 PM UTC 24
Peak memory 211580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907338752 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.1907338752
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/27.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.2657853762
Short name T1130
Test name
Test status
Simulation time 25115925 ps
CPU time 1.04 seconds
Started Sep 18 08:57:48 PM UTC 24
Finished Sep 18 08:57:50 PM UTC 24
Peak memory 211424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657853762 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.2657853762
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/28.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.576413680
Short name T1088
Test name
Test status
Simulation time 11270999 ps
CPU time 1.02 seconds
Started Sep 18 08:57:48 PM UTC 24
Finished Sep 18 08:57:50 PM UTC 24
Peak memory 211432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576413680 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.576413680
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/29.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.100740102
Short name T1104
Test name
Test status
Simulation time 691609686 ps
CPU time 36.01 seconds
Started Sep 18 08:57:07 PM UTC 24
Finished Sep 18 08:57:44 PM UTC 24
Peak memory 214856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100740102 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.100740102
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2348365680
Short name T114
Test name
Test status
Simulation time 42195909 ps
CPU time 2.09 seconds
Started Sep 18 08:57:07 PM UTC 24
Finished Sep 18 08:57:10 PM UTC 24
Peak memory 225192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348365680 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.2348365680
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3871399057
Short name T141
Test name
Test status
Simulation time 102403462 ps
CPU time 4.91 seconds
Started Sep 18 08:57:08 PM UTC 24
Finished Sep 18 08:57:14 PM UTC 24
Peak memory 227116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3871399057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.spi_device_csr_mem_rw_with_rand_reset.3871399057
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.222361814
Short name T152
Test name
Test status
Simulation time 228817190 ps
CPU time 2.81 seconds
Started Sep 18 08:57:07 PM UTC 24
Finished Sep 18 08:57:11 PM UTC 24
Peak memory 225208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222361814 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.222361814
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.2831612823
Short name T1044
Test name
Test status
Simulation time 70826406 ps
CPU time 1.07 seconds
Started Sep 18 08:57:05 PM UTC 24
Finished Sep 18 08:57:07 PM UTC 24
Peak memory 211576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831612823 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2831612823
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.3688945848
Short name T151
Test name
Test status
Simulation time 219242910 ps
CPU time 3.07 seconds
Started Sep 18 08:57:06 PM UTC 24
Finished Sep 18 08:57:10 PM UTC 24
Peak memory 225072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688945848 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.3688945848
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.4129794165
Short name T1045
Test name
Test status
Simulation time 58725495 ps
CPU time 1.05 seconds
Started Sep 18 08:57:06 PM UTC 24
Finished Sep 18 08:57:08 PM UTC 24
Peak memory 211568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129794165 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.4129794165
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.67785757
Short name T1048
Test name
Test status
Simulation time 315320627 ps
CPU time 2.36 seconds
Started Sep 18 08:57:08 PM UTC 24
Finished Sep 18 08:57:12 PM UTC 24
Peak memory 215012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67785757 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstanding.67785757
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.527774355
Short name T133
Test name
Test status
Simulation time 137173836 ps
CPU time 5.26 seconds
Started Sep 18 08:57:03 PM UTC 24
Finished Sep 18 08:57:10 PM UTC 24
Peak memory 225424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527774355 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.527774355
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.2994725235
Short name T140
Test name
Test status
Simulation time 270794243 ps
CPU time 9.4 seconds
Started Sep 18 08:57:04 PM UTC 24
Finished Sep 18 08:57:14 PM UTC 24
Peak memory 224936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994725235 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.2994725235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.3076540780
Short name T1131
Test name
Test status
Simulation time 26862549 ps
CPU time 0.91 seconds
Started Sep 18 08:57:48 PM UTC 24
Finished Sep 18 08:57:50 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076540780 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.3076540780
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/30.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.2097367852
Short name T1094
Test name
Test status
Simulation time 14176839 ps
CPU time 1.03 seconds
Started Sep 18 08:57:48 PM UTC 24
Finished Sep 18 08:57:50 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097367852 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.2097367852
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/31.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.1365712168
Short name T1109
Test name
Test status
Simulation time 47350068 ps
CPU time 0.9 seconds
Started Sep 18 08:57:49 PM UTC 24
Finished Sep 18 08:57:51 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365712168 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.1365712168
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/32.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.374250620
Short name T1133
Test name
Test status
Simulation time 29330813 ps
CPU time 0.91 seconds
Started Sep 18 08:57:50 PM UTC 24
Finished Sep 18 08:57:52 PM UTC 24
Peak memory 211580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374250620 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.374250620
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/33.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.1868834040
Short name T1132
Test name
Test status
Simulation time 38464780 ps
CPU time 0.91 seconds
Started Sep 18 08:57:50 PM UTC 24
Finished Sep 18 08:57:52 PM UTC 24
Peak memory 211572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868834040 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.1868834040
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/34.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.2778250235
Short name T1135
Test name
Test status
Simulation time 12397933 ps
CPU time 1 seconds
Started Sep 18 08:57:50 PM UTC 24
Finished Sep 18 08:57:52 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778250235 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.2778250235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/35.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.3074521447
Short name T1136
Test name
Test status
Simulation time 16428826 ps
CPU time 0.96 seconds
Started Sep 18 08:57:50 PM UTC 24
Finished Sep 18 08:57:52 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074521447 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.3074521447
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/36.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.789836534
Short name T1134
Test name
Test status
Simulation time 12556624 ps
CPU time 0.89 seconds
Started Sep 18 08:57:50 PM UTC 24
Finished Sep 18 08:57:52 PM UTC 24
Peak memory 211580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789836534 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.789836534
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/37.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.3446771889
Short name T1140
Test name
Test status
Simulation time 57959064 ps
CPU time 1.1 seconds
Started Sep 18 08:57:50 PM UTC 24
Finished Sep 18 08:57:52 PM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446771889 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.3446771889
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/38.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.2294657069
Short name T1137
Test name
Test status
Simulation time 49586417 ps
CPU time 1.06 seconds
Started Sep 18 08:57:50 PM UTC 24
Finished Sep 18 08:57:52 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294657069 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.2294657069
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/39.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.3986290646
Short name T159
Test name
Test status
Simulation time 3792594013 ps
CPU time 16.17 seconds
Started Sep 18 08:57:11 PM UTC 24
Finished Sep 18 08:57:28 PM UTC 24
Peak memory 225012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986290646 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.3986290646
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3273012784
Short name T1061
Test name
Test status
Simulation time 1026761294 ps
CPU time 17.39 seconds
Started Sep 18 08:57:11 PM UTC 24
Finished Sep 18 08:57:29 PM UTC 24
Peak memory 225008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273012784 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.3273012784
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.583992441
Short name T1049
Test name
Test status
Simulation time 20482009 ps
CPU time 1.71 seconds
Started Sep 18 08:57:10 PM UTC 24
Finished Sep 18 08:57:13 PM UTC 24
Peak memory 213608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583992441 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.583992441
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2218112898
Short name T142
Test name
Test status
Simulation time 1042617016 ps
CPU time 3.3 seconds
Started Sep 18 08:57:12 PM UTC 24
Finished Sep 18 08:57:16 PM UTC 24
Peak memory 227328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2218112898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.spi_device_csr_mem_rw_with_rand_reset.2218112898
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.2646840024
Short name T154
Test name
Test status
Simulation time 68951206 ps
CPU time 3.32 seconds
Started Sep 18 08:57:11 PM UTC 24
Finished Sep 18 08:57:15 PM UTC 24
Peak memory 216824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646840024 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2646840024
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.401345893
Short name T1047
Test name
Test status
Simulation time 40891089 ps
CPU time 1.11 seconds
Started Sep 18 08:57:09 PM UTC 24
Finished Sep 18 08:57:12 PM UTC 24
Peak memory 211580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401345893 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.401345893
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.222211347
Short name T153
Test name
Test status
Simulation time 34361198 ps
CPU time 1.96 seconds
Started Sep 18 08:57:10 PM UTC 24
Finished Sep 18 08:57:14 PM UTC 24
Peak memory 223884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222211347 -assert nopostpr
oc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.222211347
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.3863160145
Short name T1046
Test name
Test status
Simulation time 12830933 ps
CPU time 1.02 seconds
Started Sep 18 08:57:09 PM UTC 24
Finished Sep 18 08:57:12 PM UTC 24
Peak memory 211572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863160145 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.3863160145
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.871939157
Short name T1051
Test name
Test status
Simulation time 112916749 ps
CPU time 5.09 seconds
Started Sep 18 08:57:11 PM UTC 24
Finished Sep 18 08:57:17 PM UTC 24
Peak memory 225060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871939157 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstanding.871939157
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.281235654
Short name T134
Test name
Test status
Simulation time 49652972 ps
CPU time 3.47 seconds
Started Sep 18 08:57:08 PM UTC 24
Finished Sep 18 08:57:13 PM UTC 24
Peak memory 225140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281235654 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.281235654
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.1899857565
Short name T215
Test name
Test status
Simulation time 288166673 ps
CPU time 7.09 seconds
Started Sep 18 08:57:09 PM UTC 24
Finished Sep 18 08:57:18 PM UTC 24
Peak memory 227176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899857565 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.1899857565
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.2606723534
Short name T1139
Test name
Test status
Simulation time 55278400 ps
CPU time 1 seconds
Started Sep 18 08:57:50 PM UTC 24
Finished Sep 18 08:57:52 PM UTC 24
Peak memory 212276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606723534 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.2606723534
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/40.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.3515056422
Short name T1141
Test name
Test status
Simulation time 37409536 ps
CPU time 1.02 seconds
Started Sep 18 08:57:50 PM UTC 24
Finished Sep 18 08:57:52 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515056422 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.3515056422
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/41.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.2894973139
Short name T1143
Test name
Test status
Simulation time 13460275 ps
CPU time 0.98 seconds
Started Sep 18 08:57:50 PM UTC 24
Finished Sep 18 08:57:52 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894973139 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.2894973139
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/42.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.304145921
Short name T1144
Test name
Test status
Simulation time 46337503 ps
CPU time 1.06 seconds
Started Sep 18 08:57:50 PM UTC 24
Finished Sep 18 08:57:52 PM UTC 24
Peak memory 211580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304145921 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.304145921
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/43.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.2585828103
Short name T1138
Test name
Test status
Simulation time 12458931 ps
CPU time 0.87 seconds
Started Sep 18 08:57:50 PM UTC 24
Finished Sep 18 08:57:52 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585828103 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.2585828103
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/44.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.224767497
Short name T1142
Test name
Test status
Simulation time 18191721 ps
CPU time 0.86 seconds
Started Sep 18 08:57:50 PM UTC 24
Finished Sep 18 08:57:52 PM UTC 24
Peak memory 211580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224767497 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.224767497
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/45.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.4243004411
Short name T1145
Test name
Test status
Simulation time 43166769 ps
CPU time 0.95 seconds
Started Sep 18 08:57:50 PM UTC 24
Finished Sep 18 08:57:52 PM UTC 24
Peak memory 211580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243004411 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.4243004411
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/46.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.810285727
Short name T1147
Test name
Test status
Simulation time 43094057 ps
CPU time 1.07 seconds
Started Sep 18 08:57:51 PM UTC 24
Finished Sep 18 08:57:53 PM UTC 24
Peak memory 211580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810285727 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.810285727
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/47.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.3307184823
Short name T1148
Test name
Test status
Simulation time 29585271 ps
CPU time 1.12 seconds
Started Sep 18 08:57:51 PM UTC 24
Finished Sep 18 08:57:53 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307184823 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.3307184823
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/48.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.487874779
Short name T1146
Test name
Test status
Simulation time 122044201 ps
CPU time 0.79 seconds
Started Sep 18 08:57:51 PM UTC 24
Finished Sep 18 08:57:53 PM UTC 24
Peak memory 211580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487874779 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.487874779
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/49.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3594497020
Short name T187
Test name
Test status
Simulation time 563934096 ps
CPU time 4.53 seconds
Started Sep 18 08:57:14 PM UTC 24
Finished Sep 18 08:57:20 PM UTC 24
Peak memory 229376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3594497020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
5.spi_device_csr_mem_rw_with_rand_reset.3594497020
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.2066826599
Short name T155
Test name
Test status
Simulation time 141547169 ps
CPU time 1.92 seconds
Started Sep 18 08:57:14 PM UTC 24
Finished Sep 18 08:57:17 PM UTC 24
Peak memory 213604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066826599 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2066826599
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.240023129
Short name T1050
Test name
Test status
Simulation time 48063883 ps
CPU time 1.14 seconds
Started Sep 18 08:57:13 PM UTC 24
Finished Sep 18 08:57:16 PM UTC 24
Peak memory 211580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240023129 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.240023129
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2438114051
Short name T186
Test name
Test status
Simulation time 198888837 ps
CPU time 4.6 seconds
Started Sep 18 08:57:14 PM UTC 24
Finished Sep 18 08:57:20 PM UTC 24
Peak memory 225192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438114051 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstanding.2438114051
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.1377992812
Short name T131
Test name
Test status
Simulation time 40875554 ps
CPU time 3.13 seconds
Started Sep 18 08:57:13 PM UTC 24
Finished Sep 18 08:57:17 PM UTC 24
Peak memory 227408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377992812 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1377992812
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.2526937973
Short name T219
Test name
Test status
Simulation time 2822159941 ps
CPU time 18.08 seconds
Started Sep 18 08:57:13 PM UTC 24
Finished Sep 18 08:57:33 PM UTC 24
Peak memory 227184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526937973 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.2526937973
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3466964975
Short name T188
Test name
Test status
Simulation time 1523377805 ps
CPU time 5.34 seconds
Started Sep 18 08:57:17 PM UTC 24
Finished Sep 18 08:57:24 PM UTC 24
Peak memory 228812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3466964975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
6.spi_device_csr_mem_rw_with_rand_reset.3466964975
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.2224851434
Short name T157
Test name
Test status
Simulation time 98409938 ps
CPU time 2.78 seconds
Started Sep 18 08:57:16 PM UTC 24
Finished Sep 18 08:57:20 PM UTC 24
Peak memory 225136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224851434 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2224851434
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.3334413334
Short name T1052
Test name
Test status
Simulation time 35253652 ps
CPU time 1.09 seconds
Started Sep 18 08:57:16 PM UTC 24
Finished Sep 18 08:57:19 PM UTC 24
Peak memory 211432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334413334 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3334413334
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1376295880
Short name T1055
Test name
Test status
Simulation time 204126790 ps
CPU time 3.2 seconds
Started Sep 18 08:57:17 PM UTC 24
Finished Sep 18 08:57:22 PM UTC 24
Peak memory 224708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376295880 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstanding.1376295880
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.3891738269
Short name T132
Test name
Test status
Simulation time 716563794 ps
CPU time 5.46 seconds
Started Sep 18 08:57:15 PM UTC 24
Finished Sep 18 08:57:22 PM UTC 24
Peak memory 227380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891738269 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3891738269
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.3356425664
Short name T201
Test name
Test status
Simulation time 767114824 ps
CPU time 11.84 seconds
Started Sep 18 08:57:15 PM UTC 24
Finished Sep 18 08:57:29 PM UTC 24
Peak memory 225268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356425664 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.3356425664
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4063618027
Short name T135
Test name
Test status
Simulation time 911172172 ps
CPU time 4.55 seconds
Started Sep 18 08:57:21 PM UTC 24
Finished Sep 18 08:57:27 PM UTC 24
Peak memory 229164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4063618027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
7.spi_device_csr_mem_rw_with_rand_reset.4063618027
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.1190531113
Short name T1054
Test name
Test status
Simulation time 68144713 ps
CPU time 1.81 seconds
Started Sep 18 08:57:19 PM UTC 24
Finished Sep 18 08:57:22 PM UTC 24
Peak memory 215648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190531113 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1190531113
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.1420533840
Short name T1053
Test name
Test status
Simulation time 21044196 ps
CPU time 1.17 seconds
Started Sep 18 08:57:19 PM UTC 24
Finished Sep 18 08:57:21 PM UTC 24
Peak memory 211576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420533840 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1420533840
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.805997311
Short name T1057
Test name
Test status
Simulation time 150279931 ps
CPU time 5.15 seconds
Started Sep 18 08:57:20 PM UTC 24
Finished Sep 18 08:57:26 PM UTC 24
Peak memory 225136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805997311 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstanding.805997311
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2759868633
Short name T189
Test name
Test status
Simulation time 100493810 ps
CPU time 3.52 seconds
Started Sep 18 08:57:23 PM UTC 24
Finished Sep 18 08:57:28 PM UTC 24
Peak memory 227400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2759868633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
8.spi_device_csr_mem_rw_with_rand_reset.2759868633
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.574213651
Short name T158
Test name
Test status
Simulation time 62489586 ps
CPU time 1.86 seconds
Started Sep 18 08:57:22 PM UTC 24
Finished Sep 18 08:57:25 PM UTC 24
Peak memory 223824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574213651 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.574213651
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.2918720553
Short name T1056
Test name
Test status
Simulation time 15153280 ps
CPU time 0.92 seconds
Started Sep 18 08:57:22 PM UTC 24
Finished Sep 18 08:57:24 PM UTC 24
Peak memory 211576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918720553 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2918720553
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1800699118
Short name T1058
Test name
Test status
Simulation time 110227015 ps
CPU time 2.68 seconds
Started Sep 18 08:57:23 PM UTC 24
Finished Sep 18 08:57:27 PM UTC 24
Peak memory 225212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800699118 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstanding.1800699118
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.1053387677
Short name T137
Test name
Test status
Simulation time 190285384 ps
CPU time 7.42 seconds
Started Sep 18 08:57:21 PM UTC 24
Finished Sep 18 08:57:29 PM UTC 24
Peak memory 227268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053387677 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1053387677
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.186711515
Short name T210
Test name
Test status
Simulation time 2130024708 ps
CPU time 15.33 seconds
Started Sep 18 08:57:21 PM UTC 24
Finished Sep 18 08:57:38 PM UTC 24
Peak memory 227060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186711515 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.186711515
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2807039407
Short name T1063
Test name
Test status
Simulation time 54563900 ps
CPU time 1.92 seconds
Started Sep 18 08:57:28 PM UTC 24
Finished Sep 18 08:57:31 PM UTC 24
Peak memory 226024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2807039407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
9.spi_device_csr_mem_rw_with_rand_reset.2807039407
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.3249456039
Short name T1062
Test name
Test status
Simulation time 424049800 ps
CPU time 2.44 seconds
Started Sep 18 08:57:26 PM UTC 24
Finished Sep 18 08:57:30 PM UTC 24
Peak memory 225072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249456039 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3249456039
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.1321129342
Short name T1059
Test name
Test status
Simulation time 34701890 ps
CPU time 1.07 seconds
Started Sep 18 08:57:25 PM UTC 24
Finished Sep 18 08:57:28 PM UTC 24
Peak memory 211516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321129342 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1321129342
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3315137718
Short name T1069
Test name
Test status
Simulation time 115602736 ps
CPU time 4.24 seconds
Started Sep 18 08:57:28 PM UTC 24
Finished Sep 18 08:57:33 PM UTC 24
Peak memory 225184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315137718 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstanding.3315137718
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.992784548
Short name T208
Test name
Test status
Simulation time 1093406622 ps
CPU time 5.82 seconds
Started Sep 18 08:57:25 PM UTC 24
Finished Sep 18 08:57:32 PM UTC 24
Peak memory 227400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992784548 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.992784548
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.2561729842
Short name T214
Test name
Test status
Simulation time 3333590778 ps
CPU time 21.39 seconds
Started Sep 18 08:57:25 PM UTC 24
Finished Sep 18 08:57:48 PM UTC 24
Peak memory 225204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561729842 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.2561729842
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.321558706
Short name T2
Test name
Test status
Simulation time 36368923 ps
CPU time 0.88 seconds
Started Sep 18 09:02:38 PM UTC 24
Finished Sep 18 09:02:40 PM UTC 24
Peak memory 215100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321558706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.321558706
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.1939344330
Short name T54
Test name
Test status
Simulation time 3241052146 ps
CPU time 85.1 seconds
Started Sep 18 09:02:40 PM UTC 24
Finished Sep 18 09:04:08 PM UTC 24
Peak memory 278252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939344330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1939344330
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.2777863271
Short name T81
Test name
Test status
Simulation time 26244940338 ps
CPU time 49.18 seconds
Started Sep 18 09:02:41 PM UTC 24
Finished Sep 18 09:03:32 PM UTC 24
Peak memory 229924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777863271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.2777863271
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.436106520
Short name T13
Test name
Test status
Simulation time 142276636 ps
CPU time 3.99 seconds
Started Sep 18 09:02:40 PM UTC 24
Finished Sep 18 09:02:46 PM UTC 24
Peak memory 235112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436106520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.436106520
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.2519255158
Short name T104
Test name
Test status
Simulation time 9666100409 ps
CPU time 26.2 seconds
Started Sep 18 09:02:39 PM UTC 24
Finished Sep 18 09:03:08 PM UTC 24
Peak memory 235300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519255158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2519255158
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.2253318072
Short name T241
Test name
Test status
Simulation time 21901122752 ps
CPU time 51.35 seconds
Started Sep 18 09:02:39 PM UTC 24
Finished Sep 18 09:03:33 PM UTC 24
Peak memory 251696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253318072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2253318072
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.445713973
Short name T16
Test name
Test status
Simulation time 5143069959 ps
CPU time 7.49 seconds
Started Sep 18 09:02:39 PM UTC 24
Finished Sep 18 09:02:49 PM UTC 24
Peak memory 235168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445713973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.445713973
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.1684754520
Short name T15
Test name
Test status
Simulation time 397810289 ps
CPU time 5.35 seconds
Started Sep 18 09:02:39 PM UTC 24
Finished Sep 18 09:02:47 PM UTC 24
Peak memory 235036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684754520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1684754520
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.913643281
Short name T1
Test name
Test status
Simulation time 14070613 ps
CPU time 0.87 seconds
Started Sep 18 09:02:38 PM UTC 24
Finished Sep 18 09:02:40 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913643281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.913643281
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.4222040131
Short name T7
Test name
Test status
Simulation time 46891351 ps
CPU time 1.39 seconds
Started Sep 18 09:02:39 PM UTC 24
Finished Sep 18 09:02:43 PM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222040131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4222040131
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.2191860005
Short name T5
Test name
Test status
Simulation time 67655314 ps
CPU time 0.82 seconds
Started Sep 18 09:02:38 PM UTC 24
Finished Sep 18 09:02:41 PM UTC 24
Peak memory 215100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191860005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2191860005
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.2374928800
Short name T62
Test name
Test status
Simulation time 19837841652 ps
CPU time 21.22 seconds
Started Sep 18 09:02:39 PM UTC 24
Finished Sep 18 09:03:03 PM UTC 24
Peak memory 245476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374928800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2374928800
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/0.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.1736400029
Short name T39
Test name
Test status
Simulation time 14919340 ps
CPU time 1.12 seconds
Started Sep 18 09:02:48 PM UTC 24
Finished Sep 18 09:02:50 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736400029 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1736400029
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1631737028
Short name T22
Test name
Test status
Simulation time 314784801 ps
CPU time 8.15 seconds
Started Sep 18 09:02:46 PM UTC 24
Finished Sep 18 09:02:55 PM UTC 24
Peak memory 234476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631737028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1631737028
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.3726452269
Short name T8
Test name
Test status
Simulation time 111252870 ps
CPU time 0.88 seconds
Started Sep 18 09:02:42 PM UTC 24
Finished Sep 18 09:02:44 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726452269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3726452269
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.2034724453
Short name T80
Test name
Test status
Simulation time 1738370350 ps
CPU time 40.07 seconds
Started Sep 18 09:02:47 PM UTC 24
Finished Sep 18 09:03:29 PM UTC 24
Peak memory 229740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034724453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2034724453
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.867170280
Short name T21
Test name
Test status
Simulation time 6334958930 ps
CPU time 9.19 seconds
Started Sep 18 09:02:44 PM UTC 24
Finished Sep 18 09:02:54 PM UTC 24
Peak memory 235164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867170280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.867170280
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.4080109351
Short name T83
Test name
Test status
Simulation time 907859415 ps
CPU time 13.31 seconds
Started Sep 18 09:02:46 PM UTC 24
Finished Sep 18 09:03:00 PM UTC 24
Peak memory 245416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080109351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.4080109351
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.3790372616
Short name T26
Test name
Test status
Simulation time 46582264 ps
CPU time 1.57 seconds
Started Sep 18 09:02:42 PM UTC 24
Finished Sep 18 09:02:45 PM UTC 24
Peak memory 228264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790372616 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_parity.3790372616
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.3194447741
Short name T23
Test name
Test status
Simulation time 7202831367 ps
CPU time 11.8 seconds
Started Sep 18 09:02:43 PM UTC 24
Finished Sep 18 09:02:57 PM UTC 24
Peak memory 235376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194447741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.3194447741
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.2250901751
Short name T19
Test name
Test status
Simulation time 93940530 ps
CPU time 3.36 seconds
Started Sep 18 09:02:47 PM UTC 24
Finished Sep 18 09:02:51 PM UTC 24
Peak memory 233460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250901751 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.2250901751
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.3201831133
Short name T18
Test name
Test status
Simulation time 130320655 ps
CPU time 1.73 seconds
Started Sep 18 09:02:47 PM UTC 24
Finished Sep 18 09:02:50 PM UTC 24
Peak memory 257652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201831133 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3201831133
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.2847776465
Short name T42
Test name
Test status
Simulation time 160551521543 ps
CPU time 417.98 seconds
Started Sep 18 09:02:47 PM UTC 24
Finished Sep 18 09:09:51 PM UTC 24
Peak memory 264164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847776465 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.2847776465
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.2250352912
Short name T45
Test name
Test status
Simulation time 29524749607 ps
CPU time 26.41 seconds
Started Sep 18 09:02:42 PM UTC 24
Finished Sep 18 09:03:10 PM UTC 24
Peak memory 227944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250352912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2250352912
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.1191157515
Short name T11
Test name
Test status
Simulation time 14436572 ps
CPU time 1.26 seconds
Started Sep 18 09:02:42 PM UTC 24
Finished Sep 18 09:02:45 PM UTC 24
Peak memory 216836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191157515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1191157515
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.3762932933
Short name T10
Test name
Test status
Simulation time 522768565 ps
CPU time 1.41 seconds
Started Sep 18 09:02:42 PM UTC 24
Finished Sep 18 09:02:45 PM UTC 24
Peak memory 215100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762932933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3762932933
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/1.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.625024681
Short name T449
Test name
Test status
Simulation time 11293330 ps
CPU time 1.06 seconds
Started Sep 18 09:05:58 PM UTC 24
Finished Sep 18 09:06:00 PM UTC 24
Peak memory 213044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625024681 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.625024681
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.383920716
Short name T300
Test name
Test status
Simulation time 239147882 ps
CPU time 3.6 seconds
Started Sep 18 09:05:49 PM UTC 24
Finished Sep 18 09:05:54 PM UTC 24
Peak memory 245412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383920716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.383920716
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.2986187882
Short name T439
Test name
Test status
Simulation time 23406070 ps
CPU time 1.1 seconds
Started Sep 18 09:05:42 PM UTC 24
Finished Sep 18 09:05:44 PM UTC 24
Peak memory 215160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986187882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2986187882
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.684711651
Short name T445
Test name
Test status
Simulation time 12716279 ps
CPU time 1.09 seconds
Started Sep 18 09:05:55 PM UTC 24
Finished Sep 18 09:05:57 PM UTC 24
Peak memory 225972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684711651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.684711651
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.606781449
Short name T273
Test name
Test status
Simulation time 81695004897 ps
CPU time 187.68 seconds
Started Sep 18 09:05:55 PM UTC 24
Finished Sep 18 09:09:06 PM UTC 24
Peak memory 266028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606781449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.606781449
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.3080968527
Short name T451
Test name
Test status
Simulation time 637393328 ps
CPU time 11.13 seconds
Started Sep 18 09:05:51 PM UTC 24
Finished Sep 18 09:06:03 PM UTC 24
Peak memory 261740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080968527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3080968527
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.2980212606
Short name T221
Test name
Test status
Simulation time 2052224414 ps
CPU time 28.2 seconds
Started Sep 18 09:05:52 PM UTC 24
Finished Sep 18 09:06:21 PM UTC 24
Peak memory 251612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980212606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.2980212606
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.1435105267
Short name T265
Test name
Test status
Simulation time 3340394058 ps
CPU time 21.29 seconds
Started Sep 18 09:05:46 PM UTC 24
Finished Sep 18 09:06:09 PM UTC 24
Peak memory 245484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435105267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1435105267
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.3696977945
Short name T444
Test name
Test status
Simulation time 74679403 ps
CPU time 3 seconds
Started Sep 18 09:05:47 PM UTC 24
Finished Sep 18 09:05:51 PM UTC 24
Peak memory 234292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696977945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3696977945
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.444733573
Short name T440
Test name
Test status
Simulation time 26960895 ps
CPU time 1.56 seconds
Started Sep 18 09:05:43 PM UTC 24
Finished Sep 18 09:05:46 PM UTC 24
Peak memory 228260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444733573 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mem_parity.444733573
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.174214146
Short name T74
Test name
Test status
Simulation time 696203729 ps
CPU time 10.03 seconds
Started Sep 18 09:05:45 PM UTC 24
Finished Sep 18 09:05:56 PM UTC 24
Peak memory 245488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174214146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.174214146
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.3048103918
Short name T270
Test name
Test status
Simulation time 298161379 ps
CPU time 7.84 seconds
Started Sep 18 09:05:45 PM UTC 24
Finished Sep 18 09:05:54 PM UTC 24
Peak memory 245404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048103918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3048103918
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.1861983373
Short name T447
Test name
Test status
Simulation time 252347417 ps
CPU time 7.35 seconds
Started Sep 18 09:05:52 PM UTC 24
Finished Sep 18 09:06:00 PM UTC 24
Peak memory 231608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861983373 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.1861983373
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.3387268312
Short name T393
Test name
Test status
Simulation time 1568536896 ps
CPU time 22.41 seconds
Started Sep 18 09:05:45 PM UTC 24
Finished Sep 18 09:06:08 PM UTC 24
Peak memory 227808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387268312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3387268312
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.3023980728
Short name T457
Test name
Test status
Simulation time 24397250378 ps
CPU time 32.24 seconds
Started Sep 18 09:05:45 PM UTC 24
Finished Sep 18 09:06:18 PM UTC 24
Peak memory 227816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023980728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3023980728
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.1985758881
Short name T442
Test name
Test status
Simulation time 83443524 ps
CPU time 2.4 seconds
Started Sep 18 09:05:45 PM UTC 24
Finished Sep 18 09:05:48 PM UTC 24
Peak memory 227684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985758881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1985758881
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.4038303991
Short name T441
Test name
Test status
Simulation time 140909440 ps
CPU time 1.28 seconds
Started Sep 18 09:05:45 PM UTC 24
Finished Sep 18 09:05:47 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038303991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.4038303991
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.3966029161
Short name T297
Test name
Test status
Simulation time 1023010257 ps
CPU time 7.86 seconds
Started Sep 18 09:05:48 PM UTC 24
Finished Sep 18 09:05:57 PM UTC 24
Peak memory 240116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966029161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3966029161
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/10.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.1557703002
Short name T456
Test name
Test status
Simulation time 26082348 ps
CPU time 1.08 seconds
Started Sep 18 09:06:16 PM UTC 24
Finished Sep 18 09:06:18 PM UTC 24
Peak memory 213048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557703002 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.1557703002
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.2355792880
Short name T321
Test name
Test status
Simulation time 1502733021 ps
CPU time 19.22 seconds
Started Sep 18 09:06:08 PM UTC 24
Finished Sep 18 09:06:29 PM UTC 24
Peak memory 245412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355792880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2355792880
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.458854039
Short name T448
Test name
Test status
Simulation time 25983825 ps
CPU time 1.09 seconds
Started Sep 18 09:05:58 PM UTC 24
Finished Sep 18 09:06:00 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458854039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.458854039
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.2113654247
Short name T253
Test name
Test status
Simulation time 124788509933 ps
CPU time 243.61 seconds
Started Sep 18 09:06:12 PM UTC 24
Finished Sep 18 09:10:20 PM UTC 24
Peak memory 266020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113654247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2113654247
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.3718200076
Short name T247
Test name
Test status
Simulation time 3401192055 ps
CPU time 77.22 seconds
Started Sep 18 09:06:14 PM UTC 24
Finished Sep 18 09:07:33 PM UTC 24
Peak memory 264036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718200076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3718200076
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.2845241070
Short name T455
Test name
Test status
Simulation time 759451671 ps
CPU time 5.12 seconds
Started Sep 18 09:06:09 PM UTC 24
Finished Sep 18 09:06:16 PM UTC 24
Peak memory 235112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845241070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2845241070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.965157872
Short name T240
Test name
Test status
Simulation time 6167525094 ps
CPU time 106.35 seconds
Started Sep 18 09:06:09 PM UTC 24
Finished Sep 18 09:07:58 PM UTC 24
Peak memory 251688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965157872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.965157872
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.323369195
Short name T245
Test name
Test status
Simulation time 1366879470 ps
CPU time 8.24 seconds
Started Sep 18 09:06:05 PM UTC 24
Finished Sep 18 09:06:14 PM UTC 24
Peak memory 235032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323369195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.323369195
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.3149669991
Short name T271
Test name
Test status
Simulation time 3343328509 ps
CPU time 30.92 seconds
Started Sep 18 09:06:05 PM UTC 24
Finished Sep 18 09:06:37 PM UTC 24
Peak memory 247596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149669991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3149669991
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.2252883977
Short name T450
Test name
Test status
Simulation time 43186629 ps
CPU time 1.56 seconds
Started Sep 18 09:05:59 PM UTC 24
Finished Sep 18 09:06:02 PM UTC 24
Peak memory 228260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252883977 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mem_parity.2252883977
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.2804792970
Short name T453
Test name
Test status
Simulation time 73751236 ps
CPU time 3.13 seconds
Started Sep 18 09:06:04 PM UTC 24
Finished Sep 18 09:06:08 PM UTC 24
Peak memory 234372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804792970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.2804792970
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.1433318873
Short name T313
Test name
Test status
Simulation time 3074599267 ps
CPU time 19.96 seconds
Started Sep 18 09:06:03 PM UTC 24
Finished Sep 18 09:06:24 PM UTC 24
Peak memory 235228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433318873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1433318873
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.4276209803
Short name T460
Test name
Test status
Simulation time 5460729177 ps
CPU time 12.71 seconds
Started Sep 18 09:06:09 PM UTC 24
Finished Sep 18 09:06:23 PM UTC 24
Peak memory 233852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276209803 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.4276209803
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.4021231489
Short name T88
Test name
Test status
Simulation time 92447038947 ps
CPU time 867.12 seconds
Started Sep 18 09:06:15 PM UTC 24
Finished Sep 18 09:20:52 PM UTC 24
Peak memory 300840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021231489 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.4021231489
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.2638684256
Short name T401
Test name
Test status
Simulation time 3801529357 ps
CPU time 18.08 seconds
Started Sep 18 09:06:01 PM UTC 24
Finished Sep 18 09:06:21 PM UTC 24
Peak memory 227816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638684256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2638684256
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3456089034
Short name T454
Test name
Test status
Simulation time 3587474697 ps
CPU time 9.82 seconds
Started Sep 18 09:06:01 PM UTC 24
Finished Sep 18 09:06:12 PM UTC 24
Peak memory 227784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456089034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3456089034
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.2103790536
Short name T403
Test name
Test status
Simulation time 54009751 ps
CPU time 1.18 seconds
Started Sep 18 09:06:02 PM UTC 24
Finished Sep 18 09:06:04 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103790536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2103790536
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.1822392159
Short name T452
Test name
Test status
Simulation time 37648061 ps
CPU time 1.32 seconds
Started Sep 18 09:06:02 PM UTC 24
Finished Sep 18 09:06:04 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822392159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1822392159
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.2864410800
Short name T222
Test name
Test status
Simulation time 50446370 ps
CPU time 3.23 seconds
Started Sep 18 09:06:07 PM UTC 24
Finished Sep 18 09:06:11 PM UTC 24
Peak memory 245344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864410800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2864410800
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/11.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.763720441
Short name T466
Test name
Test status
Simulation time 60871188 ps
CPU time 1.09 seconds
Started Sep 18 09:06:38 PM UTC 24
Finished Sep 18 09:06:42 PM UTC 24
Peak memory 213044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763720441 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.763720441
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.269775738
Short name T352
Test name
Test status
Simulation time 2426165868 ps
CPU time 10.59 seconds
Started Sep 18 09:06:28 PM UTC 24
Finished Sep 18 09:06:40 PM UTC 24
Peak memory 245536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269775738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.269775738
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.2099801993
Short name T458
Test name
Test status
Simulation time 15973886 ps
CPU time 1.12 seconds
Started Sep 18 09:06:17 PM UTC 24
Finished Sep 18 09:06:20 PM UTC 24
Peak memory 215160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099801993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2099801993
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_all.3834044948
Short name T248
Test name
Test status
Simulation time 3405132939 ps
CPU time 60.48 seconds
Started Sep 18 09:06:31 PM UTC 24
Finished Sep 18 09:07:33 PM UTC 24
Peak memory 261924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834044948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3834044948
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.632463828
Short name T395
Test name
Test status
Simulation time 29173948840 ps
CPU time 63.81 seconds
Started Sep 18 09:06:32 PM UTC 24
Finished Sep 18 09:07:38 PM UTC 24
Peak memory 229868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632463828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.632463828
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.629023285
Short name T171
Test name
Test status
Simulation time 18371970503 ps
CPU time 226 seconds
Started Sep 18 09:06:36 PM UTC 24
Finished Sep 18 09:10:26 PM UTC 24
Peak memory 268080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629023285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.629023285
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.375447468
Short name T472
Test name
Test status
Simulation time 1847129208 ps
CPU time 17.65 seconds
Started Sep 18 09:06:28 PM UTC 24
Finished Sep 18 09:06:47 PM UTC 24
Peak memory 235116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375447468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.375447468
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.274687129
Short name T465
Test name
Test status
Simulation time 17825870 ps
CPU time 1.22 seconds
Started Sep 18 09:06:29 PM UTC 24
Finished Sep 18 09:06:31 PM UTC 24
Peak memory 225976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274687129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.274687129
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.4060478232
Short name T463
Test name
Test status
Simulation time 673774123 ps
CPU time 3.02 seconds
Started Sep 18 09:06:25 PM UTC 24
Finished Sep 18 09:06:29 PM UTC 24
Peak memory 234320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060478232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.4060478232
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.114211872
Short name T309
Test name
Test status
Simulation time 5586921847 ps
CPU time 11.64 seconds
Started Sep 18 09:06:25 PM UTC 24
Finished Sep 18 09:06:38 PM UTC 24
Peak memory 245552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114211872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.114211872
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.3355044193
Short name T459
Test name
Test status
Simulation time 270568349 ps
CPU time 1.58 seconds
Started Sep 18 09:06:17 PM UTC 24
Finished Sep 18 09:06:20 PM UTC 24
Peak memory 228260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355044193 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mem_parity.3355044193
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.1484843296
Short name T280
Test name
Test status
Simulation time 18891884126 ps
CPU time 20.27 seconds
Started Sep 18 09:06:23 PM UTC 24
Finished Sep 18 09:06:45 PM UTC 24
Peak memory 251676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484843296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.1484843296
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.2506807661
Short name T230
Test name
Test status
Simulation time 1179649989 ps
CPU time 15.01 seconds
Started Sep 18 09:06:23 PM UTC 24
Finished Sep 18 09:06:39 PM UTC 24
Peak memory 235044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506807661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2506807661
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.3789412877
Short name T473
Test name
Test status
Simulation time 2982786073 ps
CPU time 19.08 seconds
Started Sep 18 09:06:30 PM UTC 24
Finished Sep 18 09:06:50 PM UTC 24
Peak memory 231780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789412877 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.3789412877
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.1322925768
Short name T190
Test name
Test status
Simulation time 293338305 ps
CPU time 1.76 seconds
Started Sep 18 09:06:38 PM UTC 24
Finished Sep 18 09:06:42 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322925768 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.1322925768
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.418193662
Short name T402
Test name
Test status
Simulation time 2825712624 ps
CPU time 39.57 seconds
Started Sep 18 09:06:19 PM UTC 24
Finished Sep 18 09:07:01 PM UTC 24
Peak memory 227948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418193662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.418193662
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.959143198
Short name T464
Test name
Test status
Simulation time 741427290 ps
CPU time 9.37 seconds
Started Sep 18 09:06:19 PM UTC 24
Finished Sep 18 09:06:31 PM UTC 24
Peak memory 227624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959143198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.959143198
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.4180431703
Short name T462
Test name
Test status
Simulation time 280210546 ps
CPU time 3.8 seconds
Started Sep 18 09:06:21 PM UTC 24
Finished Sep 18 09:06:27 PM UTC 24
Peak memory 227876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180431703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.4180431703
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.451720155
Short name T461
Test name
Test status
Simulation time 746924150 ps
CPU time 1.45 seconds
Started Sep 18 09:06:20 PM UTC 24
Finished Sep 18 09:06:24 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451720155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.451720155
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.3687466341
Short name T474
Test name
Test status
Simulation time 10655859800 ps
CPU time 31.92 seconds
Started Sep 18 09:06:25 PM UTC 24
Finished Sep 18 09:06:58 PM UTC 24
Peak memory 235304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687466341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3687466341
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/12.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_alert_test.1158491593
Short name T476
Test name
Test status
Simulation time 100232045 ps
CPU time 1.1 seconds
Started Sep 18 09:07:00 PM UTC 24
Finished Sep 18 09:07:02 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158491593 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.1158491593
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_cfg_cmd.1248758180
Short name T311
Test name
Test status
Simulation time 1092820715 ps
CPU time 10.41 seconds
Started Sep 18 09:06:47 PM UTC 24
Finished Sep 18 09:06:59 PM UTC 24
Peak memory 235172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248758180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1248758180
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.3292740146
Short name T467
Test name
Test status
Simulation time 16630316 ps
CPU time 1.17 seconds
Started Sep 18 09:06:41 PM UTC 24
Finished Sep 18 09:06:43 PM UTC 24
Peak memory 215100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292740146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3292740146
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.4207888761
Short name T511
Test name
Test status
Simulation time 10750349578 ps
CPU time 62.86 seconds
Started Sep 18 09:06:57 PM UTC 24
Finished Sep 18 09:08:01 PM UTC 24
Peak memory 261940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207888761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.4207888761
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.3816700075
Short name T168
Test name
Test status
Simulation time 93539640069 ps
CPU time 154.96 seconds
Started Sep 18 09:06:58 PM UTC 24
Finished Sep 18 09:09:36 PM UTC 24
Peak memory 253800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816700075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3816700075
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode.505227654
Short name T387
Test name
Test status
Simulation time 746241865 ps
CPU time 15.38 seconds
Started Sep 18 09:06:51 PM UTC 24
Finished Sep 18 09:07:08 PM UTC 24
Peak memory 245416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505227654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.505227654
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.777717874
Short name T705
Test name
Test status
Simulation time 122726222861 ps
CPU time 360.86 seconds
Started Sep 18 09:06:52 PM UTC 24
Finished Sep 18 09:12:57 PM UTC 24
Peak memory 263924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777717874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.777717874
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_intercept.2523790015
Short name T315
Test name
Test status
Simulation time 758886819 ps
CPU time 7.38 seconds
Started Sep 18 09:06:47 PM UTC 24
Finished Sep 18 09:06:56 PM UTC 24
Peak memory 245360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523790015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2523790015
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mailbox.2141879006
Short name T478
Test name
Test status
Simulation time 3493290602 ps
CPU time 16.18 seconds
Started Sep 18 09:06:47 PM UTC 24
Finished Sep 18 09:07:05 PM UTC 24
Peak memory 235184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141879006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2141879006
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.2707763663
Short name T468
Test name
Test status
Simulation time 23515328 ps
CPU time 1.54 seconds
Started Sep 18 09:06:41 PM UTC 24
Finished Sep 18 09:06:43 PM UTC 24
Peak memory 228260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707763663 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mem_parity.2707763663
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.1958039199
Short name T338
Test name
Test status
Simulation time 989806765 ps
CPU time 6.69 seconds
Started Sep 18 09:06:45 PM UTC 24
Finished Sep 18 09:06:53 PM UTC 24
Peak memory 235036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958039199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.1958039199
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.853378535
Short name T234
Test name
Test status
Simulation time 1009758015 ps
CPU time 10.25 seconds
Started Sep 18 09:06:45 PM UTC 24
Finished Sep 18 09:06:56 PM UTC 24
Peak memory 245356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853378535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.853378535
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.2234263593
Short name T475
Test name
Test status
Simulation time 733942506 ps
CPU time 7 seconds
Started Sep 18 09:06:54 PM UTC 24
Finished Sep 18 09:07:02 PM UTC 24
Peak memory 231528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234263593 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.2234263593
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_all.1134872499
Short name T470
Test name
Test status
Simulation time 116906571 ps
CPU time 2.52 seconds
Started Sep 18 09:06:43 PM UTC 24
Finished Sep 18 09:06:46 PM UTC 24
Peak memory 227828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134872499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1134872499
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.593587008
Short name T485
Test name
Test status
Simulation time 11046775466 ps
CPU time 34.77 seconds
Started Sep 18 09:06:43 PM UTC 24
Finished Sep 18 09:07:19 PM UTC 24
Peak memory 227892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593587008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.593587008
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.733201179
Short name T471
Test name
Test status
Simulation time 196943168 ps
CPU time 1.69 seconds
Started Sep 18 09:06:44 PM UTC 24
Finished Sep 18 09:06:47 PM UTC 24
Peak memory 226616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733201179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.733201179
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.880745751
Short name T469
Test name
Test status
Simulation time 27639545 ps
CPU time 1.09 seconds
Started Sep 18 09:06:44 PM UTC 24
Finished Sep 18 09:06:46 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880745751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.880745751
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/13.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_alert_test.754668675
Short name T486
Test name
Test status
Simulation time 26020774 ps
CPU time 1.11 seconds
Started Sep 18 09:07:22 PM UTC 24
Finished Sep 18 09:07:24 PM UTC 24
Peak memory 215156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754668675 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.754668675
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_cfg_cmd.127949068
Short name T351
Test name
Test status
Simulation time 188798707 ps
CPU time 3.97 seconds
Started Sep 18 09:07:17 PM UTC 24
Finished Sep 18 09:07:22 PM UTC 24
Peak memory 235060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127949068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.127949068
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_csb_read.827530283
Short name T477
Test name
Test status
Simulation time 72501002 ps
CPU time 1.2 seconds
Started Sep 18 09:07:02 PM UTC 24
Finished Sep 18 09:07:04 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827530283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.827530283
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_all.2215744818
Short name T170
Test name
Test status
Simulation time 9614858812 ps
CPU time 136.09 seconds
Started Sep 18 09:07:20 PM UTC 24
Finished Sep 18 09:09:38 PM UTC 24
Peak memory 268004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215744818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2215744818
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.1874349457
Short name T263
Test name
Test status
Simulation time 23274936086 ps
CPU time 205.64 seconds
Started Sep 18 09:07:20 PM UTC 24
Finished Sep 18 09:10:49 PM UTC 24
Peak memory 266080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874349457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1874349457
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.3935804885
Short name T43
Test name
Test status
Simulation time 26415702014 ps
CPU time 297.09 seconds
Started Sep 18 09:07:22 PM UTC 24
Finished Sep 18 09:12:23 PM UTC 24
Peak memory 266092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935804885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.3935804885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode.1386775200
Short name T494
Test name
Test status
Simulation time 955066420 ps
CPU time 13.83 seconds
Started Sep 18 09:07:18 PM UTC 24
Finished Sep 18 09:07:33 PM UTC 24
Peak memory 235112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386775200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1386775200
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_intercept.579398254
Short name T252
Test name
Test status
Simulation time 177469494 ps
CPU time 7.02 seconds
Started Sep 18 09:07:09 PM UTC 24
Finished Sep 18 09:07:17 PM UTC 24
Peak memory 245416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579398254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.579398254
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mailbox.1828452896
Short name T482
Test name
Test status
Simulation time 28550600 ps
CPU time 2.72 seconds
Started Sep 18 09:07:11 PM UTC 24
Finished Sep 18 09:07:15 PM UTC 24
Peak memory 234228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828452896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1828452896
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mem_parity.1112456312
Short name T479
Test name
Test status
Simulation time 16275045 ps
CPU time 1.46 seconds
Started Sep 18 09:07:03 PM UTC 24
Finished Sep 18 09:07:06 PM UTC 24
Peak memory 228260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112456312 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mem_parity.1112456312
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.741818907
Short name T483
Test name
Test status
Simulation time 582479945 ps
CPU time 5.77 seconds
Started Sep 18 09:07:09 PM UTC 24
Finished Sep 18 09:07:16 PM UTC 24
Peak memory 235108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741818907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.741818907
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.1742522379
Short name T232
Test name
Test status
Simulation time 1069032568 ps
CPU time 11.34 seconds
Started Sep 18 09:07:08 PM UTC 24
Finished Sep 18 09:07:20 PM UTC 24
Peak memory 235120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742522379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1742522379
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.3412713999
Short name T489
Test name
Test status
Simulation time 404174474 ps
CPU time 6.41 seconds
Started Sep 18 09:07:18 PM UTC 24
Finished Sep 18 09:07:26 PM UTC 24
Peak memory 233716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412713999 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.3412713999
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.2589988459
Short name T191
Test name
Test status
Simulation time 8580112639 ps
CPU time 72.87 seconds
Started Sep 18 09:07:22 PM UTC 24
Finished Sep 18 09:08:37 PM UTC 24
Peak memory 261924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589988459 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.2589988459
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_all.2216773643
Short name T396
Test name
Test status
Simulation time 6336089205 ps
CPU time 22.23 seconds
Started Sep 18 09:07:05 PM UTC 24
Finished Sep 18 09:07:30 PM UTC 24
Peak memory 227880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216773643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2216773643
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.2084038989
Short name T484
Test name
Test status
Simulation time 1108194048 ps
CPU time 13.58 seconds
Started Sep 18 09:07:03 PM UTC 24
Finished Sep 18 09:07:18 PM UTC 24
Peak memory 227728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084038989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2084038989
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_rw.3981981282
Short name T481
Test name
Test status
Simulation time 324927832 ps
CPU time 2.39 seconds
Started Sep 18 09:07:07 PM UTC 24
Finished Sep 18 09:07:11 PM UTC 24
Peak memory 217456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981981282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3981981282
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.2769478563
Short name T480
Test name
Test status
Simulation time 44256061 ps
CPU time 1.17 seconds
Started Sep 18 09:07:06 PM UTC 24
Finished Sep 18 09:07:08 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769478563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2769478563
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_upload.3938774224
Short name T324
Test name
Test status
Simulation time 2846136642 ps
CPU time 14.85 seconds
Started Sep 18 09:07:16 PM UTC 24
Finished Sep 18 09:07:32 PM UTC 24
Peak memory 235164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938774224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3938774224
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/14.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_alert_test.3722516295
Short name T496
Test name
Test status
Simulation time 12805902 ps
CPU time 1.13 seconds
Started Sep 18 09:07:35 PM UTC 24
Finished Sep 18 09:07:38 PM UTC 24
Peak memory 213048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722516295 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.3722516295
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_cfg_cmd.236025871
Short name T320
Test name
Test status
Simulation time 535544658 ps
CPU time 2.94 seconds
Started Sep 18 09:07:31 PM UTC 24
Finished Sep 18 09:07:35 PM UTC 24
Peak memory 235100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236025871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.236025871
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_csb_read.477478756
Short name T487
Test name
Test status
Simulation time 287186309 ps
CPU time 1.22 seconds
Started Sep 18 09:07:23 PM UTC 24
Finished Sep 18 09:07:25 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477478756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.477478756
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_all.876111877
Short name T224
Test name
Test status
Simulation time 2019417841 ps
CPU time 39.03 seconds
Started Sep 18 09:07:34 PM UTC 24
Finished Sep 18 09:08:15 PM UTC 24
Peak memory 266028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876111877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.876111877
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.3672088757
Short name T406
Test name
Test status
Simulation time 5247530706 ps
CPU time 31.21 seconds
Started Sep 18 09:07:34 PM UTC 24
Finished Sep 18 09:08:07 PM UTC 24
Peak memory 229884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672088757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3672088757
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.1905218276
Short name T575
Test name
Test status
Simulation time 30040508565 ps
CPU time 157.85 seconds
Started Sep 18 09:07:34 PM UTC 24
Finished Sep 18 09:10:15 PM UTC 24
Peak memory 261928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905218276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.1905218276
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode.3870806029
Short name T278
Test name
Test status
Simulation time 1398184590 ps
CPU time 19.6 seconds
Started Sep 18 09:07:31 PM UTC 24
Finished Sep 18 09:07:52 PM UTC 24
Peak memory 245344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870806029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3870806029
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.1033273906
Short name T340
Test name
Test status
Simulation time 17778501323 ps
CPU time 16.56 seconds
Started Sep 18 09:07:33 PM UTC 24
Finished Sep 18 09:07:51 PM UTC 24
Peak memory 251752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033273906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.1033273906
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_intercept.4207570478
Short name T493
Test name
Test status
Simulation time 32357982 ps
CPU time 2.59 seconds
Started Sep 18 09:07:28 PM UTC 24
Finished Sep 18 09:07:32 PM UTC 24
Peak memory 245148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207570478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.4207570478
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mailbox.987805026
Short name T261
Test name
Test status
Simulation time 861502189 ps
CPU time 9.44 seconds
Started Sep 18 09:07:29 PM UTC 24
Finished Sep 18 09:07:39 PM UTC 24
Peak memory 245124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987805026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.987805026
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mem_parity.2259159678
Short name T488
Test name
Test status
Simulation time 25983520 ps
CPU time 1.52 seconds
Started Sep 18 09:07:23 PM UTC 24
Finished Sep 18 09:07:26 PM UTC 24
Peak memory 228260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259159678 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mem_parity.2259159678
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.1774614521
Short name T329
Test name
Test status
Simulation time 1242786809 ps
CPU time 9.24 seconds
Started Sep 18 09:07:27 PM UTC 24
Finished Sep 18 09:07:38 PM UTC 24
Peak memory 235088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774614521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.1774614521
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.1819518240
Short name T262
Test name
Test status
Simulation time 431119133 ps
CPU time 12.04 seconds
Started Sep 18 09:07:26 PM UTC 24
Finished Sep 18 09:07:40 PM UTC 24
Peak memory 245344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819518240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1819518240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.4240742869
Short name T499
Test name
Test status
Simulation time 972968988 ps
CPU time 6.6 seconds
Started Sep 18 09:07:33 PM UTC 24
Finished Sep 18 09:07:41 PM UTC 24
Peak memory 233780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240742869 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.4240742869
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_stress_all.3000416820
Short name T266
Test name
Test status
Simulation time 115556369483 ps
CPU time 336.18 seconds
Started Sep 18 09:07:35 PM UTC 24
Finished Sep 18 09:13:17 PM UTC 24
Peak memory 266088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000416820 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.3000416820
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_all.762903717
Short name T490
Test name
Test status
Simulation time 35411960 ps
CPU time 1.08 seconds
Started Sep 18 09:07:25 PM UTC 24
Finished Sep 18 09:07:28 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762903717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.762903717
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.3361740116
Short name T501
Test name
Test status
Simulation time 20198767477 ps
CPU time 24.2 seconds
Started Sep 18 09:07:24 PM UTC 24
Finished Sep 18 09:07:50 PM UTC 24
Peak memory 227896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361740116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3361740116
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_rw.3472187074
Short name T492
Test name
Test status
Simulation time 94191851 ps
CPU time 1.88 seconds
Started Sep 18 09:07:26 PM UTC 24
Finished Sep 18 09:07:29 PM UTC 24
Peak memory 226628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472187074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3472187074
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.2753703822
Short name T491
Test name
Test status
Simulation time 21341263 ps
CPU time 1.22 seconds
Started Sep 18 09:07:25 PM UTC 24
Finished Sep 18 09:07:28 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753703822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2753703822
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_upload.2457945885
Short name T495
Test name
Test status
Simulation time 248654979 ps
CPU time 5.01 seconds
Started Sep 18 09:07:31 PM UTC 24
Finished Sep 18 09:07:37 PM UTC 24
Peak memory 235036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457945885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2457945885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/15.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_alert_test.1975073366
Short name T505
Test name
Test status
Simulation time 37879187 ps
CPU time 1.09 seconds
Started Sep 18 09:07:53 PM UTC 24
Finished Sep 18 09:07:55 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975073366 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.1975073366
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_cfg_cmd.1902401976
Short name T298
Test name
Test status
Simulation time 411596369 ps
CPU time 3.18 seconds
Started Sep 18 09:07:44 PM UTC 24
Finished Sep 18 09:07:49 PM UTC 24
Peak memory 235176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902401976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1902401976
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_csb_read.3499416369
Short name T497
Test name
Test status
Simulation time 25444891 ps
CPU time 1.23 seconds
Started Sep 18 09:07:38 PM UTC 24
Finished Sep 18 09:07:40 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499416369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3499416369
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_all.3486652702
Short name T537
Test name
Test status
Simulation time 47415992133 ps
CPU time 70.58 seconds
Started Sep 18 09:07:52 PM UTC 24
Finished Sep 18 09:09:04 PM UTC 24
Peak memory 251628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486652702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3486652702
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.2915076619
Short name T717
Test name
Test status
Simulation time 71994545716 ps
CPU time 320.67 seconds
Started Sep 18 09:07:52 PM UTC 24
Finished Sep 18 09:13:17 PM UTC 24
Peak memory 261932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915076619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2915076619
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.570738595
Short name T531
Test name
Test status
Simulation time 8274309093 ps
CPU time 48.6 seconds
Started Sep 18 09:07:52 PM UTC 24
Finished Sep 18 09:08:42 PM UTC 24
Peak memory 264048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570738595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.570738595
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode.3238295742
Short name T513
Test name
Test status
Simulation time 2877566559 ps
CPU time 12.05 seconds
Started Sep 18 09:07:50 PM UTC 24
Finished Sep 18 09:08:03 PM UTC 24
Peak memory 235300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238295742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3238295742
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.2079830054
Short name T538
Test name
Test status
Simulation time 2230765825 ps
CPU time 74.45 seconds
Started Sep 18 09:07:50 PM UTC 24
Finished Sep 18 09:09:06 PM UTC 24
Peak memory 267940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079830054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.2079830054
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_intercept.589107672
Short name T238
Test name
Test status
Simulation time 590837946 ps
CPU time 6.95 seconds
Started Sep 18 09:07:41 PM UTC 24
Finished Sep 18 09:07:49 PM UTC 24
Peak memory 235040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589107672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.589107672
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mailbox.3671230108
Short name T343
Test name
Test status
Simulation time 11915610231 ps
CPU time 26.66 seconds
Started Sep 18 09:07:42 PM UTC 24
Finished Sep 18 09:08:10 PM UTC 24
Peak memory 235244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671230108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3671230108
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mem_parity.1073643913
Short name T498
Test name
Test status
Simulation time 100954898 ps
CPU time 1.48 seconds
Started Sep 18 09:07:38 PM UTC 24
Finished Sep 18 09:07:40 PM UTC 24
Peak memory 228260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073643913 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mem_parity.1073643913
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.1095103618
Short name T284
Test name
Test status
Simulation time 2057933518 ps
CPU time 15.68 seconds
Started Sep 18 09:07:41 PM UTC 24
Finished Sep 18 09:07:58 PM UTC 24
Peak memory 235116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095103618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.1095103618
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.3309604552
Short name T322
Test name
Test status
Simulation time 6421253810 ps
CPU time 11.4 seconds
Started Sep 18 09:07:41 PM UTC 24
Finished Sep 18 09:07:54 PM UTC 24
Peak memory 235432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309604552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3309604552
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.2831412948
Short name T507
Test name
Test status
Simulation time 779473831 ps
CPU time 5.12 seconds
Started Sep 18 09:07:51 PM UTC 24
Finished Sep 18 09:07:57 PM UTC 24
Peak memory 229560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831412948 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.2831412948
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.3550572322
Short name T193
Test name
Test status
Simulation time 100590951306 ps
CPU time 288.54 seconds
Started Sep 18 09:07:52 PM UTC 24
Finished Sep 18 09:12:45 PM UTC 24
Peak memory 280356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550572322 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.3550572322
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_all.724068580
Short name T404
Test name
Test status
Simulation time 15638347694 ps
CPU time 39.62 seconds
Started Sep 18 09:07:39 PM UTC 24
Finished Sep 18 09:08:20 PM UTC 24
Peak memory 227880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724068580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.724068580
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.3381806416
Short name T502
Test name
Test status
Simulation time 3867394910 ps
CPU time 10.46 seconds
Started Sep 18 09:07:39 PM UTC 24
Finished Sep 18 09:07:50 PM UTC 24
Peak memory 227744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381806416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3381806416
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_rw.2321519799
Short name T405
Test name
Test status
Simulation time 52725943 ps
CPU time 2.42 seconds
Started Sep 18 09:07:40 PM UTC 24
Finished Sep 18 09:07:44 PM UTC 24
Peak memory 217700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321519799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2321519799
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.3082216945
Short name T500
Test name
Test status
Simulation time 123448079 ps
CPU time 1.18 seconds
Started Sep 18 09:07:39 PM UTC 24
Finished Sep 18 09:07:41 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082216945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3082216945
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_upload.3057706084
Short name T503
Test name
Test status
Simulation time 1319994373 ps
CPU time 9.28 seconds
Started Sep 18 09:07:42 PM UTC 24
Finished Sep 18 09:07:53 PM UTC 24
Peak memory 245356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057706084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3057706084
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/16.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_alert_test.3562414557
Short name T516
Test name
Test status
Simulation time 12802544 ps
CPU time 0.99 seconds
Started Sep 18 09:08:18 PM UTC 24
Finished Sep 18 09:08:20 PM UTC 24
Peak memory 212964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562414557 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.3562414557
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_cfg_cmd.2358922409
Short name T515
Test name
Test status
Simulation time 2439321803 ps
CPU time 13.41 seconds
Started Sep 18 09:08:02 PM UTC 24
Finished Sep 18 09:08:17 PM UTC 24
Peak memory 245480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358922409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2358922409
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_csb_read.692036023
Short name T506
Test name
Test status
Simulation time 107228575 ps
CPU time 1.17 seconds
Started Sep 18 09:07:53 PM UTC 24
Finished Sep 18 09:07:56 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692036023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.692036023
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_all.1424569873
Short name T350
Test name
Test status
Simulation time 15535400492 ps
CPU time 25.82 seconds
Started Sep 18 09:08:08 PM UTC 24
Finished Sep 18 09:08:35 PM UTC 24
Peak memory 251688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424569873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1424569873
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.3066325237
Short name T161
Test name
Test status
Simulation time 10889312959 ps
CPU time 68.4 seconds
Started Sep 18 09:08:16 PM UTC 24
Finished Sep 18 09:09:26 PM UTC 24
Peak memory 266156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066325237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.3066325237
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode.2774963333
Short name T388
Test name
Test status
Simulation time 2683742076 ps
CPU time 60.81 seconds
Started Sep 18 09:08:04 PM UTC 24
Finished Sep 18 09:09:06 PM UTC 24
Peak memory 245548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774963333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2774963333
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.1226494472
Short name T639
Test name
Test status
Simulation time 67718255893 ps
CPU time 202.91 seconds
Started Sep 18 09:08:04 PM UTC 24
Finished Sep 18 09:11:30 PM UTC 24
Peak memory 261992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226494472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.1226494472
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_intercept.2511638480
Short name T514
Test name
Test status
Simulation time 94840963 ps
CPU time 3.01 seconds
Started Sep 18 09:07:59 PM UTC 24
Finished Sep 18 09:08:03 PM UTC 24
Peak memory 235168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511638480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2511638480
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mailbox.405796354
Short name T299
Test name
Test status
Simulation time 833448582 ps
CPU time 21.68 seconds
Started Sep 18 09:08:00 PM UTC 24
Finished Sep 18 09:08:23 PM UTC 24
Peak memory 245300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405796354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.405796354
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mem_parity.1843374037
Short name T508
Test name
Test status
Simulation time 26054295 ps
CPU time 1.58 seconds
Started Sep 18 09:07:55 PM UTC 24
Finished Sep 18 09:07:57 PM UTC 24
Peak memory 228260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843374037 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mem_parity.1843374037
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.2125034444
Short name T332
Test name
Test status
Simulation time 11515156998 ps
CPU time 18.01 seconds
Started Sep 18 09:07:59 PM UTC 24
Finished Sep 18 09:08:18 PM UTC 24
Peak memory 235312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125034444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.2125034444
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.3516325958
Short name T236
Test name
Test status
Simulation time 153779963681 ps
CPU time 46.15 seconds
Started Sep 18 09:07:58 PM UTC 24
Finished Sep 18 09:08:46 PM UTC 24
Peak memory 245468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516325958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3516325958
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.660141141
Short name T523
Test name
Test status
Simulation time 3366314151 ps
CPU time 20.72 seconds
Started Sep 18 09:08:04 PM UTC 24
Finished Sep 18 09:08:26 PM UTC 24
Peak memory 233904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660141141 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.660141141
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_stress_all.2566472424
Short name T570
Test name
Test status
Simulation time 53700313405 ps
CPU time 105.57 seconds
Started Sep 18 09:08:18 PM UTC 24
Finished Sep 18 09:10:06 PM UTC 24
Peak memory 235212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566472424 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.2566472424
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_all.2407359492
Short name T392
Test name
Test status
Simulation time 1908931381 ps
CPU time 19.71 seconds
Started Sep 18 09:07:57 PM UTC 24
Finished Sep 18 09:08:18 PM UTC 24
Peak memory 227688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407359492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2407359492
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.1895532918
Short name T512
Test name
Test status
Simulation time 1154638644 ps
CPU time 6.64 seconds
Started Sep 18 09:07:55 PM UTC 24
Finished Sep 18 09:08:02 PM UTC 24
Peak memory 227720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895532918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1895532918
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_rw.1817534366
Short name T510
Test name
Test status
Simulation time 41442188 ps
CPU time 1.05 seconds
Started Sep 18 09:07:58 PM UTC 24
Finished Sep 18 09:08:00 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817534366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1817534366
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.355288843
Short name T509
Test name
Test status
Simulation time 104698998 ps
CPU time 1.36 seconds
Started Sep 18 09:07:57 PM UTC 24
Finished Sep 18 09:07:59 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355288843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.355288843
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_upload.758152014
Short name T518
Test name
Test status
Simulation time 8434819523 ps
CPU time 18.24 seconds
Started Sep 18 09:08:01 PM UTC 24
Finished Sep 18 09:08:21 PM UTC 24
Peak memory 251692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758152014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.758152014
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/17.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_alert_test.1841954741
Short name T527
Test name
Test status
Simulation time 40969714 ps
CPU time 1.13 seconds
Started Sep 18 09:08:36 PM UTC 24
Finished Sep 18 09:08:38 PM UTC 24
Peak memory 213048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841954741 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.1841954741
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_cfg_cmd.1957275982
Short name T353
Test name
Test status
Simulation time 495707040 ps
CPU time 4.72 seconds
Started Sep 18 09:08:26 PM UTC 24
Finished Sep 18 09:08:32 PM UTC 24
Peak memory 235096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957275982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1957275982
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_csb_read.1807105997
Short name T517
Test name
Test status
Simulation time 71385942 ps
CPU time 1.17 seconds
Started Sep 18 09:08:18 PM UTC 24
Finished Sep 18 09:08:20 PM UTC 24
Peak memory 215160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807105997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1807105997
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_all.3251856561
Short name T293
Test name
Test status
Simulation time 12094495919 ps
CPU time 48.08 seconds
Started Sep 18 09:08:32 PM UTC 24
Finished Sep 18 09:09:21 PM UTC 24
Peak memory 235220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251856561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3251856561
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.478489323
Short name T310
Test name
Test status
Simulation time 50551049667 ps
CPU time 146.16 seconds
Started Sep 18 09:08:32 PM UTC 24
Finished Sep 18 09:11:01 PM UTC 24
Peak memory 255856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478489323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.478489323
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.577743117
Short name T341
Test name
Test status
Simulation time 65127027298 ps
CPU time 95.04 seconds
Started Sep 18 09:08:33 PM UTC 24
Finished Sep 18 09:10:10 PM UTC 24
Peak memory 245536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577743117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.577743117
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.3433881894
Short name T272
Test name
Test status
Simulation time 6792118859 ps
CPU time 16.3 seconds
Started Sep 18 09:08:30 PM UTC 24
Finished Sep 18 09:08:47 PM UTC 24
Peak memory 251668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433881894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.3433881894
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_intercept.18580165
Short name T319
Test name
Test status
Simulation time 421997850 ps
CPU time 4.95 seconds
Started Sep 18 09:08:25 PM UTC 24
Finished Sep 18 09:08:31 PM UTC 24
Peak memory 245356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18580165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.18580165
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mailbox.3535923042
Short name T323
Test name
Test status
Simulation time 2029786298 ps
CPU time 15.97 seconds
Started Sep 18 09:08:26 PM UTC 24
Finished Sep 18 09:08:43 PM UTC 24
Peak memory 245288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535923042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3535923042
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mem_parity.1370460409
Short name T519
Test name
Test status
Simulation time 40680318 ps
CPU time 1.46 seconds
Started Sep 18 09:08:19 PM UTC 24
Finished Sep 18 09:08:22 PM UTC 24
Peak memory 228260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370460409 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mem_parity.1370460409
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.1573735181
Short name T536
Test name
Test status
Simulation time 6249017543 ps
CPU time 38.2 seconds
Started Sep 18 09:08:23 PM UTC 24
Finished Sep 18 09:09:03 PM UTC 24
Peak memory 245600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573735181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1573735181
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.1258393531
Short name T528
Test name
Test status
Simulation time 1127977622 ps
CPU time 7.65 seconds
Started Sep 18 09:08:30 PM UTC 24
Finished Sep 18 09:08:38 PM UTC 24
Peak memory 231544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258393531 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.1258393531
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.3612200748
Short name T192
Test name
Test status
Simulation time 86577930 ps
CPU time 1.82 seconds
Started Sep 18 09:08:35 PM UTC 24
Finished Sep 18 09:08:38 PM UTC 24
Peak memory 216512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612200748 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.3612200748
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_all.1819611973
Short name T525
Test name
Test status
Simulation time 1889079892 ps
CPU time 6.43 seconds
Started Sep 18 09:08:22 PM UTC 24
Finished Sep 18 09:08:29 PM UTC 24
Peak memory 227700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819611973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1819611973
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.108020254
Short name T522
Test name
Test status
Simulation time 527810348 ps
CPU time 4.01 seconds
Started Sep 18 09:08:20 PM UTC 24
Finished Sep 18 09:08:26 PM UTC 24
Peak memory 227704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108020254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.108020254
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_rw.2565707167
Short name T521
Test name
Test status
Simulation time 132494362 ps
CPU time 2.59 seconds
Started Sep 18 09:08:22 PM UTC 24
Finished Sep 18 09:08:25 PM UTC 24
Peak memory 227748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565707167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2565707167
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.1980215894
Short name T520
Test name
Test status
Simulation time 92920914 ps
CPU time 1.13 seconds
Started Sep 18 09:08:22 PM UTC 24
Finished Sep 18 09:08:24 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980215894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1980215894
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/18.spi_device_upload.2144989857
Short name T303
Test name
Test status
Simulation time 193582810 ps
CPU time 3.32 seconds
Started Sep 18 09:08:26 PM UTC 24
Finished Sep 18 09:08:31 PM UTC 24
Peak memory 245356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144989857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2144989857
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/18.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_alert_test.3581180048
Short name T540
Test name
Test status
Simulation time 83140097 ps
CPU time 1.1 seconds
Started Sep 18 09:09:04 PM UTC 24
Finished Sep 18 09:09:06 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581180048 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.3581180048
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_cfg_cmd.343737702
Short name T535
Test name
Test status
Simulation time 410537704 ps
CPU time 6.36 seconds
Started Sep 18 09:08:46 PM UTC 24
Finished Sep 18 09:08:53 PM UTC 24
Peak memory 245420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343737702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.343737702
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_csb_read.2716606309
Short name T529
Test name
Test status
Simulation time 20904783 ps
CPU time 1.2 seconds
Started Sep 18 09:08:38 PM UTC 24
Finished Sep 18 09:08:40 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716606309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2716606309
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_all.1040641687
Short name T554
Test name
Test status
Simulation time 3264327700 ps
CPU time 49.53 seconds
Started Sep 18 09:08:54 PM UTC 24
Finished Sep 18 09:09:46 PM UTC 24
Peak memory 261860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040641687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1040641687
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.590081242
Short name T573
Test name
Test status
Simulation time 21940424417 ps
CPU time 74.1 seconds
Started Sep 18 09:08:54 PM UTC 24
Finished Sep 18 09:10:10 PM UTC 24
Peak memory 261936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590081242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.590081242
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.1806860885
Short name T542
Test name
Test status
Simulation time 1345527510 ps
CPU time 9.55 seconds
Started Sep 18 09:08:58 PM UTC 24
Finished Sep 18 09:09:08 PM UTC 24
Peak memory 229872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806860885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.1806860885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode.4129103305
Short name T545
Test name
Test status
Simulation time 6710881267 ps
CPU time 24.46 seconds
Started Sep 18 09:08:48 PM UTC 24
Finished Sep 18 09:09:14 PM UTC 24
Peak memory 261868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129103305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.4129103305
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.2791389565
Short name T257
Test name
Test status
Simulation time 12074965887 ps
CPU time 90.42 seconds
Started Sep 18 09:08:48 PM UTC 24
Finished Sep 18 09:10:21 PM UTC 24
Peak memory 278312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791389565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.2791389565
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_intercept.2227986164
Short name T348
Test name
Test status
Simulation time 2726509443 ps
CPU time 25.29 seconds
Started Sep 18 09:08:45 PM UTC 24
Finished Sep 18 09:09:11 PM UTC 24
Peak memory 235276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227986164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2227986164
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mailbox.4286471951
Short name T307
Test name
Test status
Simulation time 449420463 ps
CPU time 8.04 seconds
Started Sep 18 09:08:45 PM UTC 24
Finished Sep 18 09:08:54 PM UTC 24
Peak memory 234896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286471951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.4286471951
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mem_parity.2591029267
Short name T530
Test name
Test status
Simulation time 46659743 ps
CPU time 1.49 seconds
Started Sep 18 09:08:38 PM UTC 24
Finished Sep 18 09:08:41 PM UTC 24
Peak memory 228260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591029267 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mem_parity.2591029267
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.1069453265
Short name T335
Test name
Test status
Simulation time 6020810191 ps
CPU time 16.86 seconds
Started Sep 18 09:08:44 PM UTC 24
Finished Sep 18 09:09:02 PM UTC 24
Peak memory 245540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069453265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.1069453265
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.1263950177
Short name T275
Test name
Test status
Simulation time 2130891098 ps
CPU time 5.52 seconds
Started Sep 18 09:08:43 PM UTC 24
Finished Sep 18 09:08:49 PM UTC 24
Peak memory 235244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263950177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1263950177
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.2413926
Short name T541
Test name
Test status
Simulation time 2403817985 ps
CPU time 16.1 seconds
Started Sep 18 09:08:50 PM UTC 24
Finished Sep 18 09:09:08 PM UTC 24
Peak memory 233776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413926 -assert nopostproc +UVM_TESTNAME=spi_device_base
_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.2413926
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_stress_all.2382240681
Short name T173
Test name
Test status
Simulation time 229830607870 ps
CPU time 1139.69 seconds
Started Sep 18 09:09:03 PM UTC 24
Finished Sep 18 09:28:15 PM UTC 24
Peak memory 284452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382240681 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.2382240681
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_all.4272542358
Short name T548
Test name
Test status
Simulation time 34556245218 ps
CPU time 39.42 seconds
Started Sep 18 09:08:39 PM UTC 24
Finished Sep 18 09:09:20 PM UTC 24
Peak memory 227824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272542358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.4272542358
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.3411676981
Short name T534
Test name
Test status
Simulation time 4350254918 ps
CPU time 6.88 seconds
Started Sep 18 09:08:39 PM UTC 24
Finished Sep 18 09:08:47 PM UTC 24
Peak memory 227756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411676981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3411676981
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_rw.2862198930
Short name T533
Test name
Test status
Simulation time 26479582 ps
CPU time 1.15 seconds
Started Sep 18 09:08:42 PM UTC 24
Finished Sep 18 09:08:44 PM UTC 24
Peak memory 215088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862198930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2862198930
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.3379865292
Short name T532
Test name
Test status
Simulation time 42211182 ps
CPU time 1.16 seconds
Started Sep 18 09:08:41 PM UTC 24
Finished Sep 18 09:08:44 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379865292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3379865292
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/19.spi_device_upload.260842063
Short name T301
Test name
Test status
Simulation time 331626600 ps
CPU time 9.52 seconds
Started Sep 18 09:08:46 PM UTC 24
Finished Sep 18 09:08:57 PM UTC 24
Peak memory 235176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260842063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.260842063
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/19.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.976769674
Short name T107
Test name
Test status
Simulation time 26509369 ps
CPU time 1.14 seconds
Started Sep 18 09:03:02 PM UTC 24
Finished Sep 18 09:03:04 PM UTC 24
Peak memory 215156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976769674 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.976769674
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.3895907706
Short name T101
Test name
Test status
Simulation time 2060855766 ps
CPU time 9.29 seconds
Started Sep 18 09:02:55 PM UTC 24
Finished Sep 18 09:03:06 PM UTC 24
Peak memory 235048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895907706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3895907706
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.370819790
Short name T20
Test name
Test status
Simulation time 18404941 ps
CPU time 1.17 seconds
Started Sep 18 09:02:49 PM UTC 24
Finished Sep 18 09:02:52 PM UTC 24
Peak memory 215100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370819790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.370819790
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.1205936852
Short name T65
Test name
Test status
Simulation time 1408571259 ps
CPU time 31.09 seconds
Started Sep 18 09:02:59 PM UTC 24
Finished Sep 18 09:03:31 PM UTC 24
Peak memory 245280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205936852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1205936852
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.462111691
Short name T50
Test name
Test status
Simulation time 265895248 ps
CPU time 6.37 seconds
Started Sep 18 09:02:56 PM UTC 24
Finished Sep 18 09:03:04 PM UTC 24
Peak memory 245356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462111691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.462111691
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.2793915496
Short name T504
Test name
Test status
Simulation time 135866290346 ps
CPU time 291.61 seconds
Started Sep 18 09:02:57 PM UTC 24
Finished Sep 18 09:07:54 PM UTC 24
Peak memory 263924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793915496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.2793915496
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.283161698
Short name T57
Test name
Test status
Simulation time 215988590 ps
CPU time 4.49 seconds
Started Sep 18 09:02:54 PM UTC 24
Finished Sep 18 09:02:59 PM UTC 24
Peak memory 235116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283161698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.283161698
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.3670580189
Short name T244
Test name
Test status
Simulation time 125782666006 ps
CPU time 135.37 seconds
Started Sep 18 09:02:55 PM UTC 24
Finished Sep 18 09:05:13 PM UTC 24
Peak memory 261876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670580189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3670580189
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.439629753
Short name T44
Test name
Test status
Simulation time 42473387 ps
CPU time 1.46 seconds
Started Sep 18 09:02:50 PM UTC 24
Finished Sep 18 09:02:53 PM UTC 24
Peak memory 228264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439629753 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_parity.439629753
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.377713743
Short name T64
Test name
Test status
Simulation time 1175420816 ps
CPU time 9.39 seconds
Started Sep 18 09:02:54 PM UTC 24
Finished Sep 18 09:03:04 PM UTC 24
Peak memory 235096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377713743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.377713743
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.2961944729
Short name T63
Test name
Test status
Simulation time 11658809219 ps
CPU time 15.22 seconds
Started Sep 18 09:02:53 PM UTC 24
Finished Sep 18 09:03:09 PM UTC 24
Peak memory 261932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961944729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2961944729
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.3349518883
Short name T49
Test name
Test status
Simulation time 778077840 ps
CPU time 7.2 seconds
Started Sep 18 09:02:59 PM UTC 24
Finished Sep 18 09:03:07 PM UTC 24
Peak memory 231604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349518883 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.3349518883
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.2931219219
Short name T25
Test name
Test status
Simulation time 96459967 ps
CPU time 1.54 seconds
Started Sep 18 09:03:01 PM UTC 24
Finished Sep 18 09:03:04 PM UTC 24
Peak memory 257652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931219219 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2931219219
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.3877333805
Short name T40
Test name
Test status
Simulation time 28580469 ps
CPU time 1.02 seconds
Started Sep 18 09:02:51 PM UTC 24
Finished Sep 18 09:02:53 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877333805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3877333805
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.1995256134
Short name T30
Test name
Test status
Simulation time 1109220430 ps
CPU time 7.28 seconds
Started Sep 18 09:02:51 PM UTC 24
Finished Sep 18 09:02:59 PM UTC 24
Peak memory 227760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995256134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1995256134
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.1024734852
Short name T28
Test name
Test status
Simulation time 689567540 ps
CPU time 3.4 seconds
Started Sep 18 09:02:53 PM UTC 24
Finished Sep 18 09:02:57 PM UTC 24
Peak memory 227764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024734852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1024734852
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.1272597949
Short name T27
Test name
Test status
Simulation time 76632444 ps
CPU time 1.19 seconds
Started Sep 18 09:02:52 PM UTC 24
Finished Sep 18 09:02:54 PM UTC 24
Peak memory 215100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272597949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1272597949
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.4152304616
Short name T56
Test name
Test status
Simulation time 148776284 ps
CPU time 4.26 seconds
Started Sep 18 09:02:55 PM UTC 24
Finished Sep 18 09:03:01 PM UTC 24
Peak memory 247460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152304616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.4152304616
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/2.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_alert_test.705653855
Short name T524
Test name
Test status
Simulation time 185072353 ps
CPU time 1.1 seconds
Started Sep 18 09:09:26 PM UTC 24
Finished Sep 18 09:09:28 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705653855 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.705653855
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/20.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_cfg_cmd.1694099924
Short name T546
Test name
Test status
Simulation time 137027664 ps
CPU time 3.17 seconds
Started Sep 18 09:09:12 PM UTC 24
Finished Sep 18 09:09:16 PM UTC 24
Peak memory 235028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694099924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1694099924
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/20.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_csb_read.4130487428
Short name T539
Test name
Test status
Simulation time 13433139 ps
CPU time 1.13 seconds
Started Sep 18 09:09:04 PM UTC 24
Finished Sep 18 09:09:06 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130487428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.4130487428
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/20.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_all.2940856687
Short name T672
Test name
Test status
Simulation time 37795899264 ps
CPU time 165.96 seconds
Started Sep 18 09:09:18 PM UTC 24
Finished Sep 18 09:12:07 PM UTC 24
Peak memory 268012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940856687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2940856687
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/20.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.1800920872
Short name T565
Test name
Test status
Simulation time 8990252016 ps
CPU time 38.11 seconds
Started Sep 18 09:09:21 PM UTC 24
Finished Sep 18 09:10:01 PM UTC 24
Peak memory 262116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800920872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1800920872
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.751051564
Short name T384
Test name
Test status
Simulation time 87183138074 ps
CPU time 560.84 seconds
Started Sep 18 09:09:22 PM UTC 24
Finished Sep 18 09:18:50 PM UTC 24
Peak memory 282484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751051564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.751051564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode.2244368787
Short name T390
Test name
Test status
Simulation time 870453200 ps
CPU time 17.86 seconds
Started Sep 18 09:09:12 PM UTC 24
Finished Sep 18 09:09:31 PM UTC 24
Peak memory 245416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244368787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2244368787
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/20.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.4018769425
Short name T333
Test name
Test status
Simulation time 51612073791 ps
CPU time 112.52 seconds
Started Sep 18 09:09:15 PM UTC 24
Finished Sep 18 09:11:10 PM UTC 24
Peak memory 251676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018769425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.4018769425
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_intercept.2201773415
Short name T354
Test name
Test status
Simulation time 1021645462 ps
CPU time 14.87 seconds
Started Sep 18 09:09:09 PM UTC 24
Finished Sep 18 09:09:25 PM UTC 24
Peak memory 235036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201773415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2201773415
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/20.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_mailbox.3487670151
Short name T287
Test name
Test status
Simulation time 2690772903 ps
CPU time 39.31 seconds
Started Sep 18 09:09:10 PM UTC 24
Finished Sep 18 09:09:51 PM UTC 24
Peak memory 235300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487670151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3487670151
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/20.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.343071720
Short name T166
Test name
Test status
Simulation time 4164489749 ps
CPU time 24.68 seconds
Started Sep 18 09:09:07 PM UTC 24
Finished Sep 18 09:09:33 PM UTC 24
Peak memory 245488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343071720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.343071720
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/20.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.4219143535
Short name T557
Test name
Test status
Simulation time 30723280956 ps
CPU time 38.99 seconds
Started Sep 18 09:09:07 PM UTC 24
Finished Sep 18 09:09:48 PM UTC 24
Peak memory 263920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219143535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.4219143535
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/20.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.2675145735
Short name T549
Test name
Test status
Simulation time 654878889 ps
CPU time 5.22 seconds
Started Sep 18 09:09:17 PM UTC 24
Finished Sep 18 09:09:23 PM UTC 24
Peak memory 229496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675145735 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.2675145735
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/20.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_stress_all.261838156
Short name T268
Test name
Test status
Simulation time 26563985241 ps
CPU time 182.87 seconds
Started Sep 18 09:09:24 PM UTC 24
Finished Sep 18 09:12:30 PM UTC 24
Peak memory 268144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261838156 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.261838156
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/20.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_all.565151005
Short name T167
Test name
Test status
Simulation time 17983081835 ps
CPU time 26.54 seconds
Started Sep 18 09:09:06 PM UTC 24
Finished Sep 18 09:09:34 PM UTC 24
Peak memory 227820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565151005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.565151005
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/20.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.3267574769
Short name T544
Test name
Test status
Simulation time 1087010761 ps
CPU time 4.96 seconds
Started Sep 18 09:09:05 PM UTC 24
Finished Sep 18 09:09:11 PM UTC 24
Peak memory 227640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267574769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3267574769
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/20.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_rw.3750412752
Short name T547
Test name
Test status
Simulation time 422829047 ps
CPU time 8.56 seconds
Started Sep 18 09:09:07 PM UTC 24
Finished Sep 18 09:09:17 PM UTC 24
Peak memory 227752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750412752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3750412752
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/20.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.2680732338
Short name T543
Test name
Test status
Simulation time 158789395 ps
CPU time 1.19 seconds
Started Sep 18 09:09:07 PM UTC 24
Finished Sep 18 09:09:10 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680732338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2680732338
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/20.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_upload.467699854
Short name T526
Test name
Test status
Simulation time 9645217341 ps
CPU time 16.52 seconds
Started Sep 18 09:09:11 PM UTC 24
Finished Sep 18 09:09:28 PM UTC 24
Peak memory 251756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467699854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.467699854
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/20.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_alert_test.3546030612
Short name T555
Test name
Test status
Simulation time 39462610 ps
CPU time 1.09 seconds
Started Sep 18 09:09:43 PM UTC 24
Finished Sep 18 09:09:46 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546030612 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.3546030612
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/21.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_cfg_cmd.1131982750
Short name T314
Test name
Test status
Simulation time 753569561 ps
CPU time 3.85 seconds
Started Sep 18 09:09:37 PM UTC 24
Finished Sep 18 09:09:42 PM UTC 24
Peak memory 245296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131982750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1131982750
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/21.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_csb_read.334455291
Short name T163
Test name
Test status
Simulation time 26321203 ps
CPU time 1.11 seconds
Started Sep 18 09:09:28 PM UTC 24
Finished Sep 18 09:09:30 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334455291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.334455291
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/21.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_all.4201657391
Short name T552
Test name
Test status
Simulation time 12865324 ps
CPU time 1.18 seconds
Started Sep 18 09:09:41 PM UTC 24
Finished Sep 18 09:09:43 PM UTC 24
Peak memory 225916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201657391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.4201657391
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/21.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.3843224715
Short name T327
Test name
Test status
Simulation time 4460778471 ps
CPU time 82.67 seconds
Started Sep 18 09:09:41 PM UTC 24
Finished Sep 18 09:11:06 PM UTC 24
Peak memory 251700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843224715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3843224715
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.3303160458
Short name T574
Test name
Test status
Simulation time 6651860367 ps
CPU time 29.73 seconds
Started Sep 18 09:09:41 PM UTC 24
Finished Sep 18 09:10:12 PM UTC 24
Peak memory 230008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303160458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.3303160458
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode.2747813000
Short name T551
Test name
Test status
Simulation time 714863558 ps
CPU time 3.91 seconds
Started Sep 18 09:09:38 PM UTC 24
Finished Sep 18 09:09:43 PM UTC 24
Peak memory 235096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747813000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2747813000
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/21.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.1634567074
Short name T260
Test name
Test status
Simulation time 3984662235 ps
CPU time 38.94 seconds
Started Sep 18 09:09:39 PM UTC 24
Finished Sep 18 09:10:19 PM UTC 24
Peak memory 235244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634567074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.1634567074
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_intercept.1558366415
Short name T226
Test name
Test status
Simulation time 190873583 ps
CPU time 4.48 seconds
Started Sep 18 09:09:33 PM UTC 24
Finished Sep 18 09:09:39 PM UTC 24
Peak memory 235104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558366415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1558366415
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/21.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_mailbox.792443281
Short name T344
Test name
Test status
Simulation time 1350430253 ps
CPU time 7.25 seconds
Started Sep 18 09:09:34 PM UTC 24
Finished Sep 18 09:09:43 PM UTC 24
Peak memory 245360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792443281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.792443281
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/21.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.2279274794
Short name T347
Test name
Test status
Simulation time 665345720 ps
CPU time 10.07 seconds
Started Sep 18 09:09:32 PM UTC 24
Finished Sep 18 09:09:44 PM UTC 24
Peak memory 235036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279274794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.2279274794
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/21.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.1380518704
Short name T564
Test name
Test status
Simulation time 19659824196 ps
CPU time 25.14 seconds
Started Sep 18 09:09:32 PM UTC 24
Finished Sep 18 09:10:00 PM UTC 24
Peak memory 245476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380518704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1380518704
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/21.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.3084644553
Short name T563
Test name
Test status
Simulation time 1257937772 ps
CPU time 16.71 seconds
Started Sep 18 09:09:40 PM UTC 24
Finished Sep 18 09:09:58 PM UTC 24
Peak memory 231608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084644553 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.3084644553
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/21.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_stress_all.2397264865
Short name T553
Test name
Test status
Simulation time 96257101 ps
CPU time 1.49 seconds
Started Sep 18 09:09:42 PM UTC 24
Finished Sep 18 09:09:45 PM UTC 24
Peak memory 216804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397264865 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.2397264865
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/21.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_all.3499039046
Short name T550
Test name
Test status
Simulation time 2414571338 ps
CPU time 9.5 seconds
Started Sep 18 09:09:29 PM UTC 24
Finished Sep 18 09:09:40 PM UTC 24
Peak memory 228020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499039046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3499039046
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/21.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.1387192063
Short name T164
Test name
Test status
Simulation time 92630317 ps
CPU time 1.97 seconds
Started Sep 18 09:09:28 PM UTC 24
Finished Sep 18 09:09:31 PM UTC 24
Peak memory 216628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387192063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1387192063
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/21.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_rw.573093890
Short name T169
Test name
Test status
Simulation time 101480067 ps
CPU time 2.93 seconds
Started Sep 18 09:09:31 PM UTC 24
Finished Sep 18 09:09:36 PM UTC 24
Peak memory 227748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573093890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.573093890
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/21.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.565960831
Short name T165
Test name
Test status
Simulation time 24235491 ps
CPU time 1.12 seconds
Started Sep 18 09:09:29 PM UTC 24
Finished Sep 18 09:09:32 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565960831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.565960831
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/21.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/21.spi_device_upload.3547041640
Short name T290
Test name
Test status
Simulation time 267666202 ps
CPU time 6.87 seconds
Started Sep 18 09:09:35 PM UTC 24
Finished Sep 18 09:09:43 PM UTC 24
Peak memory 235176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547041640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3547041640
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/21.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_alert_test.478679495
Short name T566
Test name
Test status
Simulation time 48462783 ps
CPU time 0.94 seconds
Started Sep 18 09:10:01 PM UTC 24
Finished Sep 18 09:10:03 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478679495 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.478679495
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/22.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_cfg_cmd.876726582
Short name T561
Test name
Test status
Simulation time 265949942 ps
CPU time 3.13 seconds
Started Sep 18 09:09:49 PM UTC 24
Finished Sep 18 09:09:54 PM UTC 24
Peak memory 245356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876726582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.876726582
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/22.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_csb_read.1098746260
Short name T556
Test name
Test status
Simulation time 20174680 ps
CPU time 1.22 seconds
Started Sep 18 09:09:45 PM UTC 24
Finished Sep 18 09:09:47 PM UTC 24
Peak memory 215160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098746260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1098746260
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/22.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_all.4156378445
Short name T616
Test name
Test status
Simulation time 5181157317 ps
CPU time 67.57 seconds
Started Sep 18 09:09:53 PM UTC 24
Finished Sep 18 09:11:02 PM UTC 24
Peak memory 268016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156378445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.4156378445
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/22.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.3145132257
Short name T984
Test name
Test status
Simulation time 388317636771 ps
CPU time 531.38 seconds
Started Sep 18 09:09:55 PM UTC 24
Finished Sep 18 09:18:53 PM UTC 24
Peak memory 266084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145132257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3145132257
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/22.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.2718429597
Short name T648
Test name
Test status
Simulation time 2805041194 ps
CPU time 98.41 seconds
Started Sep 18 09:09:57 PM UTC 24
Finished Sep 18 09:11:38 PM UTC 24
Peak memory 278312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718429597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.2718429597
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode.2030765273
Short name T591
Test name
Test status
Simulation time 18938371780 ps
CPU time 39.49 seconds
Started Sep 18 09:09:49 PM UTC 24
Finished Sep 18 09:10:31 PM UTC 24
Peak memory 261860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030765273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2030765273
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/22.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.3591215996
Short name T609
Test name
Test status
Simulation time 4257437570 ps
CPU time 59.27 seconds
Started Sep 18 09:09:52 PM UTC 24
Finished Sep 18 09:10:53 PM UTC 24
Peak memory 284456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591215996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.3591215996
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_intercept.3772315555
Short name T560
Test name
Test status
Simulation time 120980738 ps
CPU time 3.52 seconds
Started Sep 18 09:09:47 PM UTC 24
Finished Sep 18 09:09:52 PM UTC 24
Peak memory 245352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772315555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3772315555
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/22.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_mailbox.458697318
Short name T569
Test name
Test status
Simulation time 1054236671 ps
CPU time 15.84 seconds
Started Sep 18 09:09:48 PM UTC 24
Finished Sep 18 09:10:06 PM UTC 24
Peak memory 245420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458697318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.458697318
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/22.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.3963872709
Short name T239
Test name
Test status
Simulation time 1596580753 ps
CPU time 11.37 seconds
Started Sep 18 09:09:47 PM UTC 24
Finished Sep 18 09:10:00 PM UTC 24
Peak memory 245320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963872709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.3963872709
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/22.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.748155427
Short name T345
Test name
Test status
Simulation time 641739888 ps
CPU time 11.1 seconds
Started Sep 18 09:09:47 PM UTC 24
Finished Sep 18 09:09:59 PM UTC 24
Peak memory 261868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748155427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.748155427
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/22.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.1485157895
Short name T562
Test name
Test status
Simulation time 1342264208 ps
CPU time 3.32 seconds
Started Sep 18 09:09:52 PM UTC 24
Finished Sep 18 09:09:56 PM UTC 24
Peak memory 231608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485157895 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.1485157895
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/22.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.1717341495
Short name T90
Test name
Test status
Simulation time 96356939711 ps
CPU time 946.6 seconds
Started Sep 18 09:09:58 PM UTC 24
Finished Sep 18 09:25:56 PM UTC 24
Peak memory 294748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717341495 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.1717341495
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/22.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_all.2246589109
Short name T578
Test name
Test status
Simulation time 52151650750 ps
CPU time 30.9 seconds
Started Sep 18 09:09:45 PM UTC 24
Finished Sep 18 09:10:17 PM UTC 24
Peak memory 227956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246589109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2246589109
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/22.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.2987717639
Short name T572
Test name
Test status
Simulation time 32136249680 ps
CPU time 23.32 seconds
Started Sep 18 09:09:45 PM UTC 24
Finished Sep 18 09:10:09 PM UTC 24
Peak memory 227828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987717639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2987717639
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/22.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_rw.2775052053
Short name T559
Test name
Test status
Simulation time 34842990 ps
CPU time 1.3 seconds
Started Sep 18 09:09:46 PM UTC 24
Finished Sep 18 09:09:48 PM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775052053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2775052053
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/22.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.1635978675
Short name T558
Test name
Test status
Simulation time 59712416 ps
CPU time 1.11 seconds
Started Sep 18 09:09:46 PM UTC 24
Finished Sep 18 09:09:48 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635978675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1635978675
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/22.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_upload.3769532054
Short name T577
Test name
Test status
Simulation time 5173802358 ps
CPU time 25.45 seconds
Started Sep 18 09:09:48 PM UTC 24
Finished Sep 18 09:10:15 PM UTC 24
Peak memory 235248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769532054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3769532054
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/22.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_alert_test.4258256391
Short name T581
Test name
Test status
Simulation time 14884573 ps
CPU time 1.13 seconds
Started Sep 18 09:10:19 PM UTC 24
Finished Sep 18 09:10:22 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258256391 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.4258256391
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/23.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_cfg_cmd.1671460433
Short name T582
Test name
Test status
Simulation time 3559141000 ps
CPU time 10.19 seconds
Started Sep 18 09:10:11 PM UTC 24
Finished Sep 18 09:10:22 PM UTC 24
Peak memory 245480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671460433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1671460433
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/23.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_csb_read.279403541
Short name T567
Test name
Test status
Simulation time 53789068 ps
CPU time 1.16 seconds
Started Sep 18 09:10:01 PM UTC 24
Finished Sep 18 09:10:03 PM UTC 24
Peak memory 215004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279403541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.279403541
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/23.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_all.343543110
Short name T880
Test name
Test status
Simulation time 568623245157 ps
CPU time 412 seconds
Started Sep 18 09:10:16 PM UTC 24
Finished Sep 18 09:17:13 PM UTC 24
Peak memory 266032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343543110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.343543110
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/23.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.1593409893
Short name T647
Test name
Test status
Simulation time 9039970588 ps
CPU time 79.4 seconds
Started Sep 18 09:10:16 PM UTC 24
Finished Sep 18 09:11:37 PM UTC 24
Peak memory 245540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593409893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1593409893
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.1305142313
Short name T364
Test name
Test status
Simulation time 23407264977 ps
CPU time 274.3 seconds
Started Sep 18 09:10:17 PM UTC 24
Finished Sep 18 09:14:55 PM UTC 24
Peak memory 261932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305142313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.1305142313
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode.3462834117
Short name T579
Test name
Test status
Simulation time 289872457 ps
CPU time 7.97 seconds
Started Sep 18 09:10:11 PM UTC 24
Finished Sep 18 09:10:20 PM UTC 24
Peak memory 245352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462834117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3462834117
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/23.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.443529855
Short name T728
Test name
Test status
Simulation time 380827673168 ps
CPU time 199.38 seconds
Started Sep 18 09:10:13 PM UTC 24
Finished Sep 18 09:13:36 PM UTC 24
Peak memory 268012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443529855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.443529855
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_intercept.1785224739
Short name T255
Test name
Test status
Simulation time 725241849 ps
CPU time 10.27 seconds
Started Sep 18 09:10:07 PM UTC 24
Finished Sep 18 09:10:18 PM UTC 24
Peak memory 245484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785224739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1785224739
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/23.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_mailbox.2697911813
Short name T601
Test name
Test status
Simulation time 14922890263 ps
CPU time 30.97 seconds
Started Sep 18 09:10:09 PM UTC 24
Finished Sep 18 09:10:41 PM UTC 24
Peak memory 261868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697911813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2697911813
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/23.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.23812309
Short name T355
Test name
Test status
Simulation time 490826090 ps
CPU time 8.07 seconds
Started Sep 18 09:10:07 PM UTC 24
Finished Sep 18 09:10:16 PM UTC 24
Peak memory 245404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23812309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.23812309
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/23.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.468981222
Short name T346
Test name
Test status
Simulation time 1298900679 ps
CPU time 6.06 seconds
Started Sep 18 09:10:07 PM UTC 24
Finished Sep 18 09:10:14 PM UTC 24
Peak memory 235036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468981222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.468981222
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/23.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.2633485536
Short name T584
Test name
Test status
Simulation time 480977657 ps
CPU time 7.65 seconds
Started Sep 18 09:10:15 PM UTC 24
Finished Sep 18 09:10:23 PM UTC 24
Peak memory 231608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633485536 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.2633485536
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/23.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.166595895
Short name T580
Test name
Test status
Simulation time 37485801 ps
CPU time 1.35 seconds
Started Sep 18 09:10:18 PM UTC 24
Finished Sep 18 09:10:20 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166595895 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.166595895
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/23.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_all.567314372
Short name T594
Test name
Test status
Simulation time 4992813645 ps
CPU time 29.86 seconds
Started Sep 18 09:10:02 PM UTC 24
Finished Sep 18 09:10:33 PM UTC 24
Peak memory 227880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567314372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.567314372
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/23.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.3332766990
Short name T588
Test name
Test status
Simulation time 12704813026 ps
CPU time 25.25 seconds
Started Sep 18 09:10:01 PM UTC 24
Finished Sep 18 09:10:27 PM UTC 24
Peak memory 227756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332766990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3332766990
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/23.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_rw.3105736375
Short name T571
Test name
Test status
Simulation time 83771489 ps
CPU time 2.94 seconds
Started Sep 18 09:10:04 PM UTC 24
Finished Sep 18 09:10:08 PM UTC 24
Peak memory 227688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105736375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3105736375
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/23.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.718420277
Short name T568
Test name
Test status
Simulation time 33844471 ps
CPU time 1.08 seconds
Started Sep 18 09:10:03 PM UTC 24
Finished Sep 18 09:10:05 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718420277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.718420277
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/23.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_upload.485222875
Short name T586
Test name
Test status
Simulation time 3090088680 ps
CPU time 13.38 seconds
Started Sep 18 09:10:10 PM UTC 24
Finished Sep 18 09:10:25 PM UTC 24
Peak memory 245544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485222875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.485222875
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/23.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_alert_test.4038378165
Short name T576
Test name
Test status
Simulation time 37806601 ps
CPU time 1.05 seconds
Started Sep 18 09:10:33 PM UTC 24
Finished Sep 18 09:10:35 PM UTC 24
Peak memory 213048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038378165 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.4038378165
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/24.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_cfg_cmd.4061395062
Short name T593
Test name
Test status
Simulation time 189799753 ps
CPU time 5.42 seconds
Started Sep 18 09:10:26 PM UTC 24
Finished Sep 18 09:10:33 PM UTC 24
Peak memory 235044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061395062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.4061395062
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/24.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_csb_read.1340895154
Short name T583
Test name
Test status
Simulation time 20545604 ps
CPU time 1.22 seconds
Started Sep 18 09:10:21 PM UTC 24
Finished Sep 18 09:10:23 PM UTC 24
Peak memory 215160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340895154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1340895154
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/24.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.3851516678
Short name T282
Test name
Test status
Simulation time 3247359227 ps
CPU time 42.42 seconds
Started Sep 18 09:10:29 PM UTC 24
Finished Sep 18 09:11:13 PM UTC 24
Peak memory 266028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851516678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3851516678
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/24.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.2815378115
Short name T328
Test name
Test status
Simulation time 76561482805 ps
CPU time 184.17 seconds
Started Sep 18 09:10:30 PM UTC 24
Finished Sep 18 09:13:37 PM UTC 24
Peak memory 261932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815378115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2815378115
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.1302718296
Short name T899
Test name
Test status
Simulation time 40603393461 ps
CPU time 414.37 seconds
Started Sep 18 09:10:32 PM UTC 24
Finished Sep 18 09:17:32 PM UTC 24
Peak memory 278440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302718296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.1302718296
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.3414121908
Short name T595
Test name
Test status
Simulation time 162590148 ps
CPU time 4.79 seconds
Started Sep 18 09:10:27 PM UTC 24
Finished Sep 18 09:10:33 PM UTC 24
Peak memory 235180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414121908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3414121908
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/24.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.3414375037
Short name T249
Test name
Test status
Simulation time 7550808741 ps
CPU time 32.23 seconds
Started Sep 18 09:10:27 PM UTC 24
Finished Sep 18 09:11:01 PM UTC 24
Peak memory 249576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414375037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.3414375037
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_intercept.3377060008
Short name T606
Test name
Test status
Simulation time 1416847823 ps
CPU time 19.29 seconds
Started Sep 18 09:10:25 PM UTC 24
Finished Sep 18 09:10:45 PM UTC 24
Peak memory 245416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377060008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3377060008
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/24.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_mailbox.335503657
Short name T745
Test name
Test status
Simulation time 55445540673 ps
CPU time 216.43 seconds
Started Sep 18 09:10:25 PM UTC 24
Finished Sep 18 09:14:05 PM UTC 24
Peak memory 261936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335503657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.335503657
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/24.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.931721560
Short name T596
Test name
Test status
Simulation time 1278997901 ps
CPU time 9.07 seconds
Started Sep 18 09:10:23 PM UTC 24
Finished Sep 18 09:10:34 PM UTC 24
Peak memory 235108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931721560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.931721560
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/24.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.2473754370
Short name T587
Test name
Test status
Simulation time 109693853 ps
CPU time 3.12 seconds
Started Sep 18 09:10:22 PM UTC 24
Finished Sep 18 09:10:27 PM UTC 24
Peak memory 245168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473754370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2473754370
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/24.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.2716768265
Short name T602
Test name
Test status
Simulation time 1718013011 ps
CPU time 11.47 seconds
Started Sep 18 09:10:29 PM UTC 24
Finished Sep 18 09:10:41 PM UTC 24
Peak memory 233780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716768265 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.2716768265
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/24.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_stress_all.450214311
Short name T85
Test name
Test status
Simulation time 58809387840 ps
CPU time 330.83 seconds
Started Sep 18 09:10:33 PM UTC 24
Finished Sep 18 09:16:09 PM UTC 24
Peak memory 294756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450214311 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.450214311
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/24.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_all.3843630165
Short name T589
Test name
Test status
Simulation time 303214713 ps
CPU time 4.47 seconds
Started Sep 18 09:10:22 PM UTC 24
Finished Sep 18 09:10:28 PM UTC 24
Peak memory 227824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843630165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3843630165
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/24.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.2403180208
Short name T590
Test name
Test status
Simulation time 777408611 ps
CPU time 6.9 seconds
Started Sep 18 09:10:21 PM UTC 24
Finished Sep 18 09:10:29 PM UTC 24
Peak memory 227720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403180208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2403180208
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/24.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_rw.2004631456
Short name T592
Test name
Test status
Simulation time 535717239 ps
CPU time 8.75 seconds
Started Sep 18 09:10:22 PM UTC 24
Finished Sep 18 09:10:32 PM UTC 24
Peak memory 227704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004631456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2004631456
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/24.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.2049959370
Short name T585
Test name
Test status
Simulation time 114343216 ps
CPU time 1.3 seconds
Started Sep 18 09:10:22 PM UTC 24
Finished Sep 18 09:10:25 PM UTC 24
Peak memory 214896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049959370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2049959370
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/24.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_upload.3556406714
Short name T349
Test name
Test status
Simulation time 8180756995 ps
CPU time 9.32 seconds
Started Sep 18 09:10:26 PM UTC 24
Finished Sep 18 09:10:37 PM UTC 24
Peak memory 235372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556406714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3556406714
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/24.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_alert_test.2983106528
Short name T607
Test name
Test status
Simulation time 40463882 ps
CPU time 1.1 seconds
Started Sep 18 09:10:50 PM UTC 24
Finished Sep 18 09:10:52 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983106528 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.2983106528
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/25.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_cfg_cmd.4210102601
Short name T612
Test name
Test status
Simulation time 976146845 ps
CPU time 12.37 seconds
Started Sep 18 09:10:43 PM UTC 24
Finished Sep 18 09:10:56 PM UTC 24
Peak memory 235152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210102601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.4210102601
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/25.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_csb_read.3640317767
Short name T597
Test name
Test status
Simulation time 15497475 ps
CPU time 1.18 seconds
Started Sep 18 09:10:35 PM UTC 24
Finished Sep 18 09:10:37 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640317767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3640317767
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/25.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_all.2751008874
Short name T337
Test name
Test status
Simulation time 3194387974 ps
CPU time 49.29 seconds
Started Sep 18 09:10:45 PM UTC 24
Finished Sep 18 09:11:36 PM UTC 24
Peak memory 266028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751008874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2751008874
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/25.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.3054446243
Short name T640
Test name
Test status
Simulation time 23982367894 ps
CPU time 42.09 seconds
Started Sep 18 09:10:46 PM UTC 24
Finished Sep 18 09:11:30 PM UTC 24
Peak memory 230000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054446243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3054446243
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.3120440751
Short name T621
Test name
Test status
Simulation time 2635180292 ps
CPU time 18.98 seconds
Started Sep 18 09:10:47 PM UTC 24
Finished Sep 18 09:11:07 PM UTC 24
Peak memory 229936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120440751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.3120440751
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode.2395131521
Short name T610
Test name
Test status
Simulation time 984923846 ps
CPU time 9.44 seconds
Started Sep 18 09:10:43 PM UTC 24
Finished Sep 18 09:10:53 PM UTC 24
Peak memory 235176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395131521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2395131521
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/25.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.2950552720
Short name T605
Test name
Test status
Simulation time 11301903 ps
CPU time 1.19 seconds
Started Sep 18 09:10:43 PM UTC 24
Finished Sep 18 09:10:45 PM UTC 24
Peak memory 225968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950552720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.2950552720
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_intercept.1221171542
Short name T604
Test name
Test status
Simulation time 237647305 ps
CPU time 5.49 seconds
Started Sep 18 09:10:38 PM UTC 24
Finished Sep 18 09:10:44 PM UTC 24
Peak memory 229932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221171542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1221171542
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/25.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_mailbox.300810567
Short name T254
Test name
Test status
Simulation time 54324119463 ps
CPU time 40.13 seconds
Started Sep 18 09:10:39 PM UTC 24
Finished Sep 18 09:11:21 PM UTC 24
Peak memory 245548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300810567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.300810567
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/25.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.1865664165
Short name T330
Test name
Test status
Simulation time 178075467 ps
CPU time 5.62 seconds
Started Sep 18 09:10:38 PM UTC 24
Finished Sep 18 09:10:44 PM UTC 24
Peak memory 242048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865664165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.1865664165
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/25.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.2268125821
Short name T603
Test name
Test status
Simulation time 94766589 ps
CPU time 2.93 seconds
Started Sep 18 09:10:38 PM UTC 24
Finished Sep 18 09:10:42 PM UTC 24
Peak memory 244968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268125821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2268125821
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/25.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.3929339324
Short name T619
Test name
Test status
Simulation time 1965391901 ps
CPU time 16.91 seconds
Started Sep 18 09:10:45 PM UTC 24
Finished Sep 18 09:11:03 PM UTC 24
Peak memory 233780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929339324 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.3929339324
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/25.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.1768270371
Short name T663
Test name
Test status
Simulation time 3004161106 ps
CPU time 67.84 seconds
Started Sep 18 09:10:48 PM UTC 24
Finished Sep 18 09:11:57 PM UTC 24
Peak memory 261924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768270371 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.1768270371
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/25.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_all.284238750
Short name T608
Test name
Test status
Simulation time 13657387760 ps
CPU time 16.55 seconds
Started Sep 18 09:10:35 PM UTC 24
Finished Sep 18 09:10:53 PM UTC 24
Peak memory 227960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284238750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.284238750
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/25.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.1052314881
Short name T599
Test name
Test status
Simulation time 233633635 ps
CPU time 2.62 seconds
Started Sep 18 09:10:35 PM UTC 24
Finished Sep 18 09:10:38 PM UTC 24
Peak memory 217316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052314881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1052314881
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/25.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_rw.3340756601
Short name T600
Test name
Test status
Simulation time 353614146 ps
CPU time 2.66 seconds
Started Sep 18 09:10:36 PM UTC 24
Finished Sep 18 09:10:40 PM UTC 24
Peak memory 227744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340756601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3340756601
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/25.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.2205508655
Short name T598
Test name
Test status
Simulation time 160729887 ps
CPU time 1.25 seconds
Started Sep 18 09:10:35 PM UTC 24
Finished Sep 18 09:10:37 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205508655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2205508655
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/25.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_upload.327499418
Short name T622
Test name
Test status
Simulation time 11420364103 ps
CPU time 24.64 seconds
Started Sep 18 09:10:41 PM UTC 24
Finished Sep 18 09:11:07 PM UTC 24
Peak memory 245476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327499418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.327499418
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/25.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_alert_test.3374691301
Short name T623
Test name
Test status
Simulation time 37299606 ps
CPU time 1.06 seconds
Started Sep 18 09:11:07 PM UTC 24
Finished Sep 18 09:11:10 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374691301 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.3374691301
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/26.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_cfg_cmd.3780173798
Short name T620
Test name
Test status
Simulation time 443428696 ps
CPU time 3.34 seconds
Started Sep 18 09:11:02 PM UTC 24
Finished Sep 18 09:11:06 PM UTC 24
Peak memory 235172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780173798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3780173798
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/26.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_csb_read.2195917030
Short name T611
Test name
Test status
Simulation time 23869552 ps
CPU time 1.18 seconds
Started Sep 18 09:10:53 PM UTC 24
Finished Sep 18 09:10:55 PM UTC 24
Peak memory 215160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195917030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2195917030
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/26.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.1874187211
Short name T758
Test name
Test status
Simulation time 98926273900 ps
CPU time 197.9 seconds
Started Sep 18 09:11:05 PM UTC 24
Finished Sep 18 09:14:26 PM UTC 24
Peak memory 261900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874187211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1874187211
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/26.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.3260393744
Short name T956
Test name
Test status
Simulation time 174706255030 ps
CPU time 433.76 seconds
Started Sep 18 09:11:05 PM UTC 24
Finished Sep 18 09:18:24 PM UTC 24
Peak memory 261892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260393744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3260393744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode.3475162451
Short name T629
Test name
Test status
Simulation time 134722442 ps
CPU time 9.08 seconds
Started Sep 18 09:11:03 PM UTC 24
Finished Sep 18 09:11:13 PM UTC 24
Peak memory 245420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475162451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3475162451
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/26.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.4191585491
Short name T382
Test name
Test status
Simulation time 42828813821 ps
CPU time 330.74 seconds
Started Sep 18 09:11:05 PM UTC 24
Finished Sep 18 09:16:40 PM UTC 24
Peak memory 266020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191585491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.4191585491
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_intercept.178491449
Short name T636
Test name
Test status
Simulation time 21815206402 ps
CPU time 25.34 seconds
Started Sep 18 09:10:58 PM UTC 24
Finished Sep 18 09:11:25 PM UTC 24
Peak memory 245472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178491449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.178491449
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/26.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_mailbox.1614051253
Short name T625
Test name
Test status
Simulation time 657338414 ps
CPU time 8.2 seconds
Started Sep 18 09:11:02 PM UTC 24
Finished Sep 18 09:11:11 PM UTC 24
Peak memory 235104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614051253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1614051253
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/26.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.837428618
Short name T617
Test name
Test status
Simulation time 745914662 ps
CPU time 3.55 seconds
Started Sep 18 09:10:58 PM UTC 24
Finished Sep 18 09:11:03 PM UTC 24
Peak memory 235032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837428618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.837428618
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/26.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.1651821908
Short name T615
Test name
Test status
Simulation time 51598122 ps
CPU time 3.36 seconds
Started Sep 18 09:10:57 PM UTC 24
Finished Sep 18 09:11:01 PM UTC 24
Peak memory 235096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651821908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1651821908
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/26.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.784007088
Short name T626
Test name
Test status
Simulation time 1475121524 ps
CPU time 5.79 seconds
Started Sep 18 09:11:05 PM UTC 24
Finished Sep 18 09:11:12 PM UTC 24
Peak memory 231604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784007088 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.784007088
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/26.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_all.1555880028
Short name T618
Test name
Test status
Simulation time 788898278 ps
CPU time 7.36 seconds
Started Sep 18 09:10:54 PM UTC 24
Finished Sep 18 09:11:03 PM UTC 24
Peak memory 227748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555880028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1555880028
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/26.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.3775290155
Short name T628
Test name
Test status
Simulation time 13875732018 ps
CPU time 17.66 seconds
Started Sep 18 09:10:54 PM UTC 24
Finished Sep 18 09:11:13 PM UTC 24
Peak memory 227756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775290155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3775290155
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/26.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_rw.2383201698
Short name T614
Test name
Test status
Simulation time 13149387 ps
CPU time 1.08 seconds
Started Sep 18 09:10:56 PM UTC 24
Finished Sep 18 09:10:58 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383201698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2383201698
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/26.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.3935641356
Short name T613
Test name
Test status
Simulation time 43630133 ps
CPU time 1.38 seconds
Started Sep 18 09:10:55 PM UTC 24
Finished Sep 18 09:10:57 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935641356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3935641356
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/26.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_upload.4185692222
Short name T633
Test name
Test status
Simulation time 31498111099 ps
CPU time 18.81 seconds
Started Sep 18 09:11:02 PM UTC 24
Finished Sep 18 09:11:22 PM UTC 24
Peak memory 245548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185692222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.4185692222
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/26.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_alert_test.3220581598
Short name T637
Test name
Test status
Simulation time 32880592 ps
CPU time 0.9 seconds
Started Sep 18 09:11:25 PM UTC 24
Finished Sep 18 09:11:27 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220581598 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.3220581598
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/27.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_cfg_cmd.1585008030
Short name T631
Test name
Test status
Simulation time 237454165 ps
CPU time 3.11 seconds
Started Sep 18 09:11:16 PM UTC 24
Finished Sep 18 09:11:20 PM UTC 24
Peak memory 245176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585008030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1585008030
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/27.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_csb_read.2587265442
Short name T624
Test name
Test status
Simulation time 17918120 ps
CPU time 1.18 seconds
Started Sep 18 09:11:09 PM UTC 24
Finished Sep 18 09:11:11 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587265442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2587265442
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/27.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.1503024919
Short name T643
Test name
Test status
Simulation time 2963185054 ps
CPU time 11.73 seconds
Started Sep 18 09:11:23 PM UTC 24
Finished Sep 18 09:11:35 PM UTC 24
Peak memory 231988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503024919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1503024919
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/27.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.1326334071
Short name T890
Test name
Test status
Simulation time 139961458249 ps
CPU time 355.91 seconds
Started Sep 18 09:11:23 PM UTC 24
Finished Sep 18 09:17:23 PM UTC 24
Peak memory 278312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326334071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1326334071
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.127604206
Short name T756
Test name
Test status
Simulation time 79128717537 ps
CPU time 177.12 seconds
Started Sep 18 09:11:23 PM UTC 24
Finished Sep 18 09:14:23 PM UTC 24
Peak memory 261928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127604206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.127604206
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode.1861481297
Short name T632
Test name
Test status
Simulation time 158484640 ps
CPU time 3.47 seconds
Started Sep 18 09:11:16 PM UTC 24
Finished Sep 18 09:11:20 PM UTC 24
Peak memory 245348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861481297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1861481297
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/27.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.2805050024
Short name T317
Test name
Test status
Simulation time 6838907014 ps
CPU time 43.55 seconds
Started Sep 18 09:11:21 PM UTC 24
Finished Sep 18 09:12:06 PM UTC 24
Peak memory 251688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805050024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.2805050024
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_intercept.1676442465
Short name T635
Test name
Test status
Simulation time 635828832 ps
CPU time 8.98 seconds
Started Sep 18 09:11:14 PM UTC 24
Finished Sep 18 09:11:24 PM UTC 24
Peak memory 235168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676442465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1676442465
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/27.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_mailbox.3183620626
Short name T654
Test name
Test status
Simulation time 2278405503 ps
CPU time 30.94 seconds
Started Sep 18 09:11:14 PM UTC 24
Finished Sep 18 09:11:47 PM UTC 24
Peak memory 261808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183620626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3183620626
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/27.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.105294362
Short name T381
Test name
Test status
Simulation time 275930367 ps
CPU time 6.53 seconds
Started Sep 18 09:11:14 PM UTC 24
Finished Sep 18 09:11:22 PM UTC 24
Peak memory 245488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105294362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.105294362
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/27.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.3009329821
Short name T650
Test name
Test status
Simulation time 15068467706 ps
CPU time 28.61 seconds
Started Sep 18 09:11:13 PM UTC 24
Finished Sep 18 09:11:43 PM UTC 24
Peak memory 235248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009329821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3009329821
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/27.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.58055190
Short name T644
Test name
Test status
Simulation time 1478340438 ps
CPU time 13.61 seconds
Started Sep 18 09:11:21 PM UTC 24
Finished Sep 18 09:11:36 PM UTC 24
Peak memory 231544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58055190 -assert nopostproc +UVM_TESTNAME=spi_device_bas
e_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.58055190
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/27.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.412029529
Short name T195
Test name
Test status
Simulation time 116179818881 ps
CPU time 175.94 seconds
Started Sep 18 09:11:24 PM UTC 24
Finished Sep 18 09:14:23 PM UTC 24
Peak memory 284452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412029529 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.412029529
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/27.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_all.3234414263
Short name T646
Test name
Test status
Simulation time 2546317142 ps
CPU time 24.1 seconds
Started Sep 18 09:11:11 PM UTC 24
Finished Sep 18 09:11:36 PM UTC 24
Peak memory 227952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234414263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3234414263
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/27.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.689260385
Short name T627
Test name
Test status
Simulation time 20123668 ps
CPU time 1.12 seconds
Started Sep 18 09:11:11 PM UTC 24
Finished Sep 18 09:11:13 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689260385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.689260385
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/27.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_rw.3753130551
Short name T634
Test name
Test status
Simulation time 817000690 ps
CPU time 8.76 seconds
Started Sep 18 09:11:13 PM UTC 24
Finished Sep 18 09:11:22 PM UTC 24
Peak memory 227684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753130551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3753130551
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/27.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.3641944787
Short name T630
Test name
Test status
Simulation time 20650101 ps
CPU time 1.12 seconds
Started Sep 18 09:11:13 PM UTC 24
Finished Sep 18 09:11:15 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641944787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3641944787
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/27.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_upload.406275447
Short name T649
Test name
Test status
Simulation time 14878732614 ps
CPU time 22.41 seconds
Started Sep 18 09:11:14 PM UTC 24
Finished Sep 18 09:11:38 PM UTC 24
Peak memory 245488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406275447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.406275447
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/27.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_alert_test.3805618250
Short name T657
Test name
Test status
Simulation time 62552258 ps
CPU time 1.08 seconds
Started Sep 18 09:11:47 PM UTC 24
Finished Sep 18 09:11:49 PM UTC 24
Peak memory 213048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805618250 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.3805618250
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/28.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_cfg_cmd.3677182667
Short name T653
Test name
Test status
Simulation time 353777193 ps
CPU time 7 seconds
Started Sep 18 09:11:37 PM UTC 24
Finished Sep 18 09:11:45 PM UTC 24
Peak memory 245400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677182667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3677182667
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/28.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_csb_read.2671903834
Short name T638
Test name
Test status
Simulation time 56636192 ps
CPU time 1.26 seconds
Started Sep 18 09:11:26 PM UTC 24
Finished Sep 18 09:11:29 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671903834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2671903834
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/28.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_all.3317077989
Short name T666
Test name
Test status
Simulation time 1271593917 ps
CPU time 19.64 seconds
Started Sep 18 09:11:39 PM UTC 24
Finished Sep 18 09:12:00 PM UTC 24
Peak memory 261872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317077989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3317077989
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/28.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.1628936836
Short name T690
Test name
Test status
Simulation time 4323583426 ps
CPU time 55.93 seconds
Started Sep 18 09:11:39 PM UTC 24
Finished Sep 18 09:12:37 PM UTC 24
Peak memory 234176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628936836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1628936836
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/28.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.592149535
Short name T706
Test name
Test status
Simulation time 21894670402 ps
CPU time 72.64 seconds
Started Sep 18 09:11:43 PM UTC 24
Finished Sep 18 09:12:58 PM UTC 24
Peak memory 251764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592149535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.592149535
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode.1674831789
Short name T670
Test name
Test status
Simulation time 3795527458 ps
CPU time 23.59 seconds
Started Sep 18 09:11:39 PM UTC 24
Finished Sep 18 09:12:04 PM UTC 24
Peak memory 235248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674831789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1674831789
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/28.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.262885817
Short name T250
Test name
Test status
Simulation time 61157036396 ps
CPU time 112.87 seconds
Started Sep 18 09:11:39 PM UTC 24
Finished Sep 18 09:13:34 PM UTC 24
Peak memory 261996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262885817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.262885817
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_intercept.2847840045
Short name T652
Test name
Test status
Simulation time 497134215 ps
CPU time 6.93 seconds
Started Sep 18 09:11:37 PM UTC 24
Finished Sep 18 09:11:45 PM UTC 24
Peak memory 245356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847840045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2847840045
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/28.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_mailbox.1938735483
Short name T665
Test name
Test status
Simulation time 950307572 ps
CPU time 19.72 seconds
Started Sep 18 09:11:37 PM UTC 24
Finished Sep 18 09:11:58 PM UTC 24
Peak memory 251500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938735483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1938735483
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/28.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.1417558405
Short name T368
Test name
Test status
Simulation time 70177475 ps
CPU time 2.95 seconds
Started Sep 18 09:11:34 PM UTC 24
Finished Sep 18 09:11:38 PM UTC 24
Peak memory 245412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417558405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.1417558405
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/28.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.231444968
Short name T662
Test name
Test status
Simulation time 13066114510 ps
CPU time 19.08 seconds
Started Sep 18 09:11:32 PM UTC 24
Finished Sep 18 09:11:53 PM UTC 24
Peak memory 251684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231444968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.231444968
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/28.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.132269941
Short name T658
Test name
Test status
Simulation time 1025431782 ps
CPU time 11.08 seconds
Started Sep 18 09:11:39 PM UTC 24
Finished Sep 18 09:11:51 PM UTC 24
Peak memory 231520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132269941 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.132269941
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/28.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.2224761000
Short name T814
Test name
Test status
Simulation time 25524479145 ps
CPU time 229.82 seconds
Started Sep 18 09:11:45 PM UTC 24
Finished Sep 18 09:15:39 PM UTC 24
Peak memory 251680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224761000 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.2224761000
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/28.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_all.455686769
Short name T641
Test name
Test status
Simulation time 38253502 ps
CPU time 1.03 seconds
Started Sep 18 09:11:30 PM UTC 24
Finished Sep 18 09:11:32 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455686769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.455686769
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/28.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.1779764046
Short name T655
Test name
Test status
Simulation time 7514807483 ps
CPU time 18.38 seconds
Started Sep 18 09:11:27 PM UTC 24
Finished Sep 18 09:11:47 PM UTC 24
Peak memory 227896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779764046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1779764046
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/28.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_rw.65251422
Short name T645
Test name
Test status
Simulation time 145464768 ps
CPU time 4.31 seconds
Started Sep 18 09:11:31 PM UTC 24
Finished Sep 18 09:11:36 PM UTC 24
Peak memory 227748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65251422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_devi
ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.65251422
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/28.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.2968507706
Short name T642
Test name
Test status
Simulation time 46736242 ps
CPU time 1.31 seconds
Started Sep 18 09:11:31 PM UTC 24
Finished Sep 18 09:11:33 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968507706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2968507706
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/28.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_upload.463618078
Short name T651
Test name
Test status
Simulation time 1549229102 ps
CPU time 6.12 seconds
Started Sep 18 09:11:37 PM UTC 24
Finished Sep 18 09:11:44 PM UTC 24
Peak memory 235184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463618078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.463618078
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/28.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_alert_test.779598453
Short name T674
Test name
Test status
Simulation time 11438498 ps
CPU time 1.12 seconds
Started Sep 18 09:12:07 PM UTC 24
Finished Sep 18 09:12:10 PM UTC 24
Peak memory 213044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779598453 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.779598453
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/29.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_cfg_cmd.2712543164
Short name T668
Test name
Test status
Simulation time 30490687 ps
CPU time 2.96 seconds
Started Sep 18 09:11:58 PM UTC 24
Finished Sep 18 09:12:02 PM UTC 24
Peak memory 244972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712543164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2712543164
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/29.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_csb_read.2214063649
Short name T656
Test name
Test status
Simulation time 48653101 ps
CPU time 1.14 seconds
Started Sep 18 09:11:47 PM UTC 24
Finished Sep 18 09:11:49 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214063649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2214063649
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/29.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.2160512900
Short name T383
Test name
Test status
Simulation time 106305257940 ps
CPU time 309.41 seconds
Started Sep 18 09:12:02 PM UTC 24
Finished Sep 18 09:17:15 PM UTC 24
Peak memory 282348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160512900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2160512900
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/29.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.2600294512
Short name T733
Test name
Test status
Simulation time 31821153311 ps
CPU time 103.32 seconds
Started Sep 18 09:12:03 PM UTC 24
Finished Sep 18 09:13:48 PM UTC 24
Peak memory 249648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600294512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2600294512
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.2779757720
Short name T693
Test name
Test status
Simulation time 12626978828 ps
CPU time 32.75 seconds
Started Sep 18 09:12:05 PM UTC 24
Finished Sep 18 09:12:39 PM UTC 24
Peak memory 261924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779757720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.2779757720
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode.4217344309
Short name T678
Test name
Test status
Simulation time 378100809 ps
CPU time 16.5 seconds
Started Sep 18 09:11:59 PM UTC 24
Finished Sep 18 09:12:17 PM UTC 24
Peak memory 251552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217344309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.4217344309
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/29.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.810372199
Short name T362
Test name
Test status
Simulation time 5906933497 ps
CPU time 48.16 seconds
Started Sep 18 09:11:59 PM UTC 24
Finished Sep 18 09:12:49 PM UTC 24
Peak memory 235316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810372199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.810372199
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_intercept.2683110283
Short name T669
Test name
Test status
Simulation time 2133297941 ps
CPU time 9.01 seconds
Started Sep 18 09:11:54 PM UTC 24
Finished Sep 18 09:12:04 PM UTC 24
Peak memory 245352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683110283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2683110283
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/29.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_mailbox.3415888174
Short name T694
Test name
Test status
Simulation time 11041752487 ps
CPU time 46.57 seconds
Started Sep 18 09:11:54 PM UTC 24
Finished Sep 18 09:12:42 PM UTC 24
Peak memory 251628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415888174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3415888174
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/29.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.4291984931
Short name T358
Test name
Test status
Simulation time 7547153421 ps
CPU time 28.04 seconds
Started Sep 18 09:11:53 PM UTC 24
Finished Sep 18 09:12:23 PM UTC 24
Peak memory 245540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291984931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.4291984931
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/29.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.861494855
Short name T667
Test name
Test status
Simulation time 5153712315 ps
CPU time 7.65 seconds
Started Sep 18 09:11:52 PM UTC 24
Finished Sep 18 09:12:01 PM UTC 24
Peak memory 235228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861494855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.861494855
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/29.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.3378230149
Short name T673
Test name
Test status
Simulation time 574773031 ps
CPU time 6.94 seconds
Started Sep 18 09:12:00 PM UTC 24
Finished Sep 18 09:12:08 PM UTC 24
Peak memory 231528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378230149 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.3378230149
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/29.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_stress_all.3490745112
Short name T730
Test name
Test status
Simulation time 7340157607 ps
CPU time 93.37 seconds
Started Sep 18 09:12:05 PM UTC 24
Finished Sep 18 09:13:40 PM UTC 24
Peak memory 264024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490745112 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.3490745112
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/29.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_all.1679437854
Short name T680
Test name
Test status
Simulation time 1116684104 ps
CPU time 30.29 seconds
Started Sep 18 09:11:48 PM UTC 24
Finished Sep 18 09:12:20 PM UTC 24
Peak memory 227888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679437854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1679437854
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/29.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.691084766
Short name T661
Test name
Test status
Simulation time 1915638897 ps
CPU time 3.14 seconds
Started Sep 18 09:11:48 PM UTC 24
Finished Sep 18 09:11:52 PM UTC 24
Peak memory 217308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691084766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.691084766
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/29.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_rw.3505961559
Short name T659
Test name
Test status
Simulation time 26344792 ps
CPU time 1.18 seconds
Started Sep 18 09:11:50 PM UTC 24
Finished Sep 18 09:11:52 PM UTC 24
Peak memory 215088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505961559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3505961559
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/29.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.1013916273
Short name T660
Test name
Test status
Simulation time 116070618 ps
CPU time 1.45 seconds
Started Sep 18 09:11:50 PM UTC 24
Finished Sep 18 09:11:52 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013916273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1013916273
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/29.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_upload.664632766
Short name T664
Test name
Test status
Simulation time 74091614 ps
CPU time 3.01 seconds
Started Sep 18 09:11:54 PM UTC 24
Finished Sep 18 09:11:58 PM UTC 24
Peak memory 245100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664632766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.664632766
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/29.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.2911738104
Short name T409
Test name
Test status
Simulation time 43149154 ps
CPU time 1.13 seconds
Started Sep 18 09:03:20 PM UTC 24
Finished Sep 18 09:03:22 PM UTC 24
Peak memory 213048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911738104 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2911738104
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.738100949
Short name T106
Test name
Test status
Simulation time 4228913328 ps
CPU time 6.92 seconds
Started Sep 18 09:03:10 PM UTC 24
Finished Sep 18 09:03:18 PM UTC 24
Peak memory 245544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738100949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.738100949
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.491717440
Short name T408
Test name
Test status
Simulation time 46275189 ps
CPU time 1.17 seconds
Started Sep 18 09:03:04 PM UTC 24
Finished Sep 18 09:03:06 PM UTC 24
Peak memory 215100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491717440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.491717440
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.499519012
Short name T205
Test name
Test status
Simulation time 10850677736 ps
CPU time 100.14 seconds
Started Sep 18 09:03:12 PM UTC 24
Finished Sep 18 09:04:54 PM UTC 24
Peak memory 251632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499519012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.499519012
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.3877467391
Short name T259
Test name
Test status
Simulation time 57899567657 ps
CPU time 135.52 seconds
Started Sep 18 09:03:14 PM UTC 24
Finished Sep 18 09:05:32 PM UTC 24
Peak memory 262120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877467391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3877467391
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.903346222
Short name T55
Test name
Test status
Simulation time 6496633849 ps
CPU time 11.35 seconds
Started Sep 18 09:03:11 PM UTC 24
Finished Sep 18 09:03:23 PM UTC 24
Peak memory 245484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903346222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.903346222
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.4277277970
Short name T52
Test name
Test status
Simulation time 3582883536 ps
CPU time 56.51 seconds
Started Sep 18 09:03:11 PM UTC 24
Finished Sep 18 09:04:09 PM UTC 24
Peak memory 261944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277277970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.4277277970
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.3947535695
Short name T59
Test name
Test status
Simulation time 490866335 ps
CPU time 7.56 seconds
Started Sep 18 09:03:08 PM UTC 24
Finished Sep 18 09:03:16 PM UTC 24
Peak memory 245416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947535695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3947535695
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.693771923
Short name T443
Test name
Test status
Simulation time 61071250753 ps
CPU time 159.77 seconds
Started Sep 18 09:03:09 PM UTC 24
Finished Sep 18 09:05:51 PM UTC 24
Peak memory 264056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693771923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.693771923
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.4253092604
Short name T47
Test name
Test status
Simulation time 64022342 ps
CPU time 1.57 seconds
Started Sep 18 09:03:04 PM UTC 24
Finished Sep 18 09:03:07 PM UTC 24
Peak memory 228264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253092604 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_parity.4253092604
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.3216207815
Short name T66
Test name
Test status
Simulation time 1200853054 ps
CPU time 4.29 seconds
Started Sep 18 09:03:08 PM UTC 24
Finished Sep 18 09:03:13 PM UTC 24
Peak memory 245548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216207815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.3216207815
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.150740712
Short name T179
Test name
Test status
Simulation time 2886119640 ps
CPU time 9.09 seconds
Started Sep 18 09:03:12 PM UTC 24
Finished Sep 18 09:03:22 PM UTC 24
Peak memory 231668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150740712 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.150740712
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.1267121595
Short name T32
Test name
Test status
Simulation time 182682761 ps
CPU time 2.09 seconds
Started Sep 18 09:03:18 PM UTC 24
Finished Sep 18 09:03:22 PM UTC 24
Peak memory 258600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267121595 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1267121595
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.1880237632
Short name T46
Test name
Test status
Simulation time 2796285871 ps
CPU time 12.68 seconds
Started Sep 18 09:03:05 PM UTC 24
Finished Sep 18 09:03:19 PM UTC 24
Peak memory 227820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880237632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1880237632
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.3543462412
Short name T118
Test name
Test status
Simulation time 931995777 ps
CPU time 5.19 seconds
Started Sep 18 09:03:05 PM UTC 24
Finished Sep 18 09:03:11 PM UTC 24
Peak memory 227700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543462412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3543462412
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.3744289877
Short name T48
Test name
Test status
Simulation time 212429098 ps
CPU time 2.5 seconds
Started Sep 18 09:03:06 PM UTC 24
Finished Sep 18 09:03:10 PM UTC 24
Peak memory 227740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744289877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3744289877
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.197951252
Short name T117
Test name
Test status
Simulation time 1010476053 ps
CPU time 1.22 seconds
Started Sep 18 09:03:05 PM UTC 24
Finished Sep 18 09:03:08 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197951252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.197951252
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.704171673
Short name T60
Test name
Test status
Simulation time 4678935593 ps
CPU time 17.14 seconds
Started Sep 18 09:03:09 PM UTC 24
Finished Sep 18 09:03:27 PM UTC 24
Peak memory 235232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704171673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.704171673
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/3.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_alert_test.2338984153
Short name T691
Test name
Test status
Simulation time 123452716 ps
CPU time 1.09 seconds
Started Sep 18 09:12:35 PM UTC 24
Finished Sep 18 09:12:38 PM UTC 24
Peak memory 213048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338984153 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.2338984153
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/30.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_cfg_cmd.820001949
Short name T685
Test name
Test status
Simulation time 52967311 ps
CPU time 3.56 seconds
Started Sep 18 09:12:24 PM UTC 24
Finished Sep 18 09:12:29 PM UTC 24
Peak memory 245284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820001949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.820001949
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/30.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_csb_read.1487420451
Short name T675
Test name
Test status
Simulation time 121801951 ps
CPU time 1.16 seconds
Started Sep 18 09:12:09 PM UTC 24
Finished Sep 18 09:12:11 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487420451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1487420451
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/30.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_all.999956152
Short name T749
Test name
Test status
Simulation time 13377086772 ps
CPU time 100.52 seconds
Started Sep 18 09:12:28 PM UTC 24
Finished Sep 18 09:14:11 PM UTC 24
Peak memory 261928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999956152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.999956152
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/30.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.2332016461
Short name T1029
Test name
Test status
Simulation time 548687767428 ps
CPU time 590.47 seconds
Started Sep 18 09:12:31 PM UTC 24
Finished Sep 18 09:22:29 PM UTC 24
Peak memory 262000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332016461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2332016461
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/30.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.2549830393
Short name T773
Test name
Test status
Simulation time 45570531818 ps
CPU time 133.78 seconds
Started Sep 18 09:12:32 PM UTC 24
Finished Sep 18 09:14:49 PM UTC 24
Peak memory 261564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549830393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.2549830393
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode.3161849922
Short name T688
Test name
Test status
Simulation time 157275815 ps
CPU time 6.67 seconds
Started Sep 18 09:12:25 PM UTC 24
Finished Sep 18 09:12:34 PM UTC 24
Peak memory 245356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161849922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3161849922
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/30.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.2159872600
Short name T829
Test name
Test status
Simulation time 401710144359 ps
CPU time 227.38 seconds
Started Sep 18 09:12:27 PM UTC 24
Finished Sep 18 09:16:18 PM UTC 24
Peak memory 261988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159872600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.2159872600
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_intercept.2672850673
Short name T698
Test name
Test status
Simulation time 8911498951 ps
CPU time 26.81 seconds
Started Sep 18 09:12:18 PM UTC 24
Finished Sep 18 09:12:47 PM UTC 24
Peak memory 245484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672850673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2672850673
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/30.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_mailbox.1192688321
Short name T731
Test name
Test status
Simulation time 31791430267 ps
CPU time 80.36 seconds
Started Sep 18 09:12:20 PM UTC 24
Finished Sep 18 09:13:43 PM UTC 24
Peak memory 245484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192688321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1192688321
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/30.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.3838527880
Short name T682
Test name
Test status
Simulation time 950379163 ps
CPU time 6.61 seconds
Started Sep 18 09:12:18 PM UTC 24
Finished Sep 18 09:12:26 PM UTC 24
Peak memory 235100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838527880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.3838527880
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/30.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.1162018611
Short name T686
Test name
Test status
Simulation time 6008333410 ps
CPU time 12.2 seconds
Started Sep 18 09:12:17 PM UTC 24
Finished Sep 18 09:12:30 PM UTC 24
Peak memory 245552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162018611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1162018611
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/30.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.144112391
Short name T687
Test name
Test status
Simulation time 794217204 ps
CPU time 5.2 seconds
Started Sep 18 09:12:27 PM UTC 24
Finished Sep 18 09:12:34 PM UTC 24
Peak memory 233716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144112391 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.144112391
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/30.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.694008586
Short name T689
Test name
Test status
Simulation time 123762232 ps
CPU time 1.38 seconds
Started Sep 18 09:12:32 PM UTC 24
Finished Sep 18 09:12:35 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694008586 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.694008586
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/30.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_all.1417890232
Short name T677
Test name
Test status
Simulation time 2034701781 ps
CPU time 4.7 seconds
Started Sep 18 09:12:11 PM UTC 24
Finished Sep 18 09:12:17 PM UTC 24
Peak memory 227956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417890232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1417890232
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/30.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.4227672292
Short name T683
Test name
Test status
Simulation time 19592474351 ps
CPU time 16.48 seconds
Started Sep 18 09:12:10 PM UTC 24
Finished Sep 18 09:12:28 PM UTC 24
Peak memory 227780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227672292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.4227672292
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/30.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_rw.179024701
Short name T679
Test name
Test status
Simulation time 109811017 ps
CPU time 2.77 seconds
Started Sep 18 09:12:15 PM UTC 24
Finished Sep 18 09:12:19 PM UTC 24
Peak memory 227956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179024701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.179024701
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/30.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.2424850393
Short name T676
Test name
Test status
Simulation time 29208990 ps
CPU time 1.23 seconds
Started Sep 18 09:12:12 PM UTC 24
Finished Sep 18 09:12:14 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424850393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2424850393
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/30.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_upload.3817550632
Short name T681
Test name
Test status
Simulation time 38618262 ps
CPU time 3.28 seconds
Started Sep 18 09:12:21 PM UTC 24
Finished Sep 18 09:12:26 PM UTC 24
Peak memory 234792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817550632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3817550632
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/30.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_alert_test.2061142120
Short name T707
Test name
Test status
Simulation time 12885035 ps
CPU time 1.1 seconds
Started Sep 18 09:12:57 PM UTC 24
Finished Sep 18 09:12:59 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061142120 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.2061142120
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/31.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_cfg_cmd.4290682120
Short name T703
Test name
Test status
Simulation time 45144466 ps
CPU time 2.99 seconds
Started Sep 18 09:12:46 PM UTC 24
Finished Sep 18 09:12:51 PM UTC 24
Peak memory 245404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290682120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4290682120
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/31.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_csb_read.2466936338
Short name T692
Test name
Test status
Simulation time 41447696 ps
CPU time 1.18 seconds
Started Sep 18 09:12:35 PM UTC 24
Finished Sep 18 09:12:38 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466936338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2466936338
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/31.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_all.1507699789
Short name T826
Test name
Test status
Simulation time 48993648701 ps
CPU time 200.57 seconds
Started Sep 18 09:12:49 PM UTC 24
Finished Sep 18 09:16:13 PM UTC 24
Peak memory 261932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507699789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1507699789
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/31.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.424749391
Short name T357
Test name
Test status
Simulation time 109673823798 ps
CPU time 299.41 seconds
Started Sep 18 09:12:50 PM UTC 24
Finished Sep 18 09:17:54 PM UTC 24
Peak memory 276336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424749391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.424749391
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.1536840636
Short name T770
Test name
Test status
Simulation time 9950476033 ps
CPU time 112.98 seconds
Started Sep 18 09:12:52 PM UTC 24
Finished Sep 18 09:14:47 PM UTC 24
Peak memory 261928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536840636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.1536840636
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode.2980281244
Short name T389
Test name
Test status
Simulation time 3796958666 ps
CPU time 76.1 seconds
Started Sep 18 09:12:48 PM UTC 24
Finished Sep 18 09:14:06 PM UTC 24
Peak memory 245484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980281244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2980281244
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/31.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.2603956698
Short name T711
Test name
Test status
Simulation time 1199108378 ps
CPU time 17.11 seconds
Started Sep 18 09:12:48 PM UTC 24
Finished Sep 18 09:13:06 PM UTC 24
Peak memory 245480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603956698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.2603956698
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_intercept.3995435221
Short name T700
Test name
Test status
Simulation time 34193331 ps
CPU time 2.96 seconds
Started Sep 18 09:12:43 PM UTC 24
Finished Sep 18 09:12:47 PM UTC 24
Peak memory 245140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995435221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3995435221
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/31.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_mailbox.4095717608
Short name T704
Test name
Test status
Simulation time 411737980 ps
CPU time 12 seconds
Started Sep 18 09:12:43 PM UTC 24
Finished Sep 18 09:12:56 PM UTC 24
Peak memory 251500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095717608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.4095717608
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/31.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.1731771979
Short name T336
Test name
Test status
Simulation time 7055984840 ps
CPU time 25.7 seconds
Started Sep 18 09:12:43 PM UTC 24
Finished Sep 18 09:13:10 PM UTC 24
Peak memory 261880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731771979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.1731771979
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/31.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.1354200321
Short name T699
Test name
Test status
Simulation time 1395318661 ps
CPU time 4.56 seconds
Started Sep 18 09:12:40 PM UTC 24
Finished Sep 18 09:12:47 PM UTC 24
Peak memory 235036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354200321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1354200321
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/31.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.3851800013
Short name T709
Test name
Test status
Simulation time 2152433165 ps
CPU time 12.26 seconds
Started Sep 18 09:12:48 PM UTC 24
Finished Sep 18 09:13:01 PM UTC 24
Peak memory 233908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851800013 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.3851800013
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/31.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.3113197338
Short name T729
Test name
Test status
Simulation time 7082108802 ps
CPU time 43.57 seconds
Started Sep 18 09:12:52 PM UTC 24
Finished Sep 18 09:13:37 PM UTC 24
Peak memory 245540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113197338 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.3113197338
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/31.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_all.2560417953
Short name T701
Test name
Test status
Simulation time 1557675082 ps
CPU time 7.27 seconds
Started Sep 18 09:12:38 PM UTC 24
Finished Sep 18 09:12:47 PM UTC 24
Peak memory 227892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560417953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2560417953
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/31.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.265720636
Short name T696
Test name
Test status
Simulation time 5091829722 ps
CPU time 3.77 seconds
Started Sep 18 09:12:37 PM UTC 24
Finished Sep 18 09:12:42 PM UTC 24
Peak memory 229736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265720636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.265720636
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/31.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_rw.2663646593
Short name T697
Test name
Test status
Simulation time 154517995 ps
CPU time 3.61 seconds
Started Sep 18 09:12:39 PM UTC 24
Finished Sep 18 09:12:44 PM UTC 24
Peak memory 227704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663646593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2663646593
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/31.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.132747800
Short name T695
Test name
Test status
Simulation time 88392938 ps
CPU time 1.14 seconds
Started Sep 18 09:12:39 PM UTC 24
Finished Sep 18 09:12:42 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132747800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.132747800
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/31.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_upload.1587622038
Short name T702
Test name
Test status
Simulation time 182015986 ps
CPU time 3.83 seconds
Started Sep 18 09:12:45 PM UTC 24
Finished Sep 18 09:12:50 PM UTC 24
Peak memory 235052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587622038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1587622038
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/31.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_alert_test.1010642236
Short name T720
Test name
Test status
Simulation time 11902107 ps
CPU time 1.1 seconds
Started Sep 18 09:13:20 PM UTC 24
Finished Sep 18 09:13:23 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010642236 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.1010642236
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/32.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_cfg_cmd.566360379
Short name T716
Test name
Test status
Simulation time 481216649 ps
CPU time 2.83 seconds
Started Sep 18 09:13:11 PM UTC 24
Finished Sep 18 09:13:15 PM UTC 24
Peak memory 235032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566360379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.566360379
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/32.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_csb_read.300769098
Short name T708
Test name
Test status
Simulation time 28081223 ps
CPU time 0.96 seconds
Started Sep 18 09:12:58 PM UTC 24
Finished Sep 18 09:13:00 PM UTC 24
Peak memory 215100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300769098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.300769098
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/32.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_all.3872205077
Short name T291
Test name
Test status
Simulation time 2752246759 ps
CPU time 96.08 seconds
Started Sep 18 09:13:16 PM UTC 24
Finished Sep 18 09:14:54 PM UTC 24
Peak memory 264040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872205077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3872205077
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/32.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.1985881886
Short name T722
Test name
Test status
Simulation time 413691265 ps
CPU time 7.46 seconds
Started Sep 18 09:13:17 PM UTC 24
Finished Sep 18 09:13:25 PM UTC 24
Peak memory 229876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985881886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1985881886
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.859412991
Short name T735
Test name
Test status
Simulation time 5962388164 ps
CPU time 30.35 seconds
Started Sep 18 09:13:18 PM UTC 24
Finished Sep 18 09:13:50 PM UTC 24
Peak memory 229856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859412991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.859412991
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode.3417550907
Short name T718
Test name
Test status
Simulation time 1873412276 ps
CPU time 7.09 seconds
Started Sep 18 09:13:11 PM UTC 24
Finished Sep 18 09:13:19 PM UTC 24
Peak memory 245356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417550907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3417550907
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/32.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.784431514
Short name T801
Test name
Test status
Simulation time 98787708596 ps
CPU time 121.95 seconds
Started Sep 18 09:13:16 PM UTC 24
Finished Sep 18 09:15:20 PM UTC 24
Peak memory 263976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784431514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.784431514
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_intercept.2161480062
Short name T713
Test name
Test status
Simulation time 143846668 ps
CPU time 2.67 seconds
Started Sep 18 09:13:06 PM UTC 24
Finished Sep 18 09:13:10 PM UTC 24
Peak memory 233684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161480062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2161480062
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/32.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_mailbox.3932172775
Short name T743
Test name
Test status
Simulation time 15956259678 ps
CPU time 53.16 seconds
Started Sep 18 09:13:08 PM UTC 24
Finished Sep 18 09:14:02 PM UTC 24
Peak memory 261868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932172775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3932172775
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/32.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.3379525677
Short name T258
Test name
Test status
Simulation time 3519436578 ps
CPU time 24.97 seconds
Started Sep 18 09:13:04 PM UTC 24
Finished Sep 18 09:13:30 PM UTC 24
Peak memory 245540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379525677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.3379525677
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/32.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.1910555613
Short name T308
Test name
Test status
Simulation time 14150981845 ps
CPU time 10.71 seconds
Started Sep 18 09:13:04 PM UTC 24
Finished Sep 18 09:13:16 PM UTC 24
Peak memory 235168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910555613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1910555613
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/32.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.2144642993
Short name T719
Test name
Test status
Simulation time 102194259 ps
CPU time 3.73 seconds
Started Sep 18 09:13:16 PM UTC 24
Finished Sep 18 09:13:20 PM UTC 24
Peak memory 233652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144642993 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.2144642993
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/32.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_all.207428103
Short name T725
Test name
Test status
Simulation time 7732550520 ps
CPU time 27.94 seconds
Started Sep 18 09:12:59 PM UTC 24
Finished Sep 18 09:13:29 PM UTC 24
Peak memory 227820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207428103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.207428103
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/32.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.879220711
Short name T715
Test name
Test status
Simulation time 4973068812 ps
CPU time 13.66 seconds
Started Sep 18 09:12:59 PM UTC 24
Finished Sep 18 09:13:14 PM UTC 24
Peak memory 227888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879220711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.879220711
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/32.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_rw.3990329226
Short name T712
Test name
Test status
Simulation time 76081611 ps
CPU time 3.36 seconds
Started Sep 18 09:13:02 PM UTC 24
Finished Sep 18 09:13:06 PM UTC 24
Peak memory 227688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990329226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3990329226
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/32.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.288172051
Short name T710
Test name
Test status
Simulation time 130406887 ps
CPU time 1.21 seconds
Started Sep 18 09:13:01 PM UTC 24
Finished Sep 18 09:13:03 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288172051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.288172051
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/32.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_upload.1947552309
Short name T714
Test name
Test status
Simulation time 399249451 ps
CPU time 5.35 seconds
Started Sep 18 09:13:08 PM UTC 24
Finished Sep 18 09:13:14 PM UTC 24
Peak memory 235024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947552309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1947552309
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/32.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_alert_test.516170205
Short name T737
Test name
Test status
Simulation time 42032412 ps
CPU time 1.08 seconds
Started Sep 18 09:13:49 PM UTC 24
Finished Sep 18 09:13:51 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516170205 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.516170205
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/33.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_cfg_cmd.2381085918
Short name T736
Test name
Test status
Simulation time 3264648043 ps
CPU time 14.25 seconds
Started Sep 18 09:13:36 PM UTC 24
Finished Sep 18 09:13:51 PM UTC 24
Peak memory 245476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381085918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2381085918
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/33.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_csb_read.2283404896
Short name T721
Test name
Test status
Simulation time 20023779 ps
CPU time 1.18 seconds
Started Sep 18 09:13:22 PM UTC 24
Finished Sep 18 09:13:24 PM UTC 24
Peak memory 215160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283404896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2283404896
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/33.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_all.2694939670
Short name T830
Test name
Test status
Simulation time 33166536875 ps
CPU time 160.04 seconds
Started Sep 18 09:13:38 PM UTC 24
Finished Sep 18 09:16:21 PM UTC 24
Peak memory 261860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694939670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2694939670
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/33.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.1673467110
Short name T1023
Test name
Test status
Simulation time 87886040738 ps
CPU time 406.18 seconds
Started Sep 18 09:13:42 PM UTC 24
Finished Sep 18 09:20:33 PM UTC 24
Peak memory 268124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673467110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1673467110
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.4100927938
Short name T771
Test name
Test status
Simulation time 5170551503 ps
CPU time 63.47 seconds
Started Sep 18 09:13:42 PM UTC 24
Finished Sep 18 09:14:47 PM UTC 24
Peak memory 261936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100927938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.4100927938
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode.1852268901
Short name T780
Test name
Test status
Simulation time 9933227443 ps
CPU time 79.44 seconds
Started Sep 18 09:13:36 PM UTC 24
Finished Sep 18 09:14:57 PM UTC 24
Peak memory 245608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852268901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1852268901
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/33.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.2792868554
Short name T807
Test name
Test status
Simulation time 21037829384 ps
CPU time 106.14 seconds
Started Sep 18 09:13:37 PM UTC 24
Finished Sep 18 09:15:25 PM UTC 24
Peak memory 274148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792868554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.2792868554
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_intercept.3672306417
Short name T732
Test name
Test status
Simulation time 13238067635 ps
CPU time 15.42 seconds
Started Sep 18 09:13:31 PM UTC 24
Finished Sep 18 09:13:48 PM UTC 24
Peak memory 235176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672306417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3672306417
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/33.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_mailbox.558649252
Short name T759
Test name
Test status
Simulation time 25650871795 ps
CPU time 55.29 seconds
Started Sep 18 09:13:32 PM UTC 24
Finished Sep 18 09:14:30 PM UTC 24
Peak memory 249588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558649252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.558649252
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/33.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.473794726
Short name T371
Test name
Test status
Simulation time 3279434398 ps
CPU time 9.59 seconds
Started Sep 18 09:13:30 PM UTC 24
Finished Sep 18 09:13:41 PM UTC 24
Peak memory 245484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473794726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.473794726
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/33.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.1849316015
Short name T727
Test name
Test status
Simulation time 276820262 ps
CPU time 3.51 seconds
Started Sep 18 09:13:30 PM UTC 24
Finished Sep 18 09:13:34 PM UTC 24
Peak memory 245356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849316015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1849316015
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/33.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.2711931096
Short name T734
Test name
Test status
Simulation time 8409009692 ps
CPU time 9.84 seconds
Started Sep 18 09:13:38 PM UTC 24
Finished Sep 18 09:13:50 PM UTC 24
Peak memory 231780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711931096 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.2711931096
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/33.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.3170967820
Short name T360
Test name
Test status
Simulation time 7434007658 ps
CPU time 104.33 seconds
Started Sep 18 09:13:43 PM UTC 24
Finished Sep 18 09:15:29 PM UTC 24
Peak memory 268068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170967820 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.3170967820
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/33.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_all.4077518807
Short name T723
Test name
Test status
Simulation time 25317969 ps
CPU time 1.12 seconds
Started Sep 18 09:13:25 PM UTC 24
Finished Sep 18 09:13:27 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077518807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.4077518807
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/33.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.397337720
Short name T726
Test name
Test status
Simulation time 6349937474 ps
CPU time 9.28 seconds
Started Sep 18 09:13:24 PM UTC 24
Finished Sep 18 09:13:34 PM UTC 24
Peak memory 227892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397337720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.397337720
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/33.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_rw.779889907
Short name T684
Test name
Test status
Simulation time 75148946 ps
CPU time 1.4 seconds
Started Sep 18 09:13:28 PM UTC 24
Finished Sep 18 09:13:31 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779889907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.779889907
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/33.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.934799803
Short name T724
Test name
Test status
Simulation time 44956841 ps
CPU time 1.11 seconds
Started Sep 18 09:13:26 PM UTC 24
Finished Sep 18 09:13:28 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934799803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.934799803
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/33.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_upload.4017665406
Short name T742
Test name
Test status
Simulation time 15807421373 ps
CPU time 22.95 seconds
Started Sep 18 09:13:36 PM UTC 24
Finished Sep 18 09:14:00 PM UTC 24
Peak memory 235300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017665406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.4017665406
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/33.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_alert_test.3476596114
Short name T754
Test name
Test status
Simulation time 16401856 ps
CPU time 1.04 seconds
Started Sep 18 09:14:18 PM UTC 24
Finished Sep 18 09:14:20 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476596114 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.3476596114
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/34.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_cfg_cmd.1896526249
Short name T748
Test name
Test status
Simulation time 288022513 ps
CPU time 4.73 seconds
Started Sep 18 09:14:03 PM UTC 24
Finished Sep 18 09:14:09 PM UTC 24
Peak memory 235096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896526249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1896526249
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/34.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_csb_read.1704965271
Short name T738
Test name
Test status
Simulation time 36133395 ps
CPU time 1.12 seconds
Started Sep 18 09:13:49 PM UTC 24
Finished Sep 18 09:13:51 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704965271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1704965271
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/34.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_all.4142840447
Short name T761
Test name
Test status
Simulation time 1793561842 ps
CPU time 22.67 seconds
Started Sep 18 09:14:07 PM UTC 24
Finished Sep 18 09:14:31 PM UTC 24
Peak memory 247468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142840447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.4142840447
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/34.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.56877235
Short name T916
Test name
Test status
Simulation time 39780871283 ps
CPU time 211.55 seconds
Started Sep 18 09:14:09 PM UTC 24
Finished Sep 18 09:17:44 PM UTC 24
Peak memory 263968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56877235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.56877235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/34.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.1006883869
Short name T879
Test name
Test status
Simulation time 12938755556 ps
CPU time 179.76 seconds
Started Sep 18 09:14:10 PM UTC 24
Finished Sep 18 09:17:13 PM UTC 24
Peak memory 274280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006883869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.1006883869
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode.2525995842
Short name T747
Test name
Test status
Simulation time 56391407 ps
CPU time 4.23 seconds
Started Sep 18 09:14:03 PM UTC 24
Finished Sep 18 09:14:09 PM UTC 24
Peak memory 235176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525995842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2525995842
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/34.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.1838998774
Short name T836
Test name
Test status
Simulation time 30590930263 ps
CPU time 140.51 seconds
Started Sep 18 09:14:06 PM UTC 24
Finished Sep 18 09:16:29 PM UTC 24
Peak memory 266152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838998774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.1838998774
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_intercept.2139567520
Short name T744
Test name
Test status
Simulation time 104738623 ps
CPU time 5.06 seconds
Started Sep 18 09:13:57 PM UTC 24
Finished Sep 18 09:14:03 PM UTC 24
Peak memory 245416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139567520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2139567520
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/34.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_mailbox.1316777401
Short name T227
Test name
Test status
Simulation time 4217470106 ps
CPU time 45.27 seconds
Started Sep 18 09:14:00 PM UTC 24
Finished Sep 18 09:14:47 PM UTC 24
Peak memory 245420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316777401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1316777401
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/34.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.3424350462
Short name T741
Test name
Test status
Simulation time 46881975 ps
CPU time 2.4 seconds
Started Sep 18 09:13:56 PM UTC 24
Finished Sep 18 09:13:59 PM UTC 24
Peak memory 245160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424350462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.3424350462
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/34.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.4174015032
Short name T752
Test name
Test status
Simulation time 8801401843 ps
CPU time 26.15 seconds
Started Sep 18 09:13:52 PM UTC 24
Finished Sep 18 09:14:20 PM UTC 24
Peak memory 245548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174015032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.4174015032
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/34.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.2744175350
Short name T751
Test name
Test status
Simulation time 777914943 ps
CPU time 9.32 seconds
Started Sep 18 09:14:07 PM UTC 24
Finished Sep 18 09:14:17 PM UTC 24
Peak memory 233844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744175350 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.2744175350
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/34.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.165669756
Short name T196
Test name
Test status
Simulation time 2056786141 ps
CPU time 38.31 seconds
Started Sep 18 09:14:13 PM UTC 24
Finished Sep 18 09:14:53 PM UTC 24
Peak memory 261792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165669756 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.165669756
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/34.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_all.4055697511
Short name T755
Test name
Test status
Simulation time 7437456911 ps
CPU time 28.59 seconds
Started Sep 18 09:13:51 PM UTC 24
Finished Sep 18 09:14:21 PM UTC 24
Peak memory 227944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055697511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.4055697511
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/34.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.2207135048
Short name T750
Test name
Test status
Simulation time 19737409281 ps
CPU time 24.5 seconds
Started Sep 18 09:13:51 PM UTC 24
Finished Sep 18 09:14:16 PM UTC 24
Peak memory 227872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207135048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2207135048
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/34.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_rw.866783834
Short name T740
Test name
Test status
Simulation time 587863471 ps
CPU time 2.62 seconds
Started Sep 18 09:13:52 PM UTC 24
Finished Sep 18 09:13:56 PM UTC 24
Peak memory 227688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866783834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.866783834
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/34.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.2596042736
Short name T739
Test name
Test status
Simulation time 17677111 ps
CPU time 1.12 seconds
Started Sep 18 09:13:52 PM UTC 24
Finished Sep 18 09:13:54 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596042736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2596042736
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/34.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_upload.1674562645
Short name T746
Test name
Test status
Simulation time 43918325 ps
CPU time 3.51 seconds
Started Sep 18 09:14:01 PM UTC 24
Finished Sep 18 09:14:06 PM UTC 24
Peak memory 245352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674562645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1674562645
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/34.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_alert_test.1010179478
Short name T769
Test name
Test status
Simulation time 11652946 ps
CPU time 1.08 seconds
Started Sep 18 09:14:45 PM UTC 24
Finished Sep 18 09:14:47 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010179478 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.1010179478
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/35.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_cfg_cmd.2897765495
Short name T763
Test name
Test status
Simulation time 38249870 ps
CPU time 3.15 seconds
Started Sep 18 09:14:31 PM UTC 24
Finished Sep 18 09:14:35 PM UTC 24
Peak memory 245144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897765495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2897765495
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/35.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_csb_read.148047545
Short name T753
Test name
Test status
Simulation time 31282787 ps
CPU time 1.18 seconds
Started Sep 18 09:14:18 PM UTC 24
Finished Sep 18 09:14:20 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148047545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.148047545
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/35.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.2826255814
Short name T375
Test name
Test status
Simulation time 1156747177 ps
CPU time 6.32 seconds
Started Sep 18 09:14:37 PM UTC 24
Finished Sep 18 09:14:44 PM UTC 24
Peak memory 235180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826255814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2826255814
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/35.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.2730468201
Short name T791
Test name
Test status
Simulation time 3912200497 ps
CPU time 24.12 seconds
Started Sep 18 09:14:42 PM UTC 24
Finished Sep 18 09:15:07 PM UTC 24
Peak memory 247652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730468201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2730468201
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.4079752226
Short name T876
Test name
Test status
Simulation time 41088774102 ps
CPU time 143.7 seconds
Started Sep 18 09:14:43 PM UTC 24
Finished Sep 18 09:17:09 PM UTC 24
Peak memory 262052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079752226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.4079752226
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode.3468235318
Short name T776
Test name
Test status
Simulation time 883863012 ps
CPU time 18.86 seconds
Started Sep 18 09:14:32 PM UTC 24
Finished Sep 18 09:14:52 PM UTC 24
Peak memory 245528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468235318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3468235318
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/35.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.2307713196
Short name T805
Test name
Test status
Simulation time 7266066403 ps
CPU time 50.47 seconds
Started Sep 18 09:14:32 PM UTC 24
Finished Sep 18 09:15:25 PM UTC 24
Peak memory 268056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307713196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.2307713196
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_intercept.2878255077
Short name T304
Test name
Test status
Simulation time 762184689 ps
CPU time 5.91 seconds
Started Sep 18 09:14:24 PM UTC 24
Finished Sep 18 09:14:31 PM UTC 24
Peak memory 235104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878255077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2878255077
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/35.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_mailbox.3996396867
Short name T764
Test name
Test status
Simulation time 531446644 ps
CPU time 13.47 seconds
Started Sep 18 09:14:27 PM UTC 24
Finished Sep 18 09:14:41 PM UTC 24
Peak memory 245424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996396867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3996396867
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/35.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.3955098727
Short name T760
Test name
Test status
Simulation time 1690182145 ps
CPU time 4.2 seconds
Started Sep 18 09:14:24 PM UTC 24
Finished Sep 18 09:14:30 PM UTC 24
Peak memory 235028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955098727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.3955098727
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/35.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.558626159
Short name T768
Test name
Test status
Simulation time 4550861765 ps
CPU time 19.92 seconds
Started Sep 18 09:14:24 PM UTC 24
Finished Sep 18 09:14:45 PM UTC 24
Peak memory 245548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558626159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.558626159
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/35.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.1674928771
Short name T765
Test name
Test status
Simulation time 109480974 ps
CPU time 5.87 seconds
Started Sep 18 09:14:34 PM UTC 24
Finished Sep 18 09:14:42 PM UTC 24
Peak memory 233780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674928771 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.1674928771
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/35.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_all.40995582
Short name T766
Test name
Test status
Simulation time 2659942390 ps
CPU time 19.96 seconds
Started Sep 18 09:14:22 PM UTC 24
Finished Sep 18 09:14:43 PM UTC 24
Peak memory 231916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40995582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.40995582
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/35.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.1371267904
Short name T779
Test name
Test status
Simulation time 27943658007 ps
CPU time 35.12 seconds
Started Sep 18 09:14:20 PM UTC 24
Finished Sep 18 09:14:57 PM UTC 24
Peak memory 229944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371267904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1371267904
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/35.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_rw.1813742183
Short name T762
Test name
Test status
Simulation time 1063656053 ps
CPU time 10.89 seconds
Started Sep 18 09:14:22 PM UTC 24
Finished Sep 18 09:14:34 PM UTC 24
Peak memory 227756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813742183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1813742183
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/35.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.2959200837
Short name T757
Test name
Test status
Simulation time 37826057 ps
CPU time 1.09 seconds
Started Sep 18 09:14:22 PM UTC 24
Finished Sep 18 09:14:24 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959200837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2959200837
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/35.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_upload.542011159
Short name T767
Test name
Test status
Simulation time 3521715889 ps
CPU time 11.97 seconds
Started Sep 18 09:14:31 PM UTC 24
Finished Sep 18 09:14:44 PM UTC 24
Peak memory 245456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542011159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.542011159
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/35.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_alert_test.270937956
Short name T783
Test name
Test status
Simulation time 10589453 ps
CPU time 1.07 seconds
Started Sep 18 09:14:58 PM UTC 24
Finished Sep 18 09:15:00 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270937956 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.270937956
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/36.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_cfg_cmd.221843812
Short name T778
Test name
Test status
Simulation time 34143005 ps
CPU time 3.17 seconds
Started Sep 18 09:14:52 PM UTC 24
Finished Sep 18 09:14:56 PM UTC 24
Peak memory 245360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221843812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.221843812
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/36.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_csb_read.1706498396
Short name T772
Test name
Test status
Simulation time 77394568 ps
CPU time 1.19 seconds
Started Sep 18 09:14:45 PM UTC 24
Finished Sep 18 09:14:47 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706498396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1706498396
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/36.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_all.4226326639
Short name T1026
Test name
Test status
Simulation time 38757765843 ps
CPU time 395.5 seconds
Started Sep 18 09:14:57 PM UTC 24
Finished Sep 18 09:21:38 PM UTC 24
Peak memory 268076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226326639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.4226326639
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/36.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode.3319734721
Short name T786
Test name
Test status
Simulation time 3758835148 ps
CPU time 6.95 seconds
Started Sep 18 09:14:54 PM UTC 24
Finished Sep 18 09:15:02 PM UTC 24
Peak memory 251628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319734721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3319734721
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/36.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.744987422
Short name T369
Test name
Test status
Simulation time 12394426862 ps
CPU time 98.38 seconds
Started Sep 18 09:14:54 PM UTC 24
Finished Sep 18 09:16:35 PM UTC 24
Peak memory 261936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744987422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.744987422
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_intercept.2007113766
Short name T782
Test name
Test status
Simulation time 1291092299 ps
CPU time 9.84 seconds
Started Sep 18 09:14:49 PM UTC 24
Finished Sep 18 09:15:00 PM UTC 24
Peak memory 245416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007113766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2007113766
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/36.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_mailbox.2614810538
Short name T283
Test name
Test status
Simulation time 1540660962 ps
CPU time 18.41 seconds
Started Sep 18 09:14:50 PM UTC 24
Finished Sep 18 09:15:10 PM UTC 24
Peak memory 251492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614810538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2614810538
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/36.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.1619673232
Short name T374
Test name
Test status
Simulation time 616675942 ps
CPU time 5.51 seconds
Started Sep 18 09:14:49 PM UTC 24
Finished Sep 18 09:14:56 PM UTC 24
Peak memory 235236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619673232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.1619673232
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/36.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.2111807310
Short name T790
Test name
Test status
Simulation time 5726374405 ps
CPU time 18.4 seconds
Started Sep 18 09:14:48 PM UTC 24
Finished Sep 18 09:15:07 PM UTC 24
Peak memory 251696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111807310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2111807310
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/36.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.4192841635
Short name T792
Test name
Test status
Simulation time 3303670652 ps
CPU time 13.45 seconds
Started Sep 18 09:14:55 PM UTC 24
Finished Sep 18 09:15:10 PM UTC 24
Peak memory 233908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192841635 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.4192841635
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/36.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.2626417505
Short name T87
Test name
Test status
Simulation time 26862215259 ps
CPU time 187.05 seconds
Started Sep 18 09:14:57 PM UTC 24
Finished Sep 18 09:18:07 PM UTC 24
Peak memory 268076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626417505 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.2626417505
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/36.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_all.3378253355
Short name T785
Test name
Test status
Simulation time 6930961722 ps
CPU time 14.64 seconds
Started Sep 18 09:14:46 PM UTC 24
Finished Sep 18 09:15:02 PM UTC 24
Peak memory 228000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378253355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3378253355
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/36.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.2610425948
Short name T781
Test name
Test status
Simulation time 8748088764 ps
CPU time 13.41 seconds
Started Sep 18 09:14:45 PM UTC 24
Finished Sep 18 09:14:59 PM UTC 24
Peak memory 227804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610425948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2610425948
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/36.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_rw.3620084456
Short name T775
Test name
Test status
Simulation time 121253415 ps
CPU time 1.83 seconds
Started Sep 18 09:14:48 PM UTC 24
Finished Sep 18 09:14:50 PM UTC 24
Peak memory 227088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620084456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3620084456
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/36.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.228977701
Short name T774
Test name
Test status
Simulation time 26356116 ps
CPU time 0.94 seconds
Started Sep 18 09:14:48 PM UTC 24
Finished Sep 18 09:14:49 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228977701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.228977701
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/36.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_upload.2993733042
Short name T777
Test name
Test status
Simulation time 173636404 ps
CPU time 3.56 seconds
Started Sep 18 09:14:50 PM UTC 24
Finished Sep 18 09:14:55 PM UTC 24
Peak memory 245352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993733042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2993733042
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/36.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_alert_test.3286539752
Short name T800
Test name
Test status
Simulation time 15834488 ps
CPU time 1.13 seconds
Started Sep 18 09:15:17 PM UTC 24
Finished Sep 18 09:15:19 PM UTC 24
Peak memory 213048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286539752 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.3286539752
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/37.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_cfg_cmd.784615858
Short name T796
Test name
Test status
Simulation time 1089412926 ps
CPU time 5.96 seconds
Started Sep 18 09:15:08 PM UTC 24
Finished Sep 18 09:15:15 PM UTC 24
Peak memory 235100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784615858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.784615858
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/37.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_csb_read.1754967452
Short name T784
Test name
Test status
Simulation time 23527372 ps
CPU time 1.27 seconds
Started Sep 18 09:14:58 PM UTC 24
Finished Sep 18 09:15:00 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754967452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1754967452
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/37.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.566552524
Short name T971
Test name
Test status
Simulation time 142784511715 ps
CPU time 203.43 seconds
Started Sep 18 09:15:11 PM UTC 24
Finished Sep 18 09:18:37 PM UTC 24
Peak memory 251620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566552524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.566552524
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/37.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.2774490582
Short name T331
Test name
Test status
Simulation time 3233935815 ps
CPU time 95.27 seconds
Started Sep 18 09:15:12 PM UTC 24
Finished Sep 18 09:16:50 PM UTC 24
Peak memory 266224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774490582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2774490582
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/37.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.236314571
Short name T370
Test name
Test status
Simulation time 79280429558 ps
CPU time 97.5 seconds
Started Sep 18 09:15:14 PM UTC 24
Finished Sep 18 09:16:54 PM UTC 24
Peak memory 261848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236314571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.236314571
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode.18049204
Short name T806
Test name
Test status
Simulation time 400013820 ps
CPU time 16.02 seconds
Started Sep 18 09:15:08 PM UTC 24
Finished Sep 18 09:15:26 PM UTC 24
Peak memory 251564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18049204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.18049204
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/37.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.2029287677
Short name T988
Test name
Test status
Simulation time 53091220441 ps
CPU time 220.18 seconds
Started Sep 18 09:15:11 PM UTC 24
Finished Sep 18 09:18:54 PM UTC 24
Peak memory 278316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029287677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.2029287677
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_intercept.2522845749
Short name T799
Test name
Test status
Simulation time 1416772596 ps
CPU time 13.31 seconds
Started Sep 18 09:15:04 PM UTC 24
Finished Sep 18 09:15:18 PM UTC 24
Peak memory 245488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522845749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2522845749
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/37.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_mailbox.397417378
Short name T946
Test name
Test status
Simulation time 50386153775 ps
CPU time 189.56 seconds
Started Sep 18 09:15:05 PM UTC 24
Finished Sep 18 09:18:17 PM UTC 24
Peak memory 251572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397417378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.397417378
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/37.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.2676596036
Short name T795
Test name
Test status
Simulation time 1195799867 ps
CPU time 8.96 seconds
Started Sep 18 09:15:03 PM UTC 24
Finished Sep 18 09:15:14 PM UTC 24
Peak memory 235248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676596036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.2676596036
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/37.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.1606483731
Short name T794
Test name
Test status
Simulation time 312763992 ps
CPU time 6.45 seconds
Started Sep 18 09:15:03 PM UTC 24
Finished Sep 18 09:15:11 PM UTC 24
Peak memory 235168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606483731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1606483731
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/37.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.3587592270
Short name T798
Test name
Test status
Simulation time 295792031 ps
CPU time 5.66 seconds
Started Sep 18 09:15:11 PM UTC 24
Finished Sep 18 09:15:18 PM UTC 24
Peak memory 231668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587592270 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.3587592270
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/37.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.2874665900
Short name T797
Test name
Test status
Simulation time 137002764 ps
CPU time 1.47 seconds
Started Sep 18 09:15:14 PM UTC 24
Finished Sep 18 09:15:17 PM UTC 24
Peak memory 214776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874665900 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.2874665900
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/37.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_all.3684138980
Short name T811
Test name
Test status
Simulation time 17410425547 ps
CPU time 32.49 seconds
Started Sep 18 09:15:01 PM UTC 24
Finished Sep 18 09:15:35 PM UTC 24
Peak memory 227504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684138980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3684138980
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/37.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.1881740465
Short name T787
Test name
Test status
Simulation time 31451297 ps
CPU time 0.91 seconds
Started Sep 18 09:15:01 PM UTC 24
Finished Sep 18 09:15:03 PM UTC 24
Peak memory 214804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881740465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1881740465
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/37.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_rw.284388904
Short name T789
Test name
Test status
Simulation time 80227757 ps
CPU time 1.77 seconds
Started Sep 18 09:15:02 PM UTC 24
Finished Sep 18 09:15:05 PM UTC 24
Peak memory 216876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284388904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.284388904
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/37.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.1895498133
Short name T788
Test name
Test status
Simulation time 89016697 ps
CPU time 1.45 seconds
Started Sep 18 09:15:01 PM UTC 24
Finished Sep 18 09:15:03 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895498133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1895498133
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/37.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_upload.332190438
Short name T793
Test name
Test status
Simulation time 41188442 ps
CPU time 3.32 seconds
Started Sep 18 09:15:06 PM UTC 24
Finished Sep 18 09:15:10 PM UTC 24
Peak memory 245100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332190438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.332190438
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/37.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_alert_test.3522916219
Short name T816
Test name
Test status
Simulation time 10583929 ps
CPU time 1.11 seconds
Started Sep 18 09:15:40 PM UTC 24
Finished Sep 18 09:15:43 PM UTC 24
Peak memory 213048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522916219 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.3522916219
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/38.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_cfg_cmd.1863599776
Short name T812
Test name
Test status
Simulation time 371755129 ps
CPU time 7.19 seconds
Started Sep 18 09:15:27 PM UTC 24
Finished Sep 18 09:15:35 PM UTC 24
Peak memory 235048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863599776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1863599776
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/38.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_csb_read.2493886214
Short name T802
Test name
Test status
Simulation time 26979525 ps
CPU time 1.14 seconds
Started Sep 18 09:15:18 PM UTC 24
Finished Sep 18 09:15:20 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493886214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2493886214
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/38.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_all.1237119413
Short name T1013
Test name
Test status
Simulation time 451946587502 ps
CPU time 232.54 seconds
Started Sep 18 09:15:33 PM UTC 24
Finished Sep 18 09:19:29 PM UTC 24
Peak memory 261864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237119413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1237119413
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/38.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.2233259971
Short name T933
Test name
Test status
Simulation time 17841464283 ps
CPU time 144.53 seconds
Started Sep 18 09:15:36 PM UTC 24
Finished Sep 18 09:18:03 PM UTC 24
Peak memory 268076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233259971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2233259971
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/38.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.59732378
Short name T363
Test name
Test status
Simulation time 22130257037 ps
CPU time 62.44 seconds
Started Sep 18 09:15:36 PM UTC 24
Finished Sep 18 09:16:40 PM UTC 24
Peak memory 262000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59732378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.59732378
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode.2365316712
Short name T820
Test name
Test status
Simulation time 1378325188 ps
CPU time 17.43 seconds
Started Sep 18 09:15:30 PM UTC 24
Finished Sep 18 09:15:49 PM UTC 24
Peak memory 235172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365316712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2365316712
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/38.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.4057908531
Short name T837
Test name
Test status
Simulation time 6350310612 ps
CPU time 55.96 seconds
Started Sep 18 09:15:31 PM UTC 24
Finished Sep 18 09:16:29 PM UTC 24
Peak memory 235296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057908531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.4057908531
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_intercept.3638991834
Short name T809
Test name
Test status
Simulation time 202121472 ps
CPU time 5.28 seconds
Started Sep 18 09:15:24 PM UTC 24
Finished Sep 18 09:15:31 PM UTC 24
Peak memory 235172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638991834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3638991834
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/38.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_mailbox.356282273
Short name T840
Test name
Test status
Simulation time 5506722279 ps
CPU time 65.75 seconds
Started Sep 18 09:15:25 PM UTC 24
Finished Sep 18 09:16:33 PM UTC 24
Peak memory 245552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356282273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.356282273
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/38.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.3088049461
Short name T808
Test name
Test status
Simulation time 711635142 ps
CPU time 6.29 seconds
Started Sep 18 09:15:23 PM UTC 24
Finished Sep 18 09:15:30 PM UTC 24
Peak memory 235172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088049461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.3088049461
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/38.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.102898140
Short name T822
Test name
Test status
Simulation time 14550771125 ps
CPU time 29.54 seconds
Started Sep 18 09:15:21 PM UTC 24
Finished Sep 18 09:15:52 PM UTC 24
Peak memory 247528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102898140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.102898140
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/38.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.80722814
Short name T815
Test name
Test status
Simulation time 14191887626 ps
CPU time 8.28 seconds
Started Sep 18 09:15:31 PM UTC 24
Finished Sep 18 09:15:41 PM UTC 24
Peak memory 233924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80722814 -assert nopostproc +UVM_TESTNAME=spi_device_bas
e_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.80722814
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/38.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.2781145610
Short name T89
Test name
Test status
Simulation time 32837924321 ps
CPU time 418.04 seconds
Started Sep 18 09:15:36 PM UTC 24
Finished Sep 18 09:22:40 PM UTC 24
Peak memory 284520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781145610 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.2781145610
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/38.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_all.2262458666
Short name T810
Test name
Test status
Simulation time 2451672915 ps
CPU time 10.97 seconds
Started Sep 18 09:15:19 PM UTC 24
Finished Sep 18 09:15:32 PM UTC 24
Peak memory 227896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262458666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2262458666
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/38.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.564643262
Short name T819
Test name
Test status
Simulation time 9630307088 ps
CPU time 27.55 seconds
Started Sep 18 09:15:19 PM UTC 24
Finished Sep 18 09:15:48 PM UTC 24
Peak memory 227892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564643262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.564643262
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/38.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_rw.2634496025
Short name T804
Test name
Test status
Simulation time 21833946 ps
CPU time 1.23 seconds
Started Sep 18 09:15:21 PM UTC 24
Finished Sep 18 09:15:23 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634496025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2634496025
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/38.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.4210160444
Short name T803
Test name
Test status
Simulation time 97343665 ps
CPU time 1.18 seconds
Started Sep 18 09:15:19 PM UTC 24
Finished Sep 18 09:15:22 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210160444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.4210160444
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/38.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_upload.1159504745
Short name T813
Test name
Test status
Simulation time 248297568 ps
CPU time 7.39 seconds
Started Sep 18 09:15:27 PM UTC 24
Finished Sep 18 09:15:35 PM UTC 24
Peak memory 245336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159504745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1159504745
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/38.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_alert_test.774796801
Short name T832
Test name
Test status
Simulation time 37544469 ps
CPU time 1.1 seconds
Started Sep 18 09:16:22 PM UTC 24
Finished Sep 18 09:16:25 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774796801 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.774796801
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/39.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_cfg_cmd.4126480890
Short name T825
Test name
Test status
Simulation time 490319274 ps
CPU time 3.12 seconds
Started Sep 18 09:16:04 PM UTC 24
Finished Sep 18 09:16:08 PM UTC 24
Peak memory 235160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126480890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.4126480890
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/39.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_csb_read.2504396042
Short name T817
Test name
Test status
Simulation time 42616993 ps
CPU time 1.18 seconds
Started Sep 18 09:15:42 PM UTC 24
Finished Sep 18 09:15:44 PM UTC 24
Peak memory 215160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504396042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2504396042
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/39.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.4271028860
Short name T883
Test name
Test status
Simulation time 2193849927 ps
CPU time 59.27 seconds
Started Sep 18 09:16:14 PM UTC 24
Finished Sep 18 09:17:15 PM UTC 24
Peak memory 264044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271028860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.4271028860
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/39.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.3438081174
Short name T1028
Test name
Test status
Simulation time 173585353539 ps
CPU time 362.96 seconds
Started Sep 18 09:16:18 PM UTC 24
Finished Sep 18 09:22:26 PM UTC 24
Peak memory 263980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438081174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3438081174
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/39.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.673056591
Short name T947
Test name
Test status
Simulation time 7039156325 ps
CPU time 116.56 seconds
Started Sep 18 09:16:19 PM UTC 24
Finished Sep 18 09:18:18 PM UTC 24
Peak memory 266092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673056591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.673056591
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.2455940188
Short name T852
Test name
Test status
Simulation time 8244223143 ps
CPU time 37.59 seconds
Started Sep 18 09:16:09 PM UTC 24
Finished Sep 18 09:16:48 PM UTC 24
Peak memory 251624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455940188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2455940188
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/39.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.1946261445
Short name T937
Test name
Test status
Simulation time 66926554216 ps
CPU time 115.17 seconds
Started Sep 18 09:16:10 PM UTC 24
Finished Sep 18 09:18:08 PM UTC 24
Peak memory 261868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946261445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.1946261445
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_intercept.362952666
Short name T251
Test name
Test status
Simulation time 2395791583 ps
CPU time 8.26 seconds
Started Sep 18 09:15:53 PM UTC 24
Finished Sep 18 09:16:03 PM UTC 24
Peak memory 235236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362952666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.362952666
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/39.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_mailbox.1516249790
Short name T824
Test name
Test status
Simulation time 795794914 ps
CPU time 5.79 seconds
Started Sep 18 09:15:54 PM UTC 24
Finished Sep 18 09:16:01 PM UTC 24
Peak memory 245356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516249790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1516249790
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/39.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.2544829810
Short name T828
Test name
Test status
Simulation time 12764841898 ps
CPU time 23.51 seconds
Started Sep 18 09:15:52 PM UTC 24
Finished Sep 18 09:16:17 PM UTC 24
Peak memory 235164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544829810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.2544829810
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/39.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.1463533042
Short name T827
Test name
Test status
Simulation time 11614404613 ps
CPU time 22.06 seconds
Started Sep 18 09:15:50 PM UTC 24
Finished Sep 18 09:16:13 PM UTC 24
Peak memory 245548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463533042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1463533042
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/39.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.93435961
Short name T839
Test name
Test status
Simulation time 1412421918 ps
CPU time 16.73 seconds
Started Sep 18 09:16:13 PM UTC 24
Finished Sep 18 09:16:31 PM UTC 24
Peak memory 233716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93435961 -assert nopostproc +UVM_TESTNAME=spi_device_bas
e_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.93435961
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/39.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.2488312787
Short name T833
Test name
Test status
Simulation time 247204380 ps
CPU time 1.51 seconds
Started Sep 18 09:16:22 PM UTC 24
Finished Sep 18 09:16:25 PM UTC 24
Peak memory 216508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488312787 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.2488312787
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/39.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.1170402840
Short name T835
Test name
Test status
Simulation time 2739693832 ps
CPU time 42.1 seconds
Started Sep 18 09:15:45 PM UTC 24
Finished Sep 18 09:16:29 PM UTC 24
Peak memory 227892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170402840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1170402840
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/39.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.1110635611
Short name T818
Test name
Test status
Simulation time 472517052 ps
CPU time 2.06 seconds
Started Sep 18 09:15:44 PM UTC 24
Finished Sep 18 09:15:47 PM UTC 24
Peak memory 216880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110635611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1110635611
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/39.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_rw.801392016
Short name T823
Test name
Test status
Simulation time 54880532 ps
CPU time 2.25 seconds
Started Sep 18 09:15:50 PM UTC 24
Finished Sep 18 09:15:53 PM UTC 24
Peak memory 227832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801392016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.801392016
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/39.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.740543420
Short name T821
Test name
Test status
Simulation time 166710248 ps
CPU time 1.37 seconds
Started Sep 18 09:15:48 PM UTC 24
Finished Sep 18 09:15:51 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740543420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.740543420
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/39.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_upload.135755031
Short name T831
Test name
Test status
Simulation time 5838397855 ps
CPU time 19.66 seconds
Started Sep 18 09:16:02 PM UTC 24
Finished Sep 18 09:16:23 PM UTC 24
Peak memory 251628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135755031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.135755031
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/39.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.1622667387
Short name T197
Test name
Test status
Simulation time 12465246 ps
CPU time 1.09 seconds
Started Sep 18 09:03:44 PM UTC 24
Finished Sep 18 09:03:46 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622667387 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1622667387
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.126315123
Short name T223
Test name
Test status
Simulation time 461599657 ps
CPU time 9.08 seconds
Started Sep 18 09:03:32 PM UTC 24
Finished Sep 18 09:03:43 PM UTC 24
Peak memory 235184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126315123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.126315123
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.860520017
Short name T410
Test name
Test status
Simulation time 43685115 ps
CPU time 1.15 seconds
Started Sep 18 09:03:23 PM UTC 24
Finished Sep 18 09:03:25 PM UTC 24
Peak memory 215100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860520017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.860520017
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.3089721401
Short name T100
Test name
Test status
Simulation time 10249560753 ps
CPU time 36.74 seconds
Started Sep 18 09:03:35 PM UTC 24
Finished Sep 18 09:04:13 PM UTC 24
Peak memory 261920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089721401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3089721401
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.2855191793
Short name T53
Test name
Test status
Simulation time 917591339 ps
CPU time 25.42 seconds
Started Sep 18 09:03:39 PM UTC 24
Finished Sep 18 09:04:05 PM UTC 24
Peak memory 268068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855191793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2855191793
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.474641157
Short name T233
Test name
Test status
Simulation time 26300464706 ps
CPU time 273.53 seconds
Started Sep 18 09:03:40 PM UTC 24
Finished Sep 18 09:08:17 PM UTC 24
Peak memory 268080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474641157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.474641157
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.2634907089
Short name T181
Test name
Test status
Simulation time 5447826564 ps
CPU time 17.25 seconds
Started Sep 18 09:03:33 PM UTC 24
Finished Sep 18 09:03:52 PM UTC 24
Peak memory 235244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634907089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2634907089
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.3594388800
Short name T121
Test name
Test status
Simulation time 54743290256 ps
CPU time 128.06 seconds
Started Sep 18 09:03:34 PM UTC 24
Finished Sep 18 09:05:44 PM UTC 24
Peak memory 261936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594388800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.3594388800
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.1543169199
Short name T143
Test name
Test status
Simulation time 56319302 ps
CPU time 3.26 seconds
Started Sep 18 09:03:29 PM UTC 24
Finished Sep 18 09:03:34 PM UTC 24
Peak memory 245100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543169199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1543169199
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.1071040607
Short name T296
Test name
Test status
Simulation time 12351250852 ps
CPU time 147.96 seconds
Started Sep 18 09:03:29 PM UTC 24
Finished Sep 18 09:06:00 PM UTC 24
Peak memory 261872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071040607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1071040607
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.1838772472
Short name T411
Test name
Test status
Simulation time 21998856 ps
CPU time 1.46 seconds
Started Sep 18 09:03:23 PM UTC 24
Finished Sep 18 09:03:25 PM UTC 24
Peak memory 228264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838772472 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_parity.1838772472
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.609965939
Short name T203
Test name
Test status
Simulation time 655123207 ps
CPU time 3.79 seconds
Started Sep 18 09:03:28 PM UTC 24
Finished Sep 18 09:03:33 PM UTC 24
Peak memory 245420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609965939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.609965939
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.1820321594
Short name T67
Test name
Test status
Simulation time 4916774212 ps
CPU time 9.49 seconds
Started Sep 18 09:03:27 PM UTC 24
Finished Sep 18 09:03:38 PM UTC 24
Peak memory 251692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820321594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1820321594
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.2031219357
Short name T180
Test name
Test status
Simulation time 149342679 ps
CPU time 5.62 seconds
Started Sep 18 09:03:35 PM UTC 24
Finished Sep 18 09:03:41 PM UTC 24
Peak memory 233764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031219357 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.2031219357
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.2527027490
Short name T35
Test name
Test status
Simulation time 118144026 ps
CPU time 1.53 seconds
Started Sep 18 09:03:43 PM UTC 24
Finished Sep 18 09:03:46 PM UTC 24
Peak memory 257652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527027490 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2527027490
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.3400216054
Short name T33
Test name
Test status
Simulation time 56298379 ps
CPU time 1.78 seconds
Started Sep 18 09:03:42 PM UTC 24
Finished Sep 18 09:03:45 PM UTC 24
Peak memory 215088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400216054 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.3400216054
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.1670128607
Short name T412
Test name
Test status
Simulation time 59287460 ps
CPU time 1.12 seconds
Started Sep 18 09:03:24 PM UTC 24
Finished Sep 18 09:03:26 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670128607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1670128607
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.1503905395
Short name T76
Test name
Test status
Simulation time 7458067520 ps
CPU time 37.54 seconds
Started Sep 18 09:03:24 PM UTC 24
Finished Sep 18 09:04:03 PM UTC 24
Peak memory 227892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503905395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1503905395
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.3005471727
Short name T31
Test name
Test status
Simulation time 37522481 ps
CPU time 1.88 seconds
Started Sep 18 09:03:26 PM UTC 24
Finished Sep 18 09:03:29 PM UTC 24
Peak memory 226632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005471727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3005471727
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.2831136112
Short name T413
Test name
Test status
Simulation time 253964362 ps
CPU time 1.46 seconds
Started Sep 18 09:03:26 PM UTC 24
Finished Sep 18 09:03:28 PM UTC 24
Peak memory 215100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831136112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2831136112
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.1288407270
Short name T82
Test name
Test status
Simulation time 2098548290 ps
CPU time 14.46 seconds
Started Sep 18 09:03:29 PM UTC 24
Finished Sep 18 09:03:45 PM UTC 24
Peak memory 235116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288407270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1288407270
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/4.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.4155033449
Short name T848
Test name
Test status
Simulation time 14734327 ps
CPU time 1.05 seconds
Started Sep 18 09:16:42 PM UTC 24
Finished Sep 18 09:16:44 PM UTC 24
Peak memory 213048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155033449 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.4155033449
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/40.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_cfg_cmd.1860880130
Short name T844
Test name
Test status
Simulation time 108908416 ps
CPU time 3.11 seconds
Started Sep 18 09:16:35 PM UTC 24
Finished Sep 18 09:16:39 PM UTC 24
Peak memory 234532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860880130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1860880130
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/40.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_csb_read.1647845494
Short name T834
Test name
Test status
Simulation time 57511782 ps
CPU time 1.15 seconds
Started Sep 18 09:16:24 PM UTC 24
Finished Sep 18 09:16:27 PM UTC 24
Peak memory 215100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647845494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1647845494
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/40.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.1893403123
Short name T847
Test name
Test status
Simulation time 219551063 ps
CPU time 1.6 seconds
Started Sep 18 09:16:39 PM UTC 24
Finished Sep 18 09:16:42 PM UTC 24
Peak memory 225972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893403123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1893403123
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/40.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.243050479
Short name T1025
Test name
Test status
Simulation time 25535425421 ps
CPU time 253.96 seconds
Started Sep 18 09:16:40 PM UTC 24
Finished Sep 18 09:20:57 PM UTC 24
Peak memory 262064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243050479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.243050479
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.3842687795
Short name T1036
Test name
Test status
Simulation time 607585838604 ps
CPU time 604.27 seconds
Started Sep 18 09:16:41 PM UTC 24
Finished Sep 18 09:26:53 PM UTC 24
Peak memory 278308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842687795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.3842687795
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.1161876391
Short name T854
Test name
Test status
Simulation time 542901434 ps
CPU time 11.74 seconds
Started Sep 18 09:16:36 PM UTC 24
Finished Sep 18 09:16:49 PM UTC 24
Peak memory 245356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161876391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1161876391
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/40.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.3491720829
Short name T1021
Test name
Test status
Simulation time 17670828662 ps
CPU time 223.4 seconds
Started Sep 18 09:16:37 PM UTC 24
Finished Sep 18 09:20:24 PM UTC 24
Peak memory 276200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491720829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.3491720829
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_intercept.495840837
Short name T855
Test name
Test status
Simulation time 4248470714 ps
CPU time 18.02 seconds
Started Sep 18 09:16:31 PM UTC 24
Finished Sep 18 09:16:50 PM UTC 24
Peak memory 245480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495840837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.495840837
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/40.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.2746978180
Short name T846
Test name
Test status
Simulation time 288003672 ps
CPU time 7.34 seconds
Started Sep 18 09:16:32 PM UTC 24
Finished Sep 18 09:16:41 PM UTC 24
Peak memory 235244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746978180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2746978180
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/40.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.1597097244
Short name T843
Test name
Test status
Simulation time 1246351524 ps
CPU time 5.7 seconds
Started Sep 18 09:16:31 PM UTC 24
Finished Sep 18 09:16:38 PM UTC 24
Peak memory 245416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597097244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.1597097244
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/40.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.2727356857
Short name T845
Test name
Test status
Simulation time 20938247696 ps
CPU time 18.66 seconds
Started Sep 18 09:16:31 PM UTC 24
Finished Sep 18 09:16:51 PM UTC 24
Peak memory 245552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727356857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2727356857
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/40.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.3033838012
Short name T859
Test name
Test status
Simulation time 2687211066 ps
CPU time 15.61 seconds
Started Sep 18 09:16:38 PM UTC 24
Finished Sep 18 09:16:55 PM UTC 24
Peak memory 234968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033838012 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.3033838012
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/40.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.2382966613
Short name T849
Test name
Test status
Simulation time 88337236 ps
CPU time 1.69 seconds
Started Sep 18 09:16:42 PM UTC 24
Finished Sep 18 09:16:45 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382966613 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.2382966613
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/40.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.299336457
Short name T871
Test name
Test status
Simulation time 2692841547 ps
CPU time 38.61 seconds
Started Sep 18 09:16:26 PM UTC 24
Finished Sep 18 09:17:06 PM UTC 24
Peak memory 227900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299336457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.299336457
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/40.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.1155576436
Short name T842
Test name
Test status
Simulation time 1388978767 ps
CPU time 8.82 seconds
Started Sep 18 09:16:26 PM UTC 24
Finished Sep 18 09:16:36 PM UTC 24
Peak memory 227700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155576436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1155576436
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/40.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_rw.2003155787
Short name T841
Test name
Test status
Simulation time 58071652 ps
CPU time 2.94 seconds
Started Sep 18 09:16:29 PM UTC 24
Finished Sep 18 09:16:33 PM UTC 24
Peak memory 217528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003155787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2003155787
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/40.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.2758601746
Short name T838
Test name
Test status
Simulation time 14416323 ps
CPU time 1.09 seconds
Started Sep 18 09:16:28 PM UTC 24
Finished Sep 18 09:16:30 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758601746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2758601746
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/40.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.1900349758
Short name T851
Test name
Test status
Simulation time 10614337097 ps
CPU time 11.27 seconds
Started Sep 18 09:16:34 PM UTC 24
Finished Sep 18 09:16:47 PM UTC 24
Peak memory 235244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900349758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1900349758
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/40.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.1228099299
Short name T862
Test name
Test status
Simulation time 14981559 ps
CPU time 1.08 seconds
Started Sep 18 09:16:56 PM UTC 24
Finished Sep 18 09:16:58 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228099299 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.1228099299
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/41.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.2562243546
Short name T865
Test name
Test status
Simulation time 420026635 ps
CPU time 6.2 seconds
Started Sep 18 09:16:51 PM UTC 24
Finished Sep 18 09:16:59 PM UTC 24
Peak memory 245288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562243546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2562243546
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/41.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.18264737
Short name T850
Test name
Test status
Simulation time 19854748 ps
CPU time 1.09 seconds
Started Sep 18 09:16:43 PM UTC 24
Finished Sep 18 09:16:46 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18264737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.18264737
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/41.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.3699575088
Short name T882
Test name
Test status
Simulation time 11619804316 ps
CPU time 19.52 seconds
Started Sep 18 09:16:54 PM UTC 24
Finished Sep 18 09:17:15 PM UTC 24
Peak memory 251696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699575088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3699575088
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/41.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.1393027627
Short name T1022
Test name
Test status
Simulation time 19884131662 ps
CPU time 210.26 seconds
Started Sep 18 09:16:54 PM UTC 24
Finished Sep 18 09:20:28 PM UTC 24
Peak memory 262052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393027627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1393027627
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.3329809382
Short name T863
Test name
Test status
Simulation time 49775032 ps
CPU time 1.23 seconds
Started Sep 18 09:16:56 PM UTC 24
Finished Sep 18 09:16:58 PM UTC 24
Peak memory 228256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329809382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.3329809382
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.149502734
Short name T860
Test name
Test status
Simulation time 119538000 ps
CPU time 3.87 seconds
Started Sep 18 09:16:51 PM UTC 24
Finished Sep 18 09:16:56 PM UTC 24
Peak memory 247404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149502734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.149502734
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/41.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.1765883643
Short name T903
Test name
Test status
Simulation time 21269849135 ps
CPU time 41.37 seconds
Started Sep 18 09:16:53 PM UTC 24
Finished Sep 18 09:17:36 PM UTC 24
Peak memory 249580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765883643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.1765883643
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.751975021
Short name T858
Test name
Test status
Simulation time 343729628 ps
CPU time 3.43 seconds
Started Sep 18 09:16:50 PM UTC 24
Finished Sep 18 09:16:54 PM UTC 24
Peak memory 245352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751975021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.751975021
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/41.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.2498681916
Short name T869
Test name
Test status
Simulation time 2234000029 ps
CPU time 13.81 seconds
Started Sep 18 09:16:50 PM UTC 24
Finished Sep 18 09:17:05 PM UTC 24
Peak memory 235304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498681916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2498681916
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/41.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.1284131710
Short name T359
Test name
Test status
Simulation time 668389975 ps
CPU time 4.56 seconds
Started Sep 18 09:16:49 PM UTC 24
Finished Sep 18 09:16:54 PM UTC 24
Peak memory 235032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284131710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.1284131710
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/41.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.1661162742
Short name T861
Test name
Test status
Simulation time 2674240750 ps
CPU time 8.85 seconds
Started Sep 18 09:16:47 PM UTC 24
Finished Sep 18 09:16:57 PM UTC 24
Peak memory 245548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661162742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1661162742
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/41.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3892974375
Short name T866
Test name
Test status
Simulation time 919816504 ps
CPU time 5.63 seconds
Started Sep 18 09:16:53 PM UTC 24
Finished Sep 18 09:17:00 PM UTC 24
Peak memory 233680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892974375 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.3892974375
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/41.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.2094903747
Short name T671
Test name
Test status
Simulation time 1619282090 ps
CPU time 5.37 seconds
Started Sep 18 09:16:45 PM UTC 24
Finished Sep 18 09:16:51 PM UTC 24
Peak memory 229736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094903747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2094903747
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/41.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.2195005208
Short name T857
Test name
Test status
Simulation time 1029513371 ps
CPU time 8.98 seconds
Started Sep 18 09:16:44 PM UTC 24
Finished Sep 18 09:16:54 PM UTC 24
Peak memory 227664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195005208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2195005208
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/41.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.3190690631
Short name T856
Test name
Test status
Simulation time 79713994 ps
CPU time 4.19 seconds
Started Sep 18 09:16:46 PM UTC 24
Finished Sep 18 09:16:51 PM UTC 24
Peak memory 227684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190690631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3190690631
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/41.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.63265835
Short name T853
Test name
Test status
Simulation time 87541840 ps
CPU time 1.45 seconds
Started Sep 18 09:16:46 PM UTC 24
Finished Sep 18 09:16:48 PM UTC 24
Peak memory 214796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63265835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.63265835
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/41.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.4163797542
Short name T907
Test name
Test status
Simulation time 141734256061 ps
CPU time 44.26 seconds
Started Sep 18 09:16:51 PM UTC 24
Finished Sep 18 09:17:37 PM UTC 24
Peak memory 255720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163797542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.4163797542
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/41.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.1279015988
Short name T881
Test name
Test status
Simulation time 44076913 ps
CPU time 1.13 seconds
Started Sep 18 09:17:13 PM UTC 24
Finished Sep 18 09:17:15 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279015988 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.1279015988
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/42.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.1878733968
Short name T892
Test name
Test status
Simulation time 5238923894 ps
CPU time 17.35 seconds
Started Sep 18 09:17:06 PM UTC 24
Finished Sep 18 09:17:25 PM UTC 24
Peak memory 245536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878733968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1878733968
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/42.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.2178247080
Short name T864
Test name
Test status
Simulation time 70790914 ps
CPU time 1.23 seconds
Started Sep 18 09:16:56 PM UTC 24
Finished Sep 18 09:16:58 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178247080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2178247080
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/42.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.20043064
Short name T379
Test name
Test status
Simulation time 152729738299 ps
CPU time 348.11 seconds
Started Sep 18 09:17:09 PM UTC 24
Finished Sep 18 09:23:02 PM UTC 24
Peak memory 278252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20043064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.20043064
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/42.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.618751490
Short name T376
Test name
Test status
Simulation time 4801274957 ps
CPU time 89.42 seconds
Started Sep 18 09:17:10 PM UTC 24
Finished Sep 18 09:18:42 PM UTC 24
Peak memory 278204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618751490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.618751490
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.3665887219
Short name T356
Test name
Test status
Simulation time 88267538978 ps
CPU time 248.08 seconds
Started Sep 18 09:17:10 PM UTC 24
Finished Sep 18 09:21:22 PM UTC 24
Peak memory 266000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665887219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.3665887219
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.762075850
Short name T886
Test name
Test status
Simulation time 187174818 ps
CPU time 7.79 seconds
Started Sep 18 09:17:07 PM UTC 24
Finished Sep 18 09:17:16 PM UTC 24
Peak memory 245344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762075850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.762075850
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/42.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.3182515485
Short name T934
Test name
Test status
Simulation time 4354251914 ps
CPU time 54.5 seconds
Started Sep 18 09:17:07 PM UTC 24
Finished Sep 18 09:18:04 PM UTC 24
Peak memory 263908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182515485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.3182515485
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.2828332093
Short name T873
Test name
Test status
Simulation time 793193314 ps
CPU time 6.57 seconds
Started Sep 18 09:17:00 PM UTC 24
Finished Sep 18 09:17:08 PM UTC 24
Peak memory 245484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828332093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2828332093
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/42.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.3855993714
Short name T878
Test name
Test status
Simulation time 277889505 ps
CPU time 8.56 seconds
Started Sep 18 09:17:02 PM UTC 24
Finished Sep 18 09:17:11 PM UTC 24
Peak memory 245348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855993714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3855993714
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/42.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.1577036739
Short name T872
Test name
Test status
Simulation time 2014524696 ps
CPU time 4.79 seconds
Started Sep 18 09:17:00 PM UTC 24
Finished Sep 18 09:17:06 PM UTC 24
Peak memory 235172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577036739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.1577036739
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/42.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.1525726748
Short name T870
Test name
Test status
Simulation time 1184040253 ps
CPU time 4.57 seconds
Started Sep 18 09:17:00 PM UTC 24
Finished Sep 18 09:17:06 PM UTC 24
Peak memory 235048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525726748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1525726748
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/42.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2922188864
Short name T885
Test name
Test status
Simulation time 1119010912 ps
CPU time 7.26 seconds
Started Sep 18 09:17:08 PM UTC 24
Finished Sep 18 09:17:16 PM UTC 24
Peak memory 231796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922188864 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.2922188864
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/42.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.348057272
Short name T1015
Test name
Test status
Simulation time 8669771989 ps
CPU time 138.45 seconds
Started Sep 18 09:17:12 PM UTC 24
Finished Sep 18 09:19:33 PM UTC 24
Peak memory 268068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348057272 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.348057272
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/42.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.3453474757
Short name T908
Test name
Test status
Simulation time 26541710133 ps
CPU time 37.1 seconds
Started Sep 18 09:16:59 PM UTC 24
Finished Sep 18 09:17:37 PM UTC 24
Peak memory 231912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453474757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3453474757
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/42.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.3274599517
Short name T874
Test name
Test status
Simulation time 991242640 ps
CPU time 10.69 seconds
Started Sep 18 09:16:57 PM UTC 24
Finished Sep 18 09:17:09 PM UTC 24
Peak memory 227764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274599517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3274599517
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/42.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.550206386
Short name T868
Test name
Test status
Simulation time 45880148 ps
CPU time 1.8 seconds
Started Sep 18 09:16:59 PM UTC 24
Finished Sep 18 09:17:02 PM UTC 24
Peak memory 216748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550206386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.550206386
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/42.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.3955899088
Short name T867
Test name
Test status
Simulation time 103091309 ps
CPU time 1.39 seconds
Started Sep 18 09:16:59 PM UTC 24
Finished Sep 18 09:17:01 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955899088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3955899088
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/42.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.2506207291
Short name T877
Test name
Test status
Simulation time 382449541 ps
CPU time 7.3 seconds
Started Sep 18 09:17:03 PM UTC 24
Finished Sep 18 09:17:11 PM UTC 24
Peak memory 245352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506207291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2506207291
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/42.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.1502501571
Short name T901
Test name
Test status
Simulation time 14658961 ps
CPU time 1.1 seconds
Started Sep 18 09:17:29 PM UTC 24
Finished Sep 18 09:17:32 PM UTC 24
Peak memory 215012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502501571 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.1502501571
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/43.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.2757118256
Short name T893
Test name
Test status
Simulation time 64469665 ps
CPU time 3.05 seconds
Started Sep 18 09:17:21 PM UTC 24
Finished Sep 18 09:17:25 PM UTC 24
Peak memory 244960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757118256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2757118256
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/43.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.980305407
Short name T884
Test name
Test status
Simulation time 121736533 ps
CPU time 1.16 seconds
Started Sep 18 09:17:14 PM UTC 24
Finished Sep 18 09:17:16 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980305407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.980305407
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/43.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.3956213674
Short name T373
Test name
Test status
Simulation time 10004357056 ps
CPU time 89.2 seconds
Started Sep 18 09:17:26 PM UTC 24
Finished Sep 18 09:18:57 PM UTC 24
Peak memory 263916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956213674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3956213674
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/43.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.2194250560
Short name T912
Test name
Test status
Simulation time 1133229691 ps
CPU time 14.58 seconds
Started Sep 18 09:17:26 PM UTC 24
Finished Sep 18 09:17:42 PM UTC 24
Peak memory 247524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194250560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2194250560
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.489442465
Short name T941
Test name
Test status
Simulation time 19248284910 ps
CPU time 45.12 seconds
Started Sep 18 09:17:26 PM UTC 24
Finished Sep 18 09:18:12 PM UTC 24
Peak memory 261984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489442465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.489442465
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.806354600
Short name T896
Test name
Test status
Simulation time 103672223 ps
CPU time 3.77 seconds
Started Sep 18 09:17:23 PM UTC 24
Finished Sep 18 09:17:28 PM UTC 24
Peak memory 245344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806354600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.806354600
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/43.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.3557127601
Short name T1032
Test name
Test status
Simulation time 43109874777 ps
CPU time 319.3 seconds
Started Sep 18 09:17:24 PM UTC 24
Finished Sep 18 09:22:48 PM UTC 24
Peak memory 268072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557127601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.3557127601
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.1933094727
Short name T902
Test name
Test status
Simulation time 6524766148 ps
CPU time 15.13 seconds
Started Sep 18 09:17:17 PM UTC 24
Finished Sep 18 09:17:33 PM UTC 24
Peak memory 245544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933094727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1933094727
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/43.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.1471532591
Short name T889
Test name
Test status
Simulation time 30953210 ps
CPU time 2.81 seconds
Started Sep 18 09:17:18 PM UTC 24
Finished Sep 18 09:17:22 PM UTC 24
Peak memory 233660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471532591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1471532591
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/43.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.422875431
Short name T939
Test name
Test status
Simulation time 42152519556 ps
CPU time 49.94 seconds
Started Sep 18 09:17:17 PM UTC 24
Finished Sep 18 09:18:08 PM UTC 24
Peak memory 235168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422875431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.422875431
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/43.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.3895439305
Short name T898
Test name
Test status
Simulation time 1299526414 ps
CPU time 13.03 seconds
Started Sep 18 09:17:17 PM UTC 24
Finished Sep 18 09:17:31 PM UTC 24
Peak memory 251492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895439305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3895439305
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/43.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.3918832170
Short name T914
Test name
Test status
Simulation time 3397193391 ps
CPU time 15.47 seconds
Started Sep 18 09:17:26 PM UTC 24
Finished Sep 18 09:17:42 PM UTC 24
Peak memory 233844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918832170 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.3918832170
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/43.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.3142920399
Short name T897
Test name
Test status
Simulation time 64631911 ps
CPU time 1.37 seconds
Started Sep 18 09:17:28 PM UTC 24
Finished Sep 18 09:17:30 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142920399 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.3142920399
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/43.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.3760715360
Short name T891
Test name
Test status
Simulation time 781346365 ps
CPU time 7.7 seconds
Started Sep 18 09:17:15 PM UTC 24
Finished Sep 18 09:17:24 PM UTC 24
Peak memory 227752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760715360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3760715360
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/43.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.150643048
Short name T894
Test name
Test status
Simulation time 3075169772 ps
CPU time 8.75 seconds
Started Sep 18 09:17:15 PM UTC 24
Finished Sep 18 09:17:25 PM UTC 24
Peak memory 227524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150643048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.150643048
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/43.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.2949920130
Short name T888
Test name
Test status
Simulation time 16179909 ps
CPU time 1.34 seconds
Started Sep 18 09:17:17 PM UTC 24
Finished Sep 18 09:17:19 PM UTC 24
Peak memory 217096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949920130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2949920130
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/43.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.3450577544
Short name T887
Test name
Test status
Simulation time 27070022 ps
CPU time 1.12 seconds
Started Sep 18 09:17:17 PM UTC 24
Finished Sep 18 09:17:19 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450577544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3450577544
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/43.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.3547640901
Short name T895
Test name
Test status
Simulation time 1758615808 ps
CPU time 6.76 seconds
Started Sep 18 09:17:19 PM UTC 24
Finished Sep 18 09:17:27 PM UTC 24
Peak memory 229884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547640901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3547640901
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/43.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.2344245282
Short name T918
Test name
Test status
Simulation time 13677048 ps
CPU time 0.97 seconds
Started Sep 18 09:17:44 PM UTC 24
Finished Sep 18 09:17:46 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344245282 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.2344245282
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/44.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.1122372314
Short name T919
Test name
Test status
Simulation time 261860226 ps
CPU time 7.55 seconds
Started Sep 18 09:17:37 PM UTC 24
Finished Sep 18 09:17:46 PM UTC 24
Peak memory 245476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122372314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1122372314
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/44.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.1311362288
Short name T900
Test name
Test status
Simulation time 62273611 ps
CPU time 1.06 seconds
Started Sep 18 09:17:29 PM UTC 24
Finished Sep 18 09:17:32 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311362288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1311362288
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/44.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.801872045
Short name T1007
Test name
Test status
Simulation time 31983609675 ps
CPU time 96.47 seconds
Started Sep 18 09:17:40 PM UTC 24
Finished Sep 18 09:19:19 PM UTC 24
Peak memory 251632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801872045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.801872045
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/44.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.3277066291
Short name T987
Test name
Test status
Simulation time 2820640734 ps
CPU time 70.06 seconds
Started Sep 18 09:17:42 PM UTC 24
Finished Sep 18 09:18:54 PM UTC 24
Peak memory 261924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277066291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3277066291
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.3351585000
Short name T965
Test name
Test status
Simulation time 3224726303 ps
CPU time 49.91 seconds
Started Sep 18 09:17:42 PM UTC 24
Finished Sep 18 09:18:34 PM UTC 24
Peak memory 261992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351585000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.3351585000
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.2305646057
Short name T940
Test name
Test status
Simulation time 22016846455 ps
CPU time 29.56 seconds
Started Sep 18 09:17:39 PM UTC 24
Finished Sep 18 09:18:10 PM UTC 24
Peak memory 262060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305646057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2305646057
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/44.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.708297076
Short name T911
Test name
Test status
Simulation time 158576387 ps
CPU time 1.39 seconds
Started Sep 18 09:17:39 PM UTC 24
Finished Sep 18 09:17:41 PM UTC 24
Peak memory 225976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708297076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.708297076
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.2543948198
Short name T904
Test name
Test status
Simulation time 1570758886 ps
CPU time 18.04 seconds
Started Sep 18 09:17:35 PM UTC 24
Finished Sep 18 09:17:55 PM UTC 24
Peak memory 245420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543948198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2543948198
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/44.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.189342496
Short name T921
Test name
Test status
Simulation time 775400279 ps
CPU time 9.7 seconds
Started Sep 18 09:17:37 PM UTC 24
Finished Sep 18 09:17:48 PM UTC 24
Peak memory 245360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189342496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.189342496
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/44.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.3883535188
Short name T915
Test name
Test status
Simulation time 1038817184 ps
CPU time 7.3 seconds
Started Sep 18 09:17:35 PM UTC 24
Finished Sep 18 09:17:44 PM UTC 24
Peak memory 235172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883535188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.3883535188
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/44.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.2210524527
Short name T909
Test name
Test status
Simulation time 253656523 ps
CPU time 3.17 seconds
Started Sep 18 09:17:33 PM UTC 24
Finished Sep 18 09:17:38 PM UTC 24
Peak memory 234368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210524527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2210524527
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/44.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.2289637661
Short name T917
Test name
Test status
Simulation time 253912340 ps
CPU time 5.28 seconds
Started Sep 18 09:17:39 PM UTC 24
Finished Sep 18 09:17:45 PM UTC 24
Peak memory 233868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289637661 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.2289637661
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/44.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.3517391108
Short name T1018
Test name
Test status
Simulation time 53169010008 ps
CPU time 125.16 seconds
Started Sep 18 09:17:44 PM UTC 24
Finished Sep 18 09:19:51 PM UTC 24
Peak memory 263968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517391108 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.3517391108
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/44.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.3890046007
Short name T927
Test name
Test status
Simulation time 3775133743 ps
CPU time 26.01 seconds
Started Sep 18 09:17:32 PM UTC 24
Finished Sep 18 09:17:59 PM UTC 24
Peak memory 227872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890046007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3890046007
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/44.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.133591120
Short name T910
Test name
Test status
Simulation time 4436718620 ps
CPU time 6.62 seconds
Started Sep 18 09:17:32 PM UTC 24
Finished Sep 18 09:17:39 PM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133591120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.133591120
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/44.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.3156821032
Short name T905
Test name
Test status
Simulation time 98355656 ps
CPU time 1.01 seconds
Started Sep 18 09:17:33 PM UTC 24
Finished Sep 18 09:17:36 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156821032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3156821032
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/44.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.586250402
Short name T906
Test name
Test status
Simulation time 170610398 ps
CPU time 1.28 seconds
Started Sep 18 09:17:33 PM UTC 24
Finished Sep 18 09:17:36 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586250402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.586250402
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/44.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.982839882
Short name T913
Test name
Test status
Simulation time 296699302 ps
CPU time 3.44 seconds
Started Sep 18 09:17:37 PM UTC 24
Finished Sep 18 09:17:42 PM UTC 24
Peak memory 235100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982839882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.982839882
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/44.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.351387589
Short name T931
Test name
Test status
Simulation time 15056830 ps
CPU time 1.13 seconds
Started Sep 18 09:18:01 PM UTC 24
Finished Sep 18 09:18:03 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351387589 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.351387589
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/45.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.1168057715
Short name T930
Test name
Test status
Simulation time 73911825 ps
CPU time 4.44 seconds
Started Sep 18 09:17:55 PM UTC 24
Finished Sep 18 09:18:01 PM UTC 24
Peak memory 235048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168057715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1168057715
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/45.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.3367275415
Short name T920
Test name
Test status
Simulation time 59332325 ps
CPU time 1.11 seconds
Started Sep 18 09:17:45 PM UTC 24
Finished Sep 18 09:17:47 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367275415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3367275415
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/45.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.3639684699
Short name T968
Test name
Test status
Simulation time 8298644122 ps
CPU time 38.46 seconds
Started Sep 18 09:17:56 PM UTC 24
Finished Sep 18 09:18:36 PM UTC 24
Peak memory 261924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639684699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3639684699
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/45.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.2848954402
Short name T361
Test name
Test status
Simulation time 63964775406 ps
CPU time 574.07 seconds
Started Sep 18 09:17:57 PM UTC 24
Finished Sep 18 09:27:38 PM UTC 24
Peak memory 278376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848954402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2848954402
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.4154561193
Short name T983
Test name
Test status
Simulation time 2784716303 ps
CPU time 49.37 seconds
Started Sep 18 09:17:59 PM UTC 24
Finished Sep 18 09:18:50 PM UTC 24
Peak memory 261924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154561193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.4154561193
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.3070687799
Short name T929
Test name
Test status
Simulation time 206405183 ps
CPU time 3.39 seconds
Started Sep 18 09:17:56 PM UTC 24
Finished Sep 18 09:18:00 PM UTC 24
Peak memory 245544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070687799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3070687799
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/45.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.882784487
Short name T953
Test name
Test status
Simulation time 5080942469 ps
CPU time 25.76 seconds
Started Sep 18 09:17:56 PM UTC 24
Finished Sep 18 09:18:23 PM UTC 24
Peak memory 261992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882784487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.882784487
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.2362473516
Short name T875
Test name
Test status
Simulation time 528368117 ps
CPU time 3.37 seconds
Started Sep 18 09:17:49 PM UTC 24
Finished Sep 18 09:17:54 PM UTC 24
Peak memory 235236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362473516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2362473516
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/45.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.2293119488
Short name T925
Test name
Test status
Simulation time 73567039 ps
CPU time 4.01 seconds
Started Sep 18 09:17:50 PM UTC 24
Finished Sep 18 09:17:55 PM UTC 24
Peak memory 245356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293119488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2293119488
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/45.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.4188583443
Short name T935
Test name
Test status
Simulation time 8335922454 ps
CPU time 14.3 seconds
Started Sep 18 09:17:48 PM UTC 24
Finished Sep 18 09:18:04 PM UTC 24
Peak memory 245404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188583443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.4188583443
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/45.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.2981451208
Short name T923
Test name
Test status
Simulation time 197620408 ps
CPU time 3.01 seconds
Started Sep 18 09:17:48 PM UTC 24
Finished Sep 18 09:17:52 PM UTC 24
Peak memory 234780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981451208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2981451208
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/45.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.2599519993
Short name T942
Test name
Test status
Simulation time 2146964715 ps
CPU time 15.86 seconds
Started Sep 18 09:17:56 PM UTC 24
Finished Sep 18 09:18:13 PM UTC 24
Peak memory 233716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599519993 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.2599519993
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/45.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.3580902221
Short name T973
Test name
Test status
Simulation time 30835349928 ps
CPU time 49.9 seconds
Started Sep 18 09:17:47 PM UTC 24
Finished Sep 18 09:18:38 PM UTC 24
Peak memory 228080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580902221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3580902221
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/45.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.3614230834
Short name T926
Test name
Test status
Simulation time 3127846211 ps
CPU time 11.99 seconds
Started Sep 18 09:17:45 PM UTC 24
Finished Sep 18 09:17:58 PM UTC 24
Peak memory 227772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614230834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3614230834
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/45.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.1907393477
Short name T924
Test name
Test status
Simulation time 1058010374 ps
CPU time 6.08 seconds
Started Sep 18 09:17:47 PM UTC 24
Finished Sep 18 09:17:54 PM UTC 24
Peak memory 227824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907393477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1907393477
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/45.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.1570435243
Short name T922
Test name
Test status
Simulation time 108514956 ps
CPU time 1 seconds
Started Sep 18 09:17:47 PM UTC 24
Finished Sep 18 09:17:49 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570435243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1570435243
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/45.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.2847831440
Short name T928
Test name
Test status
Simulation time 378486286 ps
CPU time 5.03 seconds
Started Sep 18 09:17:54 PM UTC 24
Finished Sep 18 09:18:00 PM UTC 24
Peak memory 245348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847831440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2847831440
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/45.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.1363432654
Short name T948
Test name
Test status
Simulation time 56933895 ps
CPU time 1.16 seconds
Started Sep 18 09:18:18 PM UTC 24
Finished Sep 18 09:18:20 PM UTC 24
Peak memory 213048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363432654 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.1363432654
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/46.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.976328135
Short name T944
Test name
Test status
Simulation time 852777607 ps
CPU time 5.96 seconds
Started Sep 18 09:18:09 PM UTC 24
Finished Sep 18 09:18:16 PM UTC 24
Peak memory 245356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976328135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.976328135
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/46.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.788905514
Short name T932
Test name
Test status
Simulation time 13435337 ps
CPU time 1.14 seconds
Started Sep 18 09:18:01 PM UTC 24
Finished Sep 18 09:18:03 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788905514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.788905514
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/46.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.1927900920
Short name T958
Test name
Test status
Simulation time 1706433758 ps
CPU time 10.06 seconds
Started Sep 18 09:18:14 PM UTC 24
Finished Sep 18 09:18:25 PM UTC 24
Peak memory 235180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927900920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1927900920
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/46.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.2648581508
Short name T1027
Test name
Test status
Simulation time 170550110967 ps
CPU time 238.89 seconds
Started Sep 18 09:18:14 PM UTC 24
Finished Sep 18 09:22:16 PM UTC 24
Peak memory 262056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648581508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2648581508
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/46.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.2994056514
Short name T1019
Test name
Test status
Simulation time 51564215906 ps
CPU time 100.4 seconds
Started Sep 18 09:18:17 PM UTC 24
Finished Sep 18 09:19:59 PM UTC 24
Peak memory 245544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994056514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.2994056514
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.1788882414
Short name T963
Test name
Test status
Simulation time 3607633371 ps
CPU time 21.86 seconds
Started Sep 18 09:18:10 PM UTC 24
Finished Sep 18 09:18:33 PM UTC 24
Peak memory 245408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788882414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1788882414
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/46.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.3635505034
Short name T1016
Test name
Test status
Simulation time 11823942578 ps
CPU time 84.94 seconds
Started Sep 18 09:18:11 PM UTC 24
Finished Sep 18 09:19:38 PM UTC 24
Peak memory 261864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635505034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.3635505034
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.2420667641
Short name T943
Test name
Test status
Simulation time 350180419 ps
CPU time 3.43 seconds
Started Sep 18 09:18:08 PM UTC 24
Finished Sep 18 09:18:13 PM UTC 24
Peak memory 235168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420667641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2420667641
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/46.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.2089916934
Short name T949
Test name
Test status
Simulation time 3465458717 ps
CPU time 10.89 seconds
Started Sep 18 09:18:09 PM UTC 24
Finished Sep 18 09:18:20 PM UTC 24
Peak memory 235304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089916934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2089916934
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/46.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.1091198904
Short name T945
Test name
Test status
Simulation time 1734336435 ps
CPU time 10.89 seconds
Started Sep 18 09:18:05 PM UTC 24
Finished Sep 18 09:18:17 PM UTC 24
Peak memory 245280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091198904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.1091198904
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/46.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.4058222698
Short name T950
Test name
Test status
Simulation time 11393907816 ps
CPU time 15.06 seconds
Started Sep 18 09:18:05 PM UTC 24
Finished Sep 18 09:18:21 PM UTC 24
Peak memory 235232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058222698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.4058222698
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/46.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.494729964
Short name T966
Test name
Test status
Simulation time 3771739613 ps
CPU time 19.13 seconds
Started Sep 18 09:18:13 PM UTC 24
Finished Sep 18 09:18:34 PM UTC 24
Peak memory 229600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494729964 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.494729964
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/46.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.3488489876
Short name T1012
Test name
Test status
Simulation time 22330617351 ps
CPU time 66.85 seconds
Started Sep 18 09:18:18 PM UTC 24
Finished Sep 18 09:19:27 PM UTC 24
Peak memory 247700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488489876 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.3488489876
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/46.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.1017183311
Short name T952
Test name
Test status
Simulation time 7879259123 ps
CPU time 16 seconds
Started Sep 18 09:18:05 PM UTC 24
Finished Sep 18 09:18:22 PM UTC 24
Peak memory 227864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017183311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1017183311
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/46.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.2545259047
Short name T954
Test name
Test status
Simulation time 25121167656 ps
CPU time 20.9 seconds
Started Sep 18 09:18:02 PM UTC 24
Finished Sep 18 09:18:24 PM UTC 24
Peak memory 227708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545259047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2545259047
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/46.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.1779241849
Short name T938
Test name
Test status
Simulation time 72927609 ps
CPU time 2.06 seconds
Started Sep 18 09:18:05 PM UTC 24
Finished Sep 18 09:18:08 PM UTC 24
Peak memory 227620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779241849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1779241849
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/46.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.3732073480
Short name T936
Test name
Test status
Simulation time 73441827 ps
CPU time 1.15 seconds
Started Sep 18 09:18:05 PM UTC 24
Finished Sep 18 09:18:07 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732073480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3732073480
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/46.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.3108044415
Short name T975
Test name
Test status
Simulation time 4466979731 ps
CPU time 29.85 seconds
Started Sep 18 09:18:09 PM UTC 24
Finished Sep 18 09:18:40 PM UTC 24
Peak memory 251628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108044415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3108044415
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/46.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.864879288
Short name T970
Test name
Test status
Simulation time 50584791 ps
CPU time 1.11 seconds
Started Sep 18 09:18:35 PM UTC 24
Finished Sep 18 09:18:37 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864879288 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.864879288
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/47.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.267285122
Short name T961
Test name
Test status
Simulation time 90772200 ps
CPU time 4.61 seconds
Started Sep 18 09:18:25 PM UTC 24
Finished Sep 18 09:18:31 PM UTC 24
Peak memory 245352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267285122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.267285122
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/47.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.241038846
Short name T951
Test name
Test status
Simulation time 30528341 ps
CPU time 1.17 seconds
Started Sep 18 09:18:19 PM UTC 24
Finished Sep 18 09:18:22 PM UTC 24
Peak memory 215100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241038846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.241038846
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/47.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.3297673791
Short name T1020
Test name
Test status
Simulation time 21517529505 ps
CPU time 103.03 seconds
Started Sep 18 09:18:32 PM UTC 24
Finished Sep 18 09:20:18 PM UTC 24
Peak memory 261932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297673791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3297673791
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/47.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3281520855
Short name T1034
Test name
Test status
Simulation time 87000815068 ps
CPU time 397.74 seconds
Started Sep 18 09:18:34 PM UTC 24
Finished Sep 18 09:25:17 PM UTC 24
Peak memory 272236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281520855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3281520855
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.862370500
Short name T1037
Test name
Test status
Simulation time 400494132073 ps
CPU time 696.46 seconds
Started Sep 18 09:18:34 PM UTC 24
Finished Sep 18 09:30:19 PM UTC 24
Peak memory 278376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862370500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.862370500
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.616073529
Short name T989
Test name
Test status
Simulation time 3849946681 ps
CPU time 27.04 seconds
Started Sep 18 09:18:27 PM UTC 24
Finished Sep 18 09:18:55 PM UTC 24
Peak memory 251628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616073529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.616073529
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/47.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.4115388185
Short name T995
Test name
Test status
Simulation time 10989270037 ps
CPU time 31.42 seconds
Started Sep 18 09:18:29 PM UTC 24
Finished Sep 18 09:19:02 PM UTC 24
Peak memory 247528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115388185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.4115388185
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.2321460735
Short name T964
Test name
Test status
Simulation time 170584911 ps
CPU time 6.77 seconds
Started Sep 18 09:18:25 PM UTC 24
Finished Sep 18 09:18:33 PM UTC 24
Peak memory 245352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321460735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2321460735
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/47.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.2173363515
Short name T979
Test name
Test status
Simulation time 8433853808 ps
CPU time 17.42 seconds
Started Sep 18 09:18:25 PM UTC 24
Finished Sep 18 09:18:44 PM UTC 24
Peak memory 235248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173363515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2173363515
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/47.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.953600280
Short name T959
Test name
Test status
Simulation time 80527242 ps
CPU time 3.23 seconds
Started Sep 18 09:18:24 PM UTC 24
Finished Sep 18 09:18:28 PM UTC 24
Peak memory 235020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953600280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.953600280
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/47.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.11134810
Short name T974
Test name
Test status
Simulation time 5573688753 ps
CPU time 13.33 seconds
Started Sep 18 09:18:24 PM UTC 24
Finished Sep 18 09:18:38 PM UTC 24
Peak memory 245488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11134810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.11134810
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/47.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.1988469985
Short name T969
Test name
Test status
Simulation time 652079515 ps
CPU time 6.65 seconds
Started Sep 18 09:18:29 PM UTC 24
Finished Sep 18 09:18:37 PM UTC 24
Peak memory 233780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988469985 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.1988469985
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/47.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.3933582767
Short name T1035
Test name
Test status
Simulation time 141590340774 ps
CPU time 441.5 seconds
Started Sep 18 09:18:35 PM UTC 24
Finished Sep 18 09:26:02 PM UTC 24
Peak memory 284516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933582767 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.3933582767
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/47.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.960712706
Short name T955
Test name
Test status
Simulation time 24773743 ps
CPU time 1.13 seconds
Started Sep 18 09:18:22 PM UTC 24
Finished Sep 18 09:18:24 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960712706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.960712706
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/47.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.1962273394
Short name T962
Test name
Test status
Simulation time 8625042271 ps
CPU time 9.86 seconds
Started Sep 18 09:18:22 PM UTC 24
Finished Sep 18 09:18:33 PM UTC 24
Peak memory 227756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962273394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1962273394
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/47.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.3125868779
Short name T960
Test name
Test status
Simulation time 106118400 ps
CPU time 5.08 seconds
Started Sep 18 09:18:22 PM UTC 24
Finished Sep 18 09:18:28 PM UTC 24
Peak memory 227752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125868779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3125868779
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/47.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.2704830093
Short name T957
Test name
Test status
Simulation time 211266054 ps
CPU time 1.29 seconds
Started Sep 18 09:18:22 PM UTC 24
Finished Sep 18 09:18:24 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704830093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2704830093
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/47.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.528416779
Short name T967
Test name
Test status
Simulation time 3351923630 ps
CPU time 8.6 seconds
Started Sep 18 09:18:25 PM UTC 24
Finished Sep 18 09:18:35 PM UTC 24
Peak memory 245484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528416779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.528416779
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/47.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.1803059602
Short name T985
Test name
Test status
Simulation time 46716128 ps
CPU time 1.1 seconds
Started Sep 18 09:18:51 PM UTC 24
Finished Sep 18 09:18:53 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803059602 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.1803059602
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/48.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.2776134927
Short name T982
Test name
Test status
Simulation time 352568054 ps
CPU time 3.65 seconds
Started Sep 18 09:18:41 PM UTC 24
Finished Sep 18 09:18:46 PM UTC 24
Peak memory 235056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776134927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2776134927
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/48.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.356356120
Short name T972
Test name
Test status
Simulation time 20425820 ps
CPU time 1.17 seconds
Started Sep 18 09:18:35 PM UTC 24
Finished Sep 18 09:18:37 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356356120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.356356120
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/48.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.340535069
Short name T380
Test name
Test status
Simulation time 127946127748 ps
CPU time 491.7 seconds
Started Sep 18 09:18:45 PM UTC 24
Finished Sep 18 09:27:03 PM UTC 24
Peak memory 268012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340535069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.340535069
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/48.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.768925270
Short name T1005
Test name
Test status
Simulation time 25100047901 ps
CPU time 30.04 seconds
Started Sep 18 09:18:45 PM UTC 24
Finished Sep 18 09:19:17 PM UTC 24
Peak memory 249704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768925270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.768925270
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.1748104515
Short name T1006
Test name
Test status
Simulation time 2734168864 ps
CPU time 31.42 seconds
Started Sep 18 09:18:45 PM UTC 24
Finished Sep 18 09:19:18 PM UTC 24
Peak memory 261928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748104515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.1748104515
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.4278878271
Short name T991
Test name
Test status
Simulation time 493233150 ps
CPU time 12.65 seconds
Started Sep 18 09:18:43 PM UTC 24
Finished Sep 18 09:18:56 PM UTC 24
Peak memory 245276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278878271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.4278878271
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/48.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.2781837644
Short name T378
Test name
Test status
Simulation time 7874524533 ps
CPU time 105.94 seconds
Started Sep 18 09:18:43 PM UTC 24
Finished Sep 18 09:20:31 PM UTC 24
Peak memory 268008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781837644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.2781837644
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.1831749963
Short name T980
Test name
Test status
Simulation time 56964777 ps
CPU time 3.13 seconds
Started Sep 18 09:18:40 PM UTC 24
Finished Sep 18 09:18:44 PM UTC 24
Peak memory 234872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831749963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1831749963
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/48.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.4271185234
Short name T981
Test name
Test status
Simulation time 61740773 ps
CPU time 3.16 seconds
Started Sep 18 09:18:40 PM UTC 24
Finished Sep 18 09:18:44 PM UTC 24
Peak memory 245356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271185234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4271185234
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/48.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.3042102344
Short name T978
Test name
Test status
Simulation time 272005139 ps
CPU time 3.78 seconds
Started Sep 18 09:18:38 PM UTC 24
Finished Sep 18 09:18:43 PM UTC 24
Peak memory 245352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042102344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.3042102344
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/48.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2452339505
Short name T996
Test name
Test status
Simulation time 3056901020 ps
CPU time 22.82 seconds
Started Sep 18 09:18:38 PM UTC 24
Finished Sep 18 09:19:02 PM UTC 24
Peak memory 245556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452339505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2452339505
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/48.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2142538431
Short name T990
Test name
Test status
Simulation time 849009270 ps
CPU time 10.12 seconds
Started Sep 18 09:18:44 PM UTC 24
Finished Sep 18 09:18:55 PM UTC 24
Peak memory 233780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142538431 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.2142538431
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/48.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.1686171120
Short name T1024
Test name
Test status
Simulation time 10406131135 ps
CPU time 123.9 seconds
Started Sep 18 09:18:47 PM UTC 24
Finished Sep 18 09:20:53 PM UTC 24
Peak memory 264100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686171120 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.1686171120
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/48.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.3089839238
Short name T1017
Test name
Test status
Simulation time 10544264699 ps
CPU time 69.77 seconds
Started Sep 18 09:18:37 PM UTC 24
Finished Sep 18 09:19:48 PM UTC 24
Peak memory 227804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089839238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3089839238
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/48.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.316630692
Short name T993
Test name
Test status
Simulation time 15770417056 ps
CPU time 19.09 seconds
Started Sep 18 09:18:37 PM UTC 24
Finished Sep 18 09:18:57 PM UTC 24
Peak memory 227876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316630692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.316630692
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/48.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.1905870711
Short name T977
Test name
Test status
Simulation time 69724808 ps
CPU time 2.4 seconds
Started Sep 18 09:18:38 PM UTC 24
Finished Sep 18 09:18:42 PM UTC 24
Peak memory 227812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905870711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1905870711
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/48.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.3322800851
Short name T976
Test name
Test status
Simulation time 18849831 ps
CPU time 1.05 seconds
Started Sep 18 09:18:38 PM UTC 24
Finished Sep 18 09:18:40 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322800851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3322800851
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/48.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.3803461804
Short name T1014
Test name
Test status
Simulation time 21639728888 ps
CPU time 46.75 seconds
Started Sep 18 09:18:41 PM UTC 24
Finished Sep 18 09:19:30 PM UTC 24
Peak memory 251688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803461804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3803461804
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/48.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.2656027945
Short name T1002
Test name
Test status
Simulation time 11456159 ps
CPU time 1.05 seconds
Started Sep 18 09:19:08 PM UTC 24
Finished Sep 18 09:19:10 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656027945 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.2656027945
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/49.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.2351237300
Short name T997
Test name
Test status
Simulation time 109428341 ps
CPU time 3.34 seconds
Started Sep 18 09:18:58 PM UTC 24
Finished Sep 18 09:19:03 PM UTC 24
Peak memory 235040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351237300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2351237300
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/49.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.3915770268
Short name T986
Test name
Test status
Simulation time 331978255 ps
CPU time 1.24 seconds
Started Sep 18 09:18:51 PM UTC 24
Finished Sep 18 09:18:53 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915770268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3915770268
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/49.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.1272389056
Short name T1030
Test name
Test status
Simulation time 128616508865 ps
CPU time 211.86 seconds
Started Sep 18 09:19:03 PM UTC 24
Finished Sep 18 09:22:38 PM UTC 24
Peak memory 261932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272389056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1272389056
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/49.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.895907526
Short name T1033
Test name
Test status
Simulation time 173826463459 ps
CPU time 328.63 seconds
Started Sep 18 09:19:03 PM UTC 24
Finished Sep 18 09:24:36 PM UTC 24
Peak memory 261936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895907526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.895907526
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.3885131364
Short name T1031
Test name
Test status
Simulation time 81136158740 ps
CPU time 217.54 seconds
Started Sep 18 09:19:04 PM UTC 24
Finished Sep 18 09:22:45 PM UTC 24
Peak memory 278376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885131364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.3885131364
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.3983226267
Short name T1001
Test name
Test status
Simulation time 763635819 ps
CPU time 10.22 seconds
Started Sep 18 09:18:58 PM UTC 24
Finished Sep 18 09:19:10 PM UTC 24
Peak memory 261736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983226267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3983226267
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/49.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.703673656
Short name T1011
Test name
Test status
Simulation time 1572854615 ps
CPU time 26.5 seconds
Started Sep 18 09:18:58 PM UTC 24
Finished Sep 18 09:19:26 PM UTC 24
Peak memory 251504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703673656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.703673656
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.2874223910
Short name T1000
Test name
Test status
Simulation time 2970154472 ps
CPU time 10.84 seconds
Started Sep 18 09:18:56 PM UTC 24
Finished Sep 18 09:19:08 PM UTC 24
Peak memory 235244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874223910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2874223910
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/49.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.521433317
Short name T1008
Test name
Test status
Simulation time 3573778489 ps
CPU time 20.21 seconds
Started Sep 18 09:18:58 PM UTC 24
Finished Sep 18 09:19:20 PM UTC 24
Peak memory 235252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521433317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.521433317
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/49.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.2285454057
Short name T998
Test name
Test status
Simulation time 512505549 ps
CPU time 8.49 seconds
Started Sep 18 09:18:56 PM UTC 24
Finished Sep 18 09:19:06 PM UTC 24
Peak memory 245340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285454057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.2285454057
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/49.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.3935154030
Short name T1004
Test name
Test status
Simulation time 8440215900 ps
CPU time 14.84 seconds
Started Sep 18 09:18:56 PM UTC 24
Finished Sep 18 09:19:12 PM UTC 24
Peak memory 245616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935154030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3935154030
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/49.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.3838896014
Short name T999
Test name
Test status
Simulation time 143185920 ps
CPU time 5.5 seconds
Started Sep 18 09:19:00 PM UTC 24
Finished Sep 18 09:19:06 PM UTC 24
Peak memory 233764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838896014 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.3838896014
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/49.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.1741569961
Short name T366
Test name
Test status
Simulation time 23456652856 ps
CPU time 239.68 seconds
Started Sep 18 09:19:06 PM UTC 24
Finished Sep 18 09:23:10 PM UTC 24
Peak memory 266144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741569961 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.1741569961
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/49.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.160652529
Short name T1010
Test name
Test status
Simulation time 7635221979 ps
CPU time 29.39 seconds
Started Sep 18 09:18:55 PM UTC 24
Finished Sep 18 09:19:25 PM UTC 24
Peak memory 227820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160652529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.160652529
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/49.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.116427242
Short name T1009
Test name
Test status
Simulation time 5851053465 ps
CPU time 27.86 seconds
Started Sep 18 09:18:55 PM UTC 24
Finished Sep 18 09:19:24 PM UTC 24
Peak memory 227896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116427242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.116427242
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/49.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.2470746515
Short name T994
Test name
Test status
Simulation time 32424905 ps
CPU time 1.13 seconds
Started Sep 18 09:18:56 PM UTC 24
Finished Sep 18 09:18:58 PM UTC 24
Peak memory 214924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470746515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2470746515
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/49.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.1541566328
Short name T992
Test name
Test status
Simulation time 84121019 ps
CPU time 1.16 seconds
Started Sep 18 09:18:55 PM UTC 24
Finished Sep 18 09:18:57 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541566328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1541566328
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/49.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.1996024498
Short name T1003
Test name
Test status
Simulation time 1444557055 ps
CPU time 12.57 seconds
Started Sep 18 09:18:58 PM UTC 24
Finished Sep 18 09:19:12 PM UTC 24
Peak memory 245412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996024498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1996024498
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/49.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.3674543819
Short name T414
Test name
Test status
Simulation time 14300308 ps
CPU time 1.18 seconds
Started Sep 18 09:04:07 PM UTC 24
Finished Sep 18 09:04:09 PM UTC 24
Peak memory 213048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674543819 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3674543819
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.3539671320
Short name T77
Test name
Test status
Simulation time 39057754 ps
CPU time 3.34 seconds
Started Sep 18 09:03:59 PM UTC 24
Finished Sep 18 09:04:04 PM UTC 24
Peak memory 245284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539671320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3539671320
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.1772284842
Short name T198
Test name
Test status
Simulation time 45488979 ps
CPU time 1.11 seconds
Started Sep 18 09:03:45 PM UTC 24
Finished Sep 18 09:03:47 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772284842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1772284842
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.2953728871
Short name T110
Test name
Test status
Simulation time 2392466527 ps
CPU time 59.01 seconds
Started Sep 18 09:04:03 PM UTC 24
Finished Sep 18 09:05:04 PM UTC 24
Peak memory 261868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953728871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2953728871
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.4089989024
Short name T229
Test name
Test status
Simulation time 199301576141 ps
CPU time 383.49 seconds
Started Sep 18 09:04:05 PM UTC 24
Finished Sep 18 09:10:33 PM UTC 24
Peak memory 267980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089989024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.4089989024
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.3985431083
Short name T281
Test name
Test status
Simulation time 91142520575 ps
CPU time 192.85 seconds
Started Sep 18 09:04:05 PM UTC 24
Finished Sep 18 09:07:21 PM UTC 24
Peak memory 261940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985431083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.3985431083
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.1103283497
Short name T182
Test name
Test status
Simulation time 4442173632 ps
CPU time 20.01 seconds
Started Sep 18 09:03:59 PM UTC 24
Finished Sep 18 09:04:20 PM UTC 24
Peak memory 235244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103283497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1103283497
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.3361635306
Short name T78
Test name
Test status
Simulation time 433661548 ps
CPU time 9.78 seconds
Started Sep 18 09:03:53 PM UTC 24
Finished Sep 18 09:04:04 PM UTC 24
Peak memory 245420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361635306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3361635306
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.90438254
Short name T79
Test name
Test status
Simulation time 3426242660 ps
CPU time 10.74 seconds
Started Sep 18 09:03:54 PM UTC 24
Finished Sep 18 09:04:06 PM UTC 24
Peak memory 245420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90438254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.90438254
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.1850010664
Short name T199
Test name
Test status
Simulation time 397423624 ps
CPU time 1.56 seconds
Started Sep 18 09:03:46 PM UTC 24
Finished Sep 18 09:03:49 PM UTC 24
Peak memory 228264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850010664 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mem_parity.1850010664
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.4251303952
Short name T61
Test name
Test status
Simulation time 4236114547 ps
CPU time 6.16 seconds
Started Sep 18 09:03:51 PM UTC 24
Finished Sep 18 09:03:58 PM UTC 24
Peak memory 235240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251303952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.4251303952
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.440007716
Short name T75
Test name
Test status
Simulation time 330483582 ps
CPU time 7.48 seconds
Started Sep 18 09:03:50 PM UTC 24
Finished Sep 18 09:03:58 PM UTC 24
Peak memory 235100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440007716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.440007716
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.641623672
Short name T120
Test name
Test status
Simulation time 3225397941 ps
CPU time 8.95 seconds
Started Sep 18 09:04:03 PM UTC 24
Finished Sep 18 09:04:13 PM UTC 24
Peak memory 233844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641623672 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.641623672
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.1387594928
Short name T36
Test name
Test status
Simulation time 82769430 ps
CPU time 1.76 seconds
Started Sep 18 09:04:07 PM UTC 24
Finished Sep 18 09:04:10 PM UTC 24
Peak memory 215088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387594928 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.1387594928
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2323733550
Short name T416
Test name
Test status
Simulation time 14959538919 ps
CPU time 24.95 seconds
Started Sep 18 09:03:46 PM UTC 24
Finished Sep 18 09:04:13 PM UTC 24
Peak memory 227756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323733550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2323733550
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.3634937376
Short name T116
Test name
Test status
Simulation time 164416314 ps
CPU time 3.73 seconds
Started Sep 18 09:03:49 PM UTC 24
Finished Sep 18 09:03:53 PM UTC 24
Peak memory 227732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634937376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3634937376
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.2223235235
Short name T200
Test name
Test status
Simulation time 10651058 ps
CPU time 1.09 seconds
Started Sep 18 09:03:47 PM UTC 24
Finished Sep 18 09:03:49 PM UTC 24
Peak memory 215100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223235235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2223235235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.2536646680
Short name T243
Test name
Test status
Simulation time 2558130564 ps
CPU time 16.66 seconds
Started Sep 18 09:03:54 PM UTC 24
Finished Sep 18 09:04:12 PM UTC 24
Peak memory 235244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536646680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2536646680
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/5.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.1864989954
Short name T419
Test name
Test status
Simulation time 22307836 ps
CPU time 1.1 seconds
Started Sep 18 09:04:27 PM UTC 24
Finished Sep 18 09:04:29 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864989954 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1864989954
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.644535773
Short name T312
Test name
Test status
Simulation time 106562467 ps
CPU time 3.26 seconds
Started Sep 18 09:04:16 PM UTC 24
Finished Sep 18 09:04:20 PM UTC 24
Peak memory 235180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644535773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.644535773
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.3144916929
Short name T415
Test name
Test status
Simulation time 52288627 ps
CPU time 1.18 seconds
Started Sep 18 09:04:09 PM UTC 24
Finished Sep 18 09:04:11 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144916929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3144916929
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.1944068178
Short name T73
Test name
Test status
Simulation time 14339860019 ps
CPU time 81.31 seconds
Started Sep 18 09:04:21 PM UTC 24
Finished Sep 18 09:05:44 PM UTC 24
Peak memory 268080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944068178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1944068178
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.3335524179
Short name T103
Test name
Test status
Simulation time 43567196764 ps
CPU time 112.93 seconds
Started Sep 18 09:04:21 PM UTC 24
Finished Sep 18 09:06:16 PM UTC 24
Peak memory 266092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335524179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3335524179
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.2274808404
Short name T102
Test name
Test status
Simulation time 2653608525 ps
CPU time 43.15 seconds
Started Sep 18 09:04:25 PM UTC 24
Finished Sep 18 09:05:10 PM UTC 24
Peak memory 261936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274808404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.2274808404
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.2681833642
Short name T274
Test name
Test status
Simulation time 29825029372 ps
CPU time 52.46 seconds
Started Sep 18 09:04:18 PM UTC 24
Finished Sep 18 09:05:12 PM UTC 24
Peak memory 263908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681833642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2681833642
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.445038616
Short name T123
Test name
Test status
Simulation time 13904175792 ps
CPU time 26.59 seconds
Started Sep 18 09:04:18 PM UTC 24
Finished Sep 18 09:04:46 PM UTC 24
Peak memory 263980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445038616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.445038616
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.2305480201
Short name T206
Test name
Test status
Simulation time 190431910 ps
CPU time 4.56 seconds
Started Sep 18 09:04:13 PM UTC 24
Finished Sep 18 09:04:19 PM UTC 24
Peak memory 245356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305480201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2305480201
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.928502231
Short name T264
Test name
Test status
Simulation time 50365403225 ps
CPU time 111.2 seconds
Started Sep 18 09:04:13 PM UTC 24
Finished Sep 18 09:06:07 PM UTC 24
Peak memory 245548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928502231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.928502231
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.3107458993
Short name T417
Test name
Test status
Simulation time 24829317 ps
CPU time 1.58 seconds
Started Sep 18 09:04:10 PM UTC 24
Finished Sep 18 09:04:13 PM UTC 24
Peak memory 228264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107458993 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mem_parity.3107458993
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.3809420770
Short name T69
Test name
Test status
Simulation time 4662528119 ps
CPU time 17.31 seconds
Started Sep 18 09:04:13 PM UTC 24
Finished Sep 18 09:04:32 PM UTC 24
Peak memory 245432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809420770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.3809420770
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.214750186
Short name T305
Test name
Test status
Simulation time 45486835123 ps
CPU time 22.16 seconds
Started Sep 18 09:04:13 PM UTC 24
Finished Sep 18 09:04:37 PM UTC 24
Peak memory 235196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214750186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.214750186
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2919538337
Short name T183
Test name
Test status
Simulation time 642662333 ps
CPU time 10.84 seconds
Started Sep 18 09:04:20 PM UTC 24
Finished Sep 18 09:04:32 PM UTC 24
Peak memory 233652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919538337 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.2919538337
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.1477958236
Short name T38
Test name
Test status
Simulation time 75340817 ps
CPU time 1.84 seconds
Started Sep 18 09:04:25 PM UTC 24
Finished Sep 18 09:04:28 PM UTC 24
Peak memory 215088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477958236 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.1477958236
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.3009663223
Short name T397
Test name
Test status
Simulation time 21417029220 ps
CPU time 57.43 seconds
Started Sep 18 09:04:10 PM UTC 24
Finished Sep 18 09:05:09 PM UTC 24
Peak memory 232044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009663223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3009663223
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.1768078114
Short name T424
Test name
Test status
Simulation time 4098576287 ps
CPU time 24.3 seconds
Started Sep 18 09:04:10 PM UTC 24
Finished Sep 18 09:04:36 PM UTC 24
Peak memory 227816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768078114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1768078114
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.2106855329
Short name T407
Test name
Test status
Simulation time 58462903 ps
CPU time 2.31 seconds
Started Sep 18 09:04:13 PM UTC 24
Finished Sep 18 09:04:17 PM UTC 24
Peak memory 227824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106855329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2106855329
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.2088056664
Short name T418
Test name
Test status
Simulation time 84946010 ps
CPU time 1.46 seconds
Started Sep 18 09:04:12 PM UTC 24
Finished Sep 18 09:04:15 PM UTC 24
Peak memory 215100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088056664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2088056664
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.3096064384
Short name T119
Test name
Test status
Simulation time 2307617251 ps
CPU time 8.67 seconds
Started Sep 18 09:04:15 PM UTC 24
Finished Sep 18 09:04:24 PM UTC 24
Peak memory 235220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096064384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3096064384
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/6.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.1255832400
Short name T427
Test name
Test status
Simulation time 29932480 ps
CPU time 1.07 seconds
Started Sep 18 09:04:55 PM UTC 24
Finished Sep 18 09:04:57 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255832400 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1255832400
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.1643078666
Short name T425
Test name
Test status
Simulation time 70849086 ps
CPU time 3.04 seconds
Started Sep 18 09:04:44 PM UTC 24
Finished Sep 18 09:04:48 PM UTC 24
Peak memory 245092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643078666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1643078666
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.3098923059
Short name T420
Test name
Test status
Simulation time 23096324 ps
CPU time 1.11 seconds
Started Sep 18 09:04:28 PM UTC 24
Finished Sep 18 09:04:30 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098923059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3098923059
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1144941381
Short name T111
Test name
Test status
Simulation time 10414916350 ps
CPU time 144.84 seconds
Started Sep 18 09:04:50 PM UTC 24
Finished Sep 18 09:07:17 PM UTC 24
Peak memory 278380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144941381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1144941381
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.664878077
Short name T237
Test name
Test status
Simulation time 125676603087 ps
CPU time 100.68 seconds
Started Sep 18 09:04:52 PM UTC 24
Finished Sep 18 09:06:35 PM UTC 24
Peak memory 261900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664878077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.664878077
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.3408312107
Short name T71
Test name
Test status
Simulation time 3680470335 ps
CPU time 40.91 seconds
Started Sep 18 09:04:46 PM UTC 24
Finished Sep 18 09:05:29 PM UTC 24
Peak memory 261944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408312107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.3408312107
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.928472164
Short name T325
Test name
Test status
Simulation time 448792395 ps
CPU time 4.68 seconds
Started Sep 18 09:04:37 PM UTC 24
Finished Sep 18 09:04:43 PM UTC 24
Peak memory 245356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928472164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.928472164
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.1491278335
Short name T446
Test name
Test status
Simulation time 20668306391 ps
CPU time 78.08 seconds
Started Sep 18 09:04:38 PM UTC 24
Finished Sep 18 09:05:58 PM UTC 24
Peak memory 245428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491278335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1491278335
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.3975320721
Short name T421
Test name
Test status
Simulation time 62373680 ps
CPU time 1.59 seconds
Started Sep 18 09:04:30 PM UTC 24
Finished Sep 18 09:04:33 PM UTC 24
Peak memory 228264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975320721 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mem_parity.3975320721
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.2253041388
Short name T70
Test name
Test status
Simulation time 1782366868 ps
CPU time 10.41 seconds
Started Sep 18 09:04:36 PM UTC 24
Finished Sep 18 09:04:47 PM UTC 24
Peak memory 249464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253041388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.2253041388
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.2722012103
Short name T306
Test name
Test status
Simulation time 4762124268 ps
CPU time 8.58 seconds
Started Sep 18 09:04:36 PM UTC 24
Finished Sep 18 09:04:46 PM UTC 24
Peak memory 235160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722012103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2722012103
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.1560280360
Short name T185
Test name
Test status
Simulation time 1817512039 ps
CPU time 20.04 seconds
Started Sep 18 09:04:48 PM UTC 24
Finished Sep 18 09:05:10 PM UTC 24
Peak memory 231584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560280360 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.1560280360
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.2137589078
Short name T41
Test name
Test status
Simulation time 3214936440 ps
CPU time 24.37 seconds
Started Sep 18 09:04:52 PM UTC 24
Finished Sep 18 09:05:18 PM UTC 24
Peak memory 249760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137589078 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.2137589078
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.227679600
Short name T422
Test name
Test status
Simulation time 12740225 ps
CPU time 1.11 seconds
Started Sep 18 09:04:33 PM UTC 24
Finished Sep 18 09:04:35 PM UTC 24
Peak memory 215100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227679600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.227679600
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1856959559
Short name T426
Test name
Test status
Simulation time 13069398856 ps
CPU time 18.09 seconds
Started Sep 18 09:04:31 PM UTC 24
Finished Sep 18 09:04:51 PM UTC 24
Peak memory 227876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856959559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1856959559
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.3447958427
Short name T400
Test name
Test status
Simulation time 177084358 ps
CPU time 2.58 seconds
Started Sep 18 09:04:34 PM UTC 24
Finished Sep 18 09:04:37 PM UTC 24
Peak memory 227680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447958427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3447958427
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.2829872419
Short name T423
Test name
Test status
Simulation time 29414956 ps
CPU time 1.26 seconds
Started Sep 18 09:04:33 PM UTC 24
Finished Sep 18 09:04:35 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829872419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2829872419
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.2148763681
Short name T292
Test name
Test status
Simulation time 813903810 ps
CPU time 8.75 seconds
Started Sep 18 09:04:39 PM UTC 24
Finished Sep 18 09:04:49 PM UTC 24
Peak memory 235032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148763681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2148763681
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/7.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.442097772
Short name T93
Test name
Test status
Simulation time 14910016 ps
CPU time 1.15 seconds
Started Sep 18 09:05:20 PM UTC 24
Finished Sep 18 09:05:22 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442097772 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.442097772
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.563457597
Short name T432
Test name
Test status
Simulation time 123916367 ps
CPU time 2.89 seconds
Started Sep 18 09:05:11 PM UTC 24
Finished Sep 18 09:05:15 PM UTC 24
Peak memory 235184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563457597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.563457597
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.3539833184
Short name T428
Test name
Test status
Simulation time 20748287 ps
CPU time 1.19 seconds
Started Sep 18 09:04:56 PM UTC 24
Finished Sep 18 09:04:58 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539833184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3539833184
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.875102813
Short name T295
Test name
Test status
Simulation time 68627198226 ps
CPU time 137.64 seconds
Started Sep 18 09:05:14 PM UTC 24
Finished Sep 18 09:07:35 PM UTC 24
Peak memory 261860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875102813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.875102813
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.511490497
Short name T162
Test name
Test status
Simulation time 92632477366 ps
CPU time 247.06 seconds
Started Sep 18 09:05:15 PM UTC 24
Finished Sep 18 09:09:26 PM UTC 24
Peak memory 262056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511490497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.511490497
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.512763937
Short name T202
Test name
Test status
Simulation time 22247384315 ps
CPU time 68.75 seconds
Started Sep 18 09:05:16 PM UTC 24
Finished Sep 18 09:06:27 PM UTC 24
Peak memory 251744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512763937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.512763937
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.2493186213
Short name T288
Test name
Test status
Simulation time 6904705469 ps
CPU time 22.48 seconds
Started Sep 18 09:05:12 PM UTC 24
Finished Sep 18 09:05:36 PM UTC 24
Peak memory 247600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493186213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2493186213
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.1476036045
Short name T433
Test name
Test status
Simulation time 18617362 ps
CPU time 1.21 seconds
Started Sep 18 09:05:13 PM UTC 24
Finished Sep 18 09:05:16 PM UTC 24
Peak memory 225980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476036045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.1476036045
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.3158335604
Short name T94
Test name
Test status
Simulation time 2471179872 ps
CPU time 12.28 seconds
Started Sep 18 09:05:09 PM UTC 24
Finished Sep 18 09:05:22 PM UTC 24
Peak memory 245480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158335604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3158335604
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.1625373257
Short name T91
Test name
Test status
Simulation time 502668160 ps
CPU time 8.17 seconds
Started Sep 18 09:05:10 PM UTC 24
Finished Sep 18 09:05:20 PM UTC 24
Peak memory 235000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625373257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1625373257
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.1571684245
Short name T429
Test name
Test status
Simulation time 17682334 ps
CPU time 1.56 seconds
Started Sep 18 09:04:58 PM UTC 24
Finished Sep 18 09:05:01 PM UTC 24
Peak memory 228264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571684245 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mem_parity.1571684245
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.1196660610
Short name T334
Test name
Test status
Simulation time 141651788 ps
CPU time 3.98 seconds
Started Sep 18 09:05:07 PM UTC 24
Finished Sep 18 09:05:12 PM UTC 24
Peak memory 245364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196660610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.1196660610
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.3958699247
Short name T204
Test name
Test status
Simulation time 101552731148 ps
CPU time 47.08 seconds
Started Sep 18 09:05:05 PM UTC 24
Finished Sep 18 09:05:54 PM UTC 24
Peak memory 251692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958699247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3958699247
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.1891107726
Short name T92
Test name
Test status
Simulation time 340758333 ps
CPU time 5.35 seconds
Started Sep 18 09:05:14 PM UTC 24
Finished Sep 18 09:05:21 PM UTC 24
Peak memory 231524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891107726 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.1891107726
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.3591576223
Short name T294
Test name
Test status
Simulation time 37958327427 ps
CPU time 122.17 seconds
Started Sep 18 09:05:19 PM UTC 24
Finished Sep 18 09:07:23 PM UTC 24
Peak memory 261988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591576223 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.3591576223
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.1217816231
Short name T399
Test name
Test status
Simulation time 5836612199 ps
CPU time 40.27 seconds
Started Sep 18 09:05:02 PM UTC 24
Finished Sep 18 09:05:44 PM UTC 24
Peak memory 232036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217816231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1217816231
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.376503916
Short name T431
Test name
Test status
Simulation time 4556944027 ps
CPU time 13.61 seconds
Started Sep 18 09:04:59 PM UTC 24
Finished Sep 18 09:05:14 PM UTC 24
Peak memory 227960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376503916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.376503916
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.4243707288
Short name T398
Test name
Test status
Simulation time 24712311 ps
CPU time 1.29 seconds
Started Sep 18 09:05:05 PM UTC 24
Finished Sep 18 09:05:08 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243707288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.4243707288
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.2227161456
Short name T430
Test name
Test status
Simulation time 72110420 ps
CPU time 1.24 seconds
Started Sep 18 09:05:02 PM UTC 24
Finished Sep 18 09:05:05 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227161456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2227161456
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.2028152309
Short name T97
Test name
Test status
Simulation time 396432241 ps
CPU time 13.61 seconds
Started Sep 18 09:05:11 PM UTC 24
Finished Sep 18 09:05:26 PM UTC 24
Peak memory 245408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028152309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2028152309
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/8.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.4009542470
Short name T437
Test name
Test status
Simulation time 30411114 ps
CPU time 1.1 seconds
Started Sep 18 09:05:39 PM UTC 24
Finished Sep 18 09:05:41 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009542470 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.4009542470
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.3062152670
Short name T436
Test name
Test status
Simulation time 55217836 ps
CPU time 3.84 seconds
Started Sep 18 09:05:33 PM UTC 24
Finished Sep 18 09:05:37 PM UTC 24
Peak memory 245420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062152670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3062152670
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.1394135993
Short name T95
Test name
Test status
Simulation time 29340932 ps
CPU time 1.22 seconds
Started Sep 18 09:05:21 PM UTC 24
Finished Sep 18 09:05:23 PM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394135993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1394135993
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.186767090
Short name T386
Test name
Test status
Simulation time 2518768623 ps
CPU time 10.7 seconds
Started Sep 18 09:05:33 PM UTC 24
Finished Sep 18 09:05:44 PM UTC 24
Peak memory 245612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186767090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.186767090
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.3750581052
Short name T220
Test name
Test status
Simulation time 17952983061 ps
CPU time 101.69 seconds
Started Sep 18 09:05:34 PM UTC 24
Finished Sep 18 09:07:18 PM UTC 24
Peak memory 268012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750581052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.3750581052
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.2282961502
Short name T277
Test name
Test status
Simulation time 409458301 ps
CPU time 5.65 seconds
Started Sep 18 09:05:28 PM UTC 24
Finished Sep 18 09:05:35 PM UTC 24
Peak memory 245352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282961502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2282961502
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.1042775386
Short name T302
Test name
Test status
Simulation time 2272751600 ps
CPU time 41.78 seconds
Started Sep 18 09:05:30 PM UTC 24
Finished Sep 18 09:06:14 PM UTC 24
Peak memory 261808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042775386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1042775386
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.2852609342
Short name T96
Test name
Test status
Simulation time 154775929 ps
CPU time 1.53 seconds
Started Sep 18 09:05:22 PM UTC 24
Finished Sep 18 09:05:24 PM UTC 24
Peak memory 228264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852609342 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mem_parity.2852609342
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.118569929
Short name T435
Test name
Test status
Simulation time 49959660 ps
CPU time 3.19 seconds
Started Sep 18 09:05:27 PM UTC 24
Finished Sep 18 09:05:32 PM UTC 24
Peak memory 245088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118569929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.118569929
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.949690714
Short name T267
Test name
Test status
Simulation time 205644040 ps
CPU time 5.05 seconds
Started Sep 18 09:05:26 PM UTC 24
Finished Sep 18 09:05:32 PM UTC 24
Peak memory 235176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949690714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.949690714
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.505070112
Short name T438
Test name
Test status
Simulation time 351426745 ps
CPU time 7.28 seconds
Started Sep 18 09:05:34 PM UTC 24
Finished Sep 18 09:05:42 PM UTC 24
Peak memory 231588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505070112 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.505070112
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.187014894
Short name T286
Test name
Test status
Simulation time 19137209665 ps
CPU time 201.35 seconds
Started Sep 18 09:05:38 PM UTC 24
Finished Sep 18 09:09:03 PM UTC 24
Peak memory 249632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187014894 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.187014894
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.2511257056
Short name T394
Test name
Test status
Simulation time 2821950958 ps
CPU time 12.5 seconds
Started Sep 18 09:05:23 PM UTC 24
Finished Sep 18 09:05:37 PM UTC 24
Peak memory 227812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511257056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2511257056
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.2201054481
Short name T434
Test name
Test status
Simulation time 2915241394 ps
CPU time 6.5 seconds
Started Sep 18 09:05:23 PM UTC 24
Finished Sep 18 09:05:31 PM UTC 24
Peak memory 227776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201054481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2201054481
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.2682567745
Short name T99
Test name
Test status
Simulation time 27217699 ps
CPU time 1.14 seconds
Started Sep 18 09:05:25 PM UTC 24
Finished Sep 18 09:05:27 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682567745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2682567745
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.2188126886
Short name T98
Test name
Test status
Simulation time 43200478 ps
CPU time 1.07 seconds
Started Sep 18 09:05:24 PM UTC 24
Finished Sep 18 09:05:26 PM UTC 24
Peak memory 215100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188126886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2188126886
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.1617337093
Short name T318
Test name
Test status
Simulation time 1750088564 ps
CPU time 12.15 seconds
Started Sep 18 09:05:32 PM UTC 24
Finished Sep 18 09:05:45 PM UTC 24
Peak memory 245348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617337093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1617337093
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/9.spi_device_upload/latest
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