| T282 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.3851516678 |
|
|
Sep 18 09:10:29 PM UTC 24 |
Sep 18 09:11:13 PM UTC 24 |
3247359227 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.689260385 |
|
|
Sep 18 09:11:11 PM UTC 24 |
Sep 18 09:11:13 PM UTC 24 |
20123668 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.3775290155 |
|
|
Sep 18 09:10:54 PM UTC 24 |
Sep 18 09:11:13 PM UTC 24 |
13875732018 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode.3475162451 |
|
|
Sep 18 09:11:03 PM UTC 24 |
Sep 18 09:11:13 PM UTC 24 |
134722442 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.3641944787 |
|
|
Sep 18 09:11:13 PM UTC 24 |
Sep 18 09:11:15 PM UTC 24 |
20650101 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.758579976 |
|
|
Sep 18 09:08:11 PM UTC 24 |
Sep 18 09:11:15 PM UTC 24 |
72040926863 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_cfg_cmd.1585008030 |
|
|
Sep 18 09:11:16 PM UTC 24 |
Sep 18 09:11:20 PM UTC 24 |
237454165 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode.1861481297 |
|
|
Sep 18 09:11:16 PM UTC 24 |
Sep 18 09:11:20 PM UTC 24 |
158484640 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_mailbox.300810567 |
|
|
Sep 18 09:10:39 PM UTC 24 |
Sep 18 09:11:21 PM UTC 24 |
54324119463 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.105294362 |
|
|
Sep 18 09:11:14 PM UTC 24 |
Sep 18 09:11:22 PM UTC 24 |
275930367 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_upload.4185692222 |
|
|
Sep 18 09:11:02 PM UTC 24 |
Sep 18 09:11:22 PM UTC 24 |
31498111099 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_rw.3753130551 |
|
|
Sep 18 09:11:13 PM UTC 24 |
Sep 18 09:11:22 PM UTC 24 |
817000690 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_intercept.1676442465 |
|
|
Sep 18 09:11:14 PM UTC 24 |
Sep 18 09:11:24 PM UTC 24 |
635828832 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_intercept.178491449 |
|
|
Sep 18 09:10:58 PM UTC 24 |
Sep 18 09:11:25 PM UTC 24 |
21815206402 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_alert_test.3220581598 |
|
|
Sep 18 09:11:25 PM UTC 24 |
Sep 18 09:11:27 PM UTC 24 |
32880592 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_csb_read.2671903834 |
|
|
Sep 18 09:11:26 PM UTC 24 |
Sep 18 09:11:29 PM UTC 24 |
56636192 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.1226494472 |
|
|
Sep 18 09:08:04 PM UTC 24 |
Sep 18 09:11:30 PM UTC 24 |
67718255893 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.3054446243 |
|
|
Sep 18 09:10:46 PM UTC 24 |
Sep 18 09:11:30 PM UTC 24 |
23982367894 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_all.455686769 |
|
|
Sep 18 09:11:30 PM UTC 24 |
Sep 18 09:11:32 PM UTC 24 |
38253502 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.2968507706 |
|
|
Sep 18 09:11:31 PM UTC 24 |
Sep 18 09:11:33 PM UTC 24 |
46736242 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.1503024919 |
|
|
Sep 18 09:11:23 PM UTC 24 |
Sep 18 09:11:35 PM UTC 24 |
2963185054 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.58055190 |
|
|
Sep 18 09:11:21 PM UTC 24 |
Sep 18 09:11:36 PM UTC 24 |
1478340438 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_all.2751008874 |
|
|
Sep 18 09:10:45 PM UTC 24 |
Sep 18 09:11:36 PM UTC 24 |
3194387974 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_rw.65251422 |
|
|
Sep 18 09:11:31 PM UTC 24 |
Sep 18 09:11:36 PM UTC 24 |
145464768 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_all.3234414263 |
|
|
Sep 18 09:11:11 PM UTC 24 |
Sep 18 09:11:36 PM UTC 24 |
2546317142 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.1593409893 |
|
|
Sep 18 09:10:16 PM UTC 24 |
Sep 18 09:11:37 PM UTC 24 |
9039970588 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.2718429597 |
|
|
Sep 18 09:09:57 PM UTC 24 |
Sep 18 09:11:38 PM UTC 24 |
2805041194 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_upload.406275447 |
|
|
Sep 18 09:11:14 PM UTC 24 |
Sep 18 09:11:38 PM UTC 24 |
14878732614 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.1417558405 |
|
|
Sep 18 09:11:34 PM UTC 24 |
Sep 18 09:11:38 PM UTC 24 |
70177475 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.3009329821 |
|
|
Sep 18 09:11:13 PM UTC 24 |
Sep 18 09:11:43 PM UTC 24 |
15068467706 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_upload.463618078 |
|
|
Sep 18 09:11:37 PM UTC 24 |
Sep 18 09:11:44 PM UTC 24 |
1549229102 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_intercept.2847840045 |
|
|
Sep 18 09:11:37 PM UTC 24 |
Sep 18 09:11:45 PM UTC 24 |
497134215 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_cfg_cmd.3677182667 |
|
|
Sep 18 09:11:37 PM UTC 24 |
Sep 18 09:11:45 PM UTC 24 |
353777193 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_mailbox.3183620626 |
|
|
Sep 18 09:11:14 PM UTC 24 |
Sep 18 09:11:47 PM UTC 24 |
2278405503 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.1779764046 |
|
|
Sep 18 09:11:27 PM UTC 24 |
Sep 18 09:11:47 PM UTC 24 |
7514807483 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_csb_read.2214063649 |
|
|
Sep 18 09:11:47 PM UTC 24 |
Sep 18 09:11:49 PM UTC 24 |
48653101 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_alert_test.3805618250 |
|
|
Sep 18 09:11:47 PM UTC 24 |
Sep 18 09:11:49 PM UTC 24 |
62552258 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.132269941 |
|
|
Sep 18 09:11:39 PM UTC 24 |
Sep 18 09:11:51 PM UTC 24 |
1025431782 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_rw.3505961559 |
|
|
Sep 18 09:11:50 PM UTC 24 |
Sep 18 09:11:52 PM UTC 24 |
26344792 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.1013916273 |
|
|
Sep 18 09:11:50 PM UTC 24 |
Sep 18 09:11:52 PM UTC 24 |
116070618 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.691084766 |
|
|
Sep 18 09:11:48 PM UTC 24 |
Sep 18 09:11:52 PM UTC 24 |
1915638897 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.231444968 |
|
|
Sep 18 09:11:32 PM UTC 24 |
Sep 18 09:11:53 PM UTC 24 |
13066114510 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.1768270371 |
|
|
Sep 18 09:10:48 PM UTC 24 |
Sep 18 09:11:57 PM UTC 24 |
3004161106 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_upload.664632766 |
|
|
Sep 18 09:11:54 PM UTC 24 |
Sep 18 09:11:58 PM UTC 24 |
74091614 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_mailbox.1938735483 |
|
|
Sep 18 09:11:37 PM UTC 24 |
Sep 18 09:11:58 PM UTC 24 |
950307572 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_all.3317077989 |
|
|
Sep 18 09:11:39 PM UTC 24 |
Sep 18 09:12:00 PM UTC 24 |
1271593917 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.861494855 |
|
|
Sep 18 09:11:52 PM UTC 24 |
Sep 18 09:12:01 PM UTC 24 |
5153712315 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_cfg_cmd.2712543164 |
|
|
Sep 18 09:11:58 PM UTC 24 |
Sep 18 09:12:02 PM UTC 24 |
30490687 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_intercept.2683110283 |
|
|
Sep 18 09:11:54 PM UTC 24 |
Sep 18 09:12:04 PM UTC 24 |
2133297941 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode.1674831789 |
|
|
Sep 18 09:11:39 PM UTC 24 |
Sep 18 09:12:04 PM UTC 24 |
3795527458 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.2805050024 |
|
|
Sep 18 09:11:21 PM UTC 24 |
Sep 18 09:12:06 PM UTC 24 |
6838907014 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.2094903747 |
|
|
Sep 18 09:16:45 PM UTC 24 |
Sep 18 09:16:51 PM UTC 24 |
1619282090 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_all.2940856687 |
|
|
Sep 18 09:09:18 PM UTC 24 |
Sep 18 09:12:07 PM UTC 24 |
37795899264 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.3378230149 |
|
|
Sep 18 09:12:00 PM UTC 24 |
Sep 18 09:12:08 PM UTC 24 |
574773031 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_alert_test.779598453 |
|
|
Sep 18 09:12:07 PM UTC 24 |
Sep 18 09:12:10 PM UTC 24 |
11438498 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_csb_read.1487420451 |
|
|
Sep 18 09:12:09 PM UTC 24 |
Sep 18 09:12:11 PM UTC 24 |
121801951 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.2424850393 |
|
|
Sep 18 09:12:12 PM UTC 24 |
Sep 18 09:12:14 PM UTC 24 |
29208990 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_all.1417890232 |
|
|
Sep 18 09:12:11 PM UTC 24 |
Sep 18 09:12:17 PM UTC 24 |
2034701781 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode.4217344309 |
|
|
Sep 18 09:11:59 PM UTC 24 |
Sep 18 09:12:17 PM UTC 24 |
378100809 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_rw.179024701 |
|
|
Sep 18 09:12:15 PM UTC 24 |
Sep 18 09:12:19 PM UTC 24 |
109811017 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_all.1679437854 |
|
|
Sep 18 09:11:48 PM UTC 24 |
Sep 18 09:12:20 PM UTC 24 |
1116684104 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.4291984931 |
|
|
Sep 18 09:11:53 PM UTC 24 |
Sep 18 09:12:23 PM UTC 24 |
7547153421 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.3935804885 |
|
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Sep 18 09:07:22 PM UTC 24 |
Sep 18 09:12:23 PM UTC 24 |
26415702014 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_upload.3817550632 |
|
|
Sep 18 09:12:21 PM UTC 24 |
Sep 18 09:12:26 PM UTC 24 |
38618262 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.3838527880 |
|
|
Sep 18 09:12:18 PM UTC 24 |
Sep 18 09:12:26 PM UTC 24 |
950379163 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.4227672292 |
|
|
Sep 18 09:12:10 PM UTC 24 |
Sep 18 09:12:28 PM UTC 24 |
19592474351 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_rw.779889907 |
|
|
Sep 18 09:13:28 PM UTC 24 |
Sep 18 09:13:31 PM UTC 24 |
75148946 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_cfg_cmd.820001949 |
|
|
Sep 18 09:12:24 PM UTC 24 |
Sep 18 09:12:29 PM UTC 24 |
52967311 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.1162018611 |
|
|
Sep 18 09:12:17 PM UTC 24 |
Sep 18 09:12:30 PM UTC 24 |
6008333410 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/20.spi_device_stress_all.261838156 |
|
|
Sep 18 09:09:24 PM UTC 24 |
Sep 18 09:12:30 PM UTC 24 |
26563985241 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.144112391 |
|
|
Sep 18 09:12:27 PM UTC 24 |
Sep 18 09:12:34 PM UTC 24 |
794217204 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode.3161849922 |
|
|
Sep 18 09:12:25 PM UTC 24 |
Sep 18 09:12:34 PM UTC 24 |
157275815 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.694008586 |
|
|
Sep 18 09:12:32 PM UTC 24 |
Sep 18 09:12:35 PM UTC 24 |
123762232 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.1628936836 |
|
|
Sep 18 09:11:39 PM UTC 24 |
Sep 18 09:12:37 PM UTC 24 |
4323583426 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_alert_test.2338984153 |
|
|
Sep 18 09:12:35 PM UTC 24 |
Sep 18 09:12:38 PM UTC 24 |
123452716 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_csb_read.2466936338 |
|
|
Sep 18 09:12:35 PM UTC 24 |
Sep 18 09:12:38 PM UTC 24 |
41447696 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.2779757720 |
|
|
Sep 18 09:12:05 PM UTC 24 |
Sep 18 09:12:39 PM UTC 24 |
12626978828 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_mailbox.3415888174 |
|
|
Sep 18 09:11:54 PM UTC 24 |
Sep 18 09:12:42 PM UTC 24 |
11041752487 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.132747800 |
|
|
Sep 18 09:12:39 PM UTC 24 |
Sep 18 09:12:42 PM UTC 24 |
88392938 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.265720636 |
|
|
Sep 18 09:12:37 PM UTC 24 |
Sep 18 09:12:42 PM UTC 24 |
5091829722 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_rw.2663646593 |
|
|
Sep 18 09:12:39 PM UTC 24 |
Sep 18 09:12:44 PM UTC 24 |
154517995 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.3550572322 |
|
|
Sep 18 09:07:52 PM UTC 24 |
Sep 18 09:12:45 PM UTC 24 |
100590951306 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_intercept.2672850673 |
|
|
Sep 18 09:12:18 PM UTC 24 |
Sep 18 09:12:47 PM UTC 24 |
8911498951 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.1354200321 |
|
|
Sep 18 09:12:40 PM UTC 24 |
Sep 18 09:12:47 PM UTC 24 |
1395318661 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_intercept.3995435221 |
|
|
Sep 18 09:12:43 PM UTC 24 |
Sep 18 09:12:47 PM UTC 24 |
34193331 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_all.2560417953 |
|
|
Sep 18 09:12:38 PM UTC 24 |
Sep 18 09:12:47 PM UTC 24 |
1557675082 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.810372199 |
|
|
Sep 18 09:11:59 PM UTC 24 |
Sep 18 09:12:49 PM UTC 24 |
5906933497 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_upload.1587622038 |
|
|
Sep 18 09:12:45 PM UTC 24 |
Sep 18 09:12:50 PM UTC 24 |
182015986 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_cfg_cmd.4290682120 |
|
|
Sep 18 09:12:46 PM UTC 24 |
Sep 18 09:12:51 PM UTC 24 |
45144466 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_mailbox.4095717608 |
|
|
Sep 18 09:12:43 PM UTC 24 |
Sep 18 09:12:56 PM UTC 24 |
411737980 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.777717874 |
|
|
Sep 18 09:06:52 PM UTC 24 |
Sep 18 09:12:57 PM UTC 24 |
122726222861 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.592149535 |
|
|
Sep 18 09:11:43 PM UTC 24 |
Sep 18 09:12:58 PM UTC 24 |
21894670402 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_alert_test.2061142120 |
|
|
Sep 18 09:12:57 PM UTC 24 |
Sep 18 09:12:59 PM UTC 24 |
12885035 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_csb_read.300769098 |
|
|
Sep 18 09:12:58 PM UTC 24 |
Sep 18 09:13:00 PM UTC 24 |
28081223 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.3851800013 |
|
|
Sep 18 09:12:48 PM UTC 24 |
Sep 18 09:13:01 PM UTC 24 |
2152433165 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.2450142174 |
|
|
Sep 18 09:11:07 PM UTC 24 |
Sep 18 09:13:03 PM UTC 24 |
31060497047 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.288172051 |
|
|
Sep 18 09:13:01 PM UTC 24 |
Sep 18 09:13:03 PM UTC 24 |
130406887 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.2603956698 |
|
|
Sep 18 09:12:48 PM UTC 24 |
Sep 18 09:13:06 PM UTC 24 |
1199108378 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_rw.3990329226 |
|
|
Sep 18 09:13:02 PM UTC 24 |
Sep 18 09:13:06 PM UTC 24 |
76081611 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_intercept.2161480062 |
|
|
Sep 18 09:13:06 PM UTC 24 |
Sep 18 09:13:10 PM UTC 24 |
143846668 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.1731771979 |
|
|
Sep 18 09:12:43 PM UTC 24 |
Sep 18 09:13:10 PM UTC 24 |
7055984840 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_upload.1947552309 |
|
|
Sep 18 09:13:08 PM UTC 24 |
Sep 18 09:13:14 PM UTC 24 |
399249451 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.879220711 |
|
|
Sep 18 09:12:59 PM UTC 24 |
Sep 18 09:13:14 PM UTC 24 |
4973068812 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_cfg_cmd.566360379 |
|
|
Sep 18 09:13:11 PM UTC 24 |
Sep 18 09:13:15 PM UTC 24 |
481216649 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.1910555613 |
|
|
Sep 18 09:13:04 PM UTC 24 |
Sep 18 09:13:16 PM UTC 24 |
14150981845 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/15.spi_device_stress_all.3000416820 |
|
|
Sep 18 09:07:35 PM UTC 24 |
Sep 18 09:13:17 PM UTC 24 |
115556369483 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.2915076619 |
|
|
Sep 18 09:07:52 PM UTC 24 |
Sep 18 09:13:17 PM UTC 24 |
71994545716 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode.3417550907 |
|
|
Sep 18 09:13:11 PM UTC 24 |
Sep 18 09:13:19 PM UTC 24 |
1873412276 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.2144642993 |
|
|
Sep 18 09:13:16 PM UTC 24 |
Sep 18 09:13:20 PM UTC 24 |
102194259 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_alert_test.1010642236 |
|
|
Sep 18 09:13:20 PM UTC 24 |
Sep 18 09:13:23 PM UTC 24 |
11902107 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_csb_read.2283404896 |
|
|
Sep 18 09:13:22 PM UTC 24 |
Sep 18 09:13:24 PM UTC 24 |
20023779 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.1985881886 |
|
|
Sep 18 09:13:17 PM UTC 24 |
Sep 18 09:13:25 PM UTC 24 |
413691265 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_all.4077518807 |
|
|
Sep 18 09:13:25 PM UTC 24 |
Sep 18 09:13:27 PM UTC 24 |
25317969 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.934799803 |
|
|
Sep 18 09:13:26 PM UTC 24 |
Sep 18 09:13:28 PM UTC 24 |
44956841 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_all.207428103 |
|
|
Sep 18 09:12:59 PM UTC 24 |
Sep 18 09:13:29 PM UTC 24 |
7732550520 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.3379525677 |
|
|
Sep 18 09:13:04 PM UTC 24 |
Sep 18 09:13:30 PM UTC 24 |
3519436578 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.262885817 |
|
|
Sep 18 09:11:39 PM UTC 24 |
Sep 18 09:13:34 PM UTC 24 |
61157036396 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.397337720 |
|
|
Sep 18 09:13:24 PM UTC 24 |
Sep 18 09:13:34 PM UTC 24 |
6349937474 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.1849316015 |
|
|
Sep 18 09:13:30 PM UTC 24 |
Sep 18 09:13:34 PM UTC 24 |
276820262 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.443529855 |
|
|
Sep 18 09:10:13 PM UTC 24 |
Sep 18 09:13:36 PM UTC 24 |
380827673168 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.3113197338 |
|
|
Sep 18 09:12:52 PM UTC 24 |
Sep 18 09:13:37 PM UTC 24 |
7082108802 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.2815378115 |
|
|
Sep 18 09:10:30 PM UTC 24 |
Sep 18 09:13:37 PM UTC 24 |
76561482805 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_stress_all.3490745112 |
|
|
Sep 18 09:12:05 PM UTC 24 |
Sep 18 09:13:40 PM UTC 24 |
7340157607 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.473794726 |
|
|
Sep 18 09:13:30 PM UTC 24 |
Sep 18 09:13:41 PM UTC 24 |
3279434398 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_mailbox.1192688321 |
|
|
Sep 18 09:12:20 PM UTC 24 |
Sep 18 09:13:43 PM UTC 24 |
31791430267 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_intercept.3672306417 |
|
|
Sep 18 09:13:31 PM UTC 24 |
Sep 18 09:13:48 PM UTC 24 |
13238067635 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.2600294512 |
|
|
Sep 18 09:12:03 PM UTC 24 |
Sep 18 09:13:48 PM UTC 24 |
31821153311 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.2711931096 |
|
|
Sep 18 09:13:38 PM UTC 24 |
Sep 18 09:13:50 PM UTC 24 |
8409009692 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.859412991 |
|
|
Sep 18 09:13:18 PM UTC 24 |
Sep 18 09:13:50 PM UTC 24 |
5962388164 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_cfg_cmd.2381085918 |
|
|
Sep 18 09:13:36 PM UTC 24 |
Sep 18 09:13:51 PM UTC 24 |
3264648043 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_alert_test.516170205 |
|
|
Sep 18 09:13:49 PM UTC 24 |
Sep 18 09:13:51 PM UTC 24 |
42032412 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_csb_read.1704965271 |
|
|
Sep 18 09:13:49 PM UTC 24 |
Sep 18 09:13:51 PM UTC 24 |
36133395 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.2596042736 |
|
|
Sep 18 09:13:52 PM UTC 24 |
Sep 18 09:13:54 PM UTC 24 |
17677111 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_rw.866783834 |
|
|
Sep 18 09:13:52 PM UTC 24 |
Sep 18 09:13:56 PM UTC 24 |
587863471 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.3424350462 |
|
|
Sep 18 09:13:56 PM UTC 24 |
Sep 18 09:13:59 PM UTC 24 |
46881975 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_upload.4017665406 |
|
|
Sep 18 09:13:36 PM UTC 24 |
Sep 18 09:14:00 PM UTC 24 |
15807421373 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_mailbox.3932172775 |
|
|
Sep 18 09:13:08 PM UTC 24 |
Sep 18 09:14:02 PM UTC 24 |
15956259678 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_intercept.2139567520 |
|
|
Sep 18 09:13:57 PM UTC 24 |
Sep 18 09:14:03 PM UTC 24 |
104738623 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_mailbox.335503657 |
|
|
Sep 18 09:10:25 PM UTC 24 |
Sep 18 09:14:05 PM UTC 24 |
55445540673 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_upload.1674562645 |
|
|
Sep 18 09:14:01 PM UTC 24 |
Sep 18 09:14:06 PM UTC 24 |
43918325 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode.2980281244 |
|
|
Sep 18 09:12:48 PM UTC 24 |
Sep 18 09:14:06 PM UTC 24 |
3796958666 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode.2525995842 |
|
|
Sep 18 09:14:03 PM UTC 24 |
Sep 18 09:14:09 PM UTC 24 |
56391407 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_cfg_cmd.1896526249 |
|
|
Sep 18 09:14:03 PM UTC 24 |
Sep 18 09:14:09 PM UTC 24 |
288022513 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_all.999956152 |
|
|
Sep 18 09:12:28 PM UTC 24 |
Sep 18 09:14:11 PM UTC 24 |
13377086772 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.2207135048 |
|
|
Sep 18 09:13:51 PM UTC 24 |
Sep 18 09:14:16 PM UTC 24 |
19737409281 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.2744175350 |
|
|
Sep 18 09:14:07 PM UTC 24 |
Sep 18 09:14:17 PM UTC 24 |
777914943 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.4174015032 |
|
|
Sep 18 09:13:52 PM UTC 24 |
Sep 18 09:14:20 PM UTC 24 |
8801401843 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_csb_read.148047545 |
|
|
Sep 18 09:14:18 PM UTC 24 |
Sep 18 09:14:20 PM UTC 24 |
31282787 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_alert_test.3476596114 |
|
|
Sep 18 09:14:18 PM UTC 24 |
Sep 18 09:14:20 PM UTC 24 |
16401856 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_all.4055697511 |
|
|
Sep 18 09:13:51 PM UTC 24 |
Sep 18 09:14:21 PM UTC 24 |
7437456911 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.127604206 |
|
|
Sep 18 09:11:23 PM UTC 24 |
Sep 18 09:14:23 PM UTC 24 |
79128717537 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.412029529 |
|
|
Sep 18 09:11:24 PM UTC 24 |
Sep 18 09:14:23 PM UTC 24 |
116179818881 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.2959200837 |
|
|
Sep 18 09:14:22 PM UTC 24 |
Sep 18 09:14:24 PM UTC 24 |
37826057 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.1874187211 |
|
|
Sep 18 09:11:05 PM UTC 24 |
Sep 18 09:14:26 PM UTC 24 |
98926273900 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_mailbox.558649252 |
|
|
Sep 18 09:13:32 PM UTC 24 |
Sep 18 09:14:30 PM UTC 24 |
25650871795 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.3955098727 |
|
|
Sep 18 09:14:24 PM UTC 24 |
Sep 18 09:14:30 PM UTC 24 |
1690182145 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_all.4142840447 |
|
|
Sep 18 09:14:07 PM UTC 24 |
Sep 18 09:14:31 PM UTC 24 |
1793561842 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_intercept.2878255077 |
|
|
Sep 18 09:14:24 PM UTC 24 |
Sep 18 09:14:31 PM UTC 24 |
762184689 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_rw.1813742183 |
|
|
Sep 18 09:14:22 PM UTC 24 |
Sep 18 09:14:34 PM UTC 24 |
1063656053 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_cfg_cmd.2897765495 |
|
|
Sep 18 09:14:31 PM UTC 24 |
Sep 18 09:14:35 PM UTC 24 |
38249870 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_mailbox.3996396867 |
|
|
Sep 18 09:14:27 PM UTC 24 |
Sep 18 09:14:41 PM UTC 24 |
531446644 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.1674928771 |
|
|
Sep 18 09:14:34 PM UTC 24 |
Sep 18 09:14:42 PM UTC 24 |
109480974 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_all.40995582 |
|
|
Sep 18 09:14:22 PM UTC 24 |
Sep 18 09:14:43 PM UTC 24 |
2659942390 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.2561873980 |
|
|
Sep 18 09:11:07 PM UTC 24 |
Sep 18 09:14:44 PM UTC 24 |
11464571279 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.2826255814 |
|
|
Sep 18 09:14:37 PM UTC 24 |
Sep 18 09:14:44 PM UTC 24 |
1156747177 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_upload.542011159 |
|
|
Sep 18 09:14:31 PM UTC 24 |
Sep 18 09:14:44 PM UTC 24 |
3521715889 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.558626159 |
|
|
Sep 18 09:14:24 PM UTC 24 |
Sep 18 09:14:45 PM UTC 24 |
4550861765 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_mailbox.1316777401 |
|
|
Sep 18 09:14:00 PM UTC 24 |
Sep 18 09:14:47 PM UTC 24 |
4217470106 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_alert_test.1010179478 |
|
|
Sep 18 09:14:45 PM UTC 24 |
Sep 18 09:14:47 PM UTC 24 |
11652946 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.1536840636 |
|
|
Sep 18 09:12:52 PM UTC 24 |
Sep 18 09:14:47 PM UTC 24 |
9950476033 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.4100927938 |
|
|
Sep 18 09:13:42 PM UTC 24 |
Sep 18 09:14:47 PM UTC 24 |
5170551503 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_csb_read.1706498396 |
|
|
Sep 18 09:14:45 PM UTC 24 |
Sep 18 09:14:47 PM UTC 24 |
77394568 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.2549830393 |
|
|
Sep 18 09:12:32 PM UTC 24 |
Sep 18 09:14:49 PM UTC 24 |
45570531818 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.228977701 |
|
|
Sep 18 09:14:48 PM UTC 24 |
Sep 18 09:14:49 PM UTC 24 |
26356116 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_rw.3620084456 |
|
|
Sep 18 09:14:48 PM UTC 24 |
Sep 18 09:14:50 PM UTC 24 |
121253415 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode.3468235318 |
|
|
Sep 18 09:14:32 PM UTC 24 |
Sep 18 09:14:52 PM UTC 24 |
883863012 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.165669756 |
|
|
Sep 18 09:14:13 PM UTC 24 |
Sep 18 09:14:53 PM UTC 24 |
2056786141 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_all.3872205077 |
|
|
Sep 18 09:13:16 PM UTC 24 |
Sep 18 09:14:54 PM UTC 24 |
2752246759 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_upload.2993733042 |
|
|
Sep 18 09:14:50 PM UTC 24 |
Sep 18 09:14:55 PM UTC 24 |
173636404 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.1305142313 |
|
|
Sep 18 09:10:17 PM UTC 24 |
Sep 18 09:14:55 PM UTC 24 |
23407264977 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.1619673232 |
|
|
Sep 18 09:14:49 PM UTC 24 |
Sep 18 09:14:56 PM UTC 24 |
616675942 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_cfg_cmd.221843812 |
|
|
Sep 18 09:14:52 PM UTC 24 |
Sep 18 09:14:56 PM UTC 24 |
34143005 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.1371267904 |
|
|
Sep 18 09:14:20 PM UTC 24 |
Sep 18 09:14:57 PM UTC 24 |
27943658007 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode.1852268901 |
|
|
Sep 18 09:13:36 PM UTC 24 |
Sep 18 09:14:57 PM UTC 24 |
9933227443 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.2610425948 |
|
|
Sep 18 09:14:45 PM UTC 24 |
Sep 18 09:14:59 PM UTC 24 |
8748088764 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_intercept.2007113766 |
|
|
Sep 18 09:14:49 PM UTC 24 |
Sep 18 09:15:00 PM UTC 24 |
1291092299 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_alert_test.270937956 |
|
|
Sep 18 09:14:58 PM UTC 24 |
Sep 18 09:15:00 PM UTC 24 |
10589453 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_csb_read.1754967452 |
|
|
Sep 18 09:14:58 PM UTC 24 |
Sep 18 09:15:00 PM UTC 24 |
23527372 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_all.3378253355 |
|
|
Sep 18 09:14:46 PM UTC 24 |
Sep 18 09:15:02 PM UTC 24 |
6930961722 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode.3319734721 |
|
|
Sep 18 09:14:54 PM UTC 24 |
Sep 18 09:15:02 PM UTC 24 |
3758835148 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.1881740465 |
|
|
Sep 18 09:15:01 PM UTC 24 |
Sep 18 09:15:03 PM UTC 24 |
31451297 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.1895498133 |
|
|
Sep 18 09:15:01 PM UTC 24 |
Sep 18 09:15:03 PM UTC 24 |
89016697 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_rw.284388904 |
|
|
Sep 18 09:15:02 PM UTC 24 |
Sep 18 09:15:05 PM UTC 24 |
80227757 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.2111807310 |
|
|
Sep 18 09:14:48 PM UTC 24 |
Sep 18 09:15:07 PM UTC 24 |
5726374405 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.2730468201 |
|
|
Sep 18 09:14:42 PM UTC 24 |
Sep 18 09:15:07 PM UTC 24 |
3912200497 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.4192841635 |
|
|
Sep 18 09:14:55 PM UTC 24 |
Sep 18 09:15:10 PM UTC 24 |
3303670652 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/36.spi_device_mailbox.2614810538 |
|
|
Sep 18 09:14:50 PM UTC 24 |
Sep 18 09:15:10 PM UTC 24 |
1540660962 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_upload.332190438 |
|
|
Sep 18 09:15:06 PM UTC 24 |
Sep 18 09:15:10 PM UTC 24 |
41188442 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.1606483731 |
|
|
Sep 18 09:15:03 PM UTC 24 |
Sep 18 09:15:11 PM UTC 24 |
312763992 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.30074983 |
|
|
Sep 18 09:13:18 PM UTC 24 |
Sep 18 09:15:13 PM UTC 24 |
4579883091 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.2676596036 |
|
|
Sep 18 09:15:03 PM UTC 24 |
Sep 18 09:15:14 PM UTC 24 |
1195799867 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_cfg_cmd.784615858 |
|
|
Sep 18 09:15:08 PM UTC 24 |
Sep 18 09:15:15 PM UTC 24 |
1089412926 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.2874665900 |
|
|
Sep 18 09:15:14 PM UTC 24 |
Sep 18 09:15:17 PM UTC 24 |
137002764 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.3587592270 |
|
|
Sep 18 09:15:11 PM UTC 24 |
Sep 18 09:15:18 PM UTC 24 |
295792031 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_intercept.2522845749 |
|
|
Sep 18 09:15:04 PM UTC 24 |
Sep 18 09:15:18 PM UTC 24 |
1416772596 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_alert_test.3286539752 |
|
|
Sep 18 09:15:17 PM UTC 24 |
Sep 18 09:15:19 PM UTC 24 |
15834488 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.784431514 |
|
|
Sep 18 09:13:16 PM UTC 24 |
Sep 18 09:15:20 PM UTC 24 |
98787708596 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_csb_read.2493886214 |
|
|
Sep 18 09:15:18 PM UTC 24 |
Sep 18 09:15:20 PM UTC 24 |
26979525 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.4210160444 |
|
|
Sep 18 09:15:19 PM UTC 24 |
Sep 18 09:15:22 PM UTC 24 |
97343665 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_rw.2634496025 |
|
|
Sep 18 09:15:21 PM UTC 24 |
Sep 18 09:15:23 PM UTC 24 |
21833946 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.2307713196 |
|
|
Sep 18 09:14:32 PM UTC 24 |
Sep 18 09:15:25 PM UTC 24 |
7266066403 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode.18049204 |
|
|
Sep 18 09:15:08 PM UTC 24 |
Sep 18 09:15:26 PM UTC 24 |
400013820 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.2792868554 |
|
|
Sep 18 09:13:37 PM UTC 24 |
Sep 18 09:15:25 PM UTC 24 |
21037829384 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.3170967820 |
|
|
Sep 18 09:13:43 PM UTC 24 |
Sep 18 09:15:29 PM UTC 24 |
7434007658 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.3088049461 |
|
|
Sep 18 09:15:23 PM UTC 24 |
Sep 18 09:15:30 PM UTC 24 |
711635142 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_intercept.3638991834 |
|
|
Sep 18 09:15:24 PM UTC 24 |
Sep 18 09:15:31 PM UTC 24 |
202121472 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_all.2262458666 |
|
|
Sep 18 09:15:19 PM UTC 24 |
Sep 18 09:15:32 PM UTC 24 |
2451672915 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_all.3684138980 |
|
|
Sep 18 09:15:01 PM UTC 24 |
Sep 18 09:15:35 PM UTC 24 |
17410425547 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_cfg_cmd.1863599776 |
|
|
Sep 18 09:15:27 PM UTC 24 |
Sep 18 09:15:35 PM UTC 24 |
371755129 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_upload.1159504745 |
|
|
Sep 18 09:15:27 PM UTC 24 |
Sep 18 09:15:35 PM UTC 24 |
248297568 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.2224761000 |
|
|
Sep 18 09:11:45 PM UTC 24 |
Sep 18 09:15:39 PM UTC 24 |
25524479145 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.80722814 |
|
|
Sep 18 09:15:31 PM UTC 24 |
Sep 18 09:15:41 PM UTC 24 |
14191887626 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_alert_test.3522916219 |
|
|
Sep 18 09:15:40 PM UTC 24 |
Sep 18 09:15:43 PM UTC 24 |
10583929 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_csb_read.2504396042 |
|
|
Sep 18 09:15:42 PM UTC 24 |
Sep 18 09:15:44 PM UTC 24 |
42616993 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.1110635611 |
|
|
Sep 18 09:15:44 PM UTC 24 |
Sep 18 09:15:47 PM UTC 24 |
472517052 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.564643262 |
|
|
Sep 18 09:15:19 PM UTC 24 |
Sep 18 09:15:48 PM UTC 24 |
9630307088 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode.2365316712 |
|
|
Sep 18 09:15:30 PM UTC 24 |
Sep 18 09:15:49 PM UTC 24 |
1378325188 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.740543420 |
|
|
Sep 18 09:15:48 PM UTC 24 |
Sep 18 09:15:51 PM UTC 24 |
166710248 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.102898140 |
|
|
Sep 18 09:15:21 PM UTC 24 |
Sep 18 09:15:52 PM UTC 24 |
14550771125 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_rw.801392016 |
|
|
Sep 18 09:15:50 PM UTC 24 |
Sep 18 09:15:53 PM UTC 24 |
54880532 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_mailbox.1516249790 |
|
|
Sep 18 09:15:54 PM UTC 24 |
Sep 18 09:16:01 PM UTC 24 |
795794914 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_intercept.362952666 |
|
|
Sep 18 09:15:53 PM UTC 24 |
Sep 18 09:16:03 PM UTC 24 |
2395791583 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_cfg_cmd.4126480890 |
|
|
Sep 18 09:16:04 PM UTC 24 |
Sep 18 09:16:08 PM UTC 24 |
490319274 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/24.spi_device_stress_all.450214311 |
|
|
Sep 18 09:10:33 PM UTC 24 |
Sep 18 09:16:09 PM UTC 24 |
58809387840 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_all.1507699789 |
|
|
Sep 18 09:12:49 PM UTC 24 |
Sep 18 09:16:13 PM UTC 24 |
48993648701 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.1463533042 |
|
|
Sep 18 09:15:50 PM UTC 24 |
Sep 18 09:16:13 PM UTC 24 |
11614404613 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.2544829810 |
|
|
Sep 18 09:15:52 PM UTC 24 |
Sep 18 09:16:17 PM UTC 24 |
12764841898 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.2159872600 |
|
|
Sep 18 09:12:27 PM UTC 24 |
Sep 18 09:16:18 PM UTC 24 |
401710144359 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_all.2694939670 |
|
|
Sep 18 09:13:38 PM UTC 24 |
Sep 18 09:16:21 PM UTC 24 |
33166536875 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_upload.135755031 |
|
|
Sep 18 09:16:02 PM UTC 24 |
Sep 18 09:16:23 PM UTC 24 |
5838397855 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_alert_test.774796801 |
|
|
Sep 18 09:16:22 PM UTC 24 |
Sep 18 09:16:25 PM UTC 24 |
37544469 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.2488312787 |
|
|
Sep 18 09:16:22 PM UTC 24 |
Sep 18 09:16:25 PM UTC 24 |
247204380 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_csb_read.1647845494 |
|
|
Sep 18 09:16:24 PM UTC 24 |
Sep 18 09:16:27 PM UTC 24 |
57511782 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.1170402840 |
|
|
Sep 18 09:15:45 PM UTC 24 |
Sep 18 09:16:29 PM UTC 24 |
2739693832 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.1838998774 |
|
|
Sep 18 09:14:06 PM UTC 24 |
Sep 18 09:16:29 PM UTC 24 |
30590930263 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.4057908531 |
|
|
Sep 18 09:15:31 PM UTC 24 |
Sep 18 09:16:29 PM UTC 24 |
6350310612 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.2758601746 |
|
|
Sep 18 09:16:28 PM UTC 24 |
Sep 18 09:16:30 PM UTC 24 |
14416323 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.93435961 |
|
|
Sep 18 09:16:13 PM UTC 24 |
Sep 18 09:16:31 PM UTC 24 |
1412421918 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/38.spi_device_mailbox.356282273 |
|
|
Sep 18 09:15:25 PM UTC 24 |
Sep 18 09:16:33 PM UTC 24 |
5506722279 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_rw.2003155787 |
|
|
Sep 18 09:16:29 PM UTC 24 |
Sep 18 09:16:33 PM UTC 24 |
58071652 ps |