| T256 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.2313967623 |
|
|
Sep 24 02:16:21 PM UTC 24 |
Sep 24 02:26:42 PM UTC 24 |
164871282681 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_all.1722688759 |
|
|
Sep 24 02:23:53 PM UTC 24 |
Sep 24 02:26:43 PM UTC 24 |
55877977925 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_alert_test.3640742005 |
|
|
Sep 24 02:26:43 PM UTC 24 |
Sep 24 02:26:45 PM UTC 24 |
14877752 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_csb_read.3073887440 |
|
|
Sep 24 02:26:44 PM UTC 24 |
Sep 24 02:26:47 PM UTC 24 |
52174143 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.2134705778 |
|
|
Sep 24 02:26:18 PM UTC 24 |
Sep 24 02:26:47 PM UTC 24 |
5431809991 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_stress_all.3275410486 |
|
|
Sep 24 02:25:27 PM UTC 24 |
Sep 24 02:26:47 PM UTC 24 |
9584954739 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_all.1417687835 |
|
|
Sep 24 02:24:34 PM UTC 24 |
Sep 24 02:26:47 PM UTC 24 |
38782564564 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.391226034 |
|
|
Sep 24 02:24:39 PM UTC 24 |
Sep 24 02:26:50 PM UTC 24 |
153223305877 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.238406879 |
|
|
Sep 24 02:26:48 PM UTC 24 |
Sep 24 02:26:50 PM UTC 24 |
132565061 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_rw.3976811007 |
|
|
Sep 24 02:26:48 PM UTC 24 |
Sep 24 02:26:50 PM UTC 24 |
37481588 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.1707434472 |
|
|
Sep 24 02:26:46 PM UTC 24 |
Sep 24 02:26:53 PM UTC 24 |
871077916 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.4294858461 |
|
|
Sep 24 02:26:51 PM UTC 24 |
Sep 24 02:26:56 PM UTC 24 |
197937523 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_intercept.304651324 |
|
|
Sep 24 02:26:51 PM UTC 24 |
Sep 24 02:26:57 PM UTC 24 |
252660817 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.3893946730 |
|
|
Sep 24 02:20:27 PM UTC 24 |
Sep 24 02:26:57 PM UTC 24 |
167049549528 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.3905441534 |
|
|
Sep 24 02:26:42 PM UTC 24 |
Sep 24 02:26:58 PM UTC 24 |
1421412131 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_upload.1784258585 |
|
|
Sep 24 02:26:33 PM UTC 24 |
Sep 24 02:26:58 PM UTC 24 |
2950476006 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_cfg_cmd.1019964555 |
|
|
Sep 24 02:26:54 PM UTC 24 |
Sep 24 02:26:58 PM UTC 24 |
118214882 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_upload.1399962547 |
|
|
Sep 24 02:26:54 PM UTC 24 |
Sep 24 02:26:59 PM UTC 24 |
115156019 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.1398802860 |
|
|
Sep 24 02:26:01 PM UTC 24 |
Sep 24 02:27:02 PM UTC 24 |
10089010029 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.1649309000 |
|
|
Sep 24 02:27:00 PM UTC 24 |
Sep 24 02:27:03 PM UTC 24 |
357665943 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_csb_read.1395688935 |
|
|
Sep 24 02:27:03 PM UTC 24 |
Sep 24 02:27:05 PM UTC 24 |
15550656 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_alert_test.1582165772 |
|
|
Sep 24 02:27:03 PM UTC 24 |
Sep 24 02:27:05 PM UTC 24 |
11777239 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.3463828615 |
|
|
Sep 24 02:23:03 PM UTC 24 |
Sep 24 02:27:06 PM UTC 24 |
18939247788 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_mailbox.351700188 |
|
|
Sep 24 02:25:51 PM UTC 24 |
Sep 24 02:27:07 PM UTC 24 |
5733265878 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode.2940480396 |
|
|
Sep 24 02:26:56 PM UTC 24 |
Sep 24 02:27:08 PM UTC 24 |
989878713 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.328007398 |
|
|
Sep 24 02:27:06 PM UTC 24 |
Sep 24 02:27:09 PM UTC 24 |
61504614 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.2683503619 |
|
|
Sep 24 02:18:12 PM UTC 24 |
Sep 24 02:27:09 PM UTC 24 |
80710904812 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_rw.1958537233 |
|
|
Sep 24 02:27:07 PM UTC 24 |
Sep 24 02:27:10 PM UTC 24 |
140175561 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.3625922899 |
|
|
Sep 24 02:26:59 PM UTC 24 |
Sep 24 02:27:10 PM UTC 24 |
2145105731 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_mailbox.2426735386 |
|
|
Sep 24 02:26:31 PM UTC 24 |
Sep 24 02:27:12 PM UTC 24 |
4048578170 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_upload.2107825363 |
|
|
Sep 24 02:27:11 PM UTC 24 |
Sep 24 02:27:15 PM UTC 24 |
40855829 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_all.2813489989 |
|
|
Sep 24 02:20:26 PM UTC 24 |
Sep 24 02:27:17 PM UTC 24 |
109120639435 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_mailbox.3286104683 |
|
|
Sep 24 02:27:11 PM UTC 24 |
Sep 24 02:27:18 PM UTC 24 |
157309874 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_cfg_cmd.1610947077 |
|
|
Sep 24 02:27:13 PM UTC 24 |
Sep 24 02:27:20 PM UTC 24 |
190493714 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_intercept.3512505300 |
|
|
Sep 24 02:27:10 PM UTC 24 |
Sep 24 02:27:21 PM UTC 24 |
1998773790 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.1571782928 |
|
|
Sep 24 02:26:40 PM UTC 24 |
Sep 24 02:27:22 PM UTC 24 |
7814894004 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.3202509578 |
|
|
Sep 24 02:18:20 PM UTC 24 |
Sep 24 02:27:22 PM UTC 24 |
256436841510 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.3120734486 |
|
|
Sep 24 02:25:26 PM UTC 24 |
Sep 24 02:27:28 PM UTC 24 |
16672199744 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.1936977549 |
|
|
Sep 24 02:26:49 PM UTC 24 |
Sep 24 02:27:30 PM UTC 24 |
10827534124 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_all.2102467639 |
|
|
Sep 24 02:21:28 PM UTC 24 |
Sep 24 02:27:31 PM UTC 24 |
161278862055 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_mailbox.1951591356 |
|
|
Sep 24 02:26:51 PM UTC 24 |
Sep 24 02:27:31 PM UTC 24 |
2156527134 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode.2292746889 |
|
|
Sep 24 02:27:16 PM UTC 24 |
Sep 24 02:27:31 PM UTC 24 |
352686964 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.3390928450 |
|
|
Sep 24 02:27:09 PM UTC 24 |
Sep 24 02:27:31 PM UTC 24 |
5234502082 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_alert_test.1298020506 |
|
|
Sep 24 02:27:30 PM UTC 24 |
Sep 24 02:27:33 PM UTC 24 |
41428482 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_csb_read.3990480911 |
|
|
Sep 24 02:27:32 PM UTC 24 |
Sep 24 02:27:34 PM UTC 24 |
18707021 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.641603544 |
|
|
Sep 24 02:27:18 PM UTC 24 |
Sep 24 02:27:34 PM UTC 24 |
781601323 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.941980377 |
|
|
Sep 24 02:27:33 PM UTC 24 |
Sep 24 02:27:36 PM UTC 24 |
217239871 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_rw.540354389 |
|
|
Sep 24 02:27:33 PM UTC 24 |
Sep 24 02:27:36 PM UTC 24 |
49623166 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.2531968204 |
|
|
Sep 24 02:22:05 PM UTC 24 |
Sep 24 02:27:36 PM UTC 24 |
296941189108 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_all.3780336139 |
|
|
Sep 24 02:26:47 PM UTC 24 |
Sep 24 02:27:37 PM UTC 24 |
7281335639 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_all.2369230743 |
|
|
Sep 24 02:27:06 PM UTC 24 |
Sep 24 02:27:39 PM UTC 24 |
21449883090 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.369951302 |
|
|
Sep 24 02:27:08 PM UTC 24 |
Sep 24 02:27:40 PM UTC 24 |
21714492748 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.53963943 |
|
|
Sep 24 02:27:35 PM UTC 24 |
Sep 24 02:27:40 PM UTC 24 |
558913189 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_cfg_cmd.1292496242 |
|
|
Sep 24 02:27:38 PM UTC 24 |
Sep 24 02:27:43 PM UTC 24 |
85406100 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.2870355596 |
|
|
Sep 24 02:27:34 PM UTC 24 |
Sep 24 02:27:43 PM UTC 24 |
403138728 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_intercept.2644057125 |
|
|
Sep 24 02:27:35 PM UTC 24 |
Sep 24 02:27:48 PM UTC 24 |
873872574 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.521875738 |
|
|
Sep 24 02:27:41 PM UTC 24 |
Sep 24 02:27:49 PM UTC 24 |
210844305 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_upload.1188546511 |
|
|
Sep 24 02:27:38 PM UTC 24 |
Sep 24 02:27:50 PM UTC 24 |
20077720790 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.3872374748 |
|
|
Sep 24 02:27:06 PM UTC 24 |
Sep 24 02:27:50 PM UTC 24 |
16176937247 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.3285899367 |
|
|
Sep 24 02:26:59 PM UTC 24 |
Sep 24 02:27:51 PM UTC 24 |
15366567588 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_stress_all.4143903257 |
|
|
Sep 24 02:27:48 PM UTC 24 |
Sep 24 02:27:51 PM UTC 24 |
87188894 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.940810141 |
|
|
Sep 24 02:26:02 PM UTC 24 |
Sep 24 02:27:52 PM UTC 24 |
6359242632 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_alert_test.923572338 |
|
|
Sep 24 02:27:50 PM UTC 24 |
Sep 24 02:27:53 PM UTC 24 |
14236022 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_csb_read.3699976256 |
|
|
Sep 24 02:27:50 PM UTC 24 |
Sep 24 02:27:53 PM UTC 24 |
34333331 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.1642867824 |
|
|
Sep 24 02:27:53 PM UTC 24 |
Sep 24 02:27:55 PM UTC 24 |
64924439 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_rw.3864893101 |
|
|
Sep 24 02:27:53 PM UTC 24 |
Sep 24 02:27:58 PM UTC 24 |
560763314 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.2066740036 |
|
|
Sep 24 02:27:54 PM UTC 24 |
Sep 24 02:28:02 PM UTC 24 |
1439867657 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.3007826811 |
|
|
Sep 24 02:26:43 PM UTC 24 |
Sep 24 02:28:03 PM UTC 24 |
11354176665 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.530245121 |
|
|
Sep 24 02:27:32 PM UTC 24 |
Sep 24 02:28:05 PM UTC 24 |
4875347044 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_intercept.2007964210 |
|
|
Sep 24 02:27:56 PM UTC 24 |
Sep 24 02:28:05 PM UTC 24 |
799088625 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.1171547530 |
|
|
Sep 24 02:26:58 PM UTC 24 |
Sep 24 02:28:07 PM UTC 24 |
65049960120 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode.826506258 |
|
|
Sep 24 02:27:38 PM UTC 24 |
Sep 24 02:28:09 PM UTC 24 |
779542289 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_all.1603449680 |
|
|
Sep 24 02:27:52 PM UTC 24 |
Sep 24 02:28:10 PM UTC 24 |
7653427391 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.3005346647 |
|
|
Sep 24 02:27:00 PM UTC 24 |
Sep 24 02:28:10 PM UTC 24 |
53953726437 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.965726752 |
|
|
Sep 24 02:27:54 PM UTC 24 |
Sep 24 02:28:13 PM UTC 24 |
2262033103 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_cfg_cmd.3058102853 |
|
|
Sep 24 02:28:03 PM UTC 24 |
Sep 24 02:28:14 PM UTC 24 |
515399720 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.909221633 |
|
|
Sep 24 02:27:22 PM UTC 24 |
Sep 24 02:28:15 PM UTC 24 |
14297311290 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.2001428919 |
|
|
Sep 24 02:28:08 PM UTC 24 |
Sep 24 02:28:15 PM UTC 24 |
1153855707 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_all.1289869873 |
|
|
Sep 24 02:26:01 PM UTC 24 |
Sep 24 02:28:15 PM UTC 24 |
51972888902 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_alert_test.2663731850 |
|
|
Sep 24 02:28:14 PM UTC 24 |
Sep 24 02:28:16 PM UTC 24 |
25362290 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_csb_read.2870390535 |
|
|
Sep 24 02:28:14 PM UTC 24 |
Sep 24 02:28:17 PM UTC 24 |
11956828 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.1560794879 |
|
|
Sep 24 02:28:15 PM UTC 24 |
Sep 24 02:28:18 PM UTC 24 |
49878162 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode.1872950998 |
|
|
Sep 24 02:28:05 PM UTC 24 |
Sep 24 02:28:19 PM UTC 24 |
1079123268 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_mailbox.2597790443 |
|
|
Sep 24 02:27:58 PM UTC 24 |
Sep 24 02:28:20 PM UTC 24 |
736048518 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.3337398454 |
|
|
Sep 24 02:21:26 PM UTC 24 |
Sep 24 02:28:21 PM UTC 24 |
135249428302 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_rw.4064000063 |
|
|
Sep 24 02:28:18 PM UTC 24 |
Sep 24 02:28:21 PM UTC 24 |
407801663 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.1443288878 |
|
|
Sep 24 02:28:18 PM UTC 24 |
Sep 24 02:28:22 PM UTC 24 |
34161081 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.3820465439 |
|
|
Sep 24 02:27:52 PM UTC 24 |
Sep 24 02:28:28 PM UTC 24 |
11700909536 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.2484431691 |
|
|
Sep 24 02:28:10 PM UTC 24 |
Sep 24 02:28:29 PM UTC 24 |
10923067654 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_cfg_cmd.344224521 |
|
|
Sep 24 02:28:22 PM UTC 24 |
Sep 24 02:28:29 PM UTC 24 |
260508226 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_upload.2333512175 |
|
|
Sep 24 02:28:21 PM UTC 24 |
Sep 24 02:28:29 PM UTC 24 |
1226775780 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_all.3480202441 |
|
|
Sep 24 02:27:33 PM UTC 24 |
Sep 24 02:28:29 PM UTC 24 |
16112427098 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_upload.3597800247 |
|
|
Sep 24 02:28:02 PM UTC 24 |
Sep 24 02:28:30 PM UTC 24 |
7147506086 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.3516530144 |
|
|
Sep 24 02:28:19 PM UTC 24 |
Sep 24 02:28:30 PM UTC 24 |
9156039776 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.639495889 |
|
|
Sep 24 02:20:00 PM UTC 24 |
Sep 24 02:28:31 PM UTC 24 |
263295633526 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.1841096189 |
|
|
Sep 24 02:28:15 PM UTC 24 |
Sep 24 02:28:32 PM UTC 24 |
5432256337 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_alert_test.763928264 |
|
|
Sep 24 02:28:32 PM UTC 24 |
Sep 24 02:28:34 PM UTC 24 |
13694131 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_csb_read.979762060 |
|
|
Sep 24 02:28:32 PM UTC 24 |
Sep 24 02:28:35 PM UTC 24 |
17355446 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.2779827441 |
|
|
Sep 24 02:26:09 PM UTC 24 |
Sep 24 02:28:36 PM UTC 24 |
17395420541 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.2840861513 |
|
|
Sep 24 02:28:33 PM UTC 24 |
Sep 24 02:28:36 PM UTC 24 |
101569555 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_all.3151504867 |
|
|
Sep 24 02:28:15 PM UTC 24 |
Sep 24 02:28:38 PM UTC 24 |
4925364140 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.2924040140 |
|
|
Sep 24 02:14:54 PM UTC 24 |
Sep 24 02:28:39 PM UTC 24 |
67915536075 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.2804848951 |
|
|
Sep 24 02:28:35 PM UTC 24 |
Sep 24 02:28:42 PM UTC 24 |
661676073 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_intercept.1239928923 |
|
|
Sep 24 02:28:38 PM UTC 24 |
Sep 24 02:28:43 PM UTC 24 |
96761699 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.2472590830 |
|
|
Sep 24 02:28:10 PM UTC 24 |
Sep 24 02:28:45 PM UTC 24 |
3467291616 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.4050748189 |
|
|
Sep 24 02:28:30 PM UTC 24 |
Sep 24 02:28:45 PM UTC 24 |
4149321798 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.3494842099 |
|
|
Sep 24 02:28:37 PM UTC 24 |
Sep 24 02:28:46 PM UTC 24 |
306149992 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_mailbox.1708544166 |
|
|
Sep 24 02:27:36 PM UTC 24 |
Sep 24 02:28:46 PM UTC 24 |
21042421342 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_rw.3378460964 |
|
|
Sep 24 02:28:35 PM UTC 24 |
Sep 24 02:28:48 PM UTC 24 |
296967637 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_cfg_cmd.523200078 |
|
|
Sep 24 02:28:43 PM UTC 24 |
Sep 24 02:28:49 PM UTC 24 |
456056250 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_intercept.2467319402 |
|
|
Sep 24 02:28:20 PM UTC 24 |
Sep 24 02:28:50 PM UTC 24 |
2498533970 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_upload.2414069102 |
|
|
Sep 24 02:28:40 PM UTC 24 |
Sep 24 02:28:52 PM UTC 24 |
2159206505 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.2225896370 |
|
|
Sep 24 02:28:49 PM UTC 24 |
Sep 24 02:28:52 PM UTC 24 |
200527812 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_alert_test.2002672709 |
|
|
Sep 24 02:28:51 PM UTC 24 |
Sep 24 02:28:53 PM UTC 24 |
14127330 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.719907433 |
|
|
Sep 24 02:28:46 PM UTC 24 |
Sep 24 02:28:53 PM UTC 24 |
650050965 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_csb_read.494529585 |
|
|
Sep 24 02:28:53 PM UTC 24 |
Sep 24 02:28:55 PM UTC 24 |
51408050 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.861396892 |
|
|
Sep 24 02:28:54 PM UTC 24 |
Sep 24 02:28:56 PM UTC 24 |
18821523 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.1914594495 |
|
|
Sep 24 02:27:18 PM UTC 24 |
Sep 24 02:28:57 PM UTC 24 |
6742236726 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode.3741055561 |
|
|
Sep 24 02:28:43 PM UTC 24 |
Sep 24 02:28:58 PM UTC 24 |
2135073274 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_rw.3082528040 |
|
|
Sep 24 02:28:56 PM UTC 24 |
Sep 24 02:28:58 PM UTC 24 |
107817112 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_all.96691396 |
|
|
Sep 24 02:28:09 PM UTC 24 |
Sep 24 02:28:59 PM UTC 24 |
2790815674 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.3593021975 |
|
|
Sep 24 02:28:32 PM UTC 24 |
Sep 24 02:29:01 PM UTC 24 |
9058749962 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode.40437945 |
|
|
Sep 24 02:28:23 PM UTC 24 |
Sep 24 02:29:02 PM UTC 24 |
3192106096 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_intercept.1414960353 |
|
|
Sep 24 02:28:59 PM UTC 24 |
Sep 24 02:29:03 PM UTC 24 |
122406340 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_all.3343311901 |
|
|
Sep 24 02:28:30 PM UTC 24 |
Sep 24 02:29:04 PM UTC 24 |
1942648051 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.1125376710 |
|
|
Sep 24 02:27:23 PM UTC 24 |
Sep 24 02:29:06 PM UTC 24 |
13385162993 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_cfg_cmd.1015247926 |
|
|
Sep 24 02:29:03 PM UTC 24 |
Sep 24 02:29:07 PM UTC 24 |
107653564 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.1543109271 |
|
|
Sep 24 02:29:05 PM UTC 24 |
Sep 24 02:29:11 PM UTC 24 |
332716685 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_mailbox.940130319 |
|
|
Sep 24 02:28:39 PM UTC 24 |
Sep 24 02:29:13 PM UTC 24 |
9763135460 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.209687928 |
|
|
Sep 24 02:25:21 PM UTC 24 |
Sep 24 02:29:14 PM UTC 24 |
47525721398 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.3812550062 |
|
|
Sep 24 02:28:57 PM UTC 24 |
Sep 24 02:29:14 PM UTC 24 |
47272221340 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_alert_test.3706197088 |
|
|
Sep 24 02:29:14 PM UTC 24 |
Sep 24 02:29:16 PM UTC 24 |
15141351 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_upload.2008580100 |
|
|
Sep 24 02:29:00 PM UTC 24 |
Sep 24 02:29:17 PM UTC 24 |
4738495247 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_csb_read.1639697365 |
|
|
Sep 24 02:29:15 PM UTC 24 |
Sep 24 02:29:18 PM UTC 24 |
27253923 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.2308234745 |
|
|
Sep 24 02:28:53 PM UTC 24 |
Sep 24 02:29:19 PM UTC 24 |
7724627424 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode.2512585156 |
|
|
Sep 24 02:29:04 PM UTC 24 |
Sep 24 02:29:21 PM UTC 24 |
3076471708 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.365327534 |
|
|
Sep 24 02:29:17 PM UTC 24 |
Sep 24 02:29:21 PM UTC 24 |
391559764 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_rw.2375751758 |
|
|
Sep 24 02:29:20 PM UTC 24 |
Sep 24 02:29:22 PM UTC 24 |
85329441 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.2202269308 |
|
|
Sep 24 02:29:20 PM UTC 24 |
Sep 24 02:29:23 PM UTC 24 |
78009169 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.3584773075 |
|
|
Sep 24 02:28:11 PM UTC 24 |
Sep 24 02:29:24 PM UTC 24 |
7036803888 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.3218457754 |
|
|
Sep 24 02:18:17 PM UTC 24 |
Sep 24 02:29:29 PM UTC 24 |
61478865759 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.2200010671 |
|
|
Sep 24 02:29:22 PM UTC 24 |
Sep 24 02:29:31 PM UTC 24 |
417926981 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.2105650615 |
|
|
Sep 24 02:28:30 PM UTC 24 |
Sep 24 02:29:32 PM UTC 24 |
9850582169 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_all.2534668228 |
|
|
Sep 24 02:28:33 PM UTC 24 |
Sep 24 02:29:34 PM UTC 24 |
127555705182 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_cfg_cmd.2707826350 |
|
|
Sep 24 02:29:30 PM UTC 24 |
Sep 24 02:29:35 PM UTC 24 |
33164892 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.2240379737 |
|
|
Sep 24 02:29:22 PM UTC 24 |
Sep 24 02:29:36 PM UTC 24 |
5750497442 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.1850957018 |
|
|
Sep 24 02:28:58 PM UTC 24 |
Sep 24 02:29:37 PM UTC 24 |
23845304682 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_all.2528032845 |
|
|
Sep 24 02:29:07 PM UTC 24 |
Sep 24 02:29:37 PM UTC 24 |
7075998313 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_upload.2802556663 |
|
|
Sep 24 02:29:25 PM UTC 24 |
Sep 24 02:29:38 PM UTC 24 |
6684882320 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_all.3758933529 |
|
|
Sep 24 02:28:54 PM UTC 24 |
Sep 24 02:29:39 PM UTC 24 |
7223020863 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.13683907 |
|
|
Sep 24 02:29:05 PM UTC 24 |
Sep 24 02:29:41 PM UTC 24 |
8047018820 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_alert_test.2728965895 |
|
|
Sep 24 02:29:39 PM UTC 24 |
Sep 24 02:29:41 PM UTC 24 |
10900198 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_csb_read.1670318258 |
|
|
Sep 24 02:29:40 PM UTC 24 |
Sep 24 02:29:43 PM UTC 24 |
20594623 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode.541674086 |
|
|
Sep 24 02:29:32 PM UTC 24 |
Sep 24 02:29:43 PM UTC 24 |
467079514 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.3420526264 |
|
|
Sep 24 02:29:35 PM UTC 24 |
Sep 24 02:29:44 PM UTC 24 |
380659834 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.216127518 |
|
|
Sep 24 02:28:46 PM UTC 24 |
Sep 24 02:29:45 PM UTC 24 |
2973399932 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.2218317638 |
|
|
Sep 24 02:29:43 PM UTC 24 |
Sep 24 02:29:46 PM UTC 24 |
53311039 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_rw.3758303007 |
|
|
Sep 24 02:29:45 PM UTC 24 |
Sep 24 02:29:48 PM UTC 24 |
39959870 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_intercept.4105920133 |
|
|
Sep 24 02:29:23 PM UTC 24 |
Sep 24 02:29:50 PM UTC 24 |
5491900811 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.562568444 |
|
|
Sep 24 02:27:44 PM UTC 24 |
Sep 24 02:29:50 PM UTC 24 |
7890915699 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.2279470511 |
|
|
Sep 24 02:27:41 PM UTC 24 |
Sep 24 02:29:52 PM UTC 24 |
15050302129 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_all.597539023 |
|
|
Sep 24 02:29:18 PM UTC 24 |
Sep 24 02:29:56 PM UTC 24 |
3231759254 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.415808381 |
|
|
Sep 24 02:29:45 PM UTC 24 |
Sep 24 02:29:57 PM UTC 24 |
1299668531 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_intercept.712336395 |
|
|
Sep 24 02:29:47 PM UTC 24 |
Sep 24 02:30:00 PM UTC 24 |
3336226170 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.1003962241 |
|
|
Sep 24 02:29:47 PM UTC 24 |
Sep 24 02:30:00 PM UTC 24 |
944269389 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode.1089705958 |
|
|
Sep 24 02:29:52 PM UTC 24 |
Sep 24 02:30:00 PM UTC 24 |
365903506 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.2330312916 |
|
|
Sep 24 02:26:41 PM UTC 24 |
Sep 24 02:30:01 PM UTC 24 |
75053282972 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.884475682 |
|
|
Sep 24 02:29:42 PM UTC 24 |
Sep 24 02:30:01 PM UTC 24 |
16531120875 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_cfg_cmd.1687565036 |
|
|
Sep 24 02:29:51 PM UTC 24 |
Sep 24 02:30:02 PM UTC 24 |
348506765 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_alert_test.499158361 |
|
|
Sep 24 02:30:02 PM UTC 24 |
Sep 24 02:30:04 PM UTC 24 |
40316787 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.2270606910 |
|
|
Sep 24 02:30:02 PM UTC 24 |
Sep 24 02:30:04 PM UTC 24 |
166608453 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_csb_read.2475602946 |
|
|
Sep 24 02:30:03 PM UTC 24 |
Sep 24 02:30:05 PM UTC 24 |
39234309 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.81523722 |
|
|
Sep 24 02:29:58 PM UTC 24 |
Sep 24 02:30:06 PM UTC 24 |
1300889974 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_all.2320460633 |
|
|
Sep 24 02:30:05 PM UTC 24 |
Sep 24 02:30:07 PM UTC 24 |
11758472 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.175180587 |
|
|
Sep 24 02:30:05 PM UTC 24 |
Sep 24 02:30:08 PM UTC 24 |
162067066 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.2858814176 |
|
|
Sep 24 02:30:06 PM UTC 24 |
Sep 24 02:30:08 PM UTC 24 |
33438118 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_upload.2044619253 |
|
|
Sep 24 02:29:50 PM UTC 24 |
Sep 24 02:30:08 PM UTC 24 |
5969618260 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.2235380120 |
|
|
Sep 24 02:29:12 PM UTC 24 |
Sep 24 02:30:10 PM UTC 24 |
8984242517 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_rw.957131317 |
|
|
Sep 24 02:30:06 PM UTC 24 |
Sep 24 02:30:11 PM UTC 24 |
54459919 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_mailbox.3602073008 |
|
|
Sep 24 02:29:49 PM UTC 24 |
Sep 24 02:30:11 PM UTC 24 |
10506420864 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.4088126486 |
|
|
Sep 24 02:30:08 PM UTC 24 |
Sep 24 02:30:13 PM UTC 24 |
3127471598 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_upload.1420660843 |
|
|
Sep 24 02:30:11 PM UTC 24 |
Sep 24 02:30:16 PM UTC 24 |
659569561 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_cfg_cmd.1166674791 |
|
|
Sep 24 02:30:12 PM UTC 24 |
Sep 24 02:30:17 PM UTC 24 |
240172401 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_mailbox.2902909662 |
|
|
Sep 24 02:30:10 PM UTC 24 |
Sep 24 02:30:20 PM UTC 24 |
1793842016 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_intercept.3756660030 |
|
|
Sep 24 02:30:10 PM UTC 24 |
Sep 24 02:30:21 PM UTC 24 |
2273952235 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.3467790482 |
|
|
Sep 24 02:30:17 PM UTC 24 |
Sep 24 02:30:22 PM UTC 24 |
155937604 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_all.3830682032 |
|
|
Sep 24 02:29:42 PM UTC 24 |
Sep 24 02:30:28 PM UTC 24 |
6037773047 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_alert_test.2138266106 |
|
|
Sep 24 02:30:29 PM UTC 24 |
Sep 24 02:30:31 PM UTC 24 |
18521567 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.118352804 |
|
|
Sep 24 02:30:08 PM UTC 24 |
Sep 24 02:30:31 PM UTC 24 |
44411082205 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode.4156362318 |
|
|
Sep 24 02:30:12 PM UTC 24 |
Sep 24 02:30:32 PM UTC 24 |
512772424 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_csb_read.1107522899 |
|
|
Sep 24 02:30:32 PM UTC 24 |
Sep 24 02:30:34 PM UTC 24 |
58858896 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.1380055495 |
|
|
Sep 24 02:30:01 PM UTC 24 |
Sep 24 02:30:36 PM UTC 24 |
2554687328 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_mailbox.336879207 |
|
|
Sep 24 02:29:24 PM UTC 24 |
Sep 24 02:30:36 PM UTC 24 |
4433847762 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.2162452602 |
|
|
Sep 24 02:30:35 PM UTC 24 |
Sep 24 02:30:37 PM UTC 24 |
81928932 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_cfg_cmd.2487843911 |
|
|
Sep 24 02:31:52 PM UTC 24 |
Sep 24 02:32:14 PM UTC 24 |
7324558034 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.1232092760 |
|
|
Sep 24 02:29:37 PM UTC 24 |
Sep 24 02:30:38 PM UTC 24 |
2064480690 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_rw.1290382472 |
|
|
Sep 24 02:30:36 PM UTC 24 |
Sep 24 02:30:39 PM UTC 24 |
246278723 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.3843165591 |
|
|
Sep 24 02:28:06 PM UTC 24 |
Sep 24 02:30:42 PM UTC 24 |
34237986268 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.150608373 |
|
|
Sep 24 02:30:32 PM UTC 24 |
Sep 24 02:30:43 PM UTC 24 |
2809785208 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_mailbox.1123869139 |
|
|
Sep 24 02:30:39 PM UTC 24 |
Sep 24 02:30:43 PM UTC 24 |
147699140 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.298986713 |
|
|
Sep 24 02:26:36 PM UTC 24 |
Sep 24 02:30:45 PM UTC 24 |
299818759983 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_mailbox.1557395762 |
|
|
Sep 24 02:28:21 PM UTC 24 |
Sep 24 02:30:47 PM UTC 24 |
54672747316 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_mailbox.2564209978 |
|
|
Sep 24 02:28:59 PM UTC 24 |
Sep 24 02:30:48 PM UTC 24 |
10139774896 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_intercept.3950429904 |
|
|
Sep 24 02:30:39 PM UTC 24 |
Sep 24 02:30:48 PM UTC 24 |
355068219 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.3429259610 |
|
|
Sep 24 02:29:38 PM UTC 24 |
Sep 24 02:30:48 PM UTC 24 |
5639146216 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.2211344481 |
|
|
Sep 24 02:29:07 PM UTC 24 |
Sep 24 02:30:54 PM UTC 24 |
6370672593 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_all.2321949326 |
|
|
Sep 24 02:30:33 PM UTC 24 |
Sep 24 02:30:54 PM UTC 24 |
923265439 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.1655079936 |
|
|
Sep 24 02:30:38 PM UTC 24 |
Sep 24 02:30:54 PM UTC 24 |
2395505669 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.4166870280 |
|
|
Sep 24 02:30:48 PM UTC 24 |
Sep 24 02:30:56 PM UTC 24 |
843181862 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_alert_test.3695857595 |
|
|
Sep 24 02:30:54 PM UTC 24 |
Sep 24 02:30:56 PM UTC 24 |
157017907 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.3332031287 |
|
|
Sep 24 02:30:22 PM UTC 24 |
Sep 24 02:30:57 PM UTC 24 |
9315277884 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_csb_read.990036593 |
|
|
Sep 24 02:30:56 PM UTC 24 |
Sep 24 02:30:58 PM UTC 24 |
15824026 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.2738732930 |
|
|
Sep 24 02:30:36 PM UTC 24 |
Sep 24 02:30:58 PM UTC 24 |
2656049907 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.2751100112 |
|
|
Sep 24 02:30:58 PM UTC 24 |
Sep 24 02:31:00 PM UTC 24 |
81900259 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_rw.4100322399 |
|
|
Sep 24 02:30:58 PM UTC 24 |
Sep 24 02:31:01 PM UTC 24 |
109913168 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_cfg_cmd.3493242359 |
|
|
Sep 24 02:30:44 PM UTC 24 |
Sep 24 02:31:02 PM UTC 24 |
3912136116 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode.1083146947 |
|
|
Sep 24 02:30:45 PM UTC 24 |
Sep 24 02:31:02 PM UTC 24 |
3015642670 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_upload.3682314148 |
|
|
Sep 24 02:30:43 PM UTC 24 |
Sep 24 02:31:07 PM UTC 24 |
7072814802 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.2320979767 |
|
|
Sep 24 02:30:14 PM UTC 24 |
Sep 24 02:31:08 PM UTC 24 |
22979486746 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_all.2581970110 |
|
|
Sep 24 02:27:20 PM UTC 24 |
Sep 24 02:31:09 PM UTC 24 |
234169024308 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.3523601796 |
|
|
Sep 24 02:28:31 PM UTC 24 |
Sep 24 02:31:11 PM UTC 24 |
68488293527 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.4068283813 |
|
|
Sep 24 02:30:59 PM UTC 24 |
Sep 24 02:31:11 PM UTC 24 |
2023306812 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode.355058134 |
|
|
Sep 24 02:31:04 PM UTC 24 |
Sep 24 02:31:12 PM UTC 24 |
100349664 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.1032474728 |
|
|
Sep 24 02:30:59 PM UTC 24 |
Sep 24 02:31:13 PM UTC 24 |
4195103328 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_alert_test.2591932273 |
|
|
Sep 24 02:31:12 PM UTC 24 |
Sep 24 02:31:15 PM UTC 24 |
42515769 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.621981854 |
|
|
Sep 24 02:31:10 PM UTC 24 |
Sep 24 02:31:16 PM UTC 24 |
239519157 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_csb_read.2881352671 |
|
|
Sep 24 02:31:14 PM UTC 24 |
Sep 24 02:31:16 PM UTC 24 |
28716918 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_cfg_cmd.604775162 |
|
|
Sep 24 02:31:03 PM UTC 24 |
Sep 24 02:31:18 PM UTC 24 |
1350871242 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.4183530078 |
|
|
Sep 24 02:30:56 PM UTC 24 |
Sep 24 02:31:18 PM UTC 24 |
13972057983 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.224682779 |
|
|
Sep 24 02:31:17 PM UTC 24 |
Sep 24 02:31:19 PM UTC 24 |
29078520 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_rw.73077252 |
|
|
Sep 24 02:31:19 PM UTC 24 |
Sep 24 02:31:22 PM UTC 24 |
42348855 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_upload.1084377608 |
|
|
Sep 24 02:31:02 PM UTC 24 |
Sep 24 02:31:24 PM UTC 24 |
5274207752 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_intercept.1396786279 |
|
|
Sep 24 02:31:01 PM UTC 24 |
Sep 24 02:31:24 PM UTC 24 |
2151474025 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_mailbox.3769204655 |
|
|
Sep 24 02:31:01 PM UTC 24 |
Sep 24 02:31:28 PM UTC 24 |
2959130179 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_all.1974627477 |
|
|
Sep 24 02:29:36 PM UTC 24 |
Sep 24 02:31:31 PM UTC 24 |
10515685041 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.4227369572 |
|
|
Sep 24 02:29:57 PM UTC 24 |
Sep 24 02:31:31 PM UTC 24 |
34076197833 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.4076922613 |
|
|
Sep 24 02:23:47 PM UTC 24 |
Sep 24 02:31:32 PM UTC 24 |
220126008617 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.770992552 |
|
|
Sep 24 02:30:24 PM UTC 24 |
Sep 24 02:31:33 PM UTC 24 |
8387879453 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_all.532073475 |
|
|
Sep 24 02:31:10 PM UTC 24 |
Sep 24 02:32:15 PM UTC 24 |
13303448294 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.2721933704 |
|
|
Sep 24 02:31:16 PM UTC 24 |
Sep 24 02:31:34 PM UTC 24 |
83305534186 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_all.2949794608 |
|
|
Sep 24 02:28:47 PM UTC 24 |
Sep 24 02:31:35 PM UTC 24 |
53449482418 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_cfg_cmd.2705346860 |
|
|
Sep 24 02:31:29 PM UTC 24 |
Sep 24 02:31:35 PM UTC 24 |
272441802 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_all.1556461825 |
|
|
Sep 24 02:30:57 PM UTC 24 |
Sep 24 02:31:35 PM UTC 24 |
8180713695 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_alert_test.3744108866 |
|
|
Sep 24 02:31:36 PM UTC 24 |
Sep 24 02:31:38 PM UTC 24 |
31734800 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.2128078347 |
|
|
Sep 24 02:31:33 PM UTC 24 |
Sep 24 02:31:41 PM UTC 24 |
371501888 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_csb_read.2089590641 |
|
|
Sep 24 02:31:39 PM UTC 24 |
Sep 24 02:31:42 PM UTC 24 |
69451846 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.3453325879 |
|
|
Sep 24 02:31:32 PM UTC 24 |
Sep 24 02:31:45 PM UTC 24 |
229043253 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.1828365979 |
|
|
Sep 24 02:31:32 PM UTC 24 |
Sep 24 02:31:48 PM UTC 24 |
1655627841 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.2676217245 |
|
|
Sep 24 02:31:46 PM UTC 24 |
Sep 24 02:31:48 PM UTC 24 |
97979718 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_mailbox.2842038534 |
|
|
Sep 24 02:31:24 PM UTC 24 |
Sep 24 02:31:49 PM UTC 24 |
782618248 ps |