| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.08 | 98.44 | 94.08 | 98.62 | 89.36 | 97.27 | 95.56 | 99.26 |
| T1045 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2613232843 | Sep 24 02:35:34 PM UTC 24 | Sep 24 02:35:38 PM UTC 24 | 122049284 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.2342437231 | Sep 24 02:35:36 PM UTC 24 | Sep 24 02:35:39 PM UTC 24 | 26029425 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.4227624763 | Sep 24 02:35:35 PM UTC 24 | Sep 24 02:35:40 PM UTC 24 | 357643272 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.2365732708 | Sep 24 02:35:36 PM UTC 24 | Sep 24 02:35:40 PM UTC 24 | 62446779 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3387528690 | Sep 24 02:35:35 PM UTC 24 | Sep 24 02:35:40 PM UTC 24 | 41357807 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3798551479 | Sep 24 02:35:38 PM UTC 24 | Sep 24 02:35:40 PM UTC 24 | 20512199 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.2029759961 | Sep 24 02:35:38 PM UTC 24 | Sep 24 02:35:41 PM UTC 24 | 23377716 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.2670141445 | Sep 24 02:35:41 PM UTC 24 | Sep 24 02:35:44 PM UTC 24 | 13127783 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.2548297853 | Sep 24 02:35:41 PM UTC 24 | Sep 24 02:35:44 PM UTC 24 | 36591037 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2095084939 | Sep 24 02:35:40 PM UTC 24 | Sep 24 02:35:46 PM UTC 24 | 254050596 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.576570445 | Sep 24 02:35:41 PM UTC 24 | Sep 24 02:35:46 PM UTC 24 | 83496419 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.2002446442 | Sep 24 02:35:44 PM UTC 24 | Sep 24 02:35:46 PM UTC 24 | 37828076 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.305921646 | Sep 24 02:35:41 PM UTC 24 | Sep 24 02:35:47 PM UTC 24 | 154677276 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1957002636 | Sep 24 02:35:45 PM UTC 24 | Sep 24 02:35:47 PM UTC 24 | 40802575 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.2434004049 | Sep 24 02:35:30 PM UTC 24 | Sep 24 02:35:48 PM UTC 24 | 728128573 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.3980423784 | Sep 24 02:35:24 PM UTC 24 | Sep 24 02:35:48 PM UTC 24 | 842611589 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.4008863811 | Sep 24 02:35:45 PM UTC 24 | Sep 24 02:35:49 PM UTC 24 | 129090272 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.4073757241 | Sep 24 02:35:28 PM UTC 24 | Sep 24 02:35:49 PM UTC 24 | 1221281883 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3643152470 | Sep 24 02:35:23 PM UTC 24 | Sep 24 02:35:50 PM UTC 24 | 1257265971 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3844841018 | Sep 24 02:35:47 PM UTC 24 | Sep 24 02:35:51 PM UTC 24 | 142755785 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.933721647 | Sep 24 02:35:49 PM UTC 24 | Sep 24 02:35:51 PM UTC 24 | 54725593 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1072946947 | Sep 24 02:35:48 PM UTC 24 | Sep 24 02:35:52 PM UTC 24 | 23973985 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.3313987742 | Sep 24 02:35:23 PM UTC 24 | Sep 24 02:35:53 PM UTC 24 | 6008436775 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.3397808196 | Sep 24 02:35:48 PM UTC 24 | Sep 24 02:35:53 PM UTC 24 | 146501664 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.804313100 | Sep 24 02:35:35 PM UTC 24 | Sep 24 02:35:53 PM UTC 24 | 2204170048 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.1955298390 | Sep 24 02:35:51 PM UTC 24 | Sep 24 02:35:53 PM UTC 24 | 45748429 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1840447440 | Sep 24 02:35:50 PM UTC 24 | Sep 24 02:35:54 PM UTC 24 | 58528619 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.3177155542 | Sep 24 02:35:34 PM UTC 24 | Sep 24 02:35:54 PM UTC 24 | 621194085 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.1434512132 | Sep 24 02:35:51 PM UTC 24 | Sep 24 02:35:54 PM UTC 24 | 38531736 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.3573292346 | Sep 24 02:35:50 PM UTC 24 | Sep 24 02:35:55 PM UTC 24 | 434214441 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1111799515 | Sep 24 02:35:50 PM UTC 24 | Sep 24 02:35:55 PM UTC 24 | 414476885 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1817754703 | Sep 24 02:35:28 PM UTC 24 | Sep 24 02:35:55 PM UTC 24 | 368111575 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.2418103433 | Sep 24 02:35:50 PM UTC 24 | Sep 24 02:35:55 PM UTC 24 | 90413506 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.3899511534 | Sep 24 02:35:54 PM UTC 24 | Sep 24 02:35:56 PM UTC 24 | 13998572 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.2816448583 | Sep 24 02:35:41 PM UTC 24 | Sep 24 02:35:56 PM UTC 24 | 824742165 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.4278502213 | Sep 24 02:35:54 PM UTC 24 | Sep 24 02:35:57 PM UTC 24 | 47598116 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.2589603259 | Sep 24 02:35:56 PM UTC 24 | Sep 24 02:35:58 PM UTC 24 | 67638948 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.2203678799 | Sep 24 02:35:54 PM UTC 24 | Sep 24 02:35:58 PM UTC 24 | 440431132 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1814708250 | Sep 24 02:35:53 PM UTC 24 | Sep 24 02:35:58 PM UTC 24 | 84996311 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.468559567 | Sep 24 02:35:47 PM UTC 24 | Sep 24 02:35:58 PM UTC 24 | 989856446 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.1741704655 | Sep 24 02:35:39 PM UTC 24 | Sep 24 02:35:59 PM UTC 24 | 2180006941 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4022509322 | Sep 24 02:35:54 PM UTC 24 | Sep 24 02:36:00 PM UTC 24 | 987160733 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.290042773 | Sep 24 02:35:55 PM UTC 24 | Sep 24 02:36:01 PM UTC 24 | 60773120 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.2843753295 | Sep 24 02:35:58 PM UTC 24 | Sep 24 02:36:01 PM UTC 24 | 411323680 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3079995529 | Sep 24 02:35:55 PM UTC 24 | Sep 24 02:36:01 PM UTC 24 | 577451617 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.2431723190 | Sep 24 02:35:59 PM UTC 24 | Sep 24 02:36:02 PM UTC 24 | 29765296 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.1308102435 | Sep 24 02:35:49 PM UTC 24 | Sep 24 02:36:02 PM UTC 24 | 192023627 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.3245448797 | Sep 24 02:35:57 PM UTC 24 | Sep 24 02:36:02 PM UTC 24 | 366887620 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3463269434 | Sep 24 02:35:57 PM UTC 24 | Sep 24 02:36:02 PM UTC 24 | 143954347 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.3647800985 | Sep 24 02:35:59 PM UTC 24 | Sep 24 02:36:02 PM UTC 24 | 171972432 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.2238210719 | Sep 24 02:36:01 PM UTC 24 | Sep 24 02:36:03 PM UTC 24 | 16635382 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.362849051 | Sep 24 02:35:55 PM UTC 24 | Sep 24 02:36:04 PM UTC 24 | 211435425 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2989244485 | Sep 24 02:36:00 PM UTC 24 | Sep 24 02:36:04 PM UTC 24 | 414858396 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3457629366 | Sep 24 02:35:57 PM UTC 24 | Sep 24 02:36:04 PM UTC 24 | 64735803 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.1651147159 | Sep 24 02:36:04 PM UTC 24 | Sep 24 02:36:06 PM UTC 24 | 29191417 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2381790411 | Sep 24 02:35:33 PM UTC 24 | Sep 24 02:36:06 PM UTC 24 | 9487921565 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1374808217 | Sep 24 02:36:00 PM UTC 24 | Sep 24 02:36:06 PM UTC 24 | 149078231 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.1885813452 | Sep 24 02:36:04 PM UTC 24 | Sep 24 02:36:07 PM UTC 24 | 18001100 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3682752148 | Sep 24 02:36:04 PM UTC 24 | Sep 24 02:36:07 PM UTC 24 | 239011469 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.753266493 | Sep 24 02:36:26 PM UTC 24 | Sep 24 02:36:28 PM UTC 24 | 54270710 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1256166016 | Sep 24 02:36:01 PM UTC 24 | Sep 24 02:36:07 PM UTC 24 | 243666743 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.3705652296 | Sep 24 02:36:26 PM UTC 24 | Sep 24 02:36:28 PM UTC 24 | 14626653 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.806614506 | Sep 24 02:36:02 PM UTC 24 | Sep 24 02:36:07 PM UTC 24 | 67200503 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3239876841 | Sep 24 02:36:02 PM UTC 24 | Sep 24 02:36:07 PM UTC 24 | 46740090 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2919074303 | Sep 24 02:36:05 PM UTC 24 | Sep 24 02:36:08 PM UTC 24 | 11266284 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.151997770 | Sep 24 02:35:58 PM UTC 24 | Sep 24 02:36:08 PM UTC 24 | 1909489366 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.527423976 | Sep 24 02:36:02 PM UTC 24 | Sep 24 02:36:08 PM UTC 24 | 298968994 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.1745855069 | Sep 24 02:36:05 PM UTC 24 | Sep 24 02:36:09 PM UTC 24 | 46104018 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.330621289 | Sep 24 02:36:05 PM UTC 24 | Sep 24 02:36:09 PM UTC 24 | 325612455 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3439612488 | Sep 24 02:36:04 PM UTC 24 | Sep 24 02:36:09 PM UTC 24 | 59248055 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1364476932 | Sep 24 02:35:39 PM UTC 24 | Sep 24 02:36:10 PM UTC 24 | 3756473593 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.2699823550 | Sep 24 02:36:08 PM UTC 24 | Sep 24 02:36:10 PM UTC 24 | 12922950 ps | ||
| T1081 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1647810429 | Sep 24 02:36:05 PM UTC 24 | Sep 24 02:36:11 PM UTC 24 | 184034079 ps | ||
| T1082 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.4195424004 | Sep 24 02:36:09 PM UTC 24 | Sep 24 02:36:11 PM UTC 24 | 16073234 ps | ||
| T1083 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.218371280 | Sep 24 02:36:07 PM UTC 24 | Sep 24 02:36:12 PM UTC 24 | 243469063 ps | ||
| T1084 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.459716689 | Sep 24 02:36:02 PM UTC 24 | Sep 24 02:36:12 PM UTC 24 | 410668150 ps | ||
| T1085 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.1890962546 | Sep 24 02:36:08 PM UTC 24 | Sep 24 02:36:12 PM UTC 24 | 270107829 ps | ||
| T1086 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.4055177487 | Sep 24 02:36:09 PM UTC 24 | Sep 24 02:36:13 PM UTC 24 | 136694123 ps | ||
| T1087 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1237159076 | Sep 24 02:36:08 PM UTC 24 | Sep 24 02:36:13 PM UTC 24 | 142927700 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.3007286523 | Sep 24 02:36:07 PM UTC 24 | Sep 24 02:36:13 PM UTC 24 | 105154346 ps | ||
| T1088 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1398293138 | Sep 24 02:36:08 PM UTC 24 | Sep 24 02:36:13 PM UTC 24 | 185247357 ps | ||
| T1089 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.1985236507 | Sep 24 02:36:10 PM UTC 24 | Sep 24 02:36:14 PM UTC 24 | 37201199 ps | ||
| T1090 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2336203542 | Sep 24 02:36:12 PM UTC 24 | Sep 24 02:36:14 PM UTC 24 | 100248109 ps | ||
| T1091 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.3564449909 | Sep 24 02:36:10 PM UTC 24 | Sep 24 02:36:14 PM UTC 24 | 69987378 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.2593036353 | Sep 24 02:36:05 PM UTC 24 | Sep 24 02:36:15 PM UTC 24 | 342398595 ps | ||
| T1092 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2610533175 | Sep 24 02:36:10 PM UTC 24 | Sep 24 02:36:15 PM UTC 24 | 612475540 ps | ||
| T1093 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.527145722 | Sep 24 02:36:26 PM UTC 24 | Sep 24 02:36:28 PM UTC 24 | 17349133 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.1154229912 | Sep 24 02:35:54 PM UTC 24 | Sep 24 02:36:15 PM UTC 24 | 575907294 ps | ||
| T1094 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.3617570727 | Sep 24 02:36:14 PM UTC 24 | Sep 24 02:36:16 PM UTC 24 | 13610099 ps | ||
| T1095 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.527407143 | Sep 24 02:36:12 PM UTC 24 | Sep 24 02:36:16 PM UTC 24 | 206780262 ps | ||
| T1096 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3323972388 | Sep 24 02:36:13 PM UTC 24 | Sep 24 02:36:17 PM UTC 24 | 716985182 ps | ||
| T1097 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.3595463019 | Sep 24 02:36:14 PM UTC 24 | Sep 24 02:36:17 PM UTC 24 | 98752001 ps | ||
| T1098 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2374504840 | Sep 24 02:36:12 PM UTC 24 | Sep 24 02:36:17 PM UTC 24 | 148747260 ps | ||
| T1099 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.2383258909 | Sep 24 02:36:15 PM UTC 24 | Sep 24 02:36:18 PM UTC 24 | 14848086 ps | ||
| T1100 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3713787852 | Sep 24 02:36:10 PM UTC 24 | Sep 24 02:36:18 PM UTC 24 | 162959594 ps | ||
| T1101 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.3839347530 | Sep 24 02:36:13 PM UTC 24 | Sep 24 02:36:18 PM UTC 24 | 97773270 ps | ||
| T1102 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3513749424 | Sep 24 02:36:14 PM UTC 24 | Sep 24 02:36:18 PM UTC 24 | 83306842 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.1150079499 | Sep 24 02:36:08 PM UTC 24 | Sep 24 02:36:19 PM UTC 24 | 625611986 ps | ||
| T1103 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.2387553185 | Sep 24 02:36:17 PM UTC 24 | Sep 24 02:36:19 PM UTC 24 | 30099313 ps | ||
| T1104 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.188371999 | Sep 24 02:35:56 PM UTC 24 | Sep 24 02:36:20 PM UTC 24 | 13282927633 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.926515860 | Sep 24 02:36:01 PM UTC 24 | Sep 24 02:36:20 PM UTC 24 | 1186377793 ps | ||
| T1105 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.3453724351 | Sep 24 02:36:15 PM UTC 24 | Sep 24 02:36:20 PM UTC 24 | 92329696 ps | ||
| T1106 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.2568779206 | Sep 24 02:36:17 PM UTC 24 | Sep 24 02:36:20 PM UTC 24 | 36137398 ps | ||
| T1107 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1487092841 | Sep 24 02:36:15 PM UTC 24 | Sep 24 02:36:20 PM UTC 24 | 420418224 ps | ||
| T1108 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2456935262 | Sep 24 02:36:15 PM UTC 24 | Sep 24 02:36:21 PM UTC 24 | 227357201 ps | ||
| T1109 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.2060925432 | Sep 24 02:36:19 PM UTC 24 | Sep 24 02:36:21 PM UTC 24 | 12111263 ps | ||
| T1110 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3064966023 | Sep 24 02:35:46 PM UTC 24 | Sep 24 02:36:21 PM UTC 24 | 2084734843 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.2159280307 | Sep 24 02:35:51 PM UTC 24 | Sep 24 02:36:22 PM UTC 24 | 1015740236 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.956077775 | Sep 24 02:36:15 PM UTC 24 | Sep 24 02:36:22 PM UTC 24 | 697651010 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.4192356358 | Sep 24 02:36:13 PM UTC 24 | Sep 24 02:36:22 PM UTC 24 | 214987173 ps | ||
| T1111 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.4272502218 | Sep 24 02:36:26 PM UTC 24 | Sep 24 02:36:28 PM UTC 24 | 34988013 ps | ||
| T1112 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.225214112 | Sep 24 02:36:19 PM UTC 24 | Sep 24 02:36:22 PM UTC 24 | 186358761 ps | ||
| T1113 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.237494544 | Sep 24 02:36:20 PM UTC 24 | Sep 24 02:36:22 PM UTC 24 | 14726586 ps | ||
| T1114 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.1068908565 | Sep 24 02:36:20 PM UTC 24 | Sep 24 02:36:23 PM UTC 24 | 36500909 ps | ||
| T1115 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.2030323701 | Sep 24 02:36:17 PM UTC 24 | Sep 24 02:36:23 PM UTC 24 | 257291680 ps | ||
| T1116 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1306851610 | Sep 24 02:36:20 PM UTC 24 | Sep 24 02:36:23 PM UTC 24 | 161057978 ps | ||
| T1117 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3536438835 | Sep 24 02:36:19 PM UTC 24 | Sep 24 02:36:23 PM UTC 24 | 532541372 ps | ||
| T1118 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4043936497 | Sep 24 02:36:17 PM UTC 24 | Sep 24 02:36:24 PM UTC 24 | 61692746 ps | ||
| T1119 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3829113742 | Sep 24 02:36:20 PM UTC 24 | Sep 24 02:36:24 PM UTC 24 | 124990934 ps | ||
| T1120 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.2203327725 | Sep 24 02:36:22 PM UTC 24 | Sep 24 02:36:24 PM UTC 24 | 11461481 ps | ||
| T1121 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1385305631 | Sep 24 02:36:22 PM UTC 24 | Sep 24 02:36:24 PM UTC 24 | 15966329 ps | ||
| T1122 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.3823138561 | Sep 24 02:36:22 PM UTC 24 | Sep 24 02:36:24 PM UTC 24 | 30814800 ps | ||
| T1123 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.2790782557 | Sep 24 02:36:22 PM UTC 24 | Sep 24 02:36:24 PM UTC 24 | 15994461 ps | ||
| T1124 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.745592111 | Sep 24 02:36:22 PM UTC 24 | Sep 24 02:36:24 PM UTC 24 | 207187902 ps | ||
| T1125 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.1581615140 | Sep 24 02:36:22 PM UTC 24 | Sep 24 02:36:24 PM UTC 24 | 33589055 ps | ||
| T1126 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.3189400783 | Sep 24 02:36:22 PM UTC 24 | Sep 24 02:36:24 PM UTC 24 | 26509821 ps | ||
| T1127 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.3279893062 | Sep 24 02:36:19 PM UTC 24 | Sep 24 02:36:25 PM UTC 24 | 226143625 ps | ||
| T1128 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.47085853 | Sep 24 02:36:26 PM UTC 24 | Sep 24 02:36:28 PM UTC 24 | 156296128 ps | ||
| T1129 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.1748616330 | Sep 24 02:36:26 PM UTC 24 | Sep 24 02:36:28 PM UTC 24 | 20527708 ps | ||
| T1130 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.3322829378 | Sep 24 02:36:26 PM UTC 24 | Sep 24 02:36:28 PM UTC 24 | 31277500 ps | ||
| T1131 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.2576555820 | Sep 24 02:36:26 PM UTC 24 | Sep 24 02:36:28 PM UTC 24 | 16945623 ps | ||
| T1132 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.208755898 | Sep 24 02:36:26 PM UTC 24 | Sep 24 02:36:28 PM UTC 24 | 18585817 ps | ||
| T1133 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.3156181217 | Sep 24 02:36:26 PM UTC 24 | Sep 24 02:36:28 PM UTC 24 | 29838342 ps | ||
| T1134 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.2103647635 | Sep 24 02:36:26 PM UTC 24 | Sep 24 02:36:28 PM UTC 24 | 34325599 ps | ||
| T1135 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.1280602575 | Sep 24 02:36:26 PM UTC 24 | Sep 24 02:36:28 PM UTC 24 | 27450857 ps | ||
| T1136 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.467248843 | Sep 24 02:36:26 PM UTC 24 | Sep 24 02:36:28 PM UTC 24 | 38483929 ps | ||
| T1137 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.990893627 | Sep 24 02:36:26 PM UTC 24 | Sep 24 02:36:28 PM UTC 24 | 67742464 ps | ||
| T1138 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.797114619 | Sep 24 02:36:26 PM UTC 24 | Sep 24 02:36:28 PM UTC 24 | 15211577 ps | ||
| T1139 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.1431122820 | Sep 24 02:36:26 PM UTC 24 | Sep 24 02:36:28 PM UTC 24 | 14788303 ps | ||
| T1140 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.1438600896 | Sep 24 02:36:26 PM UTC 24 | Sep 24 02:36:28 PM UTC 24 | 16748406 ps | ||
| T1141 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3633693807 | Sep 24 02:36:26 PM UTC 24 | Sep 24 02:36:28 PM UTC 24 | 36319966 ps | ||
| T1142 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.545974395 | Sep 24 02:36:28 PM UTC 24 | Sep 24 02:36:30 PM UTC 24 | 13073378 ps | ||
| T1143 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.2800851236 | Sep 24 02:36:28 PM UTC 24 | Sep 24 02:36:30 PM UTC 24 | 27992928 ps | ||
| T1144 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.2707895731 | Sep 24 02:36:09 PM UTC 24 | Sep 24 02:36:31 PM UTC 24 | 305813709 ps | ||
| T1145 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.4060078059 | Sep 24 02:36:17 PM UTC 24 | Sep 24 02:36:33 PM UTC 24 | 3304856208 ps | ||
| T1146 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.3867128077 | Sep 24 02:36:31 PM UTC 24 | Sep 24 02:36:33 PM UTC 24 | 56949616 ps | ||
| T1147 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.1547183684 | Sep 24 02:36:31 PM UTC 24 | Sep 24 02:36:33 PM UTC 24 | 13568871 ps | ||
| T1148 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.387671346 | Sep 24 02:36:19 PM UTC 24 | Sep 24 02:36:34 PM UTC 24 | 2242045793 ps | ||
| T1149 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.4225925311 | Sep 24 02:36:12 PM UTC 24 | Sep 24 02:36:34 PM UTC 24 | 3205897232 ps | ||
| T1150 | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.1766182309 | Sep 24 02:36:15 PM UTC 24 | Sep 24 02:36:36 PM UTC 24 | 312876216 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.4250371315 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 130487182 ps |
| CPU time | 5.76 seconds |
| Started | Sep 24 02:12:08 PM UTC 24 |
| Finished | Sep 24 02:12:15 PM UTC 24 |
| Peak memory | 245340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250371315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4250371315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.3164024906 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3437254486 ps |
| CPU time | 47.5 seconds |
| Started | Sep 24 02:12:13 PM UTC 24 |
| Finished | Sep 24 02:13:02 PM UTC 24 |
| Peak memory | 263976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164024906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.3164024906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.673026461 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 15727254928 ps |
| CPU time | 111.19 seconds |
| Started | Sep 24 02:12:35 PM UTC 24 |
| Finished | Sep 24 02:14:28 PM UTC 24 |
| Peak memory | 268140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673026461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.673026461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.4189610346 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 633995626 ps |
| CPU time | 10.66 seconds |
| Started | Sep 24 02:12:08 PM UTC 24 |
| Finished | Sep 24 02:12:20 PM UTC 24 |
| Peak memory | 235104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189610346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.4189610346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.2562165640 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 25743200069 ps |
| CPU time | 302.31 seconds |
| Started | Sep 24 02:13:35 PM UTC 24 |
| Finished | Sep 24 02:18:42 PM UTC 24 |
| Peak memory | 278320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562165640 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.2562165640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.305921646 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 154677276 ps |
| CPU time | 4.37 seconds |
| Started | Sep 24 02:35:41 PM UTC 24 |
| Finished | Sep 24 02:35:47 PM UTC 24 |
| Peak memory | 227064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=305921646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.305921646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.2120572700 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 31880727211 ps |
| CPU time | 175.91 seconds |
| Started | Sep 24 02:15:53 PM UTC 24 |
| Finished | Sep 24 02:18:52 PM UTC 24 |
| Peak memory | 261928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120572700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2120572700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.3407885309 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 767481213 ps |
| CPU time | 14.9 seconds |
| Started | Sep 24 02:12:21 PM UTC 24 |
| Finished | Sep 24 02:12:38 PM UTC 24 |
| Peak memory | 227740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407885309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3407885309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.3853631033 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3581338295 ps |
| CPU time | 116.67 seconds |
| Started | Sep 24 02:12:16 PM UTC 24 |
| Finished | Sep 24 02:14:15 PM UTC 24 |
| Peak memory | 268076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853631033 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.3853631033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.3783386345 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 45916437 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 02:12:07 PM UTC 24 |
| Finished | Sep 24 02:12:09 PM UTC 24 |
| Peak memory | 226260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783386345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3783386345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2109679918 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 19256555889 ps |
| CPU time | 205.92 seconds |
| Started | Sep 24 02:13:01 PM UTC 24 |
| Finished | Sep 24 02:16:31 PM UTC 24 |
| Peak memory | 278380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109679918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.2109679918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.224122599 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 105174065671 ps |
| CPU time | 304.31 seconds |
| Started | Sep 24 02:15:55 PM UTC 24 |
| Finished | Sep 24 02:21:04 PM UTC 24 |
| Peak memory | 280360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224122599 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.224122599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.223323940 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 214548754 ps |
| CPU time | 1.64 seconds |
| Started | Sep 24 02:12:16 PM UTC 24 |
| Finished | Sep 24 02:12:19 PM UTC 24 |
| Peak memory | 257644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223323940 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.223323940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.1691969473 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 9032174509 ps |
| CPU time | 50.22 seconds |
| Started | Sep 24 02:15:22 PM UTC 24 |
| Finished | Sep 24 02:16:14 PM UTC 24 |
| Peak memory | 268012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691969473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1691969473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2139963397 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 18197450386 ps |
| CPU time | 161.66 seconds |
| Started | Sep 24 02:20:29 PM UTC 24 |
| Finished | Sep 24 02:23:14 PM UTC 24 |
| Peak memory | 282408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139963397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.2139963397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.2031466120 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 31567935027 ps |
| CPU time | 386.05 seconds |
| Started | Sep 24 02:19:40 PM UTC 24 |
| Finished | Sep 24 02:26:11 PM UTC 24 |
| Peak memory | 280364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031466120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2031466120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.3980423784 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 842611589 ps |
| CPU time | 22.49 seconds |
| Started | Sep 24 02:35:24 PM UTC 24 |
| Finished | Sep 24 02:35:48 PM UTC 24 |
| Peak memory | 224960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980423784 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.3980423784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.771522726 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 22190987995 ps |
| CPU time | 121.06 seconds |
| Started | Sep 24 02:12:37 PM UTC 24 |
| Finished | Sep 24 02:14:40 PM UTC 24 |
| Peak memory | 284524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771522726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.771522726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_all.1417687835 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 38782564564 ps |
| CPU time | 130.29 seconds |
| Started | Sep 24 02:24:34 PM UTC 24 |
| Finished | Sep 24 02:26:47 PM UTC 24 |
| Peak memory | 268016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417687835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1417687835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/23.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.536008996 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 281455555 ps |
| CPU time | 2.73 seconds |
| Started | Sep 24 02:35:22 PM UTC 24 |
| Finished | Sep 24 02:35:26 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536008996 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.536008996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.1186895989 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2893507899 ps |
| CPU time | 101.86 seconds |
| Started | Sep 24 02:12:32 PM UTC 24 |
| Finished | Sep 24 02:14:17 PM UTC 24 |
| Peak memory | 261932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186895989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.1186895989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.557857529 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 53903305947 ps |
| CPU time | 157.98 seconds |
| Started | Sep 24 02:15:24 PM UTC 24 |
| Finished | Sep 24 02:18:05 PM UTC 24 |
| Peak memory | 278380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557857529 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.557857529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.2203678799 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 440431132 ps |
| CPU time | 3.03 seconds |
| Started | Sep 24 02:35:54 PM UTC 24 |
| Finished | Sep 24 02:35:58 PM UTC 24 |
| Peak memory | 227068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203678799 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2203678799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.336587096 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 41420515326 ps |
| CPU time | 275.88 seconds |
| Started | Sep 24 02:20:23 PM UTC 24 |
| Finished | Sep 24 02:25:03 PM UTC 24 |
| Peak memory | 278248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336587096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.336587096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.3289725805 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 33193288 ps |
| CPU time | 1.72 seconds |
| Started | Sep 24 02:12:06 PM UTC 24 |
| Finished | Sep 24 02:12:08 PM UTC 24 |
| Peak memory | 228240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289725805 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_parity.3289725805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.4165418681 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4712784210 ps |
| CPU time | 132.06 seconds |
| Started | Sep 24 02:17:31 PM UTC 24 |
| Finished | Sep 24 02:19:45 PM UTC 24 |
| Peak memory | 278312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165418681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.4165418681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.940810141 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 6359242632 ps |
| CPU time | 106.91 seconds |
| Started | Sep 24 02:26:02 PM UTC 24 |
| Finished | Sep 24 02:27:52 PM UTC 24 |
| Peak memory | 284584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940810141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.940810141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3662432064 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 6629240851 ps |
| CPU time | 35.22 seconds |
| Started | Sep 24 02:12:07 PM UTC 24 |
| Finished | Sep 24 02:12:44 PM UTC 24 |
| Peak memory | 227760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662432064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3662432064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_all.2813489989 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 109120639435 ps |
| CPU time | 405.99 seconds |
| Started | Sep 24 02:20:26 PM UTC 24 |
| Finished | Sep 24 02:27:17 PM UTC 24 |
| Peak memory | 261872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813489989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2813489989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.416530042 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 52863447140 ps |
| CPU time | 166.34 seconds |
| Started | Sep 24 02:17:33 PM UTC 24 |
| Finished | Sep 24 02:20:22 PM UTC 24 |
| Peak memory | 266020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416530042 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.416530042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.1348555190 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 8160762765 ps |
| CPU time | 57.58 seconds |
| Started | Sep 24 02:19:00 PM UTC 24 |
| Finished | Sep 24 02:19:59 PM UTC 24 |
| Peak memory | 268064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348555190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1348555190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.628342842 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 10845402261 ps |
| CPU time | 63.64 seconds |
| Started | Sep 24 02:24:27 PM UTC 24 |
| Finished | Sep 24 02:25:33 PM UTC 24 |
| Peak memory | 278240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628342842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.628342842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.2488132688 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 81886677473 ps |
| CPU time | 805.24 seconds |
| Started | Sep 24 02:34:45 PM UTC 24 |
| Finished | Sep 24 02:48:20 PM UTC 24 |
| Peak memory | 311072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488132688 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.2488132688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/47.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.1469346488 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 44843537 ps |
| CPU time | 0.99 seconds |
| Started | Sep 24 02:12:16 PM UTC 24 |
| Finished | Sep 24 02:12:18 PM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469346488 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1469346488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.4265748148 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 8887441765 ps |
| CPU time | 155.29 seconds |
| Started | Sep 24 02:20:33 PM UTC 24 |
| Finished | Sep 24 02:23:11 PM UTC 24 |
| Peak memory | 268132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265748148 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.4265748148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.2693671184 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1026193173 ps |
| CPU time | 10.85 seconds |
| Started | Sep 24 02:12:11 PM UTC 24 |
| Finished | Sep 24 02:12:23 PM UTC 24 |
| Peak memory | 245412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693671184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2693671184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.4076922613 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 220126008617 ps |
| CPU time | 458.79 seconds |
| Started | Sep 24 02:23:47 PM UTC 24 |
| Finished | Sep 24 02:31:32 PM UTC 24 |
| Peak memory | 280300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076922613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.4076922613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.587073495 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 193333274 ps |
| CPU time | 5.61 seconds |
| Started | Sep 24 02:35:24 PM UTC 24 |
| Finished | Sep 24 02:35:31 PM UTC 24 |
| Peak memory | 225156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587073495 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.587073495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.2482729719 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 2161950981 ps |
| CPU time | 44.98 seconds |
| Started | Sep 24 02:17:00 PM UTC 24 |
| Finished | Sep 24 02:17:47 PM UTC 24 |
| Peak memory | 227804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482729719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2482729719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.639495889 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 263295633526 ps |
| CPU time | 504.51 seconds |
| Started | Sep 24 02:20:00 PM UTC 24 |
| Finished | Sep 24 02:28:31 PM UTC 24 |
| Peak memory | 278372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639495889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.639495889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.209687928 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 47525721398 ps |
| CPU time | 228.54 seconds |
| Started | Sep 24 02:25:21 PM UTC 24 |
| Finished | Sep 24 02:29:14 PM UTC 24 |
| Peak memory | 263968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209687928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.209687928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/24.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.2460212072 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 271262694 ps |
| CPU time | 13.16 seconds |
| Started | Sep 24 02:25:13 PM UTC 24 |
| Finished | Sep 24 02:25:28 PM UTC 24 |
| Peak memory | 245408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460212072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2460212072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/24.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.771238255 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 16016077750 ps |
| CPU time | 135.89 seconds |
| Started | Sep 24 02:17:24 PM UTC 24 |
| Finished | Sep 24 02:19:43 PM UTC 24 |
| Peak memory | 268128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771238255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.771238255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.3202509578 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 256436841510 ps |
| CPU time | 534.83 seconds |
| Started | Sep 24 02:18:20 PM UTC 24 |
| Finished | Sep 24 02:27:22 PM UTC 24 |
| Peak memory | 278432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202509578 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.3202509578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.2692160903 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 2852703730 ps |
| CPU time | 32.57 seconds |
| Started | Sep 24 02:20:00 PM UTC 24 |
| Finished | Sep 24 02:20:34 PM UTC 24 |
| Peak memory | 245352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692160903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2692160903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.2244891717 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 30742619382 ps |
| CPU time | 231.46 seconds |
| Started | Sep 24 02:22:03 PM UTC 24 |
| Finished | Sep 24 02:25:58 PM UTC 24 |
| Peak memory | 268192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244891717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2244891717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_cfg_cmd.1019964555 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 118214882 ps |
| CPU time | 3.13 seconds |
| Started | Sep 24 02:26:54 PM UTC 24 |
| Finished | Sep 24 02:26:58 PM UTC 24 |
| Peak memory | 235056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019964555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1019964555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/27.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.311213277 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 46254131695 ps |
| CPU time | 31.73 seconds |
| Started | Sep 24 02:12:11 PM UTC 24 |
| Finished | Sep 24 02:12:44 PM UTC 24 |
| Peak memory | 229880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311213277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.311213277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.1990208643 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 591794214 ps |
| CPU time | 3.6 seconds |
| Started | Sep 24 02:12:07 PM UTC 24 |
| Finished | Sep 24 02:12:12 PM UTC 24 |
| Peak memory | 245356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990208643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.1990208643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.4225925311 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 3205897232 ps |
| CPU time | 21.33 seconds |
| Started | Sep 24 02:36:12 PM UTC 24 |
| Finished | Sep 24 02:36:34 PM UTC 24 |
| Peak memory | 225096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225925311 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.4225925311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode.475905791 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 701391931 ps |
| CPU time | 13.13 seconds |
| Started | Sep 24 02:19:32 PM UTC 24 |
| Finished | Sep 24 02:19:47 PM UTC 24 |
| Peak memory | 245356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475905791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.475905791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.881424119 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 109231050196 ps |
| CPU time | 392.99 seconds |
| Started | Sep 24 02:19:35 PM UTC 24 |
| Finished | Sep 24 02:26:13 PM UTC 24 |
| Peak memory | 278248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881424119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.881424119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.527423976 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 298968994 ps |
| CPU time | 4.33 seconds |
| Started | Sep 24 02:36:02 PM UTC 24 |
| Finished | Sep 24 02:36:08 PM UTC 24 |
| Peak memory | 225272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527423976 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.527423976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2771231898 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 36437701 ps |
| CPU time | 1.76 seconds |
| Started | Sep 24 02:35:21 PM UTC 24 |
| Finished | Sep 24 02:35:23 PM UTC 24 |
| Peak memory | 226056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771231898 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.2771231898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.502682723 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 147124497 ps |
| CPU time | 2.15 seconds |
| Started | Sep 24 02:35:27 PM UTC 24 |
| Finished | Sep 24 02:35:30 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502682723 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.502682723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.3313987742 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 6008436775 ps |
| CPU time | 27.85 seconds |
| Started | Sep 24 02:35:23 PM UTC 24 |
| Finished | Sep 24 02:35:53 PM UTC 24 |
| Peak memory | 225120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313987742 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.3313987742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3643152470 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 1257265971 ps |
| CPU time | 25.58 seconds |
| Started | Sep 24 02:35:23 PM UTC 24 |
| Finished | Sep 24 02:35:50 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643152470 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.3643152470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1841640328 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 78592748 ps |
| CPU time | 4.49 seconds |
| Started | Sep 24 02:35:24 PM UTC 24 |
| Finished | Sep 24 02:35:30 PM UTC 24 |
| Peak memory | 227328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1841640328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1841640328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.404190977 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 11313747 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 02:35:14 PM UTC 24 |
| Finished | Sep 24 02:35:17 PM UTC 24 |
| Peak memory | 212632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404190977 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.404190977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.2954839751 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 43650465 ps |
| CPU time | 3.07 seconds |
| Started | Sep 24 02:35:20 PM UTC 24 |
| Finished | Sep 24 02:35:24 PM UTC 24 |
| Peak memory | 225012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954839751 -assert nopostp roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.2954839751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2161146104 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 12863838 ps |
| CPU time | 1.08 seconds |
| Started | Sep 24 02:35:18 PM UTC 24 |
| Finished | Sep 24 02:35:20 PM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161146104 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.2161146104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4072709845 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 116126730 ps |
| CPU time | 2.65 seconds |
| Started | Sep 24 02:35:23 PM UTC 24 |
| Finished | Sep 24 02:35:27 PM UTC 24 |
| Peak memory | 214708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072709845 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstanding.4072709845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.2612158535 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 65935352 ps |
| CPU time | 6.49 seconds |
| Started | Sep 24 02:35:11 PM UTC 24 |
| Finished | Sep 24 02:35:19 PM UTC 24 |
| Peak memory | 225148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612158535 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2612158535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3382288334 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 889394151 ps |
| CPU time | 8.23 seconds |
| Started | Sep 24 02:35:13 PM UTC 24 |
| Finished | Sep 24 02:35:23 PM UTC 24 |
| Peak memory | 224876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382288334 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.3382288334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.4073757241 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 1221281883 ps |
| CPU time | 20.14 seconds |
| Started | Sep 24 02:35:28 PM UTC 24 |
| Finished | Sep 24 02:35:49 PM UTC 24 |
| Peak memory | 214700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073757241 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.4073757241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1817754703 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 368111575 ps |
| CPU time | 25.9 seconds |
| Started | Sep 24 02:35:28 PM UTC 24 |
| Finished | Sep 24 02:35:55 PM UTC 24 |
| Peak memory | 214960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817754703 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.1817754703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1018614389 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 184866370 ps |
| CPU time | 4.37 seconds |
| Started | Sep 24 02:35:29 PM UTC 24 |
| Finished | Sep 24 02:35:35 PM UTC 24 |
| Peak memory | 227052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1018614389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1018614389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.1241904997 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 104459300 ps |
| CPU time | 2.71 seconds |
| Started | Sep 24 02:35:28 PM UTC 24 |
| Finished | Sep 24 02:35:32 PM UTC 24 |
| Peak memory | 224932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241904997 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1241904997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3339526805 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 17304721 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 02:35:24 PM UTC 24 |
| Finished | Sep 24 02:35:27 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339526805 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3339526805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1403226774 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 793401992 ps |
| CPU time | 3.32 seconds |
| Started | Sep 24 02:35:27 PM UTC 24 |
| Finished | Sep 24 02:35:31 PM UTC 24 |
| Peak memory | 225076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403226774 -assert nopostp roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.1403226774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1951533152 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 19311555 ps |
| CPU time | 1.02 seconds |
| Started | Sep 24 02:35:27 PM UTC 24 |
| Finished | Sep 24 02:35:29 PM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951533152 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.1951533152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.762286245 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 38346556 ps |
| CPU time | 2.82 seconds |
| Started | Sep 24 02:35:28 PM UTC 24 |
| Finished | Sep 24 02:35:32 PM UTC 24 |
| Peak memory | 224984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762286245 -assert nopost proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstanding.762286245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.806614506 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 67200503 ps |
| CPU time | 3.86 seconds |
| Started | Sep 24 02:36:02 PM UTC 24 |
| Finished | Sep 24 02:36:07 PM UTC 24 |
| Peak memory | 227336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=806614506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.806614506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.3836488767 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 23558529 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 02:36:02 PM UTC 24 |
| Finished | Sep 24 02:36:05 PM UTC 24 |
| Peak memory | 215592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836488767 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.3836488767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.2238210719 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 16635382 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 02:36:01 PM UTC 24 |
| Finished | Sep 24 02:36:03 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238210719 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.2238210719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3239876841 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 46740090 ps |
| CPU time | 3.96 seconds |
| Started | Sep 24 02:36:02 PM UTC 24 |
| Finished | Sep 24 02:36:07 PM UTC 24 |
| Peak memory | 224888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239876841 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstanding.3239876841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1256166016 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 243666743 ps |
| CPU time | 5.08 seconds |
| Started | Sep 24 02:36:01 PM UTC 24 |
| Finished | Sep 24 02:36:07 PM UTC 24 |
| Peak memory | 227160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256166016 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.1256166016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.926515860 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1186377793 ps |
| CPU time | 17.79 seconds |
| Started | Sep 24 02:36:01 PM UTC 24 |
| Finished | Sep 24 02:36:20 PM UTC 24 |
| Peak memory | 225084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926515860 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.926515860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3439612488 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 59248055 ps |
| CPU time | 4.47 seconds |
| Started | Sep 24 02:36:04 PM UTC 24 |
| Finished | Sep 24 02:36:09 PM UTC 24 |
| Peak memory | 229104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3439612488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3439612488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.1885813452 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 18001100 ps |
| CPU time | 1.81 seconds |
| Started | Sep 24 02:36:04 PM UTC 24 |
| Finished | Sep 24 02:36:07 PM UTC 24 |
| Peak memory | 223784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885813452 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.1885813452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.1651147159 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 29191417 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 02:36:04 PM UTC 24 |
| Finished | Sep 24 02:36:06 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651147159 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.1651147159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3682752148 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 239011469 ps |
| CPU time | 2.12 seconds |
| Started | Sep 24 02:36:04 PM UTC 24 |
| Finished | Sep 24 02:36:07 PM UTC 24 |
| Peak memory | 224860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682752148 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstanding.3682752148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.459716689 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 410668150 ps |
| CPU time | 8.69 seconds |
| Started | Sep 24 02:36:02 PM UTC 24 |
| Finished | Sep 24 02:36:12 PM UTC 24 |
| Peak memory | 224952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459716689 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.459716689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.218371280 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 243469063 ps |
| CPU time | 4.18 seconds |
| Started | Sep 24 02:36:07 PM UTC 24 |
| Finished | Sep 24 02:36:12 PM UTC 24 |
| Peak memory | 227064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=218371280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.218371280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.1745855069 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 46104018 ps |
| CPU time | 2.27 seconds |
| Started | Sep 24 02:36:05 PM UTC 24 |
| Finished | Sep 24 02:36:09 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745855069 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.1745855069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2919074303 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 11266284 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 02:36:05 PM UTC 24 |
| Finished | Sep 24 02:36:08 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919074303 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.2919074303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1647810429 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 184034079 ps |
| CPU time | 4.37 seconds |
| Started | Sep 24 02:36:05 PM UTC 24 |
| Finished | Sep 24 02:36:11 PM UTC 24 |
| Peak memory | 224932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647810429 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstanding.1647810429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.330621289 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 325612455 ps |
| CPU time | 3.2 seconds |
| Started | Sep 24 02:36:05 PM UTC 24 |
| Finished | Sep 24 02:36:09 PM UTC 24 |
| Peak memory | 224972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330621289 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.330621289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.2593036353 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 342398595 ps |
| CPU time | 8.34 seconds |
| Started | Sep 24 02:36:05 PM UTC 24 |
| Finished | Sep 24 02:36:15 PM UTC 24 |
| Peak memory | 227072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593036353 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.2593036353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1398293138 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 185247357 ps |
| CPU time | 3.77 seconds |
| Started | Sep 24 02:36:08 PM UTC 24 |
| Finished | Sep 24 02:36:13 PM UTC 24 |
| Peak memory | 227048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1398293138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1398293138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.1890962546 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 270107829 ps |
| CPU time | 3.03 seconds |
| Started | Sep 24 02:36:08 PM UTC 24 |
| Finished | Sep 24 02:36:12 PM UTC 24 |
| Peak memory | 214392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890962546 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.1890962546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.2699823550 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 12922950 ps |
| CPU time | 1.04 seconds |
| Started | Sep 24 02:36:08 PM UTC 24 |
| Finished | Sep 24 02:36:10 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699823550 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.2699823550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1237159076 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 142927700 ps |
| CPU time | 3.3 seconds |
| Started | Sep 24 02:36:08 PM UTC 24 |
| Finished | Sep 24 02:36:13 PM UTC 24 |
| Peak memory | 224924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237159076 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstanding.1237159076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.3007286523 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 105154346 ps |
| CPU time | 4.94 seconds |
| Started | Sep 24 02:36:07 PM UTC 24 |
| Finished | Sep 24 02:36:13 PM UTC 24 |
| Peak memory | 225080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007286523 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.3007286523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.1150079499 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 625611986 ps |
| CPU time | 9.72 seconds |
| Started | Sep 24 02:36:08 PM UTC 24 |
| Finished | Sep 24 02:36:19 PM UTC 24 |
| Peak memory | 227060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150079499 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.1150079499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2610533175 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 612475540 ps |
| CPU time | 3.81 seconds |
| Started | Sep 24 02:36:10 PM UTC 24 |
| Finished | Sep 24 02:36:15 PM UTC 24 |
| Peak memory | 227320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2610533175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2610533175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.3564449909 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 69987378 ps |
| CPU time | 2.97 seconds |
| Started | Sep 24 02:36:10 PM UTC 24 |
| Finished | Sep 24 02:36:14 PM UTC 24 |
| Peak memory | 214704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564449909 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.3564449909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.4195424004 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 16073234 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 02:36:09 PM UTC 24 |
| Finished | Sep 24 02:36:11 PM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195424004 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.4195424004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3713787852 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 162959594 ps |
| CPU time | 6.55 seconds |
| Started | Sep 24 02:36:10 PM UTC 24 |
| Finished | Sep 24 02:36:18 PM UTC 24 |
| Peak memory | 225088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713787852 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstanding.3713787852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.4055177487 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 136694123 ps |
| CPU time | 2.96 seconds |
| Started | Sep 24 02:36:09 PM UTC 24 |
| Finished | Sep 24 02:36:13 PM UTC 24 |
| Peak memory | 225328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055177487 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.4055177487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.2707895731 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 305813709 ps |
| CPU time | 20.85 seconds |
| Started | Sep 24 02:36:09 PM UTC 24 |
| Finished | Sep 24 02:36:31 PM UTC 24 |
| Peak memory | 225000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707895731 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.2707895731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3323972388 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 716985182 ps |
| CPU time | 2.03 seconds |
| Started | Sep 24 02:36:13 PM UTC 24 |
| Finished | Sep 24 02:36:17 PM UTC 24 |
| Peak memory | 225276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3323972388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3323972388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.527407143 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 206780262 ps |
| CPU time | 3.42 seconds |
| Started | Sep 24 02:36:12 PM UTC 24 |
| Finished | Sep 24 02:36:16 PM UTC 24 |
| Peak memory | 214892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527407143 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.527407143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2336203542 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 100248109 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 02:36:12 PM UTC 24 |
| Finished | Sep 24 02:36:14 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336203542 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.2336203542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2374504840 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 148747260 ps |
| CPU time | 4 seconds |
| Started | Sep 24 02:36:12 PM UTC 24 |
| Finished | Sep 24 02:36:17 PM UTC 24 |
| Peak memory | 225172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374504840 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstanding.2374504840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.1985236507 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 37201199 ps |
| CPU time | 2.45 seconds |
| Started | Sep 24 02:36:10 PM UTC 24 |
| Finished | Sep 24 02:36:14 PM UTC 24 |
| Peak memory | 227196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985236507 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.1985236507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1487092841 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 420418224 ps |
| CPU time | 4.12 seconds |
| Started | Sep 24 02:36:15 PM UTC 24 |
| Finished | Sep 24 02:36:20 PM UTC 24 |
| Peak memory | 227124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1487092841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1487092841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.3595463019 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 98752001 ps |
| CPU time | 2.12 seconds |
| Started | Sep 24 02:36:14 PM UTC 24 |
| Finished | Sep 24 02:36:17 PM UTC 24 |
| Peak memory | 214716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595463019 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.3595463019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.3617570727 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 13610099 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 02:36:14 PM UTC 24 |
| Finished | Sep 24 02:36:16 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617570727 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.3617570727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3513749424 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 83306842 ps |
| CPU time | 3.58 seconds |
| Started | Sep 24 02:36:14 PM UTC 24 |
| Finished | Sep 24 02:36:18 PM UTC 24 |
| Peak memory | 225004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513749424 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstanding.3513749424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.3839347530 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 97773270 ps |
| CPU time | 3.67 seconds |
| Started | Sep 24 02:36:13 PM UTC 24 |
| Finished | Sep 24 02:36:18 PM UTC 24 |
| Peak memory | 225208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839347530 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.3839347530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.4192356358 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 214987173 ps |
| CPU time | 7.22 seconds |
| Started | Sep 24 02:36:13 PM UTC 24 |
| Finished | Sep 24 02:36:22 PM UTC 24 |
| Peak memory | 227076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192356358 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.4192356358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4043936497 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 61692746 ps |
| CPU time | 5.71 seconds |
| Started | Sep 24 02:36:17 PM UTC 24 |
| Finished | Sep 24 02:36:24 PM UTC 24 |
| Peak memory | 229240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4043936497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.4043936497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.3453724351 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 92329696 ps |
| CPU time | 3.76 seconds |
| Started | Sep 24 02:36:15 PM UTC 24 |
| Finished | Sep 24 02:36:20 PM UTC 24 |
| Peak memory | 224924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453724351 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.3453724351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.2383258909 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 14848086 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 02:36:15 PM UTC 24 |
| Finished | Sep 24 02:36:18 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383258909 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.2383258909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2456935262 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 227357201 ps |
| CPU time | 4.21 seconds |
| Started | Sep 24 02:36:15 PM UTC 24 |
| Finished | Sep 24 02:36:21 PM UTC 24 |
| Peak memory | 224916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456935262 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstanding.2456935262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.956077775 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 697651010 ps |
| CPU time | 5.37 seconds |
| Started | Sep 24 02:36:15 PM UTC 24 |
| Finished | Sep 24 02:36:22 PM UTC 24 |
| Peak memory | 225016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956077775 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.956077775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.1766182309 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 312876216 ps |
| CPU time | 19.42 seconds |
| Started | Sep 24 02:36:15 PM UTC 24 |
| Finished | Sep 24 02:36:36 PM UTC 24 |
| Peak memory | 224964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766182309 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.1766182309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.225214112 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 186358761 ps |
| CPU time | 2.26 seconds |
| Started | Sep 24 02:36:19 PM UTC 24 |
| Finished | Sep 24 02:36:22 PM UTC 24 |
| Peak memory | 227060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=225214112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.225214112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.2568779206 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 36137398 ps |
| CPU time | 2.03 seconds |
| Started | Sep 24 02:36:17 PM UTC 24 |
| Finished | Sep 24 02:36:20 PM UTC 24 |
| Peak memory | 225212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568779206 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.2568779206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.2387553185 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 30099313 ps |
| CPU time | 1.09 seconds |
| Started | Sep 24 02:36:17 PM UTC 24 |
| Finished | Sep 24 02:36:19 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387553185 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.2387553185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3536438835 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 532541372 ps |
| CPU time | 3.78 seconds |
| Started | Sep 24 02:36:19 PM UTC 24 |
| Finished | Sep 24 02:36:23 PM UTC 24 |
| Peak memory | 225016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536438835 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstanding.3536438835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.2030323701 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 257291680 ps |
| CPU time | 5.35 seconds |
| Started | Sep 24 02:36:17 PM UTC 24 |
| Finished | Sep 24 02:36:23 PM UTC 24 |
| Peak memory | 227332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030323701 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.2030323701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.4060078059 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 3304856208 ps |
| CPU time | 14.79 seconds |
| Started | Sep 24 02:36:17 PM UTC 24 |
| Finished | Sep 24 02:36:33 PM UTC 24 |
| Peak memory | 227192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060078059 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.4060078059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1306851610 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 161057978 ps |
| CPU time | 2.29 seconds |
| Started | Sep 24 02:36:20 PM UTC 24 |
| Finished | Sep 24 02:36:23 PM UTC 24 |
| Peak memory | 224936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1306851610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1306851610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.1068908565 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 36500909 ps |
| CPU time | 1.94 seconds |
| Started | Sep 24 02:36:20 PM UTC 24 |
| Finished | Sep 24 02:36:23 PM UTC 24 |
| Peak memory | 223784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068908565 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.1068908565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.2060925432 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 12111263 ps |
| CPU time | 1.03 seconds |
| Started | Sep 24 02:36:19 PM UTC 24 |
| Finished | Sep 24 02:36:21 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060925432 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.2060925432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3829113742 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 124990934 ps |
| CPU time | 2.83 seconds |
| Started | Sep 24 02:36:20 PM UTC 24 |
| Finished | Sep 24 02:36:24 PM UTC 24 |
| Peak memory | 225136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829113742 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstanding.3829113742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.3279893062 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 226143625 ps |
| CPU time | 4.79 seconds |
| Started | Sep 24 02:36:19 PM UTC 24 |
| Finished | Sep 24 02:36:25 PM UTC 24 |
| Peak memory | 227120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279893062 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.3279893062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.387671346 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 2242045793 ps |
| CPU time | 14.14 seconds |
| Started | Sep 24 02:36:19 PM UTC 24 |
| Finished | Sep 24 02:36:34 PM UTC 24 |
| Peak memory | 225140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387671346 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.387671346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.3177155542 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 621194085 ps |
| CPU time | 18.53 seconds |
| Started | Sep 24 02:35:34 PM UTC 24 |
| Finished | Sep 24 02:35:54 PM UTC 24 |
| Peak memory | 225132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177155542 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.3177155542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2381790411 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 9487921565 ps |
| CPU time | 31.47 seconds |
| Started | Sep 24 02:35:33 PM UTC 24 |
| Finished | Sep 24 02:36:06 PM UTC 24 |
| Peak memory | 214776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381790411 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.2381790411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3197365148 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 27710388 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 02:35:32 PM UTC 24 |
| Finished | Sep 24 02:35:34 PM UTC 24 |
| Peak memory | 212976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197365148 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.3197365148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3387528690 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 41357807 ps |
| CPU time | 3.96 seconds |
| Started | Sep 24 02:35:35 PM UTC 24 |
| Finished | Sep 24 02:35:40 PM UTC 24 |
| Peak memory | 229176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3387528690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3387528690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.1904464844 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 250429586 ps |
| CPU time | 3 seconds |
| Started | Sep 24 02:35:33 PM UTC 24 |
| Finished | Sep 24 02:35:37 PM UTC 24 |
| Peak memory | 224940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904464844 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1904464844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.3311417550 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 32073430 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 02:35:31 PM UTC 24 |
| Finished | Sep 24 02:35:34 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311417550 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3311417550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.817611307 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 28859124 ps |
| CPU time | 3.43 seconds |
| Started | Sep 24 02:35:32 PM UTC 24 |
| Finished | Sep 24 02:35:36 PM UTC 24 |
| Peak memory | 224468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817611307 -assert nopostpr oc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.817611307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.2198552806 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 17651107 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 02:35:31 PM UTC 24 |
| Finished | Sep 24 02:35:34 PM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198552806 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.2198552806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2613232843 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 122049284 ps |
| CPU time | 2.82 seconds |
| Started | Sep 24 02:35:34 PM UTC 24 |
| Finished | Sep 24 02:35:38 PM UTC 24 |
| Peak memory | 224888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613232843 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstanding.2613232843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.2165842974 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 219087915 ps |
| CPU time | 2.62 seconds |
| Started | Sep 24 02:35:30 PM UTC 24 |
| Finished | Sep 24 02:35:34 PM UTC 24 |
| Peak memory | 225068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165842974 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2165842974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.2434004049 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 728128573 ps |
| CPU time | 16.09 seconds |
| Started | Sep 24 02:35:30 PM UTC 24 |
| Finished | Sep 24 02:35:48 PM UTC 24 |
| Peak memory | 226988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434004049 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.2434004049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.237494544 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 14726586 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 02:36:20 PM UTC 24 |
| Finished | Sep 24 02:36:22 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237494544 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.237494544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/20.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.3823138561 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 30814800 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 02:36:22 PM UTC 24 |
| Finished | Sep 24 02:36:24 PM UTC 24 |
| Peak memory | 211228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823138561 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.3823138561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/21.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.2203327725 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 11461481 ps |
| CPU time | 0.99 seconds |
| Started | Sep 24 02:36:22 PM UTC 24 |
| Finished | Sep 24 02:36:24 PM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203327725 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.2203327725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/22.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1385305631 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 15966329 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 02:36:22 PM UTC 24 |
| Finished | Sep 24 02:36:24 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385305631 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.1385305631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/23.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.745592111 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 207187902 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 02:36:22 PM UTC 24 |
| Finished | Sep 24 02:36:24 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745592111 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.745592111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/24.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.1581615140 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 33589055 ps |
| CPU time | 1.14 seconds |
| Started | Sep 24 02:36:22 PM UTC 24 |
| Finished | Sep 24 02:36:24 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581615140 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.1581615140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/25.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.2790782557 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 15994461 ps |
| CPU time | 0.97 seconds |
| Started | Sep 24 02:36:22 PM UTC 24 |
| Finished | Sep 24 02:36:24 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790782557 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.2790782557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/26.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.3189400783 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 26509821 ps |
| CPU time | 1.07 seconds |
| Started | Sep 24 02:36:22 PM UTC 24 |
| Finished | Sep 24 02:36:24 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189400783 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.3189400783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/27.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.47085853 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 156296128 ps |
| CPU time | 0.95 seconds |
| Started | Sep 24 02:36:26 PM UTC 24 |
| Finished | Sep 24 02:36:28 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47085853 -assert nopostproc +UVM_TESTNAME=spi _device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.47085853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/28.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.527145722 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 17349133 ps |
| CPU time | 1.09 seconds |
| Started | Sep 24 02:36:26 PM UTC 24 |
| Finished | Sep 24 02:36:28 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527145722 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.527145722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/29.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.1741704655 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 2180006941 ps |
| CPU time | 18.76 seconds |
| Started | Sep 24 02:35:39 PM UTC 24 |
| Finished | Sep 24 02:35:59 PM UTC 24 |
| Peak memory | 214976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741704655 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.1741704655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1364476932 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 3756473593 ps |
| CPU time | 29.52 seconds |
| Started | Sep 24 02:35:39 PM UTC 24 |
| Finished | Sep 24 02:36:10 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364476932 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.1364476932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3798551479 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 20512199 ps |
| CPU time | 1.6 seconds |
| Started | Sep 24 02:35:38 PM UTC 24 |
| Finished | Sep 24 02:35:40 PM UTC 24 |
| Peak memory | 213544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798551479 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.3798551479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.2029759961 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 23377716 ps |
| CPU time | 1.99 seconds |
| Started | Sep 24 02:35:38 PM UTC 24 |
| Finished | Sep 24 02:35:41 PM UTC 24 |
| Peak memory | 223784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029759961 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2029759961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.3059130200 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 32726747 ps |
| CPU time | 1.14 seconds |
| Started | Sep 24 02:35:35 PM UTC 24 |
| Finished | Sep 24 02:35:37 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059130200 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3059130200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.2365732708 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 62446779 ps |
| CPU time | 2.09 seconds |
| Started | Sep 24 02:35:36 PM UTC 24 |
| Finished | Sep 24 02:35:40 PM UTC 24 |
| Peak memory | 224940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365732708 -assert nopostp roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.2365732708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.2342437231 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 26029425 ps |
| CPU time | 1.06 seconds |
| Started | Sep 24 02:35:36 PM UTC 24 |
| Finished | Sep 24 02:35:39 PM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342437231 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.2342437231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2095084939 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 254050596 ps |
| CPU time | 4.41 seconds |
| Started | Sep 24 02:35:40 PM UTC 24 |
| Finished | Sep 24 02:35:46 PM UTC 24 |
| Peak memory | 225040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095084939 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstanding.2095084939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.4227624763 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 357643272 ps |
| CPU time | 3.47 seconds |
| Started | Sep 24 02:35:35 PM UTC 24 |
| Finished | Sep 24 02:35:40 PM UTC 24 |
| Peak memory | 227184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227624763 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.4227624763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.804313100 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2204170048 ps |
| CPU time | 16.63 seconds |
| Started | Sep 24 02:35:35 PM UTC 24 |
| Finished | Sep 24 02:35:53 PM UTC 24 |
| Peak memory | 227328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804313100 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.804313100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.1748616330 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 20527708 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 02:36:26 PM UTC 24 |
| Finished | Sep 24 02:36:28 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748616330 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.1748616330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/30.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.3705652296 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 14626653 ps |
| CPU time | 1.07 seconds |
| Started | Sep 24 02:36:26 PM UTC 24 |
| Finished | Sep 24 02:36:28 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705652296 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.3705652296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/31.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.753266493 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 54270710 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 02:36:26 PM UTC 24 |
| Finished | Sep 24 02:36:28 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753266493 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.753266493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/32.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.4272502218 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 34988013 ps |
| CPU time | 1.06 seconds |
| Started | Sep 24 02:36:26 PM UTC 24 |
| Finished | Sep 24 02:36:28 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272502218 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.4272502218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/33.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.1280602575 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 27450857 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 02:36:26 PM UTC 24 |
| Finished | Sep 24 02:36:28 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280602575 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.1280602575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/34.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.3156181217 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 29838342 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 02:36:26 PM UTC 24 |
| Finished | Sep 24 02:36:28 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156181217 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.3156181217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/35.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.3322829378 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 31277500 ps |
| CPU time | 1.01 seconds |
| Started | Sep 24 02:36:26 PM UTC 24 |
| Finished | Sep 24 02:36:28 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322829378 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.3322829378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/36.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.467248843 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 38483929 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 02:36:26 PM UTC 24 |
| Finished | Sep 24 02:36:28 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467248843 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.467248843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/37.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.1438600896 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 16748406 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 02:36:26 PM UTC 24 |
| Finished | Sep 24 02:36:28 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438600896 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.1438600896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/38.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.2103647635 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 34325599 ps |
| CPU time | 0.95 seconds |
| Started | Sep 24 02:36:26 PM UTC 24 |
| Finished | Sep 24 02:36:28 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103647635 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.2103647635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/39.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.468559567 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 989856446 ps |
| CPU time | 9.74 seconds |
| Started | Sep 24 02:35:47 PM UTC 24 |
| Finished | Sep 24 02:35:58 PM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468559567 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.468559567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3064966023 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 2084734843 ps |
| CPU time | 34.19 seconds |
| Started | Sep 24 02:35:46 PM UTC 24 |
| Finished | Sep 24 02:36:21 PM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064966023 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.3064966023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1957002636 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 40802575 ps |
| CPU time | 1.6 seconds |
| Started | Sep 24 02:35:45 PM UTC 24 |
| Finished | Sep 24 02:35:47 PM UTC 24 |
| Peak memory | 213776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957002636 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.1957002636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1072946947 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 23973985 ps |
| CPU time | 2.54 seconds |
| Started | Sep 24 02:35:48 PM UTC 24 |
| Finished | Sep 24 02:35:52 PM UTC 24 |
| Peak memory | 224936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1072946947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1072946947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.4008863811 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 129090272 ps |
| CPU time | 3.08 seconds |
| Started | Sep 24 02:35:45 PM UTC 24 |
| Finished | Sep 24 02:35:49 PM UTC 24 |
| Peak memory | 226980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008863811 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4008863811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.2548297853 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 36591037 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 02:35:41 PM UTC 24 |
| Finished | Sep 24 02:35:44 PM UTC 24 |
| Peak memory | 211224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548297853 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2548297853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.2002446442 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 37828076 ps |
| CPU time | 1.84 seconds |
| Started | Sep 24 02:35:44 PM UTC 24 |
| Finished | Sep 24 02:35:46 PM UTC 24 |
| Peak memory | 223820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002446442 -assert nopostp roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.2002446442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.2670141445 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 13127783 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 02:35:41 PM UTC 24 |
| Finished | Sep 24 02:35:44 PM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670141445 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.2670141445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3844841018 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 142755785 ps |
| CPU time | 2.62 seconds |
| Started | Sep 24 02:35:47 PM UTC 24 |
| Finished | Sep 24 02:35:51 PM UTC 24 |
| Peak memory | 214956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844841018 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstanding.3844841018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.576570445 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 83496419 ps |
| CPU time | 3.44 seconds |
| Started | Sep 24 02:35:41 PM UTC 24 |
| Finished | Sep 24 02:35:46 PM UTC 24 |
| Peak memory | 225152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576570445 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.576570445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.2816448583 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 824742165 ps |
| CPU time | 13.88 seconds |
| Started | Sep 24 02:35:41 PM UTC 24 |
| Finished | Sep 24 02:35:56 PM UTC 24 |
| Peak memory | 227000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816448583 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.2816448583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.208755898 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 18585817 ps |
| CPU time | 1.02 seconds |
| Started | Sep 24 02:36:26 PM UTC 24 |
| Finished | Sep 24 02:36:28 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208755898 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.208755898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/40.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.2576555820 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 16945623 ps |
| CPU time | 0.91 seconds |
| Started | Sep 24 02:36:26 PM UTC 24 |
| Finished | Sep 24 02:36:28 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576555820 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.2576555820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/41.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3633693807 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 36319966 ps |
| CPU time | 1.07 seconds |
| Started | Sep 24 02:36:26 PM UTC 24 |
| Finished | Sep 24 02:36:28 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633693807 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.3633693807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/42.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.797114619 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 15211577 ps |
| CPU time | 0.91 seconds |
| Started | Sep 24 02:36:26 PM UTC 24 |
| Finished | Sep 24 02:36:28 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797114619 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.797114619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/43.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.990893627 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 67742464 ps |
| CPU time | 0.83 seconds |
| Started | Sep 24 02:36:26 PM UTC 24 |
| Finished | Sep 24 02:36:28 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990893627 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.990893627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/44.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.1431122820 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 14788303 ps |
| CPU time | 0.86 seconds |
| Started | Sep 24 02:36:26 PM UTC 24 |
| Finished | Sep 24 02:36:28 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431122820 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.1431122820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/45.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.2800851236 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 27992928 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 02:36:28 PM UTC 24 |
| Finished | Sep 24 02:36:30 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800851236 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.2800851236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/46.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.545974395 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 13073378 ps |
| CPU time | 0.98 seconds |
| Started | Sep 24 02:36:28 PM UTC 24 |
| Finished | Sep 24 02:36:30 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545974395 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.545974395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/47.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.3867128077 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 56949616 ps |
| CPU time | 0.73 seconds |
| Started | Sep 24 02:36:31 PM UTC 24 |
| Finished | Sep 24 02:36:33 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867128077 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.3867128077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/48.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.1547183684 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 13568871 ps |
| CPU time | 0.91 seconds |
| Started | Sep 24 02:36:31 PM UTC 24 |
| Finished | Sep 24 02:36:33 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547183684 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.1547183684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/49.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1111799515 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 414476885 ps |
| CPU time | 3.84 seconds |
| Started | Sep 24 02:35:50 PM UTC 24 |
| Finished | Sep 24 02:35:55 PM UTC 24 |
| Peak memory | 227268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1111799515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1111799515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.3573292346 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 434214441 ps |
| CPU time | 3.82 seconds |
| Started | Sep 24 02:35:50 PM UTC 24 |
| Finished | Sep 24 02:35:55 PM UTC 24 |
| Peak memory | 214820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573292346 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3573292346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.933721647 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 54725593 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 02:35:49 PM UTC 24 |
| Finished | Sep 24 02:35:51 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933721647 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.933721647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1840447440 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 58528619 ps |
| CPU time | 2.64 seconds |
| Started | Sep 24 02:35:50 PM UTC 24 |
| Finished | Sep 24 02:35:54 PM UTC 24 |
| Peak memory | 224832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840447440 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstanding.1840447440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.3397808196 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 146501664 ps |
| CPU time | 3.21 seconds |
| Started | Sep 24 02:35:48 PM UTC 24 |
| Finished | Sep 24 02:35:53 PM UTC 24 |
| Peak memory | 227144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397808196 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3397808196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.1308102435 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 192023627 ps |
| CPU time | 11.94 seconds |
| Started | Sep 24 02:35:49 PM UTC 24 |
| Finished | Sep 24 02:36:02 PM UTC 24 |
| Peak memory | 224960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308102435 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.1308102435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4022509322 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 987160733 ps |
| CPU time | 4.83 seconds |
| Started | Sep 24 02:35:54 PM UTC 24 |
| Finished | Sep 24 02:36:00 PM UTC 24 |
| Peak memory | 228968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4022509322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.4022509322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.1434512132 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 38531736 ps |
| CPU time | 1.8 seconds |
| Started | Sep 24 02:35:51 PM UTC 24 |
| Finished | Sep 24 02:35:54 PM UTC 24 |
| Peak memory | 223760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434512132 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1434512132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.1955298390 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 45748429 ps |
| CPU time | 1 seconds |
| Started | Sep 24 02:35:51 PM UTC 24 |
| Finished | Sep 24 02:35:53 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955298390 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1955298390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1814708250 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 84996311 ps |
| CPU time | 4.44 seconds |
| Started | Sep 24 02:35:53 PM UTC 24 |
| Finished | Sep 24 02:35:58 PM UTC 24 |
| Peak memory | 225152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814708250 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstanding.1814708250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.2418103433 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 90413506 ps |
| CPU time | 4.21 seconds |
| Started | Sep 24 02:35:50 PM UTC 24 |
| Finished | Sep 24 02:35:55 PM UTC 24 |
| Peak memory | 225068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418103433 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2418103433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.2159280307 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1015740236 ps |
| CPU time | 29 seconds |
| Started | Sep 24 02:35:51 PM UTC 24 |
| Finished | Sep 24 02:36:22 PM UTC 24 |
| Peak memory | 225200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159280307 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.2159280307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3079995529 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 577451617 ps |
| CPU time | 4.94 seconds |
| Started | Sep 24 02:35:55 PM UTC 24 |
| Finished | Sep 24 02:36:01 PM UTC 24 |
| Peak memory | 229300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3079995529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3079995529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.4278502213 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 47598116 ps |
| CPU time | 2.23 seconds |
| Started | Sep 24 02:35:54 PM UTC 24 |
| Finished | Sep 24 02:35:57 PM UTC 24 |
| Peak memory | 224984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278502213 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.4278502213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.3899511534 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 13998572 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 02:35:54 PM UTC 24 |
| Finished | Sep 24 02:35:56 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899511534 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3899511534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.290042773 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 60773120 ps |
| CPU time | 4.32 seconds |
| Started | Sep 24 02:35:55 PM UTC 24 |
| Finished | Sep 24 02:36:01 PM UTC 24 |
| Peak memory | 224916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290042773 -assert nopost proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstanding.290042773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.1154229912 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 575907294 ps |
| CPU time | 20.12 seconds |
| Started | Sep 24 02:35:54 PM UTC 24 |
| Finished | Sep 24 02:36:15 PM UTC 24 |
| Peak memory | 224816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154229912 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.1154229912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3463269434 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 143954347 ps |
| CPU time | 4.06 seconds |
| Started | Sep 24 02:35:57 PM UTC 24 |
| Finished | Sep 24 02:36:02 PM UTC 24 |
| Peak memory | 228932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3463269434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3463269434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.3245448797 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 366887620 ps |
| CPU time | 3.96 seconds |
| Started | Sep 24 02:35:57 PM UTC 24 |
| Finished | Sep 24 02:36:02 PM UTC 24 |
| Peak memory | 224992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245448797 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3245448797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.2589603259 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 67638948 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 02:35:56 PM UTC 24 |
| Finished | Sep 24 02:35:58 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589603259 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2589603259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3457629366 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 64735803 ps |
| CPU time | 5.81 seconds |
| Started | Sep 24 02:35:57 PM UTC 24 |
| Finished | Sep 24 02:36:04 PM UTC 24 |
| Peak memory | 225020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457629366 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstanding.3457629366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.362849051 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 211435425 ps |
| CPU time | 7.15 seconds |
| Started | Sep 24 02:35:55 PM UTC 24 |
| Finished | Sep 24 02:36:04 PM UTC 24 |
| Peak memory | 225360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362849051 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.362849051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.188371999 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 13282927633 ps |
| CPU time | 22.83 seconds |
| Started | Sep 24 02:35:56 PM UTC 24 |
| Finished | Sep 24 02:36:20 PM UTC 24 |
| Peak memory | 225140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188371999 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.188371999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1374808217 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 149078231 ps |
| CPU time | 5.61 seconds |
| Started | Sep 24 02:36:00 PM UTC 24 |
| Finished | Sep 24 02:36:06 PM UTC 24 |
| Peak memory | 229100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1374808217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1374808217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.3647800985 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 171972432 ps |
| CPU time | 1.85 seconds |
| Started | Sep 24 02:35:59 PM UTC 24 |
| Finished | Sep 24 02:36:02 PM UTC 24 |
| Peak memory | 213536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647800985 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3647800985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.2431723190 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 29765296 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 02:35:59 PM UTC 24 |
| Finished | Sep 24 02:36:02 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431723190 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2431723190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2989244485 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 414858396 ps |
| CPU time | 3.17 seconds |
| Started | Sep 24 02:36:00 PM UTC 24 |
| Finished | Sep 24 02:36:04 PM UTC 24 |
| Peak memory | 224892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989244485 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstanding.2989244485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.2843753295 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 411323680 ps |
| CPU time | 2.23 seconds |
| Started | Sep 24 02:35:58 PM UTC 24 |
| Finished | Sep 24 02:36:01 PM UTC 24 |
| Peak memory | 227020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843753295 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2843753295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.151997770 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1909489366 ps |
| CPU time | 8.46 seconds |
| Started | Sep 24 02:35:58 PM UTC 24 |
| Finished | Sep 24 02:36:08 PM UTC 24 |
| Peak memory | 224756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151997770 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.151997770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.1591586724 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 1408600546 ps |
| CPU time | 16.2 seconds |
| Started | Sep 24 02:12:08 PM UTC 24 |
| Finished | Sep 24 02:12:26 PM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591586724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1591586724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.3888822943 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 69908220 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 02:12:06 PM UTC 24 |
| Finished | Sep 24 02:12:08 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888822943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3888822943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.1832252375 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 6776156877 ps |
| CPU time | 46.55 seconds |
| Started | Sep 24 02:12:09 PM UTC 24 |
| Finished | Sep 24 02:12:58 PM UTC 24 |
| Peak memory | 263604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832252375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.1832252375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.3154979359 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1153095997 ps |
| CPU time | 9.15 seconds |
| Started | Sep 24 02:12:08 PM UTC 24 |
| Finished | Sep 24 02:12:19 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154979359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3154979359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.1924117993 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3540045722 ps |
| CPU time | 23.5 seconds |
| Started | Sep 24 02:12:07 PM UTC 24 |
| Finished | Sep 24 02:12:32 PM UTC 24 |
| Peak memory | 245540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924117993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1924117993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.3892484848 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 1275295536 ps |
| CPU time | 14.06 seconds |
| Started | Sep 24 02:12:10 PM UTC 24 |
| Finished | Sep 24 02:12:25 PM UTC 24 |
| Peak memory | 233368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892484848 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.3892484848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.528027008 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 5820929705 ps |
| CPU time | 38.88 seconds |
| Started | Sep 24 02:12:07 PM UTC 24 |
| Finished | Sep 24 02:12:47 PM UTC 24 |
| Peak memory | 227940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528027008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.528027008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.3524716859 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 19563497 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 02:12:07 PM UTC 24 |
| Finished | Sep 24 02:12:10 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524716859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3524716859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.4090678759 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 272310676 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 02:12:07 PM UTC 24 |
| Finished | Sep 24 02:12:10 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090678759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.4090678759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.1198907335 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 38728295036 ps |
| CPU time | 26.38 seconds |
| Started | Sep 24 02:12:08 PM UTC 24 |
| Finished | Sep 24 02:12:36 PM UTC 24 |
| Peak memory | 245464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198907335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1198907335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/0.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.3127437671 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 14200336 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 02:12:39 PM UTC 24 |
| Finished | Sep 24 02:12:41 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127437671 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3127437671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1551453112 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 268345992 ps |
| CPU time | 6.05 seconds |
| Started | Sep 24 02:12:27 PM UTC 24 |
| Finished | Sep 24 02:12:34 PM UTC 24 |
| Peak memory | 245340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551453112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1551453112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.3195881098 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 33284274 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 02:12:19 PM UTC 24 |
| Finished | Sep 24 02:12:21 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195881098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3195881098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.500987340 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3673887628 ps |
| CPU time | 31.82 seconds |
| Started | Sep 24 02:12:35 PM UTC 24 |
| Finished | Sep 24 02:13:08 PM UTC 24 |
| Peak memory | 247588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500987340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.500987340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.2468591691 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 278952566 ps |
| CPU time | 4.32 seconds |
| Started | Sep 24 02:12:28 PM UTC 24 |
| Finished | Sep 24 02:12:34 PM UTC 24 |
| Peak memory | 245360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468591691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2468591691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.1368700703 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1489145842 ps |
| CPU time | 9.95 seconds |
| Started | Sep 24 02:12:26 PM UTC 24 |
| Finished | Sep 24 02:12:37 PM UTC 24 |
| Peak memory | 231988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368700703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1368700703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.2079430355 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 2636160645 ps |
| CPU time | 42.47 seconds |
| Started | Sep 24 02:12:26 PM UTC 24 |
| Finished | Sep 24 02:13:10 PM UTC 24 |
| Peak memory | 245540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079430355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2079430355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.2335711748 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 338954821 ps |
| CPU time | 1.63 seconds |
| Started | Sep 24 02:12:19 PM UTC 24 |
| Finished | Sep 24 02:12:22 PM UTC 24 |
| Peak memory | 228192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335711748 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_parity.2335711748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.2408288746 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 6667332396 ps |
| CPU time | 43.86 seconds |
| Started | Sep 24 02:12:26 PM UTC 24 |
| Finished | Sep 24 02:13:11 PM UTC 24 |
| Peak memory | 245544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408288746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.2408288746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.4221806624 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 2373632448 ps |
| CPU time | 14.18 seconds |
| Started | Sep 24 02:12:24 PM UTC 24 |
| Finished | Sep 24 02:12:39 PM UTC 24 |
| Peak memory | 251624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221806624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4221806624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.2416196973 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 352632240 ps |
| CPU time | 9.83 seconds |
| Started | Sep 24 02:12:32 PM UTC 24 |
| Finished | Sep 24 02:12:44 PM UTC 24 |
| Peak memory | 233716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416196973 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.2416196973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.3123684797 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 153296097 ps |
| CPU time | 1.56 seconds |
| Started | Sep 24 02:12:38 PM UTC 24 |
| Finished | Sep 24 02:12:40 PM UTC 24 |
| Peak memory | 257648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123684797 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3123684797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.2878419426 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 176532147 ps |
| CPU time | 1.67 seconds |
| Started | Sep 24 02:12:38 PM UTC 24 |
| Finished | Sep 24 02:12:40 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878419426 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.2878419426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.3917557525 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 32162589463 ps |
| CPU time | 22.46 seconds |
| Started | Sep 24 02:12:19 PM UTC 24 |
| Finished | Sep 24 02:12:43 PM UTC 24 |
| Peak memory | 227768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917557525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3917557525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.4053043315 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 276572836 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 02:12:23 PM UTC 24 |
| Finished | Sep 24 02:12:25 PM UTC 24 |
| Peak memory | 214636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053043315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.4053043315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.228940000 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 23786901 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 02:12:23 PM UTC 24 |
| Finished | Sep 24 02:12:25 PM UTC 24 |
| Peak memory | 214724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228940000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.228940000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.1948473106 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 10287465532 ps |
| CPU time | 9.41 seconds |
| Started | Sep 24 02:12:26 PM UTC 24 |
| Finished | Sep 24 02:12:36 PM UTC 24 |
| Peak memory | 235292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948473106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1948473106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/1.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.1262620675 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 46209562 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 02:16:56 PM UTC 24 |
| Finished | Sep 24 02:16:58 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262620675 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.1262620675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.2904184700 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 121601949 ps |
| CPU time | 3.99 seconds |
| Started | Sep 24 02:16:47 PM UTC 24 |
| Finished | Sep 24 02:16:52 PM UTC 24 |
| Peak memory | 245344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904184700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2904184700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.101230437 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 30930545 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 02:16:36 PM UTC 24 |
| Finished | Sep 24 02:16:38 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101230437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.101230437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.761481336 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 353438380207 ps |
| CPU time | 190.42 seconds |
| Started | Sep 24 02:16:48 PM UTC 24 |
| Finished | Sep 24 02:20:02 PM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761481336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.761481336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.2577544179 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 1152458908 ps |
| CPU time | 8.23 seconds |
| Started | Sep 24 02:16:49 PM UTC 24 |
| Finished | Sep 24 02:16:59 PM UTC 24 |
| Peak memory | 229860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577544179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2577544179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.954867149 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 34094623738 ps |
| CPU time | 80.35 seconds |
| Started | Sep 24 02:16:49 PM UTC 24 |
| Finished | Sep 24 02:18:12 PM UTC 24 |
| Peak memory | 264104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954867149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.954867149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.4111112684 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 2115397070 ps |
| CPU time | 43.62 seconds |
| Started | Sep 24 02:16:47 PM UTC 24 |
| Finished | Sep 24 02:17:32 PM UTC 24 |
| Peak memory | 245400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111112684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.4111112684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.2224848321 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 4307588076 ps |
| CPU time | 88.81 seconds |
| Started | Sep 24 02:16:48 PM UTC 24 |
| Finished | Sep 24 02:18:19 PM UTC 24 |
| Peak memory | 264104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224848321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.2224848321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.3564338348 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 227570347 ps |
| CPU time | 4.28 seconds |
| Started | Sep 24 02:16:42 PM UTC 24 |
| Finished | Sep 24 02:16:47 PM UTC 24 |
| Peak memory | 245364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564338348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3564338348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.1758428400 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 10149646536 ps |
| CPU time | 55.79 seconds |
| Started | Sep 24 02:16:44 PM UTC 24 |
| Finished | Sep 24 02:17:41 PM UTC 24 |
| Peak memory | 245604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758428400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1758428400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.1654901901 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 105581822 ps |
| CPU time | 1.56 seconds |
| Started | Sep 24 02:16:36 PM UTC 24 |
| Finished | Sep 24 02:16:39 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654901901 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mem_parity.1654901901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.2702612426 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 147307910 ps |
| CPU time | 4.95 seconds |
| Started | Sep 24 02:16:42 PM UTC 24 |
| Finished | Sep 24 02:16:48 PM UTC 24 |
| Peak memory | 245480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702612426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.2702612426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.2485431046 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 18875425915 ps |
| CPU time | 5.82 seconds |
| Started | Sep 24 02:16:40 PM UTC 24 |
| Finished | Sep 24 02:16:46 PM UTC 24 |
| Peak memory | 245604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485431046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2485431046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.2455564264 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 2204510531 ps |
| CPU time | 5.69 seconds |
| Started | Sep 24 02:16:48 PM UTC 24 |
| Finished | Sep 24 02:16:55 PM UTC 24 |
| Peak memory | 233964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455564264 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.2455564264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.3563045572 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 11449127768 ps |
| CPU time | 163.15 seconds |
| Started | Sep 24 02:16:53 PM UTC 24 |
| Finished | Sep 24 02:19:39 PM UTC 24 |
| Peak memory | 264028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563045572 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.3563045572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.3264988269 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 795203818 ps |
| CPU time | 8.53 seconds |
| Started | Sep 24 02:16:37 PM UTC 24 |
| Finished | Sep 24 02:16:47 PM UTC 24 |
| Peak memory | 231840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264988269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3264988269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.785604619 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1990685732 ps |
| CPU time | 9.69 seconds |
| Started | Sep 24 02:16:37 PM UTC 24 |
| Finished | Sep 24 02:16:48 PM UTC 24 |
| Peak memory | 227716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785604619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.785604619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.126493113 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 123779531 ps |
| CPU time | 2.06 seconds |
| Started | Sep 24 02:16:40 PM UTC 24 |
| Finished | Sep 24 02:16:43 PM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126493113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.126493113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.1981894267 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 15037529 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 02:16:38 PM UTC 24 |
| Finished | Sep 24 02:16:41 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981894267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1981894267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.3761559725 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 5798746915 ps |
| CPU time | 12.63 seconds |
| Started | Sep 24 02:16:46 PM UTC 24 |
| Finished | Sep 24 02:17:00 PM UTC 24 |
| Peak memory | 245472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761559725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3761559725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/10.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.4244081217 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 207838459 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 02:17:33 PM UTC 24 |
| Finished | Sep 24 02:17:35 PM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244081217 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.4244081217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.2153086344 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 3676120148 ps |
| CPU time | 32.53 seconds |
| Started | Sep 24 02:17:09 PM UTC 24 |
| Finished | Sep 24 02:17:43 PM UTC 24 |
| Peak memory | 245476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153086344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2153086344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.1768907288 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 39211659 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 02:16:58 PM UTC 24 |
| Finished | Sep 24 02:17:00 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768907288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1768907288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.3214132472 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 52539116275 ps |
| CPU time | 272.16 seconds |
| Started | Sep 24 02:17:25 PM UTC 24 |
| Finished | Sep 24 02:22:02 PM UTC 24 |
| Peak memory | 264032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214132472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3214132472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.4100311217 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 1632196052 ps |
| CPU time | 12.17 seconds |
| Started | Sep 24 02:17:16 PM UTC 24 |
| Finished | Sep 24 02:17:29 PM UTC 24 |
| Peak memory | 245348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100311217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4100311217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.2563957371 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 16514683 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 02:17:21 PM UTC 24 |
| Finished | Sep 24 02:17:23 PM UTC 24 |
| Peak memory | 225964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563957371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.2563957371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.1183634283 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 4031617577 ps |
| CPU time | 16.08 seconds |
| Started | Sep 24 02:17:04 PM UTC 24 |
| Finished | Sep 24 02:17:21 PM UTC 24 |
| Peak memory | 245484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183634283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1183634283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.657285397 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 49315967071 ps |
| CPU time | 103.17 seconds |
| Started | Sep 24 02:17:05 PM UTC 24 |
| Finished | Sep 24 02:18:50 PM UTC 24 |
| Peak memory | 245536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657285397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.657285397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.3203141672 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 27789712 ps |
| CPU time | 1.65 seconds |
| Started | Sep 24 02:16:59 PM UTC 24 |
| Finished | Sep 24 02:17:02 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203141672 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mem_parity.3203141672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.3904386528 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 244514479 ps |
| CPU time | 4.46 seconds |
| Started | Sep 24 02:17:03 PM UTC 24 |
| Finished | Sep 24 02:17:08 PM UTC 24 |
| Peak memory | 245484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904386528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.3904386528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.2191555355 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 209004670 ps |
| CPU time | 4.38 seconds |
| Started | Sep 24 02:17:02 PM UTC 24 |
| Finished | Sep 24 02:17:08 PM UTC 24 |
| Peak memory | 235080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191555355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2191555355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.629441706 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 7141307148 ps |
| CPU time | 8.7 seconds |
| Started | Sep 24 02:17:22 PM UTC 24 |
| Finished | Sep 24 02:17:32 PM UTC 24 |
| Peak memory | 231668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629441706 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.629441706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.745093543 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 6301927186 ps |
| CPU time | 13.86 seconds |
| Started | Sep 24 02:17:00 PM UTC 24 |
| Finished | Sep 24 02:17:15 PM UTC 24 |
| Peak memory | 227872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745093543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.745093543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.2703251325 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 162473930 ps |
| CPU time | 1.7 seconds |
| Started | Sep 24 02:17:01 PM UTC 24 |
| Finished | Sep 24 02:17:04 PM UTC 24 |
| Peak memory | 216948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703251325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2703251325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.1084303204 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 48645254 ps |
| CPU time | 1.14 seconds |
| Started | Sep 24 02:17:00 PM UTC 24 |
| Finished | Sep 24 02:17:02 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084303204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1084303204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.1522124002 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 591932096 ps |
| CPU time | 10.58 seconds |
| Started | Sep 24 02:17:09 PM UTC 24 |
| Finished | Sep 24 02:17:21 PM UTC 24 |
| Peak memory | 245416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522124002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1522124002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/11.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.1512968628 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 15022279 ps |
| CPU time | 1.01 seconds |
| Started | Sep 24 02:18:21 PM UTC 24 |
| Finished | Sep 24 02:18:23 PM UTC 24 |
| Peak memory | 212976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512968628 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.1512968628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.2872146825 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 602290982 ps |
| CPU time | 7.21 seconds |
| Started | Sep 24 02:18:02 PM UTC 24 |
| Finished | Sep 24 02:18:10 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872146825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2872146825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.3943291318 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 95348899 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 02:17:36 PM UTC 24 |
| Finished | Sep 24 02:17:38 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943291318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3943291318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_all.1279603198 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 24975808998 ps |
| CPU time | 214.84 seconds |
| Started | Sep 24 02:18:11 PM UTC 24 |
| Finished | Sep 24 02:21:50 PM UTC 24 |
| Peak memory | 268144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279603198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1279603198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.2683503619 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 80710904812 ps |
| CPU time | 527.96 seconds |
| Started | Sep 24 02:18:12 PM UTC 24 |
| Finished | Sep 24 02:27:09 PM UTC 24 |
| Peak memory | 263976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683503619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2683503619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.3218457754 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 61478865759 ps |
| CPU time | 662.69 seconds |
| Started | Sep 24 02:18:17 PM UTC 24 |
| Finished | Sep 24 02:29:29 PM UTC 24 |
| Peak memory | 276328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218457754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.3218457754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.3544692343 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 3039239576 ps |
| CPU time | 36.86 seconds |
| Started | Sep 24 02:18:04 PM UTC 24 |
| Finished | Sep 24 02:18:43 PM UTC 24 |
| Peak memory | 245484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544692343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3544692343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.1809721923 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 3232533410 ps |
| CPU time | 71.88 seconds |
| Started | Sep 24 02:18:06 PM UTC 24 |
| Finished | Sep 24 02:19:20 PM UTC 24 |
| Peak memory | 261928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809721923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.1809721923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.218171554 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 421679390 ps |
| CPU time | 14.03 seconds |
| Started | Sep 24 02:17:51 PM UTC 24 |
| Finished | Sep 24 02:18:06 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218171554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.218171554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.3673871842 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1097727687 ps |
| CPU time | 6.13 seconds |
| Started | Sep 24 02:17:54 PM UTC 24 |
| Finished | Sep 24 02:18:01 PM UTC 24 |
| Peak memory | 235052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673871842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3673871842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.1830281527 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 118486850 ps |
| CPU time | 1.56 seconds |
| Started | Sep 24 02:17:39 PM UTC 24 |
| Finished | Sep 24 02:17:42 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830281527 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mem_parity.1830281527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.3761614470 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 522944082 ps |
| CPU time | 4.45 seconds |
| Started | Sep 24 02:17:48 PM UTC 24 |
| Finished | Sep 24 02:17:53 PM UTC 24 |
| Peak memory | 235168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761614470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.3761614470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.2251534482 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 111117003 ps |
| CPU time | 3.31 seconds |
| Started | Sep 24 02:17:45 PM UTC 24 |
| Finished | Sep 24 02:17:50 PM UTC 24 |
| Peak memory | 245088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251534482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2251534482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.1653918356 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 828349924 ps |
| CPU time | 14.88 seconds |
| Started | Sep 24 02:18:07 PM UTC 24 |
| Finished | Sep 24 02:18:24 PM UTC 24 |
| Peak memory | 233716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653918356 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.1653918356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.1226985614 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 4956865725 ps |
| CPU time | 32.61 seconds |
| Started | Sep 24 02:17:42 PM UTC 24 |
| Finished | Sep 24 02:18:16 PM UTC 24 |
| Peak memory | 227508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226985614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1226985614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.1819958406 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 11560639524 ps |
| CPU time | 37.24 seconds |
| Started | Sep 24 02:17:41 PM UTC 24 |
| Finished | Sep 24 02:18:20 PM UTC 24 |
| Peak memory | 227888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819958406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1819958406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.3422219141 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 234989744 ps |
| CPU time | 10.97 seconds |
| Started | Sep 24 02:17:43 PM UTC 24 |
| Finished | Sep 24 02:17:55 PM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422219141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3422219141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.3710859325 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 36694486 ps |
| CPU time | 1.43 seconds |
| Started | Sep 24 02:17:42 PM UTC 24 |
| Finished | Sep 24 02:17:45 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710859325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3710859325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.2106177137 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 1411040758 ps |
| CPU time | 5.3 seconds |
| Started | Sep 24 02:17:57 PM UTC 24 |
| Finished | Sep 24 02:18:03 PM UTC 24 |
| Peak memory | 235176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106177137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2106177137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/12.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_alert_test.2174770892 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 63555885 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 02:19:10 PM UTC 24 |
| Finished | Sep 24 02:19:12 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174770892 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.2174770892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_cfg_cmd.1211523028 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 81667592 ps |
| CPU time | 3.48 seconds |
| Started | Sep 24 02:18:50 PM UTC 24 |
| Finished | Sep 24 02:18:55 PM UTC 24 |
| Peak memory | 235036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211523028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1211523028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.274654873 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 45987364 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 02:18:21 PM UTC 24 |
| Finished | Sep 24 02:18:24 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274654873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.274654873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.3097490888 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 12248992431 ps |
| CPU time | 74.56 seconds |
| Started | Sep 24 02:19:00 PM UTC 24 |
| Finished | Sep 24 02:20:16 PM UTC 24 |
| Peak memory | 251684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097490888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3097490888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.1547343369 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 6442551709 ps |
| CPU time | 152.25 seconds |
| Started | Sep 24 02:19:01 PM UTC 24 |
| Finished | Sep 24 02:21:36 PM UTC 24 |
| Peak memory | 282408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547343369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.1547343369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode.1962374624 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 2611022785 ps |
| CPU time | 21.43 seconds |
| Started | Sep 24 02:18:51 PM UTC 24 |
| Finished | Sep 24 02:19:14 PM UTC 24 |
| Peak memory | 235240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962374624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1962374624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.1582698690 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 7974453740 ps |
| CPU time | 27.8 seconds |
| Started | Sep 24 02:18:52 PM UTC 24 |
| Finished | Sep 24 02:19:21 PM UTC 24 |
| Peak memory | 247524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582698690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.1582698690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_intercept.4253823240 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 3388338138 ps |
| CPU time | 15.27 seconds |
| Started | Sep 24 02:18:43 PM UTC 24 |
| Finished | Sep 24 02:18:59 PM UTC 24 |
| Peak memory | 235308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253823240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4253823240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mailbox.2192740578 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 2128744793 ps |
| CPU time | 23.37 seconds |
| Started | Sep 24 02:18:44 PM UTC 24 |
| Finished | Sep 24 02:19:09 PM UTC 24 |
| Peak memory | 235164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192740578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2192740578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.2999747662 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 29177735 ps |
| CPU time | 1.57 seconds |
| Started | Sep 24 02:18:24 PM UTC 24 |
| Finished | Sep 24 02:18:27 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999747662 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mem_parity.2999747662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.3611952730 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 4718689916 ps |
| CPU time | 11.22 seconds |
| Started | Sep 24 02:18:36 PM UTC 24 |
| Finished | Sep 24 02:18:48 PM UTC 24 |
| Peak memory | 249576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611952730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.3611952730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.1719117684 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 29172575186 ps |
| CPU time | 23.4 seconds |
| Started | Sep 24 02:18:34 PM UTC 24 |
| Finished | Sep 24 02:18:58 PM UTC 24 |
| Peak memory | 245604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719117684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1719117684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.3243948276 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 10091148394 ps |
| CPU time | 13.6 seconds |
| Started | Sep 24 02:18:55 PM UTC 24 |
| Finished | Sep 24 02:19:10 PM UTC 24 |
| Peak memory | 233836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243948276 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.3243948276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.3670889388 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 132235759231 ps |
| CPU time | 304.78 seconds |
| Started | Sep 24 02:19:07 PM UTC 24 |
| Finished | Sep 24 02:24:16 PM UTC 24 |
| Peak memory | 263952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670889388 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.3670889388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_all.3112095313 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 51895581108 ps |
| CPU time | 62.38 seconds |
| Started | Sep 24 02:18:24 PM UTC 24 |
| Finished | Sep 24 02:19:29 PM UTC 24 |
| Peak memory | 227892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112095313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3112095313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.1528298430 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1688835498 ps |
| CPU time | 9.36 seconds |
| Started | Sep 24 02:18:24 PM UTC 24 |
| Finished | Sep 24 02:18:35 PM UTC 24 |
| Peak memory | 227700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528298430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1528298430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.3863570946 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 90145094 ps |
| CPU time | 1.63 seconds |
| Started | Sep 24 02:18:31 PM UTC 24 |
| Finished | Sep 24 02:18:33 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863570946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3863570946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.2163745936 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 56420077 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 02:18:28 PM UTC 24 |
| Finished | Sep 24 02:18:30 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163745936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2163745936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/13.spi_device_upload.2131007606 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 3257094968 ps |
| CPU time | 15.22 seconds |
| Started | Sep 24 02:18:49 PM UTC 24 |
| Finished | Sep 24 02:19:05 PM UTC 24 |
| Peak memory | 235144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131007606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2131007606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/13.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_alert_test.2661909018 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 14713882 ps |
| CPU time | 1.14 seconds |
| Started | Sep 24 02:19:46 PM UTC 24 |
| Finished | Sep 24 02:19:48 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661909018 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.2661909018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_cfg_cmd.2294331710 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 82464718 ps |
| CPU time | 3.47 seconds |
| Started | Sep 24 02:19:30 PM UTC 24 |
| Finished | Sep 24 02:19:35 PM UTC 24 |
| Peak memory | 235044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294331710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2294331710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_csb_read.1686083853 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 26800537 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 02:19:11 PM UTC 24 |
| Finished | Sep 24 02:19:13 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686083853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1686083853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_all.964982214 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 33096774598 ps |
| CPU time | 226.8 seconds |
| Started | Sep 24 02:19:40 PM UTC 24 |
| Finished | Sep 24 02:23:30 PM UTC 24 |
| Peak memory | 261928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964982214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.964982214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.1774494761 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 43128275045 ps |
| CPU time | 106.51 seconds |
| Started | Sep 24 02:19:42 PM UTC 24 |
| Finished | Sep 24 02:21:31 PM UTC 24 |
| Peak memory | 268072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774494761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.1774494761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_intercept.240046548 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 1085430293 ps |
| CPU time | 9 seconds |
| Started | Sep 24 02:19:26 PM UTC 24 |
| Finished | Sep 24 02:19:36 PM UTC 24 |
| Peak memory | 235180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240046548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.240046548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mailbox.1420684248 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 2536033955 ps |
| CPU time | 26.32 seconds |
| Started | Sep 24 02:19:26 PM UTC 24 |
| Finished | Sep 24 02:19:54 PM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420684248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1420684248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mem_parity.3544333081 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 106964856 ps |
| CPU time | 1.67 seconds |
| Started | Sep 24 02:19:13 PM UTC 24 |
| Finished | Sep 24 02:19:16 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544333081 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mem_parity.3544333081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.34036158 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 3470494697 ps |
| CPU time | 15.03 seconds |
| Started | Sep 24 02:19:23 PM UTC 24 |
| Finished | Sep 24 02:19:39 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34036158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.34036158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.1385359493 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 33100209087 ps |
| CPU time | 36.3 seconds |
| Started | Sep 24 02:19:21 PM UTC 24 |
| Finished | Sep 24 02:19:58 PM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385359493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1385359493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.2762970547 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1286343539 ps |
| CPU time | 20.11 seconds |
| Started | Sep 24 02:19:37 PM UTC 24 |
| Finished | Sep 24 02:19:58 PM UTC 24 |
| Peak memory | 231528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762970547 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.2762970547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.3393604066 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 55636121 ps |
| CPU time | 1.44 seconds |
| Started | Sep 24 02:19:44 PM UTC 24 |
| Finished | Sep 24 02:19:46 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393604066 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.3393604066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_all.1494280808 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 7059883686 ps |
| CPU time | 59.53 seconds |
| Started | Sep 24 02:19:15 PM UTC 24 |
| Finished | Sep 24 02:20:17 PM UTC 24 |
| Peak memory | 227828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494280808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1494280808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.3339998492 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1166791077 ps |
| CPU time | 9.25 seconds |
| Started | Sep 24 02:19:14 PM UTC 24 |
| Finished | Sep 24 02:19:25 PM UTC 24 |
| Peak memory | 227668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339998492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3339998492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_rw.2101032039 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 2560720559 ps |
| CPU time | 3.97 seconds |
| Started | Sep 24 02:19:19 PM UTC 24 |
| Finished | Sep 24 02:19:24 PM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101032039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2101032039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.1664765248 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 272659630 ps |
| CPU time | 1.46 seconds |
| Started | Sep 24 02:19:16 PM UTC 24 |
| Finished | Sep 24 02:19:19 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664765248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1664765248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/14.spi_device_upload.2384335969 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1040557680 ps |
| CPU time | 12.93 seconds |
| Started | Sep 24 02:19:27 PM UTC 24 |
| Finished | Sep 24 02:19:41 PM UTC 24 |
| Peak memory | 247336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384335969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2384335969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/14.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_alert_test.3406333869 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 18065363 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 02:20:03 PM UTC 24 |
| Finished | Sep 24 02:20:05 PM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406333869 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.3406333869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_cfg_cmd.2655885220 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 45605938 ps |
| CPU time | 3.33 seconds |
| Started | Sep 24 02:19:57 PM UTC 24 |
| Finished | Sep 24 02:20:02 PM UTC 24 |
| Peak memory | 245032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655885220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2655885220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_csb_read.841673825 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 85376662 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 02:19:47 PM UTC 24 |
| Finished | Sep 24 02:19:49 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841673825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.841673825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_all.237333950 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 6131942647 ps |
| CPU time | 42.95 seconds |
| Started | Sep 24 02:20:00 PM UTC 24 |
| Finished | Sep 24 02:20:44 PM UTC 24 |
| Peak memory | 235176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237333950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.237333950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode.521686861 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 1492981031 ps |
| CPU time | 12.19 seconds |
| Started | Sep 24 02:19:58 PM UTC 24 |
| Finished | Sep 24 02:20:12 PM UTC 24 |
| Peak memory | 245020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521686861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.521686861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.1599423434 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 60535413282 ps |
| CPU time | 68.68 seconds |
| Started | Sep 24 02:19:58 PM UTC 24 |
| Finished | Sep 24 02:21:09 PM UTC 24 |
| Peak memory | 261592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599423434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.1599423434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_intercept.1395198311 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 172150609 ps |
| CPU time | 3.37 seconds |
| Started | Sep 24 02:19:54 PM UTC 24 |
| Finished | Sep 24 02:19:59 PM UTC 24 |
| Peak memory | 245356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395198311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1395198311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mailbox.818566750 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 9874643512 ps |
| CPU time | 27.25 seconds |
| Started | Sep 24 02:19:56 PM UTC 24 |
| Finished | Sep 24 02:20:25 PM UTC 24 |
| Peak memory | 261868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818566750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.818566750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mem_parity.3972666111 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 16210436 ps |
| CPU time | 1.44 seconds |
| Started | Sep 24 02:19:48 PM UTC 24 |
| Finished | Sep 24 02:19:51 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972666111 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mem_parity.3972666111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.3371191007 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 6054797244 ps |
| CPU time | 9.11 seconds |
| Started | Sep 24 02:19:54 PM UTC 24 |
| Finished | Sep 24 02:20:05 PM UTC 24 |
| Peak memory | 245480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371191007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.3371191007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.4146727832 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 95963396 ps |
| CPU time | 2.4 seconds |
| Started | Sep 24 02:19:53 PM UTC 24 |
| Finished | Sep 24 02:19:56 PM UTC 24 |
| Peak memory | 234692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146727832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.4146727832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.190108556 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 1023422807 ps |
| CPU time | 11.35 seconds |
| Started | Sep 24 02:20:00 PM UTC 24 |
| Finished | Sep 24 02:20:12 PM UTC 24 |
| Peak memory | 233656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190108556 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.190108556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_stress_all.3538149871 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 10310751881 ps |
| CPU time | 157.59 seconds |
| Started | Sep 24 02:20:03 PM UTC 24 |
| Finished | Sep 24 02:22:43 PM UTC 24 |
| Peak memory | 261984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538149871 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.3538149871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_all.3722124630 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 676262884 ps |
| CPU time | 8.24 seconds |
| Started | Sep 24 02:19:49 PM UTC 24 |
| Finished | Sep 24 02:19:59 PM UTC 24 |
| Peak memory | 227812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722124630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3722124630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.1398659436 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 10767560853 ps |
| CPU time | 6.6 seconds |
| Started | Sep 24 02:19:48 PM UTC 24 |
| Finished | Sep 24 02:19:56 PM UTC 24 |
| Peak memory | 229872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398659436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1398659436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_rw.1992919696 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 1092117652 ps |
| CPU time | 2.07 seconds |
| Started | Sep 24 02:19:52 PM UTC 24 |
| Finished | Sep 24 02:19:55 PM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992919696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1992919696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.795553633 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 29318542 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 02:19:51 PM UTC 24 |
| Finished | Sep 24 02:19:53 PM UTC 24 |
| Peak memory | 215036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795553633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.795553633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/15.spi_device_upload.2473121306 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 4641591150 ps |
| CPU time | 15.13 seconds |
| Started | Sep 24 02:19:57 PM UTC 24 |
| Finished | Sep 24 02:20:14 PM UTC 24 |
| Peak memory | 245472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473121306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2473121306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/15.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_alert_test.2221371380 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 12908993 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 02:20:35 PM UTC 24 |
| Finished | Sep 24 02:20:37 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221371380 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.2221371380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_cfg_cmd.3584316663 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 2527574519 ps |
| CPU time | 10.65 seconds |
| Started | Sep 24 02:20:22 PM UTC 24 |
| Finished | Sep 24 02:20:34 PM UTC 24 |
| Peak memory | 235292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584316663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3584316663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_csb_read.317341245 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 37573276 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 02:20:06 PM UTC 24 |
| Finished | Sep 24 02:20:08 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317341245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.317341245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.3893946730 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 167049549528 ps |
| CPU time | 384.43 seconds |
| Started | Sep 24 02:20:27 PM UTC 24 |
| Finished | Sep 24 02:26:57 PM UTC 24 |
| Peak memory | 263972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893946730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3893946730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode.533187593 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 872847345 ps |
| CPU time | 14.07 seconds |
| Started | Sep 24 02:20:23 PM UTC 24 |
| Finished | Sep 24 02:20:38 PM UTC 24 |
| Peak memory | 235088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533187593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.533187593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_intercept.396887734 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 12330137520 ps |
| CPU time | 50.88 seconds |
| Started | Sep 24 02:20:17 PM UTC 24 |
| Finished | Sep 24 02:21:09 PM UTC 24 |
| Peak memory | 235292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396887734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.396887734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mailbox.3202588321 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 380262698 ps |
| CPU time | 9.41 seconds |
| Started | Sep 24 02:20:18 PM UTC 24 |
| Finished | Sep 24 02:20:28 PM UTC 24 |
| Peak memory | 235116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202588321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3202588321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mem_parity.679099143 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 45750596 ps |
| CPU time | 1.7 seconds |
| Started | Sep 24 02:20:06 PM UTC 24 |
| Finished | Sep 24 02:20:09 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679099143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mem_parity.679099143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.1000787974 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 3161327019 ps |
| CPU time | 8.91 seconds |
| Started | Sep 24 02:20:17 PM UTC 24 |
| Finished | Sep 24 02:20:27 PM UTC 24 |
| Peak memory | 235224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000787974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.1000787974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.2862559626 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 4091043012 ps |
| CPU time | 33.3 seconds |
| Started | Sep 24 02:20:14 PM UTC 24 |
| Finished | Sep 24 02:20:49 PM UTC 24 |
| Peak memory | 245464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862559626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2862559626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.3061580314 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 22154893544 ps |
| CPU time | 24.18 seconds |
| Started | Sep 24 02:20:25 PM UTC 24 |
| Finished | Sep 24 02:20:51 PM UTC 24 |
| Peak memory | 231672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061580314 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.3061580314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_all.1282885142 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 2806763053 ps |
| CPU time | 21.7 seconds |
| Started | Sep 24 02:20:09 PM UTC 24 |
| Finished | Sep 24 02:20:32 PM UTC 24 |
| Peak memory | 227808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282885142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1282885142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.3461915212 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 911332065 ps |
| CPU time | 11.68 seconds |
| Started | Sep 24 02:20:09 PM UTC 24 |
| Finished | Sep 24 02:20:22 PM UTC 24 |
| Peak memory | 227628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461915212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3461915212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_rw.570438076 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 470985389 ps |
| CPU time | 2.36 seconds |
| Started | Sep 24 02:20:13 PM UTC 24 |
| Finished | Sep 24 02:20:17 PM UTC 24 |
| Peak memory | 227628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570438076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.570438076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.378714203 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 136569310 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 02:20:13 PM UTC 24 |
| Finished | Sep 24 02:20:16 PM UTC 24 |
| Peak memory | 215036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378714203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.378714203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/16.spi_device_upload.3999855687 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 350716328 ps |
| CPU time | 5.32 seconds |
| Started | Sep 24 02:20:18 PM UTC 24 |
| Finished | Sep 24 02:20:24 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999855687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3999855687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/16.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/17.spi_device_alert_test.103380102 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 14459357 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 02:21:10 PM UTC 24 |
| Finished | Sep 24 02:21:12 PM UTC 24 |
| Peak memory | 215152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103380102 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.103380102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/17.spi_device_cfg_cmd.1141115772 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 35491755 ps |
| CPU time | 3.42 seconds |
| Started | Sep 24 02:20:53 PM UTC 24 |
| Finished | Sep 24 02:20:57 PM UTC 24 |
| Peak memory | 245412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141115772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1141115772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/17.spi_device_csb_read.3845009592 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 48480025 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 02:20:35 PM UTC 24 |
| Finished | Sep 24 02:20:37 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845009592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3845009592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_all.1338810398 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 111666545 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 02:21:03 PM UTC 24 |
| Finished | Sep 24 02:21:05 PM UTC 24 |
| Peak memory | 225968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338810398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1338810398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.1287809700 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 11084432245 ps |
| CPU time | 142.35 seconds |
| Started | Sep 24 02:21:05 PM UTC 24 |
| Finished | Sep 24 02:23:30 PM UTC 24 |
| Peak memory | 268132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287809700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1287809700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.3158159281 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 72596607522 ps |
| CPU time | 163.62 seconds |
| Started | Sep 24 02:21:06 PM UTC 24 |
| Finished | Sep 24 02:23:53 PM UTC 24 |
| Peak memory | 261992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158159281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.3158159281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode.2574259097 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 977980340 ps |
| CPU time | 26.84 seconds |
| Started | Sep 24 02:20:58 PM UTC 24 |
| Finished | Sep 24 02:21:26 PM UTC 24 |
| Peak memory | 245360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574259097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2574259097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.528129388 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 9509315224 ps |
| CPU time | 41.55 seconds |
| Started | Sep 24 02:20:59 PM UTC 24 |
| Finished | Sep 24 02:21:42 PM UTC 24 |
| Peak memory | 247584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528129388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.528129388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/17.spi_device_intercept.3082965471 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 983644917 ps |
| CPU time | 9.67 seconds |
| Started | Sep 24 02:20:50 PM UTC 24 |
| Finished | Sep 24 02:21:01 PM UTC 24 |
| Peak memory | 235040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082965471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3082965471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mailbox.58353339 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 6812038635 ps |
| CPU time | 20.41 seconds |
| Started | Sep 24 02:20:51 PM UTC 24 |
| Finished | Sep 24 02:21:13 PM UTC 24 |
| Peak memory | 235252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58353339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.58353339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mem_parity.4272705088 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 15273734 ps |
| CPU time | 1.56 seconds |
| Started | Sep 24 02:20:38 PM UTC 24 |
| Finished | Sep 24 02:20:40 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272705088 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mem_parity.4272705088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.47264659 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 23687893144 ps |
| CPU time | 24.78 seconds |
| Started | Sep 24 02:20:47 PM UTC 24 |
| Finished | Sep 24 02:21:13 PM UTC 24 |
| Peak memory | 235228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47264659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.47264659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.3319394486 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 480026327 ps |
| CPU time | 4.95 seconds |
| Started | Sep 24 02:20:45 PM UTC 24 |
| Finished | Sep 24 02:20:51 PM UTC 24 |
| Peak memory | 235156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319394486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3319394486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.652842947 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 6617709204 ps |
| CPU time | 21.83 seconds |
| Started | Sep 24 02:21:02 PM UTC 24 |
| Finished | Sep 24 02:21:25 PM UTC 24 |
| Peak memory | 233692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652842947 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.652842947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/17.spi_device_stress_all.1504043469 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 40573250 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 02:21:10 PM UTC 24 |
| Finished | Sep 24 02:21:13 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504043469 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.1504043469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_all.3937398830 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1892050392 ps |
| CPU time | 21.44 seconds |
| Started | Sep 24 02:20:39 PM UTC 24 |
| Finished | Sep 24 02:21:02 PM UTC 24 |
| Peak memory | 229808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937398830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3937398830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.961395011 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 13440550664 ps |
| CPU time | 11.71 seconds |
| Started | Sep 24 02:20:38 PM UTC 24 |
| Finished | Sep 24 02:20:51 PM UTC 24 |
| Peak memory | 227808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961395011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.961395011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_rw.3750817024 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 12089080 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 02:20:44 PM UTC 24 |
| Finished | Sep 24 02:20:46 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750817024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3750817024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.2908187161 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 36765212 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 02:20:41 PM UTC 24 |
| Finished | Sep 24 02:20:43 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908187161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2908187161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/17.spi_device_upload.495649837 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 8364804014 ps |
| CPU time | 23.71 seconds |
| Started | Sep 24 02:20:51 PM UTC 24 |
| Finished | Sep 24 02:21:16 PM UTC 24 |
| Peak memory | 251620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495649837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.495649837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/17.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_alert_test.2952240668 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 36317510 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 02:21:36 PM UTC 24 |
| Finished | Sep 24 02:21:38 PM UTC 24 |
| Peak memory | 214808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952240668 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.2952240668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_cfg_cmd.187589379 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 5442592286 ps |
| CPU time | 15.44 seconds |
| Started | Sep 24 02:21:18 PM UTC 24 |
| Finished | Sep 24 02:21:35 PM UTC 24 |
| Peak memory | 245412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187589379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.187589379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_csb_read.1018701072 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 16756241 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 02:21:13 PM UTC 24 |
| Finished | Sep 24 02:21:16 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018701072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1018701072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_all.2102467639 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 161278862055 ps |
| CPU time | 357.15 seconds |
| Started | Sep 24 02:21:28 PM UTC 24 |
| Finished | Sep 24 02:27:31 PM UTC 24 |
| Peak memory | 268080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102467639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2102467639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.3204165752 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 57704145154 ps |
| CPU time | 795.63 seconds |
| Started | Sep 24 02:21:32 PM UTC 24 |
| Finished | Sep 24 02:34:58 PM UTC 24 |
| Peak memory | 278432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204165752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3204165752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.976362370 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 8579573964 ps |
| CPU time | 52.21 seconds |
| Started | Sep 24 02:21:34 PM UTC 24 |
| Finished | Sep 24 02:22:28 PM UTC 24 |
| Peak memory | 261992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976362370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.976362370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode.3544874524 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 2820832959 ps |
| CPU time | 42.25 seconds |
| Started | Sep 24 02:21:22 PM UTC 24 |
| Finished | Sep 24 02:22:06 PM UTC 24 |
| Peak memory | 245540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544874524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3544874524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.3337398454 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 135249428302 ps |
| CPU time | 408.96 seconds |
| Started | Sep 24 02:21:26 PM UTC 24 |
| Finished | Sep 24 02:28:21 PM UTC 24 |
| Peak memory | 278312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337398454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.3337398454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_intercept.1252359146 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 773924387 ps |
| CPU time | 9.04 seconds |
| Started | Sep 24 02:21:17 PM UTC 24 |
| Finished | Sep 24 02:21:27 PM UTC 24 |
| Peak memory | 235036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252359146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1252359146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mailbox.1512569993 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 3360776698 ps |
| CPU time | 55.48 seconds |
| Started | Sep 24 02:21:18 PM UTC 24 |
| Finished | Sep 24 02:22:15 PM UTC 24 |
| Peak memory | 245468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512569993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1512569993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mem_parity.3127634321 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 27461291 ps |
| CPU time | 1.14 seconds |
| Started | Sep 24 02:21:14 PM UTC 24 |
| Finished | Sep 24 02:21:16 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127634321 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mem_parity.3127634321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.2542996796 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 10187013486 ps |
| CPU time | 19.7 seconds |
| Started | Sep 24 02:21:17 PM UTC 24 |
| Finished | Sep 24 02:21:38 PM UTC 24 |
| Peak memory | 245536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542996796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.2542996796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.305402765 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 26369658777 ps |
| CPU time | 22.18 seconds |
| Started | Sep 24 02:21:17 PM UTC 24 |
| Finished | Sep 24 02:21:40 PM UTC 24 |
| Peak memory | 251812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305402765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.305402765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.746769327 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 379817759 ps |
| CPU time | 6.72 seconds |
| Started | Sep 24 02:21:27 PM UTC 24 |
| Finished | Sep 24 02:21:35 PM UTC 24 |
| Peak memory | 231524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746769327 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.746769327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.2905036402 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 13446456344 ps |
| CPU time | 51.89 seconds |
| Started | Sep 24 02:21:36 PM UTC 24 |
| Finished | Sep 24 02:22:30 PM UTC 24 |
| Peak memory | 261776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905036402 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.2905036402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_all.3500822349 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 327580851 ps |
| CPU time | 7.16 seconds |
| Started | Sep 24 02:21:14 PM UTC 24 |
| Finished | Sep 24 02:21:22 PM UTC 24 |
| Peak memory | 231904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500822349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3500822349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.1610139650 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 45881578036 ps |
| CPU time | 21.34 seconds |
| Started | Sep 24 02:21:14 PM UTC 24 |
| Finished | Sep 24 02:21:36 PM UTC 24 |
| Peak memory | 227828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610139650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1610139650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_rw.728598154 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 83758087 ps |
| CPU time | 1.86 seconds |
| Started | Sep 24 02:21:15 PM UTC 24 |
| Finished | Sep 24 02:21:18 PM UTC 24 |
| Peak memory | 226612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728598154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.728598154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.1620917230 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 258730427 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 02:21:15 PM UTC 24 |
| Finished | Sep 24 02:21:17 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620917230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1620917230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_upload.3792442001 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 18578842281 ps |
| CPU time | 13.3 seconds |
| Started | Sep 24 02:21:18 PM UTC 24 |
| Finished | Sep 24 02:21:33 PM UTC 24 |
| Peak memory | 245608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792442001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3792442001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/18.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_alert_test.542107605 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 94657797 ps |
| CPU time | 1.14 seconds |
| Started | Sep 24 02:22:08 PM UTC 24 |
| Finished | Sep 24 02:22:10 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542107605 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.542107605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_cfg_cmd.3763130552 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 389557170 ps |
| CPU time | 3.94 seconds |
| Started | Sep 24 02:21:51 PM UTC 24 |
| Finished | Sep 24 02:21:56 PM UTC 24 |
| Peak memory | 235036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763130552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3763130552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_csb_read.2821112762 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 13784747 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 02:21:37 PM UTC 24 |
| Finished | Sep 24 02:21:40 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821112762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2821112762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_all.266270280 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 46016085431 ps |
| CPU time | 175.02 seconds |
| Started | Sep 24 02:21:59 PM UTC 24 |
| Finished | Sep 24 02:24:57 PM UTC 24 |
| Peak memory | 268008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266270280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.266270280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.2531968204 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 296941189108 ps |
| CPU time | 326.21 seconds |
| Started | Sep 24 02:22:05 PM UTC 24 |
| Finished | Sep 24 02:27:36 PM UTC 24 |
| Peak memory | 266092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531968204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.2531968204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode.2778801800 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 55408230 ps |
| CPU time | 3.4 seconds |
| Started | Sep 24 02:21:53 PM UTC 24 |
| Finished | Sep 24 02:21:58 PM UTC 24 |
| Peak memory | 245360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778801800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2778801800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.3432403217 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 11087497324 ps |
| CPU time | 131.49 seconds |
| Started | Sep 24 02:21:55 PM UTC 24 |
| Finished | Sep 24 02:24:08 PM UTC 24 |
| Peak memory | 263972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432403217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.3432403217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_intercept.3154252035 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 302507003 ps |
| CPU time | 8.42 seconds |
| Started | Sep 24 02:21:44 PM UTC 24 |
| Finished | Sep 24 02:21:54 PM UTC 24 |
| Peak memory | 245356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154252035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3154252035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mailbox.1525071664 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 914902385 ps |
| CPU time | 19.73 seconds |
| Started | Sep 24 02:21:50 PM UTC 24 |
| Finished | Sep 24 02:22:11 PM UTC 24 |
| Peak memory | 245352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525071664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1525071664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mem_parity.2048245440 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 33633537 ps |
| CPU time | 1.64 seconds |
| Started | Sep 24 02:21:37 PM UTC 24 |
| Finished | Sep 24 02:21:40 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048245440 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mem_parity.2048245440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.1772363387 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 628596134 ps |
| CPU time | 6.53 seconds |
| Started | Sep 24 02:21:43 PM UTC 24 |
| Finished | Sep 24 02:21:51 PM UTC 24 |
| Peak memory | 235100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772363387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.1772363387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.3494917292 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 4581710915 ps |
| CPU time | 23.58 seconds |
| Started | Sep 24 02:21:42 PM UTC 24 |
| Finished | Sep 24 02:22:07 PM UTC 24 |
| Peak memory | 235300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494917292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3494917292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.4283569236 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 5418158100 ps |
| CPU time | 18.55 seconds |
| Started | Sep 24 02:21:58 PM UTC 24 |
| Finished | Sep 24 02:22:17 PM UTC 24 |
| Peak memory | 233844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283569236 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.4283569236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_stress_all.4134334641 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 408372093579 ps |
| CPU time | 706.57 seconds |
| Started | Sep 24 02:22:07 PM UTC 24 |
| Finished | Sep 24 02:34:03 PM UTC 24 |
| Peak memory | 268068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134334641 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.4134334641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_all.646140249 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 1822705533 ps |
| CPU time | 34.51 seconds |
| Started | Sep 24 02:21:40 PM UTC 24 |
| Finished | Sep 24 02:22:16 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646140249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.646140249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.2840456314 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 15381103974 ps |
| CPU time | 12.74 seconds |
| Started | Sep 24 02:21:38 PM UTC 24 |
| Finished | Sep 24 02:21:52 PM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840456314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2840456314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_rw.1420433827 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 1149962433 ps |
| CPU time | 8.66 seconds |
| Started | Sep 24 02:21:41 PM UTC 24 |
| Finished | Sep 24 02:21:51 PM UTC 24 |
| Peak memory | 227956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420433827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1420433827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.2927525169 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 42067775 ps |
| CPU time | 1.46 seconds |
| Started | Sep 24 02:21:41 PM UTC 24 |
| Finished | Sep 24 02:21:43 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927525169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2927525169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_upload.1328456403 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 2650797292 ps |
| CPU time | 11.51 seconds |
| Started | Sep 24 02:21:51 PM UTC 24 |
| Finished | Sep 24 02:22:04 PM UTC 24 |
| Peak memory | 245476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328456403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1328456403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/19.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.2350873626 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 13733454 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 02:13:03 PM UTC 24 |
| Finished | Sep 24 02:13:05 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350873626 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2350873626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.89484372 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 701504208 ps |
| CPU time | 3.75 seconds |
| Started | Sep 24 02:12:46 PM UTC 24 |
| Finished | Sep 24 02:12:51 PM UTC 24 |
| Peak memory | 235048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89484372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.89484372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.3567128076 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 17248340 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 02:12:40 PM UTC 24 |
| Finished | Sep 24 02:12:42 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567128076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3567128076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.3607281989 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 40704902720 ps |
| CPU time | 103.97 seconds |
| Started | Sep 24 02:12:51 PM UTC 24 |
| Finished | Sep 24 02:14:37 PM UTC 24 |
| Peak memory | 263916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607281989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3607281989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.1056502376 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 164679810240 ps |
| CPU time | 344.59 seconds |
| Started | Sep 24 02:12:58 PM UTC 24 |
| Finished | Sep 24 02:18:49 PM UTC 24 |
| Peak memory | 261924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056502376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1056502376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.327346263 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 396815613 ps |
| CPU time | 12.11 seconds |
| Started | Sep 24 02:12:47 PM UTC 24 |
| Finished | Sep 24 02:13:00 PM UTC 24 |
| Peak memory | 245412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327346263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.327346263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.2038756974 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 23312638655 ps |
| CPU time | 174.59 seconds |
| Started | Sep 24 02:12:48 PM UTC 24 |
| Finished | Sep 24 02:15:46 PM UTC 24 |
| Peak memory | 280356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038756974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.2038756974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.2080984068 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2356892488 ps |
| CPU time | 37.97 seconds |
| Started | Sep 24 02:12:45 PM UTC 24 |
| Finished | Sep 24 02:13:24 PM UTC 24 |
| Peak memory | 235364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080984068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2080984068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.2920030441 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1134888806 ps |
| CPU time | 14.62 seconds |
| Started | Sep 24 02:12:45 PM UTC 24 |
| Finished | Sep 24 02:13:01 PM UTC 24 |
| Peak memory | 251552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920030441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2920030441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.905640928 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 31606066 ps |
| CPU time | 1.6 seconds |
| Started | Sep 24 02:12:41 PM UTC 24 |
| Finished | Sep 24 02:12:44 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905640928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_parity.905640928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.366381132 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 12511757378 ps |
| CPU time | 33.76 seconds |
| Started | Sep 24 02:12:45 PM UTC 24 |
| Finished | Sep 24 02:13:20 PM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366381132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.366381132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.2472188643 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 101434823 ps |
| CPU time | 2.99 seconds |
| Started | Sep 24 02:12:45 PM UTC 24 |
| Finished | Sep 24 02:12:49 PM UTC 24 |
| Peak memory | 233632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472188643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2472188643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.1690172382 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 12533123431 ps |
| CPU time | 17.81 seconds |
| Started | Sep 24 02:12:49 PM UTC 24 |
| Finished | Sep 24 02:13:09 PM UTC 24 |
| Peak memory | 231672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690172382 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.1690172382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.2662610922 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 197603254 ps |
| CPU time | 1.8 seconds |
| Started | Sep 24 02:13:02 PM UTC 24 |
| Finished | Sep 24 02:13:04 PM UTC 24 |
| Peak memory | 257648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662610922 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2662610922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.3459412732 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 48002507076 ps |
| CPU time | 581.89 seconds |
| Started | Sep 24 02:13:01 PM UTC 24 |
| Finished | Sep 24 02:22:51 PM UTC 24 |
| Peak memory | 294576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459412732 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.3459412732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.4045143927 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 15357419031 ps |
| CPU time | 43.17 seconds |
| Started | Sep 24 02:12:42 PM UTC 24 |
| Finished | Sep 24 02:13:27 PM UTC 24 |
| Peak memory | 227864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045143927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.4045143927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.2333644187 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 42696550951 ps |
| CPU time | 44.23 seconds |
| Started | Sep 24 02:12:41 PM UTC 24 |
| Finished | Sep 24 02:13:27 PM UTC 24 |
| Peak memory | 229936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333644187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2333644187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.1764262138 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 40330969 ps |
| CPU time | 1.09 seconds |
| Started | Sep 24 02:12:43 PM UTC 24 |
| Finished | Sep 24 02:12:46 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764262138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1764262138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.1205287569 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 61220059 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 02:12:42 PM UTC 24 |
| Finished | Sep 24 02:12:44 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205287569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1205287569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.2444172921 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 5315534153 ps |
| CPU time | 14.61 seconds |
| Started | Sep 24 02:12:45 PM UTC 24 |
| Finished | Sep 24 02:13:01 PM UTC 24 |
| Peak memory | 235212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444172921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2444172921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/2.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/20.spi_device_alert_test.3670834551 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 92623243 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 02:22:38 PM UTC 24 |
| Finished | Sep 24 02:22:40 PM UTC 24 |
| Peak memory | 214292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670834551 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.3670834551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/20.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/20.spi_device_cfg_cmd.4033702417 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 162205735 ps |
| CPU time | 5.88 seconds |
| Started | Sep 24 02:22:29 PM UTC 24 |
| Finished | Sep 24 02:22:37 PM UTC 24 |
| Peak memory | 245292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033702417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.4033702417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/20.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/20.spi_device_csb_read.3989625650 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 15898575 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 02:22:11 PM UTC 24 |
| Finished | Sep 24 02:22:14 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989625650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3989625650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/20.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_all.2963988564 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 83022003245 ps |
| CPU time | 215.48 seconds |
| Started | Sep 24 02:22:32 PM UTC 24 |
| Finished | Sep 24 02:26:11 PM UTC 24 |
| Peak memory | 268004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963988564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2963988564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/20.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.209380736 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 66261817373 ps |
| CPU time | 156.09 seconds |
| Started | Sep 24 02:22:37 PM UTC 24 |
| Finished | Sep 24 02:25:16 PM UTC 24 |
| Peak memory | 261992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209380736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.209380736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.2527520581 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 5060754030 ps |
| CPU time | 53.99 seconds |
| Started | Sep 24 02:22:37 PM UTC 24 |
| Finished | Sep 24 02:23:32 PM UTC 24 |
| Peak memory | 235368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527520581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.2527520581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode.4141049400 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 1291356706 ps |
| CPU time | 5.19 seconds |
| Started | Sep 24 02:22:29 PM UTC 24 |
| Finished | Sep 24 02:22:36 PM UTC 24 |
| Peak memory | 245352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141049400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.4141049400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/20.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.3417248337 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 846531071 ps |
| CPU time | 10.59 seconds |
| Started | Sep 24 02:22:30 PM UTC 24 |
| Finished | Sep 24 02:22:42 PM UTC 24 |
| Peak memory | 247460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417248337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.3417248337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/20.spi_device_intercept.138158889 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 3502716882 ps |
| CPU time | 35.47 seconds |
| Started | Sep 24 02:22:21 PM UTC 24 |
| Finished | Sep 24 02:22:58 PM UTC 24 |
| Peak memory | 235228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138158889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.138158889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/20.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/20.spi_device_mailbox.3419103496 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 32066631 ps |
| CPU time | 3.09 seconds |
| Started | Sep 24 02:22:24 PM UTC 24 |
| Finished | Sep 24 02:22:28 PM UTC 24 |
| Peak memory | 245028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419103496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3419103496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/20.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.277673292 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 3822975249 ps |
| CPU time | 7.82 seconds |
| Started | Sep 24 02:22:20 PM UTC 24 |
| Finished | Sep 24 02:22:29 PM UTC 24 |
| Peak memory | 235168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277673292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.277673292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/20.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.2888672908 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 1326488262 ps |
| CPU time | 9.84 seconds |
| Started | Sep 24 02:22:19 PM UTC 24 |
| Finished | Sep 24 02:22:30 PM UTC 24 |
| Peak memory | 235220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888672908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2888672908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/20.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.2806456988 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 109119829 ps |
| CPU time | 5.39 seconds |
| Started | Sep 24 02:22:30 PM UTC 24 |
| Finished | Sep 24 02:22:37 PM UTC 24 |
| Peak memory | 233720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806456988 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.2806456988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/20.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/20.spi_device_stress_all.3826866030 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 11990859310 ps |
| CPU time | 181 seconds |
| Started | Sep 24 02:22:38 PM UTC 24 |
| Finished | Sep 24 02:25:42 PM UTC 24 |
| Peak memory | 263896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826866030 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.3826866030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/20.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_all.4085281641 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 6121579961 ps |
| CPU time | 15.17 seconds |
| Started | Sep 24 02:22:14 PM UTC 24 |
| Finished | Sep 24 02:22:31 PM UTC 24 |
| Peak memory | 227868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085281641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.4085281641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/20.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.3511797444 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 2417104679 ps |
| CPU time | 9.59 seconds |
| Started | Sep 24 02:22:12 PM UTC 24 |
| Finished | Sep 24 02:22:23 PM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511797444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3511797444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/20.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_rw.1349525653 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 88791532 ps |
| CPU time | 2.58 seconds |
| Started | Sep 24 02:22:17 PM UTC 24 |
| Finished | Sep 24 02:22:20 PM UTC 24 |
| Peak memory | 227764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349525653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1349525653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/20.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.3005743239 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 99688015 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 02:22:17 PM UTC 24 |
| Finished | Sep 24 02:22:19 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005743239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3005743239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/20.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/20.spi_device_upload.2139771631 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 12230730816 ps |
| CPU time | 74.58 seconds |
| Started | Sep 24 02:22:29 PM UTC 24 |
| Finished | Sep 24 02:23:46 PM UTC 24 |
| Peak memory | 245468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139771631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2139771631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/20.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_alert_test.1314928373 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 13844804 ps |
| CPU time | 1.01 seconds |
| Started | Sep 24 02:23:20 PM UTC 24 |
| Finished | Sep 24 02:23:22 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314928373 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.1314928373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/21.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_cfg_cmd.3331651585 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 19030239767 ps |
| CPU time | 19.44 seconds |
| Started | Sep 24 02:22:59 PM UTC 24 |
| Finished | Sep 24 02:23:20 PM UTC 24 |
| Peak memory | 245544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331651585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3331651585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/21.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_csb_read.2714397229 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 27485241 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 02:22:41 PM UTC 24 |
| Finished | Sep 24 02:22:43 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714397229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2714397229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/21.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_all.258194958 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 39814424486 ps |
| CPU time | 55.78 seconds |
| Started | Sep 24 02:23:13 PM UTC 24 |
| Finished | Sep 24 02:24:10 PM UTC 24 |
| Peak memory | 251620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258194958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.258194958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/21.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.1793251336 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 39699525125 ps |
| CPU time | 200.17 seconds |
| Started | Sep 24 02:23:13 PM UTC 24 |
| Finished | Sep 24 02:26:36 PM UTC 24 |
| Peak memory | 278432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793251336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1793251336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.1935274463 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 110971933002 ps |
| CPU time | 195.52 seconds |
| Started | Sep 24 02:23:15 PM UTC 24 |
| Finished | Sep 24 02:26:34 PM UTC 24 |
| Peak memory | 266024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935274463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.1935274463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode.2552815885 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 567240058 ps |
| CPU time | 7.84 seconds |
| Started | Sep 24 02:23:02 PM UTC 24 |
| Finished | Sep 24 02:23:11 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552815885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2552815885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/21.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.3463828615 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 18939247788 ps |
| CPU time | 238.5 seconds |
| Started | Sep 24 02:23:03 PM UTC 24 |
| Finished | Sep 24 02:27:06 PM UTC 24 |
| Peak memory | 261864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463828615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.3463828615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_intercept.629881753 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 12276127066 ps |
| CPU time | 26.45 seconds |
| Started | Sep 24 02:22:52 PM UTC 24 |
| Finished | Sep 24 02:23:19 PM UTC 24 |
| Peak memory | 245472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629881753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.629881753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/21.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_mailbox.2436269102 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 2855690644 ps |
| CPU time | 8.15 seconds |
| Started | Sep 24 02:22:56 PM UTC 24 |
| Finished | Sep 24 02:23:05 PM UTC 24 |
| Peak memory | 235116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436269102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2436269102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/21.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.3382551763 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 2563846820 ps |
| CPU time | 8.85 seconds |
| Started | Sep 24 02:22:52 PM UTC 24 |
| Finished | Sep 24 02:23:02 PM UTC 24 |
| Peak memory | 235160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382551763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.3382551763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/21.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.3504778060 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 658244163 ps |
| CPU time | 5.97 seconds |
| Started | Sep 24 02:22:48 PM UTC 24 |
| Finished | Sep 24 02:22:55 PM UTC 24 |
| Peak memory | 235084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504778060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3504778060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/21.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.4074260462 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 122123650 ps |
| CPU time | 6.22 seconds |
| Started | Sep 24 02:23:06 PM UTC 24 |
| Finished | Sep 24 02:23:14 PM UTC 24 |
| Peak memory | 229480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074260462 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.4074260462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/21.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_stress_all.718360716 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 476711008951 ps |
| CPU time | 515.61 seconds |
| Started | Sep 24 02:23:15 PM UTC 24 |
| Finished | Sep 24 02:31:58 PM UTC 24 |
| Peak memory | 268060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718360716 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.718360716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/21.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_all.1603660392 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 93831080 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 02:22:44 PM UTC 24 |
| Finished | Sep 24 02:22:46 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603660392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1603660392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/21.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.1501995167 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 1891901911 ps |
| CPU time | 12.21 seconds |
| Started | Sep 24 02:22:43 PM UTC 24 |
| Finished | Sep 24 02:22:57 PM UTC 24 |
| Peak memory | 227656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501995167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1501995167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/21.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_rw.2204636001 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 201739820 ps |
| CPU time | 1.71 seconds |
| Started | Sep 24 02:22:48 PM UTC 24 |
| Finished | Sep 24 02:22:50 PM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204636001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2204636001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/21.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.2444696134 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 36339965 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 02:22:44 PM UTC 24 |
| Finished | Sep 24 02:22:47 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444696134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2444696134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/21.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_upload.891193841 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 165514481 ps |
| CPU time | 3.8 seconds |
| Started | Sep 24 02:22:57 PM UTC 24 |
| Finished | Sep 24 02:23:02 PM UTC 24 |
| Peak memory | 235036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891193841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.891193841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/21.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_alert_test.489868955 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 47644965 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 02:23:58 PM UTC 24 |
| Finished | Sep 24 02:24:00 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489868955 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.489868955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/22.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_cfg_cmd.2113789436 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 2028409856 ps |
| CPU time | 9.66 seconds |
| Started | Sep 24 02:23:43 PM UTC 24 |
| Finished | Sep 24 02:23:54 PM UTC 24 |
| Peak memory | 235100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113789436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2113789436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/22.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_csb_read.2489902127 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 56056063 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 02:23:21 PM UTC 24 |
| Finished | Sep 24 02:23:24 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489902127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2489902127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/22.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_all.1722688759 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 55877977925 ps |
| CPU time | 167.81 seconds |
| Started | Sep 24 02:23:53 PM UTC 24 |
| Finished | Sep 24 02:26:43 PM UTC 24 |
| Peak memory | 263920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722688759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1722688759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/22.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.3792587703 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 42398992813 ps |
| CPU time | 89.36 seconds |
| Started | Sep 24 02:23:54 PM UTC 24 |
| Finished | Sep 24 02:25:25 PM UTC 24 |
| Peak memory | 266020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792587703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3792587703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/22.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.3627070992 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 11251094395 ps |
| CPU time | 122.47 seconds |
| Started | Sep 24 02:23:55 PM UTC 24 |
| Finished | Sep 24 02:26:00 PM UTC 24 |
| Peak memory | 261980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627070992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.3627070992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode.1066327112 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 213408136 ps |
| CPU time | 8.4 seconds |
| Started | Sep 24 02:23:44 PM UTC 24 |
| Finished | Sep 24 02:23:54 PM UTC 24 |
| Peak memory | 251492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066327112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1066327112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/22.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_intercept.3998197587 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 586487927 ps |
| CPU time | 7.76 seconds |
| Started | Sep 24 02:23:34 PM UTC 24 |
| Finished | Sep 24 02:23:43 PM UTC 24 |
| Peak memory | 245420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998197587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3998197587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/22.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_mailbox.3600642366 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 771015197 ps |
| CPU time | 15.14 seconds |
| Started | Sep 24 02:23:34 PM UTC 24 |
| Finished | Sep 24 02:23:50 PM UTC 24 |
| Peak memory | 249448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600642366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3600642366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/22.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.1598513544 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 180054001 ps |
| CPU time | 8.46 seconds |
| Started | Sep 24 02:23:34 PM UTC 24 |
| Finished | Sep 24 02:23:43 PM UTC 24 |
| Peak memory | 245416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598513544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.1598513544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/22.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.1771106376 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 16432646609 ps |
| CPU time | 25.47 seconds |
| Started | Sep 24 02:23:32 PM UTC 24 |
| Finished | Sep 24 02:23:58 PM UTC 24 |
| Peak memory | 249636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771106376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1771106376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/22.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.984388855 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 169246881 ps |
| CPU time | 4.51 seconds |
| Started | Sep 24 02:23:51 PM UTC 24 |
| Finished | Sep 24 02:23:57 PM UTC 24 |
| Peak memory | 231648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984388855 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.984388855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/22.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.673393054 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 9394860333 ps |
| CPU time | 36.97 seconds |
| Started | Sep 24 02:23:55 PM UTC 24 |
| Finished | Sep 24 02:24:33 PM UTC 24 |
| Peak memory | 235428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673393054 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.673393054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/22.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_all.3342148448 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 34706750627 ps |
| CPU time | 61.58 seconds |
| Started | Sep 24 02:23:24 PM UTC 24 |
| Finished | Sep 24 02:24:28 PM UTC 24 |
| Peak memory | 232044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342148448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3342148448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/22.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.1281281585 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 16763242582 ps |
| CPU time | 5.41 seconds |
| Started | Sep 24 02:23:23 PM UTC 24 |
| Finished | Sep 24 02:23:30 PM UTC 24 |
| Peak memory | 227752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281281585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1281281585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/22.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_rw.1614789153 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 41017740 ps |
| CPU time | 1.33 seconds |
| Started | Sep 24 02:23:30 PM UTC 24 |
| Finished | Sep 24 02:23:33 PM UTC 24 |
| Peak memory | 226620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614789153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1614789153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/22.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.4246411576 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 99454634 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 02:23:30 PM UTC 24 |
| Finished | Sep 24 02:23:33 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246411576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.4246411576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/22.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/22.spi_device_upload.3193894230 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 2267726581 ps |
| CPU time | 7.01 seconds |
| Started | Sep 24 02:23:43 PM UTC 24 |
| Finished | Sep 24 02:23:51 PM UTC 24 |
| Peak memory | 245604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193894230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3193894230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/22.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_alert_test.1165120517 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 40840155 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 02:24:41 PM UTC 24 |
| Finished | Sep 24 02:24:43 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165120517 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.1165120517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/23.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_cfg_cmd.2388163343 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 928430825 ps |
| CPU time | 10.23 seconds |
| Started | Sep 24 02:24:23 PM UTC 24 |
| Finished | Sep 24 02:24:34 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388163343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2388163343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/23.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_csb_read.429266231 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 17048747 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 02:23:59 PM UTC 24 |
| Finished | Sep 24 02:24:01 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429266231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.429266231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/23.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.1474413428 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 54327261444 ps |
| CPU time | 492.65 seconds |
| Started | Sep 24 02:24:36 PM UTC 24 |
| Finished | Sep 24 02:32:55 PM UTC 24 |
| Peak memory | 284452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474413428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1474413428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.391226034 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 153223305877 ps |
| CPU time | 128.24 seconds |
| Started | Sep 24 02:24:39 PM UTC 24 |
| Finished | Sep 24 02:26:50 PM UTC 24 |
| Peak memory | 251684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391226034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.391226034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode.409708543 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 544210645 ps |
| CPU time | 13.56 seconds |
| Started | Sep 24 02:24:23 PM UTC 24 |
| Finished | Sep 24 02:24:38 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409708543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.409708543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/23.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_intercept.268939158 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 180731334 ps |
| CPU time | 3.95 seconds |
| Started | Sep 24 02:24:17 PM UTC 24 |
| Finished | Sep 24 02:24:22 PM UTC 24 |
| Peak memory | 244152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268939158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.268939158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/23.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_mailbox.2126001571 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 7704521121 ps |
| CPU time | 62.96 seconds |
| Started | Sep 24 02:24:20 PM UTC 24 |
| Finished | Sep 24 02:25:25 PM UTC 24 |
| Peak memory | 245416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126001571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2126001571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/23.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.1964930376 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 896136803 ps |
| CPU time | 3.67 seconds |
| Started | Sep 24 02:24:15 PM UTC 24 |
| Finished | Sep 24 02:24:19 PM UTC 24 |
| Peak memory | 235172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964930376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.1964930376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/23.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.4271599198 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 7528395853 ps |
| CPU time | 8.05 seconds |
| Started | Sep 24 02:24:13 PM UTC 24 |
| Finished | Sep 24 02:24:22 PM UTC 24 |
| Peak memory | 245544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271599198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4271599198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/23.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.2742469801 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 2100845940 ps |
| CPU time | 22.19 seconds |
| Started | Sep 24 02:24:28 PM UTC 24 |
| Finished | Sep 24 02:24:52 PM UTC 24 |
| Peak memory | 233780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742469801 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.2742469801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/23.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.1039739138 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 120562268504 ps |
| CPU time | 756.76 seconds |
| Started | Sep 24 02:24:40 PM UTC 24 |
| Finished | Sep 24 02:37:26 PM UTC 24 |
| Peak memory | 278300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039739138 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.1039739138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/23.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_all.4146911876 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 1290105525 ps |
| CPU time | 17.48 seconds |
| Started | Sep 24 02:24:02 PM UTC 24 |
| Finished | Sep 24 02:24:21 PM UTC 24 |
| Peak memory | 227740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146911876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.4146911876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/23.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.2285149090 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 43996456615 ps |
| CPU time | 24.39 seconds |
| Started | Sep 24 02:24:01 PM UTC 24 |
| Finished | Sep 24 02:24:27 PM UTC 24 |
| Peak memory | 227800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285149090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2285149090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/23.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_rw.3453129073 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 345679828 ps |
| CPU time | 1.55 seconds |
| Started | Sep 24 02:24:11 PM UTC 24 |
| Finished | Sep 24 02:24:14 PM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453129073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3453129073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/23.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.2537731097 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 88474946 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 02:24:09 PM UTC 24 |
| Finished | Sep 24 02:24:12 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537731097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2537731097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/23.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_upload.311444495 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 2351756011 ps |
| CPU time | 15.21 seconds |
| Started | Sep 24 02:24:22 PM UTC 24 |
| Finished | Sep 24 02:24:38 PM UTC 24 |
| Peak memory | 247528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311444495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.311444495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/23.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_alert_test.1641695103 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 12469236 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 02:25:29 PM UTC 24 |
| Finished | Sep 24 02:25:31 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641695103 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.1641695103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/24.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_cfg_cmd.3855929825 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 97804922 ps |
| CPU time | 3.39 seconds |
| Started | Sep 24 02:25:11 PM UTC 24 |
| Finished | Sep 24 02:25:15 PM UTC 24 |
| Peak memory | 235036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855929825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3855929825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/24.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_csb_read.880659202 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 16556737 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 02:24:44 PM UTC 24 |
| Finished | Sep 24 02:24:47 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880659202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.880659202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/24.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.754968219 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 3392691957 ps |
| CPU time | 27.43 seconds |
| Started | Sep 24 02:25:22 PM UTC 24 |
| Finished | Sep 24 02:25:51 PM UTC 24 |
| Peak memory | 229996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754968219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.754968219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.3120734486 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 16672199744 ps |
| CPU time | 120.14 seconds |
| Started | Sep 24 02:25:26 PM UTC 24 |
| Finished | Sep 24 02:27:28 PM UTC 24 |
| Peak memory | 280356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120734486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.3120734486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.3279499290 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 2550021757 ps |
| CPU time | 57.83 seconds |
| Started | Sep 24 02:25:16 PM UTC 24 |
| Finished | Sep 24 02:26:16 PM UTC 24 |
| Peak memory | 251684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279499290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.3279499290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_intercept.1782526384 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 186393486 ps |
| CPU time | 3.44 seconds |
| Started | Sep 24 02:25:06 PM UTC 24 |
| Finished | Sep 24 02:25:10 PM UTC 24 |
| Peak memory | 235188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782526384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1782526384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/24.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_mailbox.1559629943 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 8110587014 ps |
| CPU time | 14.09 seconds |
| Started | Sep 24 02:25:06 PM UTC 24 |
| Finished | Sep 24 02:25:21 PM UTC 24 |
| Peak memory | 235244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559629943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1559629943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/24.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.3481729098 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 5123787532 ps |
| CPU time | 29.46 seconds |
| Started | Sep 24 02:25:05 PM UTC 24 |
| Finished | Sep 24 02:25:36 PM UTC 24 |
| Peak memory | 235160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481729098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.3481729098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/24.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.3160266296 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 156096230 ps |
| CPU time | 4.45 seconds |
| Started | Sep 24 02:25:03 PM UTC 24 |
| Finished | Sep 24 02:25:08 PM UTC 24 |
| Peak memory | 245272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160266296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3160266296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/24.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.1354268797 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 286291176 ps |
| CPU time | 4.58 seconds |
| Started | Sep 24 02:25:16 PM UTC 24 |
| Finished | Sep 24 02:25:22 PM UTC 24 |
| Peak memory | 233748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354268797 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.1354268797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/24.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_stress_all.3275410486 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 9584954739 ps |
| CPU time | 78.13 seconds |
| Started | Sep 24 02:25:27 PM UTC 24 |
| Finished | Sep 24 02:26:47 PM UTC 24 |
| Peak memory | 261924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275410486 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.3275410486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/24.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_all.1318860158 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 1789161545 ps |
| CPU time | 11.63 seconds |
| Started | Sep 24 02:24:52 PM UTC 24 |
| Finished | Sep 24 02:25:05 PM UTC 24 |
| Peak memory | 227800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318860158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1318860158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/24.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.2566985154 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 24774632127 ps |
| CPU time | 12.9 seconds |
| Started | Sep 24 02:24:47 PM UTC 24 |
| Finished | Sep 24 02:25:01 PM UTC 24 |
| Peak memory | 227876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566985154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2566985154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/24.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_rw.269561676 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 209168357 ps |
| CPU time | 2.05 seconds |
| Started | Sep 24 02:25:01 PM UTC 24 |
| Finished | Sep 24 02:25:05 PM UTC 24 |
| Peak memory | 227708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269561676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.269561676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/24.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.2836870973 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 124516510 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 02:24:58 PM UTC 24 |
| Finished | Sep 24 02:25:01 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836870973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2836870973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/24.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/24.spi_device_upload.121061798 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 116866457 ps |
| CPU time | 2.3 seconds |
| Started | Sep 24 02:25:09 PM UTC 24 |
| Finished | Sep 24 02:25:12 PM UTC 24 |
| Peak memory | 245420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121061798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.121061798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/24.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_alert_test.3786068353 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 54868991 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 02:26:12 PM UTC 24 |
| Finished | Sep 24 02:26:14 PM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786068353 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.3786068353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/25.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_cfg_cmd.3427480543 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 168496756 ps |
| CPU time | 3.87 seconds |
| Started | Sep 24 02:25:55 PM UTC 24 |
| Finished | Sep 24 02:26:00 PM UTC 24 |
| Peak memory | 235116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427480543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3427480543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/25.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_csb_read.347158049 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 60853384 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 02:25:32 PM UTC 24 |
| Finished | Sep 24 02:25:34 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347158049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.347158049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/25.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_all.1289869873 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 51972888902 ps |
| CPU time | 130.61 seconds |
| Started | Sep 24 02:26:01 PM UTC 24 |
| Finished | Sep 24 02:28:15 PM UTC 24 |
| Peak memory | 261936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289869873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1289869873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/25.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.1398802860 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 10089010029 ps |
| CPU time | 59.23 seconds |
| Started | Sep 24 02:26:01 PM UTC 24 |
| Finished | Sep 24 02:27:02 PM UTC 24 |
| Peak memory | 261984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398802860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1398802860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode.1603014938 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 220177847 ps |
| CPU time | 4.09 seconds |
| Started | Sep 24 02:25:56 PM UTC 24 |
| Finished | Sep 24 02:26:01 PM UTC 24 |
| Peak memory | 235116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603014938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1603014938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/25.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.4091842210 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 44088009008 ps |
| CPU time | 390.42 seconds |
| Started | Sep 24 02:25:59 PM UTC 24 |
| Finished | Sep 24 02:32:36 PM UTC 24 |
| Peak memory | 266024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091842210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.4091842210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_intercept.3028080557 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 913726351 ps |
| CPU time | 10.41 seconds |
| Started | Sep 24 02:25:44 PM UTC 24 |
| Finished | Sep 24 02:25:55 PM UTC 24 |
| Peak memory | 245356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028080557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3028080557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/25.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_mailbox.351700188 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 5733265878 ps |
| CPU time | 74.07 seconds |
| Started | Sep 24 02:25:51 PM UTC 24 |
| Finished | Sep 24 02:27:07 PM UTC 24 |
| Peak memory | 261928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351700188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.351700188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/25.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.482972 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 4991976234 ps |
| CPU time | 10.64 seconds |
| Started | Sep 24 02:25:42 PM UTC 24 |
| Finished | Sep 24 02:25:54 PM UTC 24 |
| Peak memory | 245540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_ TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.482972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/25.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.53227373 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 2482948554 ps |
| CPU time | 16.63 seconds |
| Started | Sep 24 02:25:42 PM UTC 24 |
| Finished | Sep 24 02:26:00 PM UTC 24 |
| Peak memory | 245532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53227373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.53227373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/25.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.1164954491 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 8552040311 ps |
| CPU time | 25.63 seconds |
| Started | Sep 24 02:26:00 PM UTC 24 |
| Finished | Sep 24 02:26:27 PM UTC 24 |
| Peak memory | 233840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164954491 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.1164954491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/25.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.2779827441 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 17395420541 ps |
| CPU time | 143.89 seconds |
| Started | Sep 24 02:26:09 PM UTC 24 |
| Finished | Sep 24 02:28:36 PM UTC 24 |
| Peak memory | 278308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779827441 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.2779827441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/25.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_all.3566080667 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 1129758927 ps |
| CPU time | 13.25 seconds |
| Started | Sep 24 02:25:35 PM UTC 24 |
| Finished | Sep 24 02:25:50 PM UTC 24 |
| Peak memory | 227680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566080667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3566080667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/25.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.798247151 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 2288984545 ps |
| CPU time | 7.12 seconds |
| Started | Sep 24 02:25:33 PM UTC 24 |
| Finished | Sep 24 02:25:41 PM UTC 24 |
| Peak memory | 227704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798247151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.798247151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/25.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_rw.2760374055 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 161312522 ps |
| CPU time | 1.95 seconds |
| Started | Sep 24 02:25:39 PM UTC 24 |
| Finished | Sep 24 02:25:42 PM UTC 24 |
| Peak memory | 226956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760374055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2760374055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/25.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.2844116160 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 78777796 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 02:25:36 PM UTC 24 |
| Finished | Sep 24 02:25:38 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844116160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2844116160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/25.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_upload.1874030330 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 703881261 ps |
| CPU time | 15.86 seconds |
| Started | Sep 24 02:25:52 PM UTC 24 |
| Finished | Sep 24 02:26:09 PM UTC 24 |
| Peak memory | 261740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874030330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1874030330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/25.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_alert_test.3640742005 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 14877752 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 02:26:43 PM UTC 24 |
| Finished | Sep 24 02:26:45 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640742005 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.3640742005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/26.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_cfg_cmd.2211078595 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 484993620 ps |
| CPU time | 5.16 seconds |
| Started | Sep 24 02:26:34 PM UTC 24 |
| Finished | Sep 24 02:26:40 PM UTC 24 |
| Peak memory | 245400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211078595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2211078595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/26.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_csb_read.2927805423 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 15890275 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 02:26:12 PM UTC 24 |
| Finished | Sep 24 02:26:14 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927805423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2927805423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/26.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.1571782928 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 7814894004 ps |
| CPU time | 40.57 seconds |
| Started | Sep 24 02:26:40 PM UTC 24 |
| Finished | Sep 24 02:27:22 PM UTC 24 |
| Peak memory | 261872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571782928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1571782928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/26.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.2330312916 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 75053282972 ps |
| CPU time | 196.83 seconds |
| Started | Sep 24 02:26:41 PM UTC 24 |
| Finished | Sep 24 02:30:01 PM UTC 24 |
| Peak memory | 278312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330312916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2330312916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.3905441534 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 1421412131 ps |
| CPU time | 14.54 seconds |
| Started | Sep 24 02:26:42 PM UTC 24 |
| Finished | Sep 24 02:26:58 PM UTC 24 |
| Peak memory | 245416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905441534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.3905441534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode.3469324835 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 218034844 ps |
| CPU time | 5.38 seconds |
| Started | Sep 24 02:26:35 PM UTC 24 |
| Finished | Sep 24 02:26:41 PM UTC 24 |
| Peak memory | 235108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469324835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3469324835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/26.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.298986713 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 299818759983 ps |
| CPU time | 245.76 seconds |
| Started | Sep 24 02:26:36 PM UTC 24 |
| Finished | Sep 24 02:30:45 PM UTC 24 |
| Peak memory | 261920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298986713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.298986713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_intercept.851528634 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 1447421381 ps |
| CPU time | 9.51 seconds |
| Started | Sep 24 02:26:28 PM UTC 24 |
| Finished | Sep 24 02:26:39 PM UTC 24 |
| Peak memory | 245352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851528634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.851528634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/26.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_mailbox.2426735386 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 4048578170 ps |
| CPU time | 39.55 seconds |
| Started | Sep 24 02:26:31 PM UTC 24 |
| Finished | Sep 24 02:27:12 PM UTC 24 |
| Peak memory | 251684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426735386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2426735386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/26.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.632476813 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 468235701 ps |
| CPU time | 6.39 seconds |
| Started | Sep 24 02:26:23 PM UTC 24 |
| Finished | Sep 24 02:26:31 PM UTC 24 |
| Peak memory | 245416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632476813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.632476813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/26.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.2134705778 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 5431809991 ps |
| CPU time | 27.01 seconds |
| Started | Sep 24 02:26:18 PM UTC 24 |
| Finished | Sep 24 02:26:47 PM UTC 24 |
| Peak memory | 235216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134705778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2134705778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/26.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.2276202212 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 97200474 ps |
| CPU time | 4.3 seconds |
| Started | Sep 24 02:26:37 PM UTC 24 |
| Finished | Sep 24 02:26:42 PM UTC 24 |
| Peak memory | 233804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276202212 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.2276202212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/26.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.3007826811 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 11354176665 ps |
| CPU time | 77.66 seconds |
| Started | Sep 24 02:26:43 PM UTC 24 |
| Finished | Sep 24 02:28:03 PM UTC 24 |
| Peak memory | 268196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007826811 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.3007826811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/26.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_all.3387985641 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 1050753185 ps |
| CPU time | 16.27 seconds |
| Started | Sep 24 02:26:15 PM UTC 24 |
| Finished | Sep 24 02:26:32 PM UTC 24 |
| Peak memory | 231796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387985641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3387985641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/26.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.520990762 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 43018714441 ps |
| CPU time | 16.3 seconds |
| Started | Sep 24 02:26:15 PM UTC 24 |
| Finished | Sep 24 02:26:32 PM UTC 24 |
| Peak memory | 227876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520990762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.520990762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/26.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_rw.2644661116 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 504104466 ps |
| CPU time | 4.25 seconds |
| Started | Sep 24 02:26:17 PM UTC 24 |
| Finished | Sep 24 02:26:23 PM UTC 24 |
| Peak memory | 227888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644661116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2644661116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/26.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.3209436563 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 129522200 ps |
| CPU time | 1.33 seconds |
| Started | Sep 24 02:26:15 PM UTC 24 |
| Finished | Sep 24 02:26:17 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209436563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3209436563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/26.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/26.spi_device_upload.1784258585 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 2950476006 ps |
| CPU time | 23.11 seconds |
| Started | Sep 24 02:26:33 PM UTC 24 |
| Finished | Sep 24 02:26:58 PM UTC 24 |
| Peak memory | 261932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784258585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1784258585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/26.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_alert_test.1582165772 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 11777239 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 02:27:03 PM UTC 24 |
| Finished | Sep 24 02:27:05 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582165772 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.1582165772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/27.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_csb_read.3073887440 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 52174143 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 02:26:44 PM UTC 24 |
| Finished | Sep 24 02:26:47 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073887440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3073887440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/27.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.3285899367 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 15366567588 ps |
| CPU time | 50.76 seconds |
| Started | Sep 24 02:26:59 PM UTC 24 |
| Finished | Sep 24 02:27:51 PM UTC 24 |
| Peak memory | 245608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285899367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3285899367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/27.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.1334866135 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 250164602122 ps |
| CPU time | 718.64 seconds |
| Started | Sep 24 02:26:59 PM UTC 24 |
| Finished | Sep 24 02:39:06 PM UTC 24 |
| Peak memory | 278376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334866135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1334866135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.3005346647 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 53953726437 ps |
| CPU time | 68.13 seconds |
| Started | Sep 24 02:27:00 PM UTC 24 |
| Finished | Sep 24 02:28:10 PM UTC 24 |
| Peak memory | 249644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005346647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.3005346647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode.2940480396 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 989878713 ps |
| CPU time | 10.23 seconds |
| Started | Sep 24 02:26:56 PM UTC 24 |
| Finished | Sep 24 02:27:08 PM UTC 24 |
| Peak memory | 245352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940480396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2940480396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/27.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.1171547530 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 65049960120 ps |
| CPU time | 67.28 seconds |
| Started | Sep 24 02:26:58 PM UTC 24 |
| Finished | Sep 24 02:28:07 PM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171547530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.1171547530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_intercept.304651324 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 252660817 ps |
| CPU time | 5.21 seconds |
| Started | Sep 24 02:26:51 PM UTC 24 |
| Finished | Sep 24 02:26:57 PM UTC 24 |
| Peak memory | 235112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304651324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.304651324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/27.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_mailbox.1951591356 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 2156527134 ps |
| CPU time | 38.86 seconds |
| Started | Sep 24 02:26:51 PM UTC 24 |
| Finished | Sep 24 02:27:31 PM UTC 24 |
| Peak memory | 235240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951591356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1951591356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/27.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.4294858461 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 197937523 ps |
| CPU time | 3.75 seconds |
| Started | Sep 24 02:26:51 PM UTC 24 |
| Finished | Sep 24 02:26:56 PM UTC 24 |
| Peak memory | 235216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294858461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.4294858461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/27.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.1936977549 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 10827534124 ps |
| CPU time | 40.07 seconds |
| Started | Sep 24 02:26:49 PM UTC 24 |
| Finished | Sep 24 02:27:30 PM UTC 24 |
| Peak memory | 245532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936977549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1936977549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/27.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.3625922899 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 2145105731 ps |
| CPU time | 10.49 seconds |
| Started | Sep 24 02:26:59 PM UTC 24 |
| Finished | Sep 24 02:27:10 PM UTC 24 |
| Peak memory | 231548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625922899 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.3625922899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/27.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.1649309000 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 357665943 ps |
| CPU time | 1.65 seconds |
| Started | Sep 24 02:27:00 PM UTC 24 |
| Finished | Sep 24 02:27:03 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649309000 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.1649309000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/27.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_all.3780336139 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 7281335639 ps |
| CPU time | 47.63 seconds |
| Started | Sep 24 02:26:47 PM UTC 24 |
| Finished | Sep 24 02:27:37 PM UTC 24 |
| Peak memory | 227952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780336139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3780336139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/27.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.1707434472 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 871077916 ps |
| CPU time | 5.49 seconds |
| Started | Sep 24 02:26:46 PM UTC 24 |
| Finished | Sep 24 02:26:53 PM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707434472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1707434472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/27.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_rw.3976811007 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 37481588 ps |
| CPU time | 1.62 seconds |
| Started | Sep 24 02:26:48 PM UTC 24 |
| Finished | Sep 24 02:26:50 PM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976811007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3976811007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/27.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.238406879 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 132565061 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 02:26:48 PM UTC 24 |
| Finished | Sep 24 02:26:50 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238406879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.238406879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/27.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_upload.1399962547 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 115156019 ps |
| CPU time | 3.33 seconds |
| Started | Sep 24 02:26:54 PM UTC 24 |
| Finished | Sep 24 02:26:59 PM UTC 24 |
| Peak memory | 244976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399962547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1399962547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/27.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_alert_test.1298020506 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 41428482 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 02:27:30 PM UTC 24 |
| Finished | Sep 24 02:27:33 PM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298020506 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.1298020506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/28.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_cfg_cmd.1610947077 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 190493714 ps |
| CPU time | 5.87 seconds |
| Started | Sep 24 02:27:13 PM UTC 24 |
| Finished | Sep 24 02:27:20 PM UTC 24 |
| Peak memory | 245356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610947077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1610947077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/28.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_csb_read.1395688935 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 15550656 ps |
| CPU time | 1.07 seconds |
| Started | Sep 24 02:27:03 PM UTC 24 |
| Finished | Sep 24 02:27:05 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395688935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1395688935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/28.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_all.2581970110 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 234169024308 ps |
| CPU time | 224.82 seconds |
| Started | Sep 24 02:27:20 PM UTC 24 |
| Finished | Sep 24 02:31:09 PM UTC 24 |
| Peak memory | 263988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581970110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2581970110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/28.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.909221633 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 14297311290 ps |
| CPU time | 50.53 seconds |
| Started | Sep 24 02:27:22 PM UTC 24 |
| Finished | Sep 24 02:28:15 PM UTC 24 |
| Peak memory | 245540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909221633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.909221633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/28.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.1125376710 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 13385162993 ps |
| CPU time | 100.38 seconds |
| Started | Sep 24 02:27:23 PM UTC 24 |
| Finished | Sep 24 02:29:06 PM UTC 24 |
| Peak memory | 274216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125376710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.1125376710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode.2292746889 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 352686964 ps |
| CPU time | 14.27 seconds |
| Started | Sep 24 02:27:16 PM UTC 24 |
| Finished | Sep 24 02:27:31 PM UTC 24 |
| Peak memory | 251556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292746889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2292746889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/28.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.1914594495 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 6742236726 ps |
| CPU time | 97.23 seconds |
| Started | Sep 24 02:27:18 PM UTC 24 |
| Finished | Sep 24 02:28:57 PM UTC 24 |
| Peak memory | 268008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914594495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.1914594495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_intercept.3512505300 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1998773790 ps |
| CPU time | 10.52 seconds |
| Started | Sep 24 02:27:10 PM UTC 24 |
| Finished | Sep 24 02:27:21 PM UTC 24 |
| Peak memory | 235188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512505300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3512505300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/28.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_mailbox.3286104683 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 157309874 ps |
| CPU time | 5.78 seconds |
| Started | Sep 24 02:27:11 PM UTC 24 |
| Finished | Sep 24 02:27:18 PM UTC 24 |
| Peak memory | 245352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286104683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3286104683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/28.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.3390928450 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 5234502082 ps |
| CPU time | 20.66 seconds |
| Started | Sep 24 02:27:09 PM UTC 24 |
| Finished | Sep 24 02:27:31 PM UTC 24 |
| Peak memory | 245544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390928450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.3390928450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/28.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.369951302 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 21714492748 ps |
| CPU time | 29.83 seconds |
| Started | Sep 24 02:27:08 PM UTC 24 |
| Finished | Sep 24 02:27:40 PM UTC 24 |
| Peak memory | 245608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369951302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.369951302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/28.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.641603544 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 781601323 ps |
| CPU time | 15.07 seconds |
| Started | Sep 24 02:27:18 PM UTC 24 |
| Finished | Sep 24 02:27:34 PM UTC 24 |
| Peak memory | 233704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641603544 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.641603544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/28.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.1280044858 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 158133088779 ps |
| CPU time | 370.69 seconds |
| Started | Sep 24 02:27:23 PM UTC 24 |
| Finished | Sep 24 02:33:40 PM UTC 24 |
| Peak memory | 268072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280044858 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.1280044858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/28.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_all.2369230743 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 21449883090 ps |
| CPU time | 31.64 seconds |
| Started | Sep 24 02:27:06 PM UTC 24 |
| Finished | Sep 24 02:27:39 PM UTC 24 |
| Peak memory | 228016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369230743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2369230743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/28.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.3872374748 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 16176937247 ps |
| CPU time | 42.65 seconds |
| Started | Sep 24 02:27:06 PM UTC 24 |
| Finished | Sep 24 02:27:50 PM UTC 24 |
| Peak memory | 227896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872374748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3872374748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/28.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_rw.1958537233 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 140175561 ps |
| CPU time | 1.75 seconds |
| Started | Sep 24 02:27:07 PM UTC 24 |
| Finished | Sep 24 02:27:10 PM UTC 24 |
| Peak memory | 216752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958537233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1958537233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/28.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.328007398 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 61504614 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 02:27:06 PM UTC 24 |
| Finished | Sep 24 02:27:09 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328007398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.328007398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/28.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_upload.2107825363 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 40855829 ps |
| CPU time | 3.2 seconds |
| Started | Sep 24 02:27:11 PM UTC 24 |
| Finished | Sep 24 02:27:15 PM UTC 24 |
| Peak memory | 234920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107825363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2107825363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/28.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_alert_test.923572338 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 14236022 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 02:27:50 PM UTC 24 |
| Finished | Sep 24 02:27:53 PM UTC 24 |
| Peak memory | 213040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923572338 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.923572338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/29.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_cfg_cmd.1292496242 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 85406100 ps |
| CPU time | 3.71 seconds |
| Started | Sep 24 02:27:38 PM UTC 24 |
| Finished | Sep 24 02:27:43 PM UTC 24 |
| Peak memory | 245284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292496242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1292496242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/29.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_csb_read.3990480911 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 18707021 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 02:27:32 PM UTC 24 |
| Finished | Sep 24 02:27:34 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990480911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3990480911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/29.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.2279470511 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 15050302129 ps |
| CPU time | 128 seconds |
| Started | Sep 24 02:27:41 PM UTC 24 |
| Finished | Sep 24 02:29:52 PM UTC 24 |
| Peak memory | 261860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279470511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2279470511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/29.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.829183726 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 20277259093 ps |
| CPU time | 269.39 seconds |
| Started | Sep 24 02:27:43 PM UTC 24 |
| Finished | Sep 24 02:32:17 PM UTC 24 |
| Peak memory | 268072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829183726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.829183726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.562568444 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 7890915699 ps |
| CPU time | 122.97 seconds |
| Started | Sep 24 02:27:44 PM UTC 24 |
| Finished | Sep 24 02:29:50 PM UTC 24 |
| Peak memory | 261872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562568444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.562568444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode.826506258 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 779542289 ps |
| CPU time | 29.51 seconds |
| Started | Sep 24 02:27:38 PM UTC 24 |
| Finished | Sep 24 02:28:09 PM UTC 24 |
| Peak memory | 261860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826506258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.826506258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/29.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_intercept.2644057125 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 873872574 ps |
| CPU time | 10.72 seconds |
| Started | Sep 24 02:27:35 PM UTC 24 |
| Finished | Sep 24 02:27:48 PM UTC 24 |
| Peak memory | 245356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644057125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2644057125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/29.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_mailbox.1708544166 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 21042421342 ps |
| CPU time | 67.7 seconds |
| Started | Sep 24 02:27:36 PM UTC 24 |
| Finished | Sep 24 02:28:46 PM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708544166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1708544166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/29.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.53963943 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 558913189 ps |
| CPU time | 3.63 seconds |
| Started | Sep 24 02:27:35 PM UTC 24 |
| Finished | Sep 24 02:27:40 PM UTC 24 |
| Peak memory | 245476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53963943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.53963943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/29.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.2870355596 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 403138728 ps |
| CPU time | 6.93 seconds |
| Started | Sep 24 02:27:34 PM UTC 24 |
| Finished | Sep 24 02:27:43 PM UTC 24 |
| Peak memory | 251560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870355596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2870355596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/29.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.521875738 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 210844305 ps |
| CPU time | 6.94 seconds |
| Started | Sep 24 02:27:41 PM UTC 24 |
| Finished | Sep 24 02:27:49 PM UTC 24 |
| Peak memory | 233568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521875738 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.521875738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/29.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_stress_all.4143903257 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 87188894 ps |
| CPU time | 1.56 seconds |
| Started | Sep 24 02:27:48 PM UTC 24 |
| Finished | Sep 24 02:27:51 PM UTC 24 |
| Peak memory | 216320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143903257 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.4143903257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/29.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_all.3480202441 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 16112427098 ps |
| CPU time | 53.95 seconds |
| Started | Sep 24 02:27:33 PM UTC 24 |
| Finished | Sep 24 02:28:29 PM UTC 24 |
| Peak memory | 227996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480202441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3480202441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/29.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.530245121 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 4875347044 ps |
| CPU time | 31.08 seconds |
| Started | Sep 24 02:27:32 PM UTC 24 |
| Finished | Sep 24 02:28:05 PM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530245121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.530245121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/29.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_rw.540354389 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 49623166 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 02:27:33 PM UTC 24 |
| Finished | Sep 24 02:27:36 PM UTC 24 |
| Peak memory | 215096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540354389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.540354389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/29.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.941980377 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 217239871 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 02:27:33 PM UTC 24 |
| Finished | Sep 24 02:27:36 PM UTC 24 |
| Peak memory | 215036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941980377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.941980377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/29.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_upload.1188546511 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 20077720790 ps |
| CPU time | 10.82 seconds |
| Started | Sep 24 02:27:38 PM UTC 24 |
| Finished | Sep 24 02:27:50 PM UTC 24 |
| Peak memory | 245512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188546511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1188546511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/29.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.1995524146 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 15116632 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 02:13:36 PM UTC 24 |
| Finished | Sep 24 02:13:39 PM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995524146 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1995524146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.239840311 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 3926611749 ps |
| CPU time | 14.91 seconds |
| Started | Sep 24 02:13:21 PM UTC 24 |
| Finished | Sep 24 02:13:37 PM UTC 24 |
| Peak memory | 235228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239840311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.239840311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.3043001724 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 25077066 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 02:13:05 PM UTC 24 |
| Finished | Sep 24 02:13:07 PM UTC 24 |
| Peak memory | 215036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043001724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3043001724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.3116101576 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 22961449655 ps |
| CPU time | 208.91 seconds |
| Started | Sep 24 02:13:29 PM UTC 24 |
| Finished | Sep 24 02:17:02 PM UTC 24 |
| Peak memory | 278380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116101576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3116101576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.3924199382 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 802556772 ps |
| CPU time | 32.41 seconds |
| Started | Sep 24 02:13:29 PM UTC 24 |
| Finished | Sep 24 02:14:03 PM UTC 24 |
| Peak memory | 251624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924199382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3924199382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.1475104809 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1349220039 ps |
| CPU time | 6.94 seconds |
| Started | Sep 24 02:13:32 PM UTC 24 |
| Finished | Sep 24 02:13:40 PM UTC 24 |
| Peak memory | 229800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475104809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.1475104809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.4164065369 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 189619223 ps |
| CPU time | 4.92 seconds |
| Started | Sep 24 02:13:25 PM UTC 24 |
| Finished | Sep 24 02:13:31 PM UTC 24 |
| Peak memory | 245352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164065369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.4164065369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.3893348455 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 2508476404 ps |
| CPU time | 50.18 seconds |
| Started | Sep 24 02:13:28 PM UTC 24 |
| Finished | Sep 24 02:14:20 PM UTC 24 |
| Peak memory | 261924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893348455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.3893348455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.3566388318 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 895800653 ps |
| CPU time | 20.2 seconds |
| Started | Sep 24 02:13:12 PM UTC 24 |
| Finished | Sep 24 02:13:34 PM UTC 24 |
| Peak memory | 235040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566388318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3566388318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.1042867035 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 983288850 ps |
| CPU time | 14.61 seconds |
| Started | Sep 24 02:13:12 PM UTC 24 |
| Finished | Sep 24 02:13:28 PM UTC 24 |
| Peak memory | 245352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042867035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1042867035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.384884146 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 46965096 ps |
| CPU time | 1.6 seconds |
| Started | Sep 24 02:13:06 PM UTC 24 |
| Finished | Sep 24 02:13:09 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384884146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_parity.384884146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.1225774822 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 27781391619 ps |
| CPU time | 37.8 seconds |
| Started | Sep 24 02:13:11 PM UTC 24 |
| Finished | Sep 24 02:13:51 PM UTC 24 |
| Peak memory | 245544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225774822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.1225774822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.299056485 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 9159728015 ps |
| CPU time | 16.03 seconds |
| Started | Sep 24 02:13:11 PM UTC 24 |
| Finished | Sep 24 02:13:28 PM UTC 24 |
| Peak memory | 249644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299056485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.299056485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.2268717928 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 154247521 ps |
| CPU time | 5.87 seconds |
| Started | Sep 24 02:13:28 PM UTC 24 |
| Finished | Sep 24 02:13:35 PM UTC 24 |
| Peak memory | 231460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268717928 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.2268717928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.1631417355 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 57036839 ps |
| CPU time | 1.85 seconds |
| Started | Sep 24 02:13:36 PM UTC 24 |
| Finished | Sep 24 02:13:39 PM UTC 24 |
| Peak memory | 257648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631417355 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1631417355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.3855532006 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2651310817 ps |
| CPU time | 25.44 seconds |
| Started | Sep 24 02:13:09 PM UTC 24 |
| Finished | Sep 24 02:13:36 PM UTC 24 |
| Peak memory | 227884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855532006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3855532006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.2186508861 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 42512446 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 02:13:08 PM UTC 24 |
| Finished | Sep 24 02:13:10 PM UTC 24 |
| Peak memory | 215096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186508861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2186508861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.1229092587 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 366083752 ps |
| CPU time | 1.81 seconds |
| Started | Sep 24 02:13:10 PM UTC 24 |
| Finished | Sep 24 02:13:13 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229092587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1229092587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.1533818411 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 47037944 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 02:13:09 PM UTC 24 |
| Finished | Sep 24 02:13:11 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533818411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1533818411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.536813007 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 4413460688 ps |
| CPU time | 27.95 seconds |
| Started | Sep 24 02:13:14 PM UTC 24 |
| Finished | Sep 24 02:13:43 PM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536813007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.536813007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/3.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_alert_test.2663731850 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 25362290 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 02:28:14 PM UTC 24 |
| Finished | Sep 24 02:28:16 PM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663731850 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.2663731850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/30.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_cfg_cmd.3058102853 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 515399720 ps |
| CPU time | 9.33 seconds |
| Started | Sep 24 02:28:03 PM UTC 24 |
| Finished | Sep 24 02:28:14 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058102853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3058102853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/30.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_csb_read.3699976256 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 34333331 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 02:27:50 PM UTC 24 |
| Finished | Sep 24 02:27:53 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699976256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3699976256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/30.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_all.96691396 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2790815674 ps |
| CPU time | 48.9 seconds |
| Started | Sep 24 02:28:09 PM UTC 24 |
| Finished | Sep 24 02:28:59 PM UTC 24 |
| Peak memory | 261992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96691396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.96691396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/30.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.2484431691 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 10923067654 ps |
| CPU time | 17.46 seconds |
| Started | Sep 24 02:28:10 PM UTC 24 |
| Finished | Sep 24 02:28:29 PM UTC 24 |
| Peak memory | 232056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484431691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2484431691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/30.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.2472590830 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 3467291616 ps |
| CPU time | 33.45 seconds |
| Started | Sep 24 02:28:10 PM UTC 24 |
| Finished | Sep 24 02:28:45 PM UTC 24 |
| Peak memory | 261992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472590830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.2472590830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode.1872950998 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 1079123268 ps |
| CPU time | 12.32 seconds |
| Started | Sep 24 02:28:05 PM UTC 24 |
| Finished | Sep 24 02:28:19 PM UTC 24 |
| Peak memory | 261736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872950998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1872950998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/30.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.3843165591 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 34237986268 ps |
| CPU time | 153.54 seconds |
| Started | Sep 24 02:28:06 PM UTC 24 |
| Finished | Sep 24 02:30:42 PM UTC 24 |
| Peak memory | 261920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843165591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.3843165591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_intercept.2007964210 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 799088625 ps |
| CPU time | 7.87 seconds |
| Started | Sep 24 02:27:56 PM UTC 24 |
| Finished | Sep 24 02:28:05 PM UTC 24 |
| Peak memory | 235056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007964210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2007964210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/30.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_mailbox.2597790443 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 736048518 ps |
| CPU time | 20.49 seconds |
| Started | Sep 24 02:27:58 PM UTC 24 |
| Finished | Sep 24 02:28:20 PM UTC 24 |
| Peak memory | 251620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597790443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2597790443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/30.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.2066740036 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 1439867657 ps |
| CPU time | 6.6 seconds |
| Started | Sep 24 02:27:54 PM UTC 24 |
| Finished | Sep 24 02:28:02 PM UTC 24 |
| Peak memory | 245348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066740036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.2066740036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/30.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.965726752 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 2262033103 ps |
| CPU time | 17.64 seconds |
| Started | Sep 24 02:27:54 PM UTC 24 |
| Finished | Sep 24 02:28:13 PM UTC 24 |
| Peak memory | 235300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965726752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.965726752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/30.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.2001428919 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 1153855707 ps |
| CPU time | 5.87 seconds |
| Started | Sep 24 02:28:08 PM UTC 24 |
| Finished | Sep 24 02:28:15 PM UTC 24 |
| Peak memory | 231588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001428919 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.2001428919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/30.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.3584773075 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 7036803888 ps |
| CPU time | 70.93 seconds |
| Started | Sep 24 02:28:11 PM UTC 24 |
| Finished | Sep 24 02:29:24 PM UTC 24 |
| Peak memory | 262116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584773075 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.3584773075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/30.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_all.1603449680 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 7653427391 ps |
| CPU time | 16.5 seconds |
| Started | Sep 24 02:27:52 PM UTC 24 |
| Finished | Sep 24 02:28:10 PM UTC 24 |
| Peak memory | 227832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603449680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1603449680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/30.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.3820465439 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 11700909536 ps |
| CPU time | 35.07 seconds |
| Started | Sep 24 02:27:52 PM UTC 24 |
| Finished | Sep 24 02:28:28 PM UTC 24 |
| Peak memory | 227868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820465439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3820465439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/30.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_rw.3864893101 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 560763314 ps |
| CPU time | 3.75 seconds |
| Started | Sep 24 02:27:53 PM UTC 24 |
| Finished | Sep 24 02:27:58 PM UTC 24 |
| Peak memory | 227728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864893101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3864893101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/30.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.1642867824 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 64924439 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 02:27:53 PM UTC 24 |
| Finished | Sep 24 02:27:55 PM UTC 24 |
| Peak memory | 214576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642867824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1642867824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/30.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/30.spi_device_upload.3597800247 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 7147506086 ps |
| CPU time | 25.83 seconds |
| Started | Sep 24 02:28:02 PM UTC 24 |
| Finished | Sep 24 02:28:30 PM UTC 24 |
| Peak memory | 245600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597800247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3597800247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/30.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_alert_test.763928264 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 13694131 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 02:28:32 PM UTC 24 |
| Finished | Sep 24 02:28:34 PM UTC 24 |
| Peak memory | 215152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763928264 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.763928264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/31.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_cfg_cmd.344224521 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 260508226 ps |
| CPU time | 5.38 seconds |
| Started | Sep 24 02:28:22 PM UTC 24 |
| Finished | Sep 24 02:28:29 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344224521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.344224521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/31.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_csb_read.2870390535 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 11956828 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 02:28:14 PM UTC 24 |
| Finished | Sep 24 02:28:17 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870390535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2870390535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/31.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_all.3343311901 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 1942648051 ps |
| CPU time | 32.74 seconds |
| Started | Sep 24 02:28:30 PM UTC 24 |
| Finished | Sep 24 02:29:04 PM UTC 24 |
| Peak memory | 245416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343311901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3343311901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/31.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.2105650615 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 9850582169 ps |
| CPU time | 60.45 seconds |
| Started | Sep 24 02:28:30 PM UTC 24 |
| Finished | Sep 24 02:29:32 PM UTC 24 |
| Peak memory | 268064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105650615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2105650615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.227583338 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 324665302896 ps |
| CPU time | 345.89 seconds |
| Started | Sep 24 02:28:30 PM UTC 24 |
| Finished | Sep 24 02:34:21 PM UTC 24 |
| Peak memory | 268132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227583338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.227583338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode.40437945 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 3192106096 ps |
| CPU time | 37.41 seconds |
| Started | Sep 24 02:28:23 PM UTC 24 |
| Finished | Sep 24 02:29:02 PM UTC 24 |
| Peak memory | 235228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40437945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.40437945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/31.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.1869775991 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 43381947736 ps |
| CPU time | 222.13 seconds |
| Started | Sep 24 02:28:29 PM UTC 24 |
| Finished | Sep 24 02:32:16 PM UTC 24 |
| Peak memory | 268000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869775991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.1869775991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_intercept.2467319402 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 2498533970 ps |
| CPU time | 28.28 seconds |
| Started | Sep 24 02:28:20 PM UTC 24 |
| Finished | Sep 24 02:28:50 PM UTC 24 |
| Peak memory | 235380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467319402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2467319402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/31.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_mailbox.1557395762 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 54672747316 ps |
| CPU time | 143.1 seconds |
| Started | Sep 24 02:28:21 PM UTC 24 |
| Finished | Sep 24 02:30:47 PM UTC 24 |
| Peak memory | 261588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557395762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1557395762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/31.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.3516530144 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 9156039776 ps |
| CPU time | 10.46 seconds |
| Started | Sep 24 02:28:19 PM UTC 24 |
| Finished | Sep 24 02:28:30 PM UTC 24 |
| Peak memory | 235152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516530144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.3516530144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/31.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.1443288878 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 34161081 ps |
| CPU time | 3.17 seconds |
| Started | Sep 24 02:28:18 PM UTC 24 |
| Finished | Sep 24 02:28:22 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443288878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1443288878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/31.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.4050748189 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 4149321798 ps |
| CPU time | 14 seconds |
| Started | Sep 24 02:28:30 PM UTC 24 |
| Finished | Sep 24 02:28:45 PM UTC 24 |
| Peak memory | 233844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050748189 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.4050748189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/31.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.3523601796 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 68488293527 ps |
| CPU time | 157.39 seconds |
| Started | Sep 24 02:28:31 PM UTC 24 |
| Finished | Sep 24 02:31:11 PM UTC 24 |
| Peak memory | 264036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523601796 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.3523601796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/31.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_all.3151504867 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 4925364140 ps |
| CPU time | 21.34 seconds |
| Started | Sep 24 02:28:15 PM UTC 24 |
| Finished | Sep 24 02:28:38 PM UTC 24 |
| Peak memory | 227812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151504867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3151504867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/31.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.1841096189 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 5432256337 ps |
| CPU time | 15.78 seconds |
| Started | Sep 24 02:28:15 PM UTC 24 |
| Finished | Sep 24 02:28:32 PM UTC 24 |
| Peak memory | 227888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841096189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1841096189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/31.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_rw.4064000063 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 407801663 ps |
| CPU time | 2.39 seconds |
| Started | Sep 24 02:28:18 PM UTC 24 |
| Finished | Sep 24 02:28:21 PM UTC 24 |
| Peak memory | 227876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064000063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.4064000063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/31.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.1560794879 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 49878162 ps |
| CPU time | 1.53 seconds |
| Started | Sep 24 02:28:15 PM UTC 24 |
| Finished | Sep 24 02:28:18 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560794879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1560794879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/31.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_upload.2333512175 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 1226775780 ps |
| CPU time | 6.47 seconds |
| Started | Sep 24 02:28:21 PM UTC 24 |
| Finished | Sep 24 02:28:29 PM UTC 24 |
| Peak memory | 245160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333512175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2333512175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/31.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_alert_test.2002672709 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 14127330 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 02:28:51 PM UTC 24 |
| Finished | Sep 24 02:28:53 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002672709 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.2002672709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/32.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_cfg_cmd.523200078 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 456056250 ps |
| CPU time | 4.96 seconds |
| Started | Sep 24 02:28:43 PM UTC 24 |
| Finished | Sep 24 02:28:49 PM UTC 24 |
| Peak memory | 235096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523200078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.523200078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/32.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_csb_read.979762060 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 17355446 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 02:28:32 PM UTC 24 |
| Finished | Sep 24 02:28:35 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979762060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.979762060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/32.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_all.2949794608 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 53449482418 ps |
| CPU time | 164.58 seconds |
| Started | Sep 24 02:28:47 PM UTC 24 |
| Finished | Sep 24 02:31:35 PM UTC 24 |
| Peak memory | 268084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949794608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2949794608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/32.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.276381969 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 90428248868 ps |
| CPU time | 291.12 seconds |
| Started | Sep 24 02:28:47 PM UTC 24 |
| Finished | Sep 24 02:33:43 PM UTC 24 |
| Peak memory | 268064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276381969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.276381969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.1327817937 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 140324368789 ps |
| CPU time | 325.5 seconds |
| Started | Sep 24 02:28:49 PM UTC 24 |
| Finished | Sep 24 02:34:19 PM UTC 24 |
| Peak memory | 268004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327817937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.1327817937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode.3741055561 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 2135073274 ps |
| CPU time | 14.08 seconds |
| Started | Sep 24 02:28:43 PM UTC 24 |
| Finished | Sep 24 02:28:58 PM UTC 24 |
| Peak memory | 245548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741055561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3741055561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/32.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.216127518 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 2973399932 ps |
| CPU time | 57.57 seconds |
| Started | Sep 24 02:28:46 PM UTC 24 |
| Finished | Sep 24 02:29:45 PM UTC 24 |
| Peak memory | 251628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216127518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.216127518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_intercept.1239928923 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 96761699 ps |
| CPU time | 3.74 seconds |
| Started | Sep 24 02:28:38 PM UTC 24 |
| Finished | Sep 24 02:28:43 PM UTC 24 |
| Peak memory | 242116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239928923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1239928923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/32.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_mailbox.940130319 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 9763135460 ps |
| CPU time | 33.13 seconds |
| Started | Sep 24 02:28:39 PM UTC 24 |
| Finished | Sep 24 02:29:13 PM UTC 24 |
| Peak memory | 245480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940130319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.940130319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/32.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.3494842099 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 306149992 ps |
| CPU time | 8.42 seconds |
| Started | Sep 24 02:28:37 PM UTC 24 |
| Finished | Sep 24 02:28:46 PM UTC 24 |
| Peak memory | 245356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494842099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.3494842099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/32.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.2804848951 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 661676073 ps |
| CPU time | 5.1 seconds |
| Started | Sep 24 02:28:35 PM UTC 24 |
| Finished | Sep 24 02:28:42 PM UTC 24 |
| Peak memory | 245352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804848951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2804848951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/32.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.719907433 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 650050965 ps |
| CPU time | 5.61 seconds |
| Started | Sep 24 02:28:46 PM UTC 24 |
| Finished | Sep 24 02:28:53 PM UTC 24 |
| Peak memory | 233728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719907433 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.719907433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/32.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.2225896370 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 200527812 ps |
| CPU time | 1.64 seconds |
| Started | Sep 24 02:28:49 PM UTC 24 |
| Finished | Sep 24 02:28:52 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225896370 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.2225896370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/32.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_all.2534668228 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 127555705182 ps |
| CPU time | 58.91 seconds |
| Started | Sep 24 02:28:33 PM UTC 24 |
| Finished | Sep 24 02:29:34 PM UTC 24 |
| Peak memory | 227868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534668228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2534668228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/32.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.3593021975 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 9058749962 ps |
| CPU time | 27.83 seconds |
| Started | Sep 24 02:28:32 PM UTC 24 |
| Finished | Sep 24 02:29:01 PM UTC 24 |
| Peak memory | 227828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593021975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3593021975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/32.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_rw.3378460964 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 296967637 ps |
| CPU time | 11.48 seconds |
| Started | Sep 24 02:28:35 PM UTC 24 |
| Finished | Sep 24 02:28:48 PM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378460964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3378460964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/32.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.2840861513 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 101569555 ps |
| CPU time | 1.87 seconds |
| Started | Sep 24 02:28:33 PM UTC 24 |
| Finished | Sep 24 02:28:36 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840861513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2840861513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/32.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_upload.2414069102 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 2159206505 ps |
| CPU time | 10.95 seconds |
| Started | Sep 24 02:28:40 PM UTC 24 |
| Finished | Sep 24 02:28:52 PM UTC 24 |
| Peak memory | 251628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414069102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2414069102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/32.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_alert_test.3706197088 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 15141351 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 02:29:14 PM UTC 24 |
| Finished | Sep 24 02:29:16 PM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706197088 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.3706197088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/33.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_cfg_cmd.1015247926 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 107653564 ps |
| CPU time | 2.93 seconds |
| Started | Sep 24 02:29:03 PM UTC 24 |
| Finished | Sep 24 02:29:07 PM UTC 24 |
| Peak memory | 234664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015247926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1015247926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/33.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_csb_read.494529585 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 51408050 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 02:28:53 PM UTC 24 |
| Finished | Sep 24 02:28:55 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494529585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.494529585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/33.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_all.2528032845 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 7075998313 ps |
| CPU time | 29.09 seconds |
| Started | Sep 24 02:29:07 PM UTC 24 |
| Finished | Sep 24 02:29:37 PM UTC 24 |
| Peak memory | 261928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528032845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2528032845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/33.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.2211344481 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 6370672593 ps |
| CPU time | 104.45 seconds |
| Started | Sep 24 02:29:07 PM UTC 24 |
| Finished | Sep 24 02:30:54 PM UTC 24 |
| Peak memory | 266084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211344481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2211344481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.2235380120 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 8984242517 ps |
| CPU time | 55.99 seconds |
| Started | Sep 24 02:29:12 PM UTC 24 |
| Finished | Sep 24 02:30:10 PM UTC 24 |
| Peak memory | 245536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235380120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.2235380120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode.2512585156 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 3076471708 ps |
| CPU time | 16.12 seconds |
| Started | Sep 24 02:29:04 PM UTC 24 |
| Finished | Sep 24 02:29:21 PM UTC 24 |
| Peak memory | 245480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512585156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2512585156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/33.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.13683907 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 8047018820 ps |
| CPU time | 35.17 seconds |
| Started | Sep 24 02:29:05 PM UTC 24 |
| Finished | Sep 24 02:29:41 PM UTC 24 |
| Peak memory | 268064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13683907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.13683907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_intercept.1414960353 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 122406340 ps |
| CPU time | 3.16 seconds |
| Started | Sep 24 02:28:59 PM UTC 24 |
| Finished | Sep 24 02:29:03 PM UTC 24 |
| Peak memory | 233660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414960353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1414960353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/33.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_mailbox.2564209978 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 10139774896 ps |
| CPU time | 105.87 seconds |
| Started | Sep 24 02:28:59 PM UTC 24 |
| Finished | Sep 24 02:30:48 PM UTC 24 |
| Peak memory | 235244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564209978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2564209978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/33.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.1850957018 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 23845304682 ps |
| CPU time | 36.91 seconds |
| Started | Sep 24 02:28:58 PM UTC 24 |
| Finished | Sep 24 02:29:37 PM UTC 24 |
| Peak memory | 245468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850957018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.1850957018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/33.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.3812550062 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 47272221340 ps |
| CPU time | 16.2 seconds |
| Started | Sep 24 02:28:57 PM UTC 24 |
| Finished | Sep 24 02:29:14 PM UTC 24 |
| Peak memory | 245544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812550062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3812550062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/33.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.1543109271 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 332716685 ps |
| CPU time | 5.31 seconds |
| Started | Sep 24 02:29:05 PM UTC 24 |
| Finished | Sep 24 02:29:11 PM UTC 24 |
| Peak memory | 233780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543109271 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.1543109271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/33.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.307063291 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 179721927491 ps |
| CPU time | 717.28 seconds |
| Started | Sep 24 02:29:14 PM UTC 24 |
| Finished | Sep 24 02:41:22 PM UTC 24 |
| Peak memory | 294756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307063291 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.307063291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/33.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_all.3758933529 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 7223020863 ps |
| CPU time | 43.49 seconds |
| Started | Sep 24 02:28:54 PM UTC 24 |
| Finished | Sep 24 02:29:39 PM UTC 24 |
| Peak memory | 227812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758933529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3758933529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/33.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.2308234745 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 7724627424 ps |
| CPU time | 24.87 seconds |
| Started | Sep 24 02:28:53 PM UTC 24 |
| Finished | Sep 24 02:29:19 PM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308234745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2308234745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/33.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_rw.3082528040 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 107817112 ps |
| CPU time | 1.52 seconds |
| Started | Sep 24 02:28:56 PM UTC 24 |
| Finished | Sep 24 02:28:58 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082528040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3082528040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/33.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.861396892 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 18821523 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 02:28:54 PM UTC 24 |
| Finished | Sep 24 02:28:56 PM UTC 24 |
| Peak memory | 215036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861396892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.861396892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/33.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_upload.2008580100 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 4738495247 ps |
| CPU time | 15.12 seconds |
| Started | Sep 24 02:29:00 PM UTC 24 |
| Finished | Sep 24 02:29:17 PM UTC 24 |
| Peak memory | 251628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008580100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2008580100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/33.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_alert_test.2728965895 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 10900198 ps |
| CPU time | 0.91 seconds |
| Started | Sep 24 02:29:39 PM UTC 24 |
| Finished | Sep 24 02:29:41 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728965895 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.2728965895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/34.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_cfg_cmd.2707826350 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 33164892 ps |
| CPU time | 3.13 seconds |
| Started | Sep 24 02:29:30 PM UTC 24 |
| Finished | Sep 24 02:29:35 PM UTC 24 |
| Peak memory | 235112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707826350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2707826350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/34.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_csb_read.1639697365 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 27253923 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 02:29:15 PM UTC 24 |
| Finished | Sep 24 02:29:18 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639697365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1639697365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/34.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_all.1974627477 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 10515685041 ps |
| CPU time | 112.12 seconds |
| Started | Sep 24 02:29:36 PM UTC 24 |
| Finished | Sep 24 02:31:31 PM UTC 24 |
| Peak memory | 261936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974627477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1974627477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/34.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.1232092760 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 2064480690 ps |
| CPU time | 59.26 seconds |
| Started | Sep 24 02:29:37 PM UTC 24 |
| Finished | Sep 24 02:30:38 PM UTC 24 |
| Peak memory | 261792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232092760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1232092760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/34.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.3429259610 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 5639146216 ps |
| CPU time | 67.9 seconds |
| Started | Sep 24 02:29:38 PM UTC 24 |
| Finished | Sep 24 02:30:48 PM UTC 24 |
| Peak memory | 249700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429259610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.3429259610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode.541674086 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 467079514 ps |
| CPU time | 9.3 seconds |
| Started | Sep 24 02:29:32 PM UTC 24 |
| Finished | Sep 24 02:29:43 PM UTC 24 |
| Peak memory | 245412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541674086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.541674086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/34.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.124703883 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 223400375933 ps |
| CPU time | 208.67 seconds |
| Started | Sep 24 02:29:34 PM UTC 24 |
| Finished | Sep 24 02:33:06 PM UTC 24 |
| Peak memory | 264048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124703883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.124703883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_intercept.4105920133 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 5491900811 ps |
| CPU time | 24.9 seconds |
| Started | Sep 24 02:29:23 PM UTC 24 |
| Finished | Sep 24 02:29:50 PM UTC 24 |
| Peak memory | 245556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105920133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4105920133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/34.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_mailbox.336879207 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 4433847762 ps |
| CPU time | 69.26 seconds |
| Started | Sep 24 02:29:24 PM UTC 24 |
| Finished | Sep 24 02:30:36 PM UTC 24 |
| Peak memory | 263916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336879207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.336879207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/34.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.2200010671 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 417926981 ps |
| CPU time | 7.91 seconds |
| Started | Sep 24 02:29:22 PM UTC 24 |
| Finished | Sep 24 02:29:31 PM UTC 24 |
| Peak memory | 245276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200010671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.2200010671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/34.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.2240379737 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 5750497442 ps |
| CPU time | 12.61 seconds |
| Started | Sep 24 02:29:22 PM UTC 24 |
| Finished | Sep 24 02:29:36 PM UTC 24 |
| Peak memory | 235216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240379737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2240379737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/34.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.3420526264 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 380659834 ps |
| CPU time | 7.91 seconds |
| Started | Sep 24 02:29:35 PM UTC 24 |
| Finished | Sep 24 02:29:44 PM UTC 24 |
| Peak memory | 231588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420526264 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.3420526264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/34.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.2950546086 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 494808100790 ps |
| CPU time | 325.64 seconds |
| Started | Sep 24 02:29:38 PM UTC 24 |
| Finished | Sep 24 02:35:09 PM UTC 24 |
| Peak memory | 294744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950546086 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.2950546086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/34.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_all.597539023 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 3231759254 ps |
| CPU time | 37 seconds |
| Started | Sep 24 02:29:18 PM UTC 24 |
| Finished | Sep 24 02:29:56 PM UTC 24 |
| Peak memory | 227876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597539023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.597539023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/34.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.365327534 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 391559764 ps |
| CPU time | 2.98 seconds |
| Started | Sep 24 02:29:17 PM UTC 24 |
| Finished | Sep 24 02:29:21 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365327534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.365327534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/34.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_rw.2375751758 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 85329441 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 02:29:20 PM UTC 24 |
| Finished | Sep 24 02:29:22 PM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375751758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2375751758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/34.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.2202269308 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 78009169 ps |
| CPU time | 1.7 seconds |
| Started | Sep 24 02:29:20 PM UTC 24 |
| Finished | Sep 24 02:29:23 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202269308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2202269308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/34.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_upload.2802556663 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 6684882320 ps |
| CPU time | 11.34 seconds |
| Started | Sep 24 02:29:25 PM UTC 24 |
| Finished | Sep 24 02:29:38 PM UTC 24 |
| Peak memory | 251612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802556663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2802556663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/34.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_alert_test.499158361 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 40316787 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 02:30:02 PM UTC 24 |
| Finished | Sep 24 02:30:04 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499158361 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.499158361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/35.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_cfg_cmd.1687565036 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 348506765 ps |
| CPU time | 10.19 seconds |
| Started | Sep 24 02:29:51 PM UTC 24 |
| Finished | Sep 24 02:30:02 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687565036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1687565036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/35.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_csb_read.1670318258 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 20594623 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 02:29:40 PM UTC 24 |
| Finished | Sep 24 02:29:43 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670318258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1670318258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/35.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.1380055495 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 2554687328 ps |
| CPU time | 33.54 seconds |
| Started | Sep 24 02:30:01 PM UTC 24 |
| Finished | Sep 24 02:30:36 PM UTC 24 |
| Peak memory | 261880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380055495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1380055495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/35.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.2888054924 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 54051249796 ps |
| CPU time | 271.13 seconds |
| Started | Sep 24 02:30:01 PM UTC 24 |
| Finished | Sep 24 02:34:36 PM UTC 24 |
| Peak memory | 263972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888054924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2888054924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.1133125404 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 58358521377 ps |
| CPU time | 686.85 seconds |
| Started | Sep 24 02:30:02 PM UTC 24 |
| Finished | Sep 24 02:41:39 PM UTC 24 |
| Peak memory | 268072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133125404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.1133125404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode.1089705958 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 365903506 ps |
| CPU time | 6.95 seconds |
| Started | Sep 24 02:29:52 PM UTC 24 |
| Finished | Sep 24 02:30:00 PM UTC 24 |
| Peak memory | 235184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089705958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1089705958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/35.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.4227369572 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 34076197833 ps |
| CPU time | 91.24 seconds |
| Started | Sep 24 02:29:57 PM UTC 24 |
| Finished | Sep 24 02:31:31 PM UTC 24 |
| Peak memory | 247452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227369572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.4227369572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_intercept.712336395 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3336226170 ps |
| CPU time | 11.61 seconds |
| Started | Sep 24 02:29:47 PM UTC 24 |
| Finished | Sep 24 02:30:00 PM UTC 24 |
| Peak memory | 235144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712336395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.712336395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/35.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_mailbox.3602073008 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 10506420864 ps |
| CPU time | 20.78 seconds |
| Started | Sep 24 02:29:49 PM UTC 24 |
| Finished | Sep 24 02:30:11 PM UTC 24 |
| Peak memory | 245480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602073008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3602073008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/35.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.1003962241 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 944269389 ps |
| CPU time | 11.91 seconds |
| Started | Sep 24 02:29:47 PM UTC 24 |
| Finished | Sep 24 02:30:00 PM UTC 24 |
| Peak memory | 245336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003962241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.1003962241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/35.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.415808381 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 1299668531 ps |
| CPU time | 11.75 seconds |
| Started | Sep 24 02:29:45 PM UTC 24 |
| Finished | Sep 24 02:29:57 PM UTC 24 |
| Peak memory | 245444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415808381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.415808381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/35.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.81523722 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 1300889974 ps |
| CPU time | 6.15 seconds |
| Started | Sep 24 02:29:58 PM UTC 24 |
| Finished | Sep 24 02:30:06 PM UTC 24 |
| Peak memory | 233648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81523722 -assert nopostproc +UVM_TESTNAME=spi_device_bas e_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.81523722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/35.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.2270606910 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 166608453 ps |
| CPU time | 1.63 seconds |
| Started | Sep 24 02:30:02 PM UTC 24 |
| Finished | Sep 24 02:30:04 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270606910 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.2270606910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/35.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_all.3830682032 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 6037773047 ps |
| CPU time | 43.36 seconds |
| Started | Sep 24 02:29:42 PM UTC 24 |
| Finished | Sep 24 02:30:28 PM UTC 24 |
| Peak memory | 227872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830682032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3830682032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/35.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.884475682 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 16531120875 ps |
| CPU time | 17.48 seconds |
| Started | Sep 24 02:29:42 PM UTC 24 |
| Finished | Sep 24 02:30:01 PM UTC 24 |
| Peak memory | 227892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884475682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.884475682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/35.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_rw.3758303007 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 39959870 ps |
| CPU time | 2.03 seconds |
| Started | Sep 24 02:29:45 PM UTC 24 |
| Finished | Sep 24 02:29:48 PM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758303007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3758303007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/35.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.2218317638 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 53311039 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 02:29:43 PM UTC 24 |
| Finished | Sep 24 02:29:46 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218317638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2218317638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/35.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_upload.2044619253 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 5969618260 ps |
| CPU time | 17.18 seconds |
| Started | Sep 24 02:29:50 PM UTC 24 |
| Finished | Sep 24 02:30:08 PM UTC 24 |
| Peak memory | 235244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044619253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2044619253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/35.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_alert_test.2138266106 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 18521567 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 02:30:29 PM UTC 24 |
| Finished | Sep 24 02:30:31 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138266106 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.2138266106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/36.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_cfg_cmd.1166674791 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 240172401 ps |
| CPU time | 4.37 seconds |
| Started | Sep 24 02:30:12 PM UTC 24 |
| Finished | Sep 24 02:30:17 PM UTC 24 |
| Peak memory | 235088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166674791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1166674791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/36.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_csb_read.2475602946 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 39234309 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 02:30:03 PM UTC 24 |
| Finished | Sep 24 02:30:05 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475602946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2475602946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/36.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_all.1691945891 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 29613209629 ps |
| CPU time | 281.36 seconds |
| Started | Sep 24 02:30:18 PM UTC 24 |
| Finished | Sep 24 02:35:04 PM UTC 24 |
| Peak memory | 265968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691945891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1691945891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/36.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.1976487372 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 24244923877 ps |
| CPU time | 182.89 seconds |
| Started | Sep 24 02:30:20 PM UTC 24 |
| Finished | Sep 24 02:33:26 PM UTC 24 |
| Peak memory | 266084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976487372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1976487372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/36.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.3332031287 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 9315277884 ps |
| CPU time | 32.92 seconds |
| Started | Sep 24 02:30:22 PM UTC 24 |
| Finished | Sep 24 02:30:57 PM UTC 24 |
| Peak memory | 245416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332031287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.3332031287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode.4156362318 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 512772424 ps |
| CPU time | 18.94 seconds |
| Started | Sep 24 02:30:12 PM UTC 24 |
| Finished | Sep 24 02:30:32 PM UTC 24 |
| Peak memory | 235176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156362318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.4156362318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/36.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.2320979767 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 22979486746 ps |
| CPU time | 52.81 seconds |
| Started | Sep 24 02:30:14 PM UTC 24 |
| Finished | Sep 24 02:31:08 PM UTC 24 |
| Peak memory | 261852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320979767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.2320979767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_intercept.3756660030 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 2273952235 ps |
| CPU time | 10.8 seconds |
| Started | Sep 24 02:30:10 PM UTC 24 |
| Finished | Sep 24 02:30:21 PM UTC 24 |
| Peak memory | 235240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756660030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3756660030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/36.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_mailbox.2902909662 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 1793842016 ps |
| CPU time | 9.03 seconds |
| Started | Sep 24 02:30:10 PM UTC 24 |
| Finished | Sep 24 02:30:20 PM UTC 24 |
| Peak memory | 235172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902909662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2902909662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/36.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.118352804 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 44411082205 ps |
| CPU time | 21.44 seconds |
| Started | Sep 24 02:30:08 PM UTC 24 |
| Finished | Sep 24 02:30:31 PM UTC 24 |
| Peak memory | 235292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118352804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.118352804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/36.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.4088126486 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 3127471598 ps |
| CPU time | 3.66 seconds |
| Started | Sep 24 02:30:08 PM UTC 24 |
| Finished | Sep 24 02:30:13 PM UTC 24 |
| Peak memory | 245472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088126486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.4088126486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/36.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.3467790482 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 155937604 ps |
| CPU time | 4.27 seconds |
| Started | Sep 24 02:30:17 PM UTC 24 |
| Finished | Sep 24 02:30:22 PM UTC 24 |
| Peak memory | 231588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467790482 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.3467790482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/36.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.770992552 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 8387879453 ps |
| CPU time | 67.8 seconds |
| Started | Sep 24 02:30:24 PM UTC 24 |
| Finished | Sep 24 02:31:33 PM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770992552 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.770992552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/36.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_all.2320460633 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 11758472 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 02:30:05 PM UTC 24 |
| Finished | Sep 24 02:30:07 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320460633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2320460633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/36.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.175180587 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 162067066 ps |
| CPU time | 1.85 seconds |
| Started | Sep 24 02:30:05 PM UTC 24 |
| Finished | Sep 24 02:30:08 PM UTC 24 |
| Peak memory | 217156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175180587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.175180587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/36.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_rw.957131317 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 54459919 ps |
| CPU time | 3.5 seconds |
| Started | Sep 24 02:30:06 PM UTC 24 |
| Finished | Sep 24 02:30:11 PM UTC 24 |
| Peak memory | 227828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957131317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.957131317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/36.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.2858814176 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 33438118 ps |
| CPU time | 1.14 seconds |
| Started | Sep 24 02:30:06 PM UTC 24 |
| Finished | Sep 24 02:30:08 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858814176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2858814176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/36.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_upload.1420660843 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 659569561 ps |
| CPU time | 4.45 seconds |
| Started | Sep 24 02:30:11 PM UTC 24 |
| Finished | Sep 24 02:30:16 PM UTC 24 |
| Peak memory | 235096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420660843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1420660843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/36.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_alert_test.3695857595 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 157017907 ps |
| CPU time | 0.97 seconds |
| Started | Sep 24 02:30:54 PM UTC 24 |
| Finished | Sep 24 02:30:56 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695857595 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.3695857595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/37.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_cfg_cmd.3493242359 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 3912136116 ps |
| CPU time | 16.78 seconds |
| Started | Sep 24 02:30:44 PM UTC 24 |
| Finished | Sep 24 02:31:02 PM UTC 24 |
| Peak memory | 235164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493242359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3493242359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/37.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_csb_read.1107522899 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 58858896 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 02:30:32 PM UTC 24 |
| Finished | Sep 24 02:30:34 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107522899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1107522899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/37.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.3201304485 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 43281156532 ps |
| CPU time | 199.96 seconds |
| Started | Sep 24 02:30:49 PM UTC 24 |
| Finished | Sep 24 02:34:12 PM UTC 24 |
| Peak memory | 268016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201304485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3201304485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/37.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.3795295288 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 15161629365 ps |
| CPU time | 67.55 seconds |
| Started | Sep 24 02:30:49 PM UTC 24 |
| Finished | Sep 24 02:31:58 PM UTC 24 |
| Peak memory | 261924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795295288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3795295288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/37.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.151886682 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 20513277897 ps |
| CPU time | 112.28 seconds |
| Started | Sep 24 02:30:49 PM UTC 24 |
| Finished | Sep 24 02:32:44 PM UTC 24 |
| Peak memory | 266088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151886682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.151886682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode.1083146947 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 3015642670 ps |
| CPU time | 16.31 seconds |
| Started | Sep 24 02:30:45 PM UTC 24 |
| Finished | Sep 24 02:31:02 PM UTC 24 |
| Peak memory | 261916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083146947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1083146947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/37.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.3477556205 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 35106290263 ps |
| CPU time | 321.26 seconds |
| Started | Sep 24 02:30:46 PM UTC 24 |
| Finished | Sep 24 02:36:12 PM UTC 24 |
| Peak memory | 278236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477556205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.3477556205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_intercept.3950429904 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 355068219 ps |
| CPU time | 7.23 seconds |
| Started | Sep 24 02:30:39 PM UTC 24 |
| Finished | Sep 24 02:30:48 PM UTC 24 |
| Peak memory | 245428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950429904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3950429904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/37.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_mailbox.1123869139 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 147699140 ps |
| CPU time | 2.97 seconds |
| Started | Sep 24 02:30:39 PM UTC 24 |
| Finished | Sep 24 02:30:43 PM UTC 24 |
| Peak memory | 234328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123869139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1123869139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/37.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.1655079936 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 2395505669 ps |
| CPU time | 14.84 seconds |
| Started | Sep 24 02:30:38 PM UTC 24 |
| Finished | Sep 24 02:30:54 PM UTC 24 |
| Peak memory | 230052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655079936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.1655079936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/37.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.2738732930 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 2656049907 ps |
| CPU time | 20.49 seconds |
| Started | Sep 24 02:30:36 PM UTC 24 |
| Finished | Sep 24 02:30:58 PM UTC 24 |
| Peak memory | 245544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738732930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2738732930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/37.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.4166870280 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 843181862 ps |
| CPU time | 7.26 seconds |
| Started | Sep 24 02:30:48 PM UTC 24 |
| Finished | Sep 24 02:30:56 PM UTC 24 |
| Peak memory | 231660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166870280 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.4166870280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/37.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.4046094150 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 67584110289 ps |
| CPU time | 211.75 seconds |
| Started | Sep 24 02:30:51 PM UTC 24 |
| Finished | Sep 24 02:34:26 PM UTC 24 |
| Peak memory | 278300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046094150 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.4046094150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/37.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_all.2321949326 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 923265439 ps |
| CPU time | 19.89 seconds |
| Started | Sep 24 02:30:33 PM UTC 24 |
| Finished | Sep 24 02:30:54 PM UTC 24 |
| Peak memory | 231856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321949326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2321949326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/37.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.150608373 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 2809785208 ps |
| CPU time | 10.27 seconds |
| Started | Sep 24 02:30:32 PM UTC 24 |
| Finished | Sep 24 02:30:43 PM UTC 24 |
| Peak memory | 227800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150608373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.150608373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/37.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_rw.1290382472 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 246278723 ps |
| CPU time | 1.81 seconds |
| Started | Sep 24 02:30:36 PM UTC 24 |
| Finished | Sep 24 02:30:39 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290382472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1290382472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/37.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.2162452602 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 81928932 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 02:30:35 PM UTC 24 |
| Finished | Sep 24 02:30:37 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162452602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2162452602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/37.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_upload.3682314148 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 7072814802 ps |
| CPU time | 23.4 seconds |
| Started | Sep 24 02:30:43 PM UTC 24 |
| Finished | Sep 24 02:31:07 PM UTC 24 |
| Peak memory | 235364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682314148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3682314148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/37.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_alert_test.2591932273 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 42515769 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 02:31:12 PM UTC 24 |
| Finished | Sep 24 02:31:15 PM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591932273 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.2591932273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/38.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_cfg_cmd.604775162 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 1350871242 ps |
| CPU time | 14.15 seconds |
| Started | Sep 24 02:31:03 PM UTC 24 |
| Finished | Sep 24 02:31:18 PM UTC 24 |
| Peak memory | 235044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604775162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.604775162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/38.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_csb_read.990036593 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 15824026 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 02:30:56 PM UTC 24 |
| Finished | Sep 24 02:30:58 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990036593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.990036593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/38.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_all.532073475 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 13303448294 ps |
| CPU time | 62.76 seconds |
| Started | Sep 24 02:31:10 PM UTC 24 |
| Finished | Sep 24 02:32:15 PM UTC 24 |
| Peak memory | 268068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532073475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.532073475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/38.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.154010610 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 24167410018 ps |
| CPU time | 159.26 seconds |
| Started | Sep 24 02:31:10 PM UTC 24 |
| Finished | Sep 24 02:33:53 PM UTC 24 |
| Peak memory | 245592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154010610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.154010610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/38.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.1268763652 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 19968310097 ps |
| CPU time | 286.98 seconds |
| Started | Sep 24 02:31:12 PM UTC 24 |
| Finished | Sep 24 02:36:04 PM UTC 24 |
| Peak memory | 276332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268763652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.1268763652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode.355058134 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 100349664 ps |
| CPU time | 7 seconds |
| Started | Sep 24 02:31:04 PM UTC 24 |
| Finished | Sep 24 02:31:12 PM UTC 24 |
| Peak memory | 261920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355058134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.355058134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/38.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.2990394000 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 28423366118 ps |
| CPU time | 254.07 seconds |
| Started | Sep 24 02:31:09 PM UTC 24 |
| Finished | Sep 24 02:35:27 PM UTC 24 |
| Peak memory | 263916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990394000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.2990394000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_intercept.1396786279 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 2151474025 ps |
| CPU time | 21.44 seconds |
| Started | Sep 24 02:31:01 PM UTC 24 |
| Finished | Sep 24 02:31:24 PM UTC 24 |
| Peak memory | 235256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396786279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1396786279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/38.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_mailbox.3769204655 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 2959130179 ps |
| CPU time | 25.83 seconds |
| Started | Sep 24 02:31:01 PM UTC 24 |
| Finished | Sep 24 02:31:28 PM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769204655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3769204655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/38.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.4068283813 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 2023306812 ps |
| CPU time | 11.15 seconds |
| Started | Sep 24 02:30:59 PM UTC 24 |
| Finished | Sep 24 02:31:11 PM UTC 24 |
| Peak memory | 245276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068283813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.4068283813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/38.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.1032474728 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 4195103328 ps |
| CPU time | 12.59 seconds |
| Started | Sep 24 02:30:59 PM UTC 24 |
| Finished | Sep 24 02:31:13 PM UTC 24 |
| Peak memory | 245396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032474728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1032474728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/38.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.621981854 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 239519157 ps |
| CPU time | 4.94 seconds |
| Started | Sep 24 02:31:10 PM UTC 24 |
| Finished | Sep 24 02:31:16 PM UTC 24 |
| Peak memory | 233776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621981854 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.621981854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/38.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.2488791863 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 41721261241 ps |
| CPU time | 455.47 seconds |
| Started | Sep 24 02:31:12 PM UTC 24 |
| Finished | Sep 24 02:38:55 PM UTC 24 |
| Peak memory | 261924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488791863 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.2488791863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/38.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_all.1556461825 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 8180713695 ps |
| CPU time | 36.86 seconds |
| Started | Sep 24 02:30:57 PM UTC 24 |
| Finished | Sep 24 02:31:35 PM UTC 24 |
| Peak memory | 227808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556461825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1556461825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/38.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.4183530078 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 13972057983 ps |
| CPU time | 21.15 seconds |
| Started | Sep 24 02:30:56 PM UTC 24 |
| Finished | Sep 24 02:31:18 PM UTC 24 |
| Peak memory | 227944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183530078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.4183530078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/38.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_rw.4100322399 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 109913168 ps |
| CPU time | 1.84 seconds |
| Started | Sep 24 02:30:58 PM UTC 24 |
| Finished | Sep 24 02:31:01 PM UTC 24 |
| Peak memory | 226604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100322399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4100322399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/38.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.2751100112 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 81900259 ps |
| CPU time | 1.57 seconds |
| Started | Sep 24 02:30:58 PM UTC 24 |
| Finished | Sep 24 02:31:00 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751100112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2751100112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/38.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_upload.1084377608 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 5274207752 ps |
| CPU time | 19.78 seconds |
| Started | Sep 24 02:31:02 PM UTC 24 |
| Finished | Sep 24 02:31:24 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084377608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1084377608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/38.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_alert_test.3744108866 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 31734800 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 02:31:36 PM UTC 24 |
| Finished | Sep 24 02:31:38 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744108866 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.3744108866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/39.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_cfg_cmd.2705346860 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 272441802 ps |
| CPU time | 3.85 seconds |
| Started | Sep 24 02:31:29 PM UTC 24 |
| Finished | Sep 24 02:31:35 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705346860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2705346860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/39.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_csb_read.2881352671 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 28716918 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 02:31:14 PM UTC 24 |
| Finished | Sep 24 02:31:16 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881352671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2881352671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/39.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.2843964966 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 13310230179 ps |
| CPU time | 120.83 seconds |
| Started | Sep 24 02:31:34 PM UTC 24 |
| Finished | Sep 24 02:33:37 PM UTC 24 |
| Peak memory | 245556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843964966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2843964966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/39.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.887500295 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 10599874115 ps |
| CPU time | 163.22 seconds |
| Started | Sep 24 02:31:35 PM UTC 24 |
| Finished | Sep 24 02:34:21 PM UTC 24 |
| Peak memory | 278444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887500295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.887500295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/39.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.3956171550 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 14688856868 ps |
| CPU time | 148.19 seconds |
| Started | Sep 24 02:31:36 PM UTC 24 |
| Finished | Sep 24 02:34:07 PM UTC 24 |
| Peak memory | 264104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956171550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.3956171550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.3453325879 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 229043253 ps |
| CPU time | 11.4 seconds |
| Started | Sep 24 02:31:32 PM UTC 24 |
| Finished | Sep 24 02:31:45 PM UTC 24 |
| Peak memory | 235172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453325879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3453325879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/39.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.1828365979 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 1655627841 ps |
| CPU time | 14.67 seconds |
| Started | Sep 24 02:31:32 PM UTC 24 |
| Finished | Sep 24 02:31:48 PM UTC 24 |
| Peak memory | 247468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828365979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.1828365979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_intercept.2204525584 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 28396957549 ps |
| CPU time | 59.11 seconds |
| Started | Sep 24 02:31:23 PM UTC 24 |
| Finished | Sep 24 02:32:24 PM UTC 24 |
| Peak memory | 245492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204525584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2204525584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/39.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_mailbox.2842038534 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 782618248 ps |
| CPU time | 23.4 seconds |
| Started | Sep 24 02:31:24 PM UTC 24 |
| Finished | Sep 24 02:31:49 PM UTC 24 |
| Peak memory | 261804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842038534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2842038534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/39.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.344799641 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 12165115597 ps |
| CPU time | 55.85 seconds |
| Started | Sep 24 02:31:20 PM UTC 24 |
| Finished | Sep 24 02:32:18 PM UTC 24 |
| Peak memory | 235164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344799641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.344799641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/39.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.1652811544 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 9466905848 ps |
| CPU time | 31.04 seconds |
| Started | Sep 24 02:31:19 PM UTC 24 |
| Finished | Sep 24 02:31:52 PM UTC 24 |
| Peak memory | 245544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652811544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1652811544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/39.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.2128078347 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 371501888 ps |
| CPU time | 7.05 seconds |
| Started | Sep 24 02:31:33 PM UTC 24 |
| Finished | Sep 24 02:31:41 PM UTC 24 |
| Peak memory | 233924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128078347 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.2128078347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/39.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.2899889949 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1196748108 ps |
| CPU time | 43.77 seconds |
| Started | Sep 24 02:31:36 PM UTC 24 |
| Finished | Sep 24 02:32:22 PM UTC 24 |
| Peak memory | 263904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899889949 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.2899889949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/39.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.1376354760 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 43865474371 ps |
| CPU time | 32.25 seconds |
| Started | Sep 24 02:31:17 PM UTC 24 |
| Finished | Sep 24 02:31:51 PM UTC 24 |
| Peak memory | 227884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376354760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1376354760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/39.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.2721933704 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 83305534186 ps |
| CPU time | 17 seconds |
| Started | Sep 24 02:31:16 PM UTC 24 |
| Finished | Sep 24 02:31:34 PM UTC 24 |
| Peak memory | 227752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721933704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2721933704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/39.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_rw.73077252 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 42348855 ps |
| CPU time | 1.85 seconds |
| Started | Sep 24 02:31:19 PM UTC 24 |
| Finished | Sep 24 02:31:22 PM UTC 24 |
| Peak memory | 227084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73077252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_devi ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.73077252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/39.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.224682779 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 29078520 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 02:31:17 PM UTC 24 |
| Finished | Sep 24 02:31:19 PM UTC 24 |
| Peak memory | 215036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224682779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.224682779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/39.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_upload.1628181151 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 3273669888 ps |
| CPU time | 23.85 seconds |
| Started | Sep 24 02:31:25 PM UTC 24 |
| Finished | Sep 24 02:31:51 PM UTC 24 |
| Peak memory | 251684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628181151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1628181151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/39.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.2624118048 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 26526841 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 02:14:05 PM UTC 24 |
| Finished | Sep 24 02:14:07 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624118048 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2624118048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.3831779046 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 48316918 ps |
| CPU time | 3.89 seconds |
| Started | Sep 24 02:13:50 PM UTC 24 |
| Finished | Sep 24 02:13:55 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831779046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3831779046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.4052452813 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 63601492 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 02:13:38 PM UTC 24 |
| Finished | Sep 24 02:13:40 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052452813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.4052452813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.1848813848 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 45699244755 ps |
| CPU time | 434.98 seconds |
| Started | Sep 24 02:13:53 PM UTC 24 |
| Finished | Sep 24 02:21:14 PM UTC 24 |
| Peak memory | 261920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848813848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1848813848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.1246818891 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 181532814672 ps |
| CPU time | 380.34 seconds |
| Started | Sep 24 02:13:55 PM UTC 24 |
| Finished | Sep 24 02:20:21 PM UTC 24 |
| Peak memory | 264108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246818891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1246818891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.1090511211 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 29025066248 ps |
| CPU time | 178.57 seconds |
| Started | Sep 24 02:13:57 PM UTC 24 |
| Finished | Sep 24 02:16:59 PM UTC 24 |
| Peak memory | 245536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090511211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.1090511211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.2178416373 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 2367690634 ps |
| CPU time | 25.55 seconds |
| Started | Sep 24 02:13:50 PM UTC 24 |
| Finished | Sep 24 02:14:16 PM UTC 24 |
| Peak memory | 235244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178416373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2178416373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.2615034828 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 28219530041 ps |
| CPU time | 89.06 seconds |
| Started | Sep 24 02:13:52 PM UTC 24 |
| Finished | Sep 24 02:15:23 PM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615034828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.2615034828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.3239826575 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 115904337 ps |
| CPU time | 3.95 seconds |
| Started | Sep 24 02:13:44 PM UTC 24 |
| Finished | Sep 24 02:13:49 PM UTC 24 |
| Peak memory | 235172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239826575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3239826575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.4141716869 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 113739272 ps |
| CPU time | 4.44 seconds |
| Started | Sep 24 02:13:46 PM UTC 24 |
| Finished | Sep 24 02:13:52 PM UTC 24 |
| Peak memory | 245352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141716869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4141716869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.281916535 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 338375884 ps |
| CPU time | 1.63 seconds |
| Started | Sep 24 02:13:40 PM UTC 24 |
| Finished | Sep 24 02:13:42 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281916535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_parity.281916535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.1317901089 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1003144445 ps |
| CPU time | 10.67 seconds |
| Started | Sep 24 02:13:44 PM UTC 24 |
| Finished | Sep 24 02:13:56 PM UTC 24 |
| Peak memory | 245412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317901089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.1317901089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.2195039477 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 125227891 ps |
| CPU time | 4.5 seconds |
| Started | Sep 24 02:13:43 PM UTC 24 |
| Finished | Sep 24 02:13:49 PM UTC 24 |
| Peak memory | 245404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195039477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2195039477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.4232223939 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 3510778502 ps |
| CPU time | 12.64 seconds |
| Started | Sep 24 02:13:52 PM UTC 24 |
| Finished | Sep 24 02:14:06 PM UTC 24 |
| Peak memory | 231720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232223939 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.4232223939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.378845332 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 62559446 ps |
| CPU time | 1.81 seconds |
| Started | Sep 24 02:14:03 PM UTC 24 |
| Finished | Sep 24 02:14:05 PM UTC 24 |
| Peak memory | 257644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378845332 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.378845332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.4235364503 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 62839223 ps |
| CPU time | 1.71 seconds |
| Started | Sep 24 02:13:59 PM UTC 24 |
| Finished | Sep 24 02:14:02 PM UTC 24 |
| Peak memory | 216928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235364503 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.4235364503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.687160113 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 5641208496 ps |
| CPU time | 36.42 seconds |
| Started | Sep 24 02:13:40 PM UTC 24 |
| Finished | Sep 24 02:14:18 PM UTC 24 |
| Peak memory | 227948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687160113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.687160113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2507643749 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 9030457266 ps |
| CPU time | 25.27 seconds |
| Started | Sep 24 02:13:40 PM UTC 24 |
| Finished | Sep 24 02:14:06 PM UTC 24 |
| Peak memory | 227764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507643749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2507643749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.334087251 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 70913964 ps |
| CPU time | 4.69 seconds |
| Started | Sep 24 02:13:41 PM UTC 24 |
| Finished | Sep 24 02:13:47 PM UTC 24 |
| Peak memory | 227680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334087251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.334087251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.2694179800 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 518122975 ps |
| CPU time | 1.68 seconds |
| Started | Sep 24 02:13:41 PM UTC 24 |
| Finished | Sep 24 02:13:44 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694179800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2694179800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.1101213581 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 769958942 ps |
| CPU time | 9.66 seconds |
| Started | Sep 24 02:13:48 PM UTC 24 |
| Finished | Sep 24 02:13:58 PM UTC 24 |
| Peak memory | 235088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101213581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1101213581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/4.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.3071464708 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 13956878 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 02:32:07 PM UTC 24 |
| Finished | Sep 24 02:32:09 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071464708 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.3071464708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/40.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_cfg_cmd.2487843911 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 7324558034 ps |
| CPU time | 20.59 seconds |
| Started | Sep 24 02:31:52 PM UTC 24 |
| Finished | Sep 24 02:32:14 PM UTC 24 |
| Peak memory | 245544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487843911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2487843911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/40.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_csb_read.2089590641 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 69451846 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 02:31:39 PM UTC 24 |
| Finished | Sep 24 02:31:42 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089590641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2089590641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/40.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.4199988943 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 1193557764 ps |
| CPU time | 11.48 seconds |
| Started | Sep 24 02:31:59 PM UTC 24 |
| Finished | Sep 24 02:32:11 PM UTC 24 |
| Peak memory | 245352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199988943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.4199988943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/40.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.3937132397 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 4692309920 ps |
| CPU time | 146.33 seconds |
| Started | Sep 24 02:32:00 PM UTC 24 |
| Finished | Sep 24 02:34:29 PM UTC 24 |
| Peak memory | 282404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937132397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3937132397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.1998998172 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 1140022590 ps |
| CPU time | 6.44 seconds |
| Started | Sep 24 02:32:02 PM UTC 24 |
| Finished | Sep 24 02:32:09 PM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998998172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.1998998172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.2046017729 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 1149379867 ps |
| CPU time | 11.04 seconds |
| Started | Sep 24 02:31:54 PM UTC 24 |
| Finished | Sep 24 02:32:07 PM UTC 24 |
| Peak memory | 235244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046017729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2046017729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/40.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.3869925625 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 13633466417 ps |
| CPU time | 86.42 seconds |
| Started | Sep 24 02:31:57 PM UTC 24 |
| Finished | Sep 24 02:33:25 PM UTC 24 |
| Peak memory | 263916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869925625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.3869925625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_intercept.1246925774 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 269046423 ps |
| CPU time | 5.74 seconds |
| Started | Sep 24 02:31:51 PM UTC 24 |
| Finished | Sep 24 02:31:58 PM UTC 24 |
| Peak memory | 245364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246925774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1246925774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/40.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.3420110140 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 291178847 ps |
| CPU time | 8.2 seconds |
| Started | Sep 24 02:31:52 PM UTC 24 |
| Finished | Sep 24 02:32:01 PM UTC 24 |
| Peak memory | 242104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420110140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3420110140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/40.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.2892565797 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 616824241 ps |
| CPU time | 2.77 seconds |
| Started | Sep 24 02:31:50 PM UTC 24 |
| Finished | Sep 24 02:31:54 PM UTC 24 |
| Peak memory | 245352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892565797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.2892565797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/40.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.4101342199 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 676694243 ps |
| CPU time | 16.13 seconds |
| Started | Sep 24 02:31:49 PM UTC 24 |
| Finished | Sep 24 02:32:06 PM UTC 24 |
| Peak memory | 251556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101342199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4101342199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/40.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.1372797048 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 980422912 ps |
| CPU time | 14.9 seconds |
| Started | Sep 24 02:31:59 PM UTC 24 |
| Finished | Sep 24 02:32:15 PM UTC 24 |
| Peak memory | 233716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372797048 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.1372797048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/40.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.4254709297 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 493102009025 ps |
| CPU time | 443.67 seconds |
| Started | Sep 24 02:32:07 PM UTC 24 |
| Finished | Sep 24 02:39:38 PM UTC 24 |
| Peak memory | 262048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254709297 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.4254709297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/40.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.3881331795 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 7856920742 ps |
| CPU time | 26.11 seconds |
| Started | Sep 24 02:31:43 PM UTC 24 |
| Finished | Sep 24 02:32:10 PM UTC 24 |
| Peak memory | 227940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881331795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3881331795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/40.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.2465480752 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 5085336090 ps |
| CPU time | 11.85 seconds |
| Started | Sep 24 02:31:43 PM UTC 24 |
| Finished | Sep 24 02:31:56 PM UTC 24 |
| Peak memory | 227744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465480752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2465480752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/40.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_rw.1839369197 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 144695321 ps |
| CPU time | 2 seconds |
| Started | Sep 24 02:31:49 PM UTC 24 |
| Finished | Sep 24 02:31:52 PM UTC 24 |
| Peak memory | 216672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839369197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1839369197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/40.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.2676217245 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 97979718 ps |
| CPU time | 1.4 seconds |
| Started | Sep 24 02:31:46 PM UTC 24 |
| Finished | Sep 24 02:31:48 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676217245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2676217245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/40.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.4281849225 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 21070795175 ps |
| CPU time | 29.9 seconds |
| Started | Sep 24 02:31:52 PM UTC 24 |
| Finished | Sep 24 02:32:24 PM UTC 24 |
| Peak memory | 245408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281849225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.4281849225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/40.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.1823460594 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 16585739 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 02:32:25 PM UTC 24 |
| Finished | Sep 24 02:32:27 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823460594 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.1823460594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/41.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.350617152 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 1351007478 ps |
| CPU time | 7.21 seconds |
| Started | Sep 24 02:32:16 PM UTC 24 |
| Finished | Sep 24 02:32:24 PM UTC 24 |
| Peak memory | 235044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350617152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.350617152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/41.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.2659673947 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 44123864 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 02:32:07 PM UTC 24 |
| Finished | Sep 24 02:32:10 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659673947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2659673947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/41.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.992796954 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 23182668647 ps |
| CPU time | 87.51 seconds |
| Started | Sep 24 02:32:19 PM UTC 24 |
| Finished | Sep 24 02:33:49 PM UTC 24 |
| Peak memory | 268000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992796954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.992796954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/41.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.2565592575 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 12422005271 ps |
| CPU time | 206.81 seconds |
| Started | Sep 24 02:32:23 PM UTC 24 |
| Finished | Sep 24 02:35:53 PM UTC 24 |
| Peak memory | 278432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565592575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2565592575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.3011844834 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 10830149834 ps |
| CPU time | 112.66 seconds |
| Started | Sep 24 02:32:24 PM UTC 24 |
| Finished | Sep 24 02:34:19 PM UTC 24 |
| Peak memory | 261860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011844834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.3011844834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.2361173254 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 3502264410 ps |
| CPU time | 17.48 seconds |
| Started | Sep 24 02:32:17 PM UTC 24 |
| Finished | Sep 24 02:32:36 PM UTC 24 |
| Peak memory | 235240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361173254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2361173254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/41.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.3907216134 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 9849441581 ps |
| CPU time | 123.18 seconds |
| Started | Sep 24 02:32:18 PM UTC 24 |
| Finished | Sep 24 02:34:24 PM UTC 24 |
| Peak memory | 261856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907216134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.3907216134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.1705576060 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 2321679163 ps |
| CPU time | 26.07 seconds |
| Started | Sep 24 02:32:15 PM UTC 24 |
| Finished | Sep 24 02:32:42 PM UTC 24 |
| Peak memory | 242308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705576060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1705576060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/41.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.3263742561 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 4096785729 ps |
| CPU time | 43.25 seconds |
| Started | Sep 24 02:32:16 PM UTC 24 |
| Finished | Sep 24 02:33:01 PM UTC 24 |
| Peak memory | 245608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263742561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3263742561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/41.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.658343201 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 71847664 ps |
| CPU time | 3.5 seconds |
| Started | Sep 24 02:32:14 PM UTC 24 |
| Finished | Sep 24 02:32:18 PM UTC 24 |
| Peak memory | 245420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658343201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.658343201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/41.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.2419246575 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 32983403802 ps |
| CPU time | 20.98 seconds |
| Started | Sep 24 02:32:13 PM UTC 24 |
| Finished | Sep 24 02:32:35 PM UTC 24 |
| Peak memory | 245288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419246575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2419246575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/41.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.207544342 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 8304438175 ps |
| CPU time | 14.4 seconds |
| Started | Sep 24 02:32:18 PM UTC 24 |
| Finished | Sep 24 02:32:34 PM UTC 24 |
| Peak memory | 233920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207544342 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.207544342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/41.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.1130655942 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 46731586578 ps |
| CPU time | 243.95 seconds |
| Started | Sep 24 02:32:25 PM UTC 24 |
| Finished | Sep 24 02:36:32 PM UTC 24 |
| Peak memory | 280232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130655942 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.1130655942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/41.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.680531406 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1573574848 ps |
| CPU time | 21.52 seconds |
| Started | Sep 24 02:32:10 PM UTC 24 |
| Finished | Sep 24 02:32:33 PM UTC 24 |
| Peak memory | 227688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680531406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.680531406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/41.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.2909262830 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 757683419 ps |
| CPU time | 12.26 seconds |
| Started | Sep 24 02:32:10 PM UTC 24 |
| Finished | Sep 24 02:32:24 PM UTC 24 |
| Peak memory | 227788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909262830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2909262830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/41.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.3784847645 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 54578995 ps |
| CPU time | 2.18 seconds |
| Started | Sep 24 02:32:12 PM UTC 24 |
| Finished | Sep 24 02:32:15 PM UTC 24 |
| Peak memory | 227752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784847645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3784847645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/41.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.204637182 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 23738954 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 02:32:10 PM UTC 24 |
| Finished | Sep 24 02:32:13 PM UTC 24 |
| Peak memory | 215036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204637182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.204637182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/41.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.1900254508 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 204275659 ps |
| CPU time | 5.37 seconds |
| Started | Sep 24 02:32:16 PM UTC 24 |
| Finished | Sep 24 02:32:22 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900254508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1900254508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/41.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.2092874658 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 16708606 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 02:32:46 PM UTC 24 |
| Finished | Sep 24 02:32:48 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092874658 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.2092874658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/42.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.1537154970 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 3890027053 ps |
| CPU time | 9.08 seconds |
| Started | Sep 24 02:32:37 PM UTC 24 |
| Finished | Sep 24 02:32:47 PM UTC 24 |
| Peak memory | 235156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537154970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1537154970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/42.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.1644496780 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 31865415 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 02:32:25 PM UTC 24 |
| Finished | Sep 24 02:32:27 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644496780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1644496780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/42.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.3721084750 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 50845229626 ps |
| CPU time | 60.11 seconds |
| Started | Sep 24 02:32:41 PM UTC 24 |
| Finished | Sep 24 02:33:43 PM UTC 24 |
| Peak memory | 261872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721084750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3721084750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/42.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.797350699 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 103041353353 ps |
| CPU time | 123.01 seconds |
| Started | Sep 24 02:32:43 PM UTC 24 |
| Finished | Sep 24 02:34:49 PM UTC 24 |
| Peak memory | 282468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797350699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.797350699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.1004039829 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 6518185989 ps |
| CPU time | 61.47 seconds |
| Started | Sep 24 02:32:44 PM UTC 24 |
| Finished | Sep 24 02:33:48 PM UTC 24 |
| Peak memory | 235300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004039829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.1004039829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.3998576831 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 360357027 ps |
| CPU time | 4.82 seconds |
| Started | Sep 24 02:32:38 PM UTC 24 |
| Finished | Sep 24 02:32:44 PM UTC 24 |
| Peak memory | 245408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998576831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3998576831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/42.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.2209540246 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 35460272798 ps |
| CPU time | 100.57 seconds |
| Started | Sep 24 02:32:38 PM UTC 24 |
| Finished | Sep 24 02:34:21 PM UTC 24 |
| Peak memory | 268016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209540246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.2209540246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.1162535366 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 115297356 ps |
| CPU time | 2.93 seconds |
| Started | Sep 24 02:32:34 PM UTC 24 |
| Finished | Sep 24 02:32:38 PM UTC 24 |
| Peak memory | 245048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162535366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1162535366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/42.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.1645684801 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 9073870561 ps |
| CPU time | 91.76 seconds |
| Started | Sep 24 02:32:36 PM UTC 24 |
| Finished | Sep 24 02:34:09 PM UTC 24 |
| Peak memory | 235180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645684801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1645684801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/42.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.1105179051 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 15994056909 ps |
| CPU time | 10.64 seconds |
| Started | Sep 24 02:32:34 PM UTC 24 |
| Finished | Sep 24 02:32:46 PM UTC 24 |
| Peak memory | 235308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105179051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.1105179051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/42.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.3248778056 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 330688498 ps |
| CPU time | 4.91 seconds |
| Started | Sep 24 02:32:31 PM UTC 24 |
| Finished | Sep 24 02:32:37 PM UTC 24 |
| Peak memory | 245480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248778056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3248778056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/42.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.904762429 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 83092446 ps |
| CPU time | 4.93 seconds |
| Started | Sep 24 02:32:39 PM UTC 24 |
| Finished | Sep 24 02:32:45 PM UTC 24 |
| Peak memory | 233712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904762429 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.904762429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/42.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.3072741828 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 34876616437 ps |
| CPU time | 372.36 seconds |
| Started | Sep 24 02:32:44 PM UTC 24 |
| Finished | Sep 24 02:39:02 PM UTC 24 |
| Peak memory | 284576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072741828 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.3072741828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/42.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.847846968 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 11249939 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 02:32:28 PM UTC 24 |
| Finished | Sep 24 02:32:30 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847846968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.847846968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/42.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.3051237668 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 2100915202 ps |
| CPU time | 14.49 seconds |
| Started | Sep 24 02:32:25 PM UTC 24 |
| Finished | Sep 24 02:32:41 PM UTC 24 |
| Peak memory | 227584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051237668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3051237668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/42.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.1630418788 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 333457065 ps |
| CPU time | 4.61 seconds |
| Started | Sep 24 02:32:31 PM UTC 24 |
| Finished | Sep 24 02:32:37 PM UTC 24 |
| Peak memory | 227688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630418788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1630418788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/42.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.2606521319 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 238784428 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 02:32:28 PM UTC 24 |
| Finished | Sep 24 02:32:30 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606521319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2606521319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/42.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.3277699656 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 13120565954 ps |
| CPU time | 19.75 seconds |
| Started | Sep 24 02:32:37 PM UTC 24 |
| Finished | Sep 24 02:32:58 PM UTC 24 |
| Peak memory | 235228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277699656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3277699656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/42.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.1150251882 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 28855625 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 02:33:22 PM UTC 24 |
| Finished | Sep 24 02:33:25 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150251882 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.1150251882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/43.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.2100256777 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 318467630 ps |
| CPU time | 9.56 seconds |
| Started | Sep 24 02:33:07 PM UTC 24 |
| Finished | Sep 24 02:33:18 PM UTC 24 |
| Peak memory | 235044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100256777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2100256777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/43.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.1560163121 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 50441841 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 02:32:47 PM UTC 24 |
| Finished | Sep 24 02:32:49 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560163121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1560163121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/43.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.3323213723 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 2185473145 ps |
| CPU time | 46.7 seconds |
| Started | Sep 24 02:33:15 PM UTC 24 |
| Finished | Sep 24 02:34:03 PM UTC 24 |
| Peak memory | 261872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323213723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3323213723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/43.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.1385053852 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 367101017675 ps |
| CPU time | 263.84 seconds |
| Started | Sep 24 02:33:18 PM UTC 24 |
| Finished | Sep 24 02:37:46 PM UTC 24 |
| Peak memory | 268136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385053852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1385053852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.1046765410 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 13025105868 ps |
| CPU time | 146.2 seconds |
| Started | Sep 24 02:33:18 PM UTC 24 |
| Finished | Sep 24 02:35:47 PM UTC 24 |
| Peak memory | 266152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046765410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.1046765410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.4106346573 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 482265083 ps |
| CPU time | 13.91 seconds |
| Started | Sep 24 02:33:09 PM UTC 24 |
| Finished | Sep 24 02:33:24 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106346573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4106346573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/43.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.3893745386 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 11564500533 ps |
| CPU time | 131.64 seconds |
| Started | Sep 24 02:33:11 PM UTC 24 |
| Finished | Sep 24 02:35:25 PM UTC 24 |
| Peak memory | 265956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893745386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.3893745386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.899359868 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 409988306 ps |
| CPU time | 10.46 seconds |
| Started | Sep 24 02:32:58 PM UTC 24 |
| Finished | Sep 24 02:33:10 PM UTC 24 |
| Peak memory | 245484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899359868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.899359868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/43.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.1655294700 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 5164858752 ps |
| CPU time | 16.93 seconds |
| Started | Sep 24 02:32:59 PM UTC 24 |
| Finished | Sep 24 02:33:18 PM UTC 24 |
| Peak memory | 235112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655294700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1655294700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/43.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.3831029665 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 2724102359 ps |
| CPU time | 18.51 seconds |
| Started | Sep 24 02:32:57 PM UTC 24 |
| Finished | Sep 24 02:33:17 PM UTC 24 |
| Peak memory | 245416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831029665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.3831029665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/43.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.126035185 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 5454273393 ps |
| CPU time | 15.61 seconds |
| Started | Sep 24 02:32:56 PM UTC 24 |
| Finished | Sep 24 02:33:13 PM UTC 24 |
| Peak memory | 251684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126035185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.126035185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/43.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.147198268 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 438262344 ps |
| CPU time | 6.36 seconds |
| Started | Sep 24 02:33:14 PM UTC 24 |
| Finished | Sep 24 02:33:21 PM UTC 24 |
| Peak memory | 233712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147198268 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.147198268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/43.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.1843037328 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 6883253831 ps |
| CPU time | 97.49 seconds |
| Started | Sep 24 02:33:18 PM UTC 24 |
| Finished | Sep 24 02:34:58 PM UTC 24 |
| Peak memory | 268076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843037328 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.1843037328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/43.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.4290116913 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 3081536759 ps |
| CPU time | 23.79 seconds |
| Started | Sep 24 02:32:49 PM UTC 24 |
| Finished | Sep 24 02:33:14 PM UTC 24 |
| Peak memory | 227808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290116913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.4290116913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/43.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.4293014401 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 3053494207 ps |
| CPU time | 9.96 seconds |
| Started | Sep 24 02:32:48 PM UTC 24 |
| Finished | Sep 24 02:32:59 PM UTC 24 |
| Peak memory | 227716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293014401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.4293014401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/43.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.3080704661 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 71221431 ps |
| CPU time | 2.87 seconds |
| Started | Sep 24 02:32:53 PM UTC 24 |
| Finished | Sep 24 02:32:57 PM UTC 24 |
| Peak memory | 227684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080704661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3080704661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/43.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.1359089974 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 19680551 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 02:32:50 PM UTC 24 |
| Finished | Sep 24 02:32:52 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359089974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1359089974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/43.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.3119748448 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 305427035 ps |
| CPU time | 5.73 seconds |
| Started | Sep 24 02:33:02 PM UTC 24 |
| Finished | Sep 24 02:33:08 PM UTC 24 |
| Peak memory | 245352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119748448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3119748448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/43.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.3318957588 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 34566484 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 02:33:51 PM UTC 24 |
| Finished | Sep 24 02:33:53 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318957588 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.3318957588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/44.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.2515109512 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 52552837 ps |
| CPU time | 3.19 seconds |
| Started | Sep 24 02:33:40 PM UTC 24 |
| Finished | Sep 24 02:33:45 PM UTC 24 |
| Peak memory | 234692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515109512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2515109512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/44.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.1718750215 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 46519362 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 02:33:25 PM UTC 24 |
| Finished | Sep 24 02:33:27 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718750215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1718750215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/44.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.324708605 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 3414273444 ps |
| CPU time | 55.36 seconds |
| Started | Sep 24 02:33:46 PM UTC 24 |
| Finished | Sep 24 02:34:43 PM UTC 24 |
| Peak memory | 261864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324708605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.324708605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/44.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.4039086574 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 10892780921 ps |
| CPU time | 101.44 seconds |
| Started | Sep 24 02:33:49 PM UTC 24 |
| Finished | Sep 24 02:35:33 PM UTC 24 |
| Peak memory | 268136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039086574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.4039086574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.1799725106 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 9762423645 ps |
| CPU time | 89.23 seconds |
| Started | Sep 24 02:33:50 PM UTC 24 |
| Finished | Sep 24 02:35:21 PM UTC 24 |
| Peak memory | 268136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799725106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.1799725106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.2610475164 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 865316719 ps |
| CPU time | 8.55 seconds |
| Started | Sep 24 02:33:41 PM UTC 24 |
| Finished | Sep 24 02:33:50 PM UTC 24 |
| Peak memory | 245352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610475164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2610475164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/44.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.3636910934 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 104147042975 ps |
| CPU time | 209.7 seconds |
| Started | Sep 24 02:33:44 PM UTC 24 |
| Finished | Sep 24 02:37:17 PM UTC 24 |
| Peak memory | 261992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636910934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.3636910934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.4071911750 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 7292266312 ps |
| CPU time | 28.55 seconds |
| Started | Sep 24 02:33:36 PM UTC 24 |
| Finished | Sep 24 02:34:06 PM UTC 24 |
| Peak memory | 235300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071911750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.4071911750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/44.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.3573753084 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 1799431065 ps |
| CPU time | 19.22 seconds |
| Started | Sep 24 02:33:38 PM UTC 24 |
| Finished | Sep 24 02:33:59 PM UTC 24 |
| Peak memory | 245416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573753084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3573753084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/44.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2977283025 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 292338529 ps |
| CPU time | 6.77 seconds |
| Started | Sep 24 02:33:32 PM UTC 24 |
| Finished | Sep 24 02:33:40 PM UTC 24 |
| Peak memory | 245416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977283025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.2977283025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/44.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.28277823 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 2068915656 ps |
| CPU time | 5.9 seconds |
| Started | Sep 24 02:33:30 PM UTC 24 |
| Finished | Sep 24 02:33:37 PM UTC 24 |
| Peak memory | 245416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28277823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.28277823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/44.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.736232704 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 847795161 ps |
| CPU time | 13.5 seconds |
| Started | Sep 24 02:33:45 PM UTC 24 |
| Finished | Sep 24 02:33:59 PM UTC 24 |
| Peak memory | 233588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736232704 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.736232704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/44.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.1876903361 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 7059905112 ps |
| CPU time | 43.97 seconds |
| Started | Sep 24 02:33:50 PM UTC 24 |
| Finished | Sep 24 02:34:36 PM UTC 24 |
| Peak memory | 249580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876903361 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.1876903361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/44.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.715347980 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 12333269759 ps |
| CPU time | 50.41 seconds |
| Started | Sep 24 02:33:26 PM UTC 24 |
| Finished | Sep 24 02:34:18 PM UTC 24 |
| Peak memory | 228008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715347980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.715347980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/44.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.4141752333 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 528372106 ps |
| CPU time | 8.31 seconds |
| Started | Sep 24 02:33:26 PM UTC 24 |
| Finished | Sep 24 02:33:35 PM UTC 24 |
| Peak memory | 227704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141752333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.4141752333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/44.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.3812838199 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 222611648 ps |
| CPU time | 2.37 seconds |
| Started | Sep 24 02:33:28 PM UTC 24 |
| Finished | Sep 24 02:33:31 PM UTC 24 |
| Peak memory | 227736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812838199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3812838199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/44.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.2851836490 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 59547581 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 02:33:27 PM UTC 24 |
| Finished | Sep 24 02:33:29 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851836490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2851836490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/44.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.2829070115 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 682462810 ps |
| CPU time | 9.07 seconds |
| Started | Sep 24 02:33:38 PM UTC 24 |
| Finished | Sep 24 02:33:49 PM UTC 24 |
| Peak memory | 235120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829070115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2829070115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/44.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.1689422111 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 40662874 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 02:34:15 PM UTC 24 |
| Finished | Sep 24 02:34:17 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689422111 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.1689422111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/45.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.2181687775 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 777735590 ps |
| CPU time | 8.83 seconds |
| Started | Sep 24 02:34:04 PM UTC 24 |
| Finished | Sep 24 02:34:14 PM UTC 24 |
| Peak memory | 245468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181687775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2181687775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/45.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.2713485616 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 33673691 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 02:33:53 PM UTC 24 |
| Finished | Sep 24 02:33:56 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713485616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2713485616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/45.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.2725685914 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 37756712959 ps |
| CPU time | 98.96 seconds |
| Started | Sep 24 02:34:08 PM UTC 24 |
| Finished | Sep 24 02:35:49 PM UTC 24 |
| Peak memory | 261872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725685914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2725685914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/45.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.1243155832 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 9281840262 ps |
| CPU time | 90.74 seconds |
| Started | Sep 24 02:34:10 PM UTC 24 |
| Finished | Sep 24 02:35:43 PM UTC 24 |
| Peak memory | 247648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243155832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1243155832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.380757403 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 43788459262 ps |
| CPU time | 165.7 seconds |
| Started | Sep 24 02:34:11 PM UTC 24 |
| Finished | Sep 24 02:37:00 PM UTC 24 |
| Peak memory | 278188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380757403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.380757403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.4196515996 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 9335861243 ps |
| CPU time | 44.57 seconds |
| Started | Sep 24 02:34:05 PM UTC 24 |
| Finished | Sep 24 02:34:52 PM UTC 24 |
| Peak memory | 245536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196515996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.4196515996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/45.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.2773768951 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 25868810429 ps |
| CPU time | 227.63 seconds |
| Started | Sep 24 02:34:06 PM UTC 24 |
| Finished | Sep 24 02:37:57 PM UTC 24 |
| Peak memory | 268072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773768951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.2773768951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.880827205 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 45843208 ps |
| CPU time | 3.47 seconds |
| Started | Sep 24 02:34:00 PM UTC 24 |
| Finished | Sep 24 02:34:05 PM UTC 24 |
| Peak memory | 235176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880827205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.880827205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/45.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.2186553280 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 1902044742 ps |
| CPU time | 23.49 seconds |
| Started | Sep 24 02:34:02 PM UTC 24 |
| Finished | Sep 24 02:34:27 PM UTC 24 |
| Peak memory | 251496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186553280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2186553280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/45.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.3925471871 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 1217140699 ps |
| CPU time | 8.14 seconds |
| Started | Sep 24 02:34:00 PM UTC 24 |
| Finished | Sep 24 02:34:09 PM UTC 24 |
| Peak memory | 245356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925471871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.3925471871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/45.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.2840441520 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 269035154 ps |
| CPU time | 3.2 seconds |
| Started | Sep 24 02:34:00 PM UTC 24 |
| Finished | Sep 24 02:34:04 PM UTC 24 |
| Peak memory | 234260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840441520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2840441520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/45.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.90729073 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 293854798 ps |
| CPU time | 5.77 seconds |
| Started | Sep 24 02:34:08 PM UTC 24 |
| Finished | Sep 24 02:34:14 PM UTC 24 |
| Peak memory | 231596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90729073 -assert nopostproc +UVM_TESTNAME=spi_device_bas e_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.90729073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/45.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.1205315017 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 55446129597 ps |
| CPU time | 284.57 seconds |
| Started | Sep 24 02:34:13 PM UTC 24 |
| Finished | Sep 24 02:39:02 PM UTC 24 |
| Peak memory | 284444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205315017 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.1205315017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/45.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.1086801577 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 20615908105 ps |
| CPU time | 42.94 seconds |
| Started | Sep 24 02:33:56 PM UTC 24 |
| Finished | Sep 24 02:34:40 PM UTC 24 |
| Peak memory | 227812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086801577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1086801577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/45.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.1763256983 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 102611308 ps |
| CPU time | 2.36 seconds |
| Started | Sep 24 02:33:54 PM UTC 24 |
| Finished | Sep 24 02:33:58 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763256983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1763256983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/45.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.4253191753 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 59210504 ps |
| CPU time | 1.68 seconds |
| Started | Sep 24 02:33:59 PM UTC 24 |
| Finished | Sep 24 02:34:02 PM UTC 24 |
| Peak memory | 226896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253191753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.4253191753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/45.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.1989468048 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 27787485 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 02:33:57 PM UTC 24 |
| Finished | Sep 24 02:33:59 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989468048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1989468048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/45.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.4025456302 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 12579201851 ps |
| CPU time | 38.14 seconds |
| Started | Sep 24 02:34:04 PM UTC 24 |
| Finished | Sep 24 02:34:44 PM UTC 24 |
| Peak memory | 245424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025456302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.4025456302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/45.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.3752705794 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 14570218 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 02:34:32 PM UTC 24 |
| Finished | Sep 24 02:34:34 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752705794 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.3752705794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/46.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.3928309121 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 765764470 ps |
| CPU time | 9.92 seconds |
| Started | Sep 24 02:34:22 PM UTC 24 |
| Finished | Sep 24 02:34:33 PM UTC 24 |
| Peak memory | 235096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928309121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3928309121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/46.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.1045617039 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 22059262 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 02:34:15 PM UTC 24 |
| Finished | Sep 24 02:34:17 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045617039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1045617039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/46.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.4213769845 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 26234432618 ps |
| CPU time | 43.6 seconds |
| Started | Sep 24 02:34:28 PM UTC 24 |
| Finished | Sep 24 02:35:13 PM UTC 24 |
| Peak memory | 245476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213769845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.4213769845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/46.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.539843783 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 133177456516 ps |
| CPU time | 317.23 seconds |
| Started | Sep 24 02:34:30 PM UTC 24 |
| Finished | Sep 24 02:39:52 PM UTC 24 |
| Peak memory | 261932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539843783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.539843783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/46.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.1137406567 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 11898287102 ps |
| CPU time | 51.1 seconds |
| Started | Sep 24 02:34:31 PM UTC 24 |
| Finished | Sep 24 02:35:24 PM UTC 24 |
| Peak memory | 261992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137406567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.1137406567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.549713363 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 842901860 ps |
| CPU time | 15.08 seconds |
| Started | Sep 24 02:34:22 PM UTC 24 |
| Finished | Sep 24 02:34:39 PM UTC 24 |
| Peak memory | 245412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549713363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.549713363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/46.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.2862539203 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 6802688798 ps |
| CPU time | 18.58 seconds |
| Started | Sep 24 02:34:24 PM UTC 24 |
| Finished | Sep 24 02:34:44 PM UTC 24 |
| Peak memory | 235232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862539203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.2862539203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.1332692771 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 305140064 ps |
| CPU time | 6.46 seconds |
| Started | Sep 24 02:34:22 PM UTC 24 |
| Finished | Sep 24 02:34:30 PM UTC 24 |
| Peak memory | 235180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332692771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1332692771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/46.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.4072652382 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 13518563183 ps |
| CPU time | 71.65 seconds |
| Started | Sep 24 02:34:22 PM UTC 24 |
| Finished | Sep 24 02:35:36 PM UTC 24 |
| Peak memory | 247524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072652382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.4072652382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/46.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.438755662 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 11555369488 ps |
| CPU time | 8.44 seconds |
| Started | Sep 24 02:34:21 PM UTC 24 |
| Finished | Sep 24 02:34:30 PM UTC 24 |
| Peak memory | 235180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438755662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.438755662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/46.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.612905674 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 4304188376 ps |
| CPU time | 11.31 seconds |
| Started | Sep 24 02:34:20 PM UTC 24 |
| Finished | Sep 24 02:34:32 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612905674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.612905674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/46.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.135703500 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 1380771514 ps |
| CPU time | 15.99 seconds |
| Started | Sep 24 02:34:28 PM UTC 24 |
| Finished | Sep 24 02:34:45 PM UTC 24 |
| Peak memory | 231540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135703500 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.135703500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/46.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.3963177705 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 36468027027 ps |
| CPU time | 86.64 seconds |
| Started | Sep 24 02:34:31 PM UTC 24 |
| Finished | Sep 24 02:36:00 PM UTC 24 |
| Peak memory | 268068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963177705 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.3963177705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/46.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.4201457343 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 37997591469 ps |
| CPU time | 35.35 seconds |
| Started | Sep 24 02:34:18 PM UTC 24 |
| Finished | Sep 24 02:34:55 PM UTC 24 |
| Peak memory | 227572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201457343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.4201457343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/46.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.3743554231 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 1319921608 ps |
| CPU time | 10.83 seconds |
| Started | Sep 24 02:34:18 PM UTC 24 |
| Finished | Sep 24 02:34:30 PM UTC 24 |
| Peak memory | 227648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743554231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3743554231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/46.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.2998706681 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 88603396 ps |
| CPU time | 1.77 seconds |
| Started | Sep 24 02:34:19 PM UTC 24 |
| Finished | Sep 24 02:34:21 PM UTC 24 |
| Peak memory | 226956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998706681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2998706681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/46.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.3001048415 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 75407383 ps |
| CPU time | 1.4 seconds |
| Started | Sep 24 02:34:19 PM UTC 24 |
| Finished | Sep 24 02:34:21 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001048415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3001048415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/46.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.479891847 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 860158297 ps |
| CPU time | 10.98 seconds |
| Started | Sep 24 02:34:22 PM UTC 24 |
| Finished | Sep 24 02:34:34 PM UTC 24 |
| Peak memory | 235100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479891847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.479891847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/46.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.2162033470 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 16096530 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 02:34:45 PM UTC 24 |
| Finished | Sep 24 02:34:47 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162033470 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.2162033470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/47.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.2996327424 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 61496021 ps |
| CPU time | 4.69 seconds |
| Started | Sep 24 02:34:41 PM UTC 24 |
| Finished | Sep 24 02:34:47 PM UTC 24 |
| Peak memory | 245408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996327424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2996327424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/47.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.1239998241 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 28236242 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 02:34:33 PM UTC 24 |
| Finished | Sep 24 02:34:35 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239998241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1239998241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/47.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.1253215047 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 78781239606 ps |
| CPU time | 194.36 seconds |
| Started | Sep 24 02:34:43 PM UTC 24 |
| Finished | Sep 24 02:38:01 PM UTC 24 |
| Peak memory | 262060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253215047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1253215047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/47.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3963199261 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 244824070268 ps |
| CPU time | 171.92 seconds |
| Started | Sep 24 02:34:44 PM UTC 24 |
| Finished | Sep 24 02:37:39 PM UTC 24 |
| Peak memory | 261924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963199261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3963199261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.572790386 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 7336216755 ps |
| CPU time | 132.16 seconds |
| Started | Sep 24 02:34:45 PM UTC 24 |
| Finished | Sep 24 02:37:00 PM UTC 24 |
| Peak memory | 278316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572790386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.572790386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.2518113995 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 201302670 ps |
| CPU time | 6.68 seconds |
| Started | Sep 24 02:34:42 PM UTC 24 |
| Finished | Sep 24 02:34:50 PM UTC 24 |
| Peak memory | 235116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518113995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2518113995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/47.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.109843177 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 16803258 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 02:34:43 PM UTC 24 |
| Finished | Sep 24 02:34:46 PM UTC 24 |
| Peak memory | 225964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109843177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.109843177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.1866849014 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 825152169 ps |
| CPU time | 5.13 seconds |
| Started | Sep 24 02:34:37 PM UTC 24 |
| Finished | Sep 24 02:34:43 PM UTC 24 |
| Peak memory | 235192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866849014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1866849014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/47.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.3855730068 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 980445202 ps |
| CPU time | 4.1 seconds |
| Started | Sep 24 02:34:39 PM UTC 24 |
| Finished | Sep 24 02:34:44 PM UTC 24 |
| Peak memory | 235172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855730068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3855730068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/47.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.2764060119 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 16199247847 ps |
| CPU time | 20.87 seconds |
| Started | Sep 24 02:34:37 PM UTC 24 |
| Finished | Sep 24 02:34:59 PM UTC 24 |
| Peak memory | 245396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764060119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.2764060119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/47.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.2655882319 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 223122719 ps |
| CPU time | 3.72 seconds |
| Started | Sep 24 02:34:37 PM UTC 24 |
| Finished | Sep 24 02:34:41 PM UTC 24 |
| Peak memory | 245472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655882319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2655882319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/47.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.2686233434 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 1083137791 ps |
| CPU time | 10.99 seconds |
| Started | Sep 24 02:34:43 PM UTC 24 |
| Finished | Sep 24 02:34:56 PM UTC 24 |
| Peak memory | 229620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686233434 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.2686233434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/47.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.2724444017 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 1630325009 ps |
| CPU time | 33.83 seconds |
| Started | Sep 24 02:34:34 PM UTC 24 |
| Finished | Sep 24 02:35:10 PM UTC 24 |
| Peak memory | 227744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724444017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2724444017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/47.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.1685780449 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 3288293376 ps |
| CPU time | 13.26 seconds |
| Started | Sep 24 02:34:34 PM UTC 24 |
| Finished | Sep 24 02:34:49 PM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685780449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1685780449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/47.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.2589089813 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 118519786 ps |
| CPU time | 5.31 seconds |
| Started | Sep 24 02:34:35 PM UTC 24 |
| Finished | Sep 24 02:34:42 PM UTC 24 |
| Peak memory | 227828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589089813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2589089813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/47.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.1373623038 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 248824497 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 02:34:35 PM UTC 24 |
| Finished | Sep 24 02:34:38 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373623038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1373623038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/47.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.1259638919 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 432972635 ps |
| CPU time | 7.52 seconds |
| Started | Sep 24 02:34:40 PM UTC 24 |
| Finished | Sep 24 02:34:48 PM UTC 24 |
| Peak memory | 235036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259638919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1259638919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/47.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.4111781119 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 23524860 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 02:34:59 PM UTC 24 |
| Finished | Sep 24 02:35:02 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111781119 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.4111781119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/48.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.5794190 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 62848798 ps |
| CPU time | 3.09 seconds |
| Started | Sep 24 02:34:51 PM UTC 24 |
| Finished | Sep 24 02:34:56 PM UTC 24 |
| Peak memory | 244972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5794190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM _TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_devi ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.5794190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/48.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.813728552 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 85439754 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 02:34:45 PM UTC 24 |
| Finished | Sep 24 02:34:47 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813728552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.813728552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/48.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.1748044702 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 22876100 ps |
| CPU time | 1.01 seconds |
| Started | Sep 24 02:34:56 PM UTC 24 |
| Finished | Sep 24 02:34:58 PM UTC 24 |
| Peak memory | 225968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748044702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1748044702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/48.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.3781310275 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 37321470377 ps |
| CPU time | 324.82 seconds |
| Started | Sep 24 02:34:56 PM UTC 24 |
| Finished | Sep 24 02:40:26 PM UTC 24 |
| Peak memory | 264036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781310275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3781310275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.3919503244 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 49324646637 ps |
| CPU time | 145.28 seconds |
| Started | Sep 24 02:34:56 PM UTC 24 |
| Finished | Sep 24 02:37:24 PM UTC 24 |
| Peak memory | 261924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919503244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.3919503244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.37698470 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 963379781 ps |
| CPU time | 4.63 seconds |
| Started | Sep 24 02:34:53 PM UTC 24 |
| Finished | Sep 24 02:34:59 PM UTC 24 |
| Peak memory | 235152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37698470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.37698470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/48.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.938984511 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 439757638081 ps |
| CPU time | 234.2 seconds |
| Started | Sep 24 02:34:53 PM UTC 24 |
| Finished | Sep 24 02:38:51 PM UTC 24 |
| Peak memory | 261860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938984511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.938984511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.3502442776 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 2944503034 ps |
| CPU time | 39.16 seconds |
| Started | Sep 24 02:34:50 PM UTC 24 |
| Finished | Sep 24 02:35:30 PM UTC 24 |
| Peak memory | 235316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502442776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3502442776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/48.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.3320465410 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 1774014247 ps |
| CPU time | 10.84 seconds |
| Started | Sep 24 02:34:50 PM UTC 24 |
| Finished | Sep 24 02:35:03 PM UTC 24 |
| Peak memory | 229804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320465410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3320465410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/48.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.1243836171 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 253743535 ps |
| CPU time | 3.33 seconds |
| Started | Sep 24 02:34:50 PM UTC 24 |
| Finished | Sep 24 02:34:54 PM UTC 24 |
| Peak memory | 245420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243836171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.1243836171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/48.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2124362016 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 5909335813 ps |
| CPU time | 13.14 seconds |
| Started | Sep 24 02:34:48 PM UTC 24 |
| Finished | Sep 24 02:35:03 PM UTC 24 |
| Peak memory | 245540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124362016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2124362016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/48.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2379334342 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 4219816139 ps |
| CPU time | 13.77 seconds |
| Started | Sep 24 02:34:55 PM UTC 24 |
| Finished | Sep 24 02:35:10 PM UTC 24 |
| Peak memory | 231656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379334342 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.2379334342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/48.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.1520926850 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 621939504 ps |
| CPU time | 1.47 seconds |
| Started | Sep 24 02:34:57 PM UTC 24 |
| Finished | Sep 24 02:35:01 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520926850 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.1520926850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/48.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.1760969103 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 3565033382 ps |
| CPU time | 11.13 seconds |
| Started | Sep 24 02:34:46 PM UTC 24 |
| Finished | Sep 24 02:34:58 PM UTC 24 |
| Peak memory | 227868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760969103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1760969103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/48.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.2662169849 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 31485206934 ps |
| CPU time | 22.43 seconds |
| Started | Sep 24 02:34:46 PM UTC 24 |
| Finished | Sep 24 02:35:10 PM UTC 24 |
| Peak memory | 227576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662169849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2662169849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/48.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.3527680950 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 61483267 ps |
| CPU time | 1.96 seconds |
| Started | Sep 24 02:34:48 PM UTC 24 |
| Finished | Sep 24 02:34:51 PM UTC 24 |
| Peak memory | 227084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527680950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3527680950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/48.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.3247306683 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 213271451 ps |
| CPU time | 1.52 seconds |
| Started | Sep 24 02:34:47 PM UTC 24 |
| Finished | Sep 24 02:34:50 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247306683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3247306683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/48.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.4207475557 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 2169487193 ps |
| CPU time | 4.2 seconds |
| Started | Sep 24 02:34:51 PM UTC 24 |
| Finished | Sep 24 02:34:57 PM UTC 24 |
| Peak memory | 235144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207475557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.4207475557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/48.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.850202879 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 14557146 ps |
| CPU time | 0.95 seconds |
| Started | Sep 24 02:35:11 PM UTC 24 |
| Finished | Sep 24 02:35:13 PM UTC 24 |
| Peak memory | 213040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850202879 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.850202879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/49.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.2425066484 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 7561776025 ps |
| CPU time | 23.57 seconds |
| Started | Sep 24 02:35:05 PM UTC 24 |
| Finished | Sep 24 02:35:30 PM UTC 24 |
| Peak memory | 235160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425066484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2425066484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/49.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.1868838355 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 16622379 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 02:35:00 PM UTC 24 |
| Finished | Sep 24 02:35:03 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868838355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1868838355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/49.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.3486395316 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 84816382991 ps |
| CPU time | 345.57 seconds |
| Started | Sep 24 02:35:10 PM UTC 24 |
| Finished | Sep 24 02:41:01 PM UTC 24 |
| Peak memory | 268016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486395316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3486395316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/49.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.2834895323 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 53623784036 ps |
| CPU time | 144.46 seconds |
| Started | Sep 24 02:35:10 PM UTC 24 |
| Finished | Sep 24 02:37:37 PM UTC 24 |
| Peak memory | 261984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834895323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2834895323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.3866047589 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 11460681891 ps |
| CPU time | 149.78 seconds |
| Started | Sep 24 02:35:11 PM UTC 24 |
| Finished | Sep 24 02:37:44 PM UTC 24 |
| Peak memory | 276324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866047589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.3866047589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.2370454617 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 96535551 ps |
| CPU time | 4.2 seconds |
| Started | Sep 24 02:35:05 PM UTC 24 |
| Finished | Sep 24 02:35:10 PM UTC 24 |
| Peak memory | 245480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370454617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2370454617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/49.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.1295385177 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 12862418974 ps |
| CPU time | 65.73 seconds |
| Started | Sep 24 02:35:06 PM UTC 24 |
| Finished | Sep 24 02:36:13 PM UTC 24 |
| Peak memory | 261992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295385177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.1295385177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.2527570418 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 17427631133 ps |
| CPU time | 15.32 seconds |
| Started | Sep 24 02:35:04 PM UTC 24 |
| Finished | Sep 24 02:35:22 PM UTC 24 |
| Peak memory | 245540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527570418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2527570418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/49.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.1272336019 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 424961182 ps |
| CPU time | 16.24 seconds |
| Started | Sep 24 02:35:04 PM UTC 24 |
| Finished | Sep 24 02:35:22 PM UTC 24 |
| Peak memory | 245412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272336019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1272336019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/49.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.4245792716 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 4865027054 ps |
| CPU time | 26.56 seconds |
| Started | Sep 24 02:35:04 PM UTC 24 |
| Finished | Sep 24 02:35:33 PM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245792716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.4245792716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/49.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.989766964 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 3494923507 ps |
| CPU time | 17.9 seconds |
| Started | Sep 24 02:35:02 PM UTC 24 |
| Finished | Sep 24 02:35:22 PM UTC 24 |
| Peak memory | 235156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989766964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.989766964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/49.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.818946602 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 6623965478 ps |
| CPU time | 18.47 seconds |
| Started | Sep 24 02:35:06 PM UTC 24 |
| Finished | Sep 24 02:35:26 PM UTC 24 |
| Peak memory | 233904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818946602 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.818946602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/49.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.963472289 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 57974875436 ps |
| CPU time | 366.08 seconds |
| Started | Sep 24 02:35:11 PM UTC 24 |
| Finished | Sep 24 02:41:22 PM UTC 24 |
| Peak memory | 268132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963472289 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.963472289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/49.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.2034690972 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 85102322 ps |
| CPU time | 0.93 seconds |
| Started | Sep 24 02:35:00 PM UTC 24 |
| Finished | Sep 24 02:35:03 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034690972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2034690972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/49.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.2997879869 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 5449629743 ps |
| CPU time | 24.44 seconds |
| Started | Sep 24 02:35:00 PM UTC 24 |
| Finished | Sep 24 02:35:26 PM UTC 24 |
| Peak memory | 227956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997879869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2997879869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/49.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.737384155 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 374929879 ps |
| CPU time | 3.06 seconds |
| Started | Sep 24 02:35:00 PM UTC 24 |
| Finished | Sep 24 02:35:05 PM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737384155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.737384155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/49.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2712810221 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 54230750 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 02:35:00 PM UTC 24 |
| Finished | Sep 24 02:35:03 PM UTC 24 |
| Peak memory | 214928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712810221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2712810221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/49.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.741313859 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 138324852 ps |
| CPU time | 2.84 seconds |
| Started | Sep 24 02:35:04 PM UTC 24 |
| Finished | Sep 24 02:35:09 PM UTC 24 |
| Peak memory | 235240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741313859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.741313859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/49.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.1111625686 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 13224348 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 02:14:30 PM UTC 24 |
| Finished | Sep 24 02:14:33 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111625686 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1111625686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.2382883063 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 578723605 ps |
| CPU time | 4.28 seconds |
| Started | Sep 24 02:14:18 PM UTC 24 |
| Finished | Sep 24 02:14:23 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382883063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2382883063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.1500286583 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 60562586 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 02:14:06 PM UTC 24 |
| Finished | Sep 24 02:14:08 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500286583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1500286583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.1745665776 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 4117713534 ps |
| CPU time | 44.58 seconds |
| Started | Sep 24 02:14:24 PM UTC 24 |
| Finished | Sep 24 02:15:10 PM UTC 24 |
| Peak memory | 245472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745665776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1745665776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.3678568237 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 5900723089 ps |
| CPU time | 40.44 seconds |
| Started | Sep 24 02:14:26 PM UTC 24 |
| Finished | Sep 24 02:15:09 PM UTC 24 |
| Peak memory | 229940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678568237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3678568237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.3896510035 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 58670964220 ps |
| CPU time | 111.24 seconds |
| Started | Sep 24 02:14:27 PM UTC 24 |
| Finished | Sep 24 02:16:21 PM UTC 24 |
| Peak memory | 264040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896510035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.3896510035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.1362876350 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 3405717139 ps |
| CPU time | 23.45 seconds |
| Started | Sep 24 02:14:19 PM UTC 24 |
| Finished | Sep 24 02:14:43 PM UTC 24 |
| Peak memory | 235248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362876350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1362876350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.1881113349 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 53537153727 ps |
| CPU time | 332.97 seconds |
| Started | Sep 24 02:14:20 PM UTC 24 |
| Finished | Sep 24 02:19:58 PM UTC 24 |
| Peak memory | 261928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881113349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.1881113349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.569297719 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 227127698 ps |
| CPU time | 8.12 seconds |
| Started | Sep 24 02:14:16 PM UTC 24 |
| Finished | Sep 24 02:14:26 PM UTC 24 |
| Peak memory | 245416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569297719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.569297719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.503557660 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1456395422 ps |
| CPU time | 20.49 seconds |
| Started | Sep 24 02:14:18 PM UTC 24 |
| Finished | Sep 24 02:14:39 PM UTC 24 |
| Peak memory | 235172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503557660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.503557660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.3590829829 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 82758065 ps |
| CPU time | 1.73 seconds |
| Started | Sep 24 02:14:07 PM UTC 24 |
| Finished | Sep 24 02:14:10 PM UTC 24 |
| Peak memory | 228256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590829829 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mem_parity.3590829829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.3599972922 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 25308102125 ps |
| CPU time | 12.68 seconds |
| Started | Sep 24 02:14:14 PM UTC 24 |
| Finished | Sep 24 02:14:28 PM UTC 24 |
| Peak memory | 245480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599972922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.3599972922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.1014844647 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 277346184 ps |
| CPU time | 3.54 seconds |
| Started | Sep 24 02:14:12 PM UTC 24 |
| Finished | Sep 24 02:14:17 PM UTC 24 |
| Peak memory | 235172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014844647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1014844647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.4012929634 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1526073681 ps |
| CPU time | 14.94 seconds |
| Started | Sep 24 02:14:21 PM UTC 24 |
| Finished | Sep 24 02:14:37 PM UTC 24 |
| Peak memory | 231524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012929634 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.4012929634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.2970171378 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 610612834 ps |
| CPU time | 1.82 seconds |
| Started | Sep 24 02:14:30 PM UTC 24 |
| Finished | Sep 24 02:14:33 PM UTC 24 |
| Peak memory | 226656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970171378 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.2970171378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.1485768851 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 33390579054 ps |
| CPU time | 79.26 seconds |
| Started | Sep 24 02:14:08 PM UTC 24 |
| Finished | Sep 24 02:15:29 PM UTC 24 |
| Peak memory | 227944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485768851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1485768851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.461387111 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 29831334258 ps |
| CPU time | 31.28 seconds |
| Started | Sep 24 02:14:07 PM UTC 24 |
| Finished | Sep 24 02:14:40 PM UTC 24 |
| Peak memory | 229872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461387111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.461387111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.3051056043 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 122436378 ps |
| CPU time | 2.02 seconds |
| Started | Sep 24 02:14:10 PM UTC 24 |
| Finished | Sep 24 02:14:13 PM UTC 24 |
| Peak memory | 217428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051056043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3051056043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.3036620750 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 30030136 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 02:14:09 PM UTC 24 |
| Finished | Sep 24 02:14:11 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036620750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3036620750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.1277536698 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 22576140088 ps |
| CPU time | 33.47 seconds |
| Started | Sep 24 02:14:18 PM UTC 24 |
| Finished | Sep 24 02:14:53 PM UTC 24 |
| Peak memory | 245528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277536698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1277536698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/5.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.2010417075 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 21238517 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 02:14:54 PM UTC 24 |
| Finished | Sep 24 02:14:56 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010417075 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2010417075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.2770248609 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 1012333642 ps |
| CPU time | 6.26 seconds |
| Started | Sep 24 02:14:42 PM UTC 24 |
| Finished | Sep 24 02:14:49 PM UTC 24 |
| Peak memory | 245276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770248609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2770248609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.1203956204 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 50852692 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 02:14:30 PM UTC 24 |
| Finished | Sep 24 02:14:33 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203956204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1203956204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.3512326901 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 25216298918 ps |
| CPU time | 102.35 seconds |
| Started | Sep 24 02:14:46 PM UTC 24 |
| Finished | Sep 24 02:16:31 PM UTC 24 |
| Peak memory | 263912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512326901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3512326901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.2801408488 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 277712159178 ps |
| CPU time | 694.12 seconds |
| Started | Sep 24 02:14:50 PM UTC 24 |
| Finished | Sep 24 02:26:34 PM UTC 24 |
| Peak memory | 282472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801408488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2801408488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.21952742 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 16521815155 ps |
| CPU time | 71.97 seconds |
| Started | Sep 24 02:14:51 PM UTC 24 |
| Finished | Sep 24 02:16:05 PM UTC 24 |
| Peak memory | 272296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21952742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.21952742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.2808198029 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 3784361911 ps |
| CPU time | 43.86 seconds |
| Started | Sep 24 02:14:44 PM UTC 24 |
| Finished | Sep 24 02:15:29 PM UTC 24 |
| Peak memory | 245472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808198029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2808198029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.4127674851 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 3451689048 ps |
| CPU time | 22.83 seconds |
| Started | Sep 24 02:14:44 PM UTC 24 |
| Finished | Sep 24 02:15:08 PM UTC 24 |
| Peak memory | 247588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127674851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.4127674851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.497399516 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 9832676046 ps |
| CPU time | 39.76 seconds |
| Started | Sep 24 02:14:41 PM UTC 24 |
| Finished | Sep 24 02:15:22 PM UTC 24 |
| Peak memory | 235236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497399516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.497399516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.28096723 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 1430734228 ps |
| CPU time | 15.56 seconds |
| Started | Sep 24 02:14:41 PM UTC 24 |
| Finished | Sep 24 02:14:58 PM UTC 24 |
| Peak memory | 235048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28096723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.28096723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.2947297622 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 120785958 ps |
| CPU time | 1.64 seconds |
| Started | Sep 24 02:14:33 PM UTC 24 |
| Finished | Sep 24 02:14:36 PM UTC 24 |
| Peak memory | 228256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947297622 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mem_parity.2947297622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.3649348039 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3223561278 ps |
| CPU time | 28.32 seconds |
| Started | Sep 24 02:14:39 PM UTC 24 |
| Finished | Sep 24 02:15:09 PM UTC 24 |
| Peak memory | 261864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649348039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.3649348039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.2349865743 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 6063822557 ps |
| CPU time | 10.65 seconds |
| Started | Sep 24 02:14:38 PM UTC 24 |
| Finished | Sep 24 02:14:50 PM UTC 24 |
| Peak memory | 245536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349865743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2349865743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.1101939255 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 134217383 ps |
| CPU time | 5.72 seconds |
| Started | Sep 24 02:14:46 PM UTC 24 |
| Finished | Sep 24 02:14:53 PM UTC 24 |
| Peak memory | 233716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101939255 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.1101939255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.2924040140 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 67915536075 ps |
| CPU time | 814.48 seconds |
| Started | Sep 24 02:14:54 PM UTC 24 |
| Finished | Sep 24 02:28:39 PM UTC 24 |
| Peak memory | 278432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924040140 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.2924040140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.1331564605 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 7103583898 ps |
| CPU time | 42.23 seconds |
| Started | Sep 24 02:14:34 PM UTC 24 |
| Finished | Sep 24 02:15:18 PM UTC 24 |
| Peak memory | 227808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331564605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1331564605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.50653496 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 5320208349 ps |
| CPU time | 9.92 seconds |
| Started | Sep 24 02:14:34 PM UTC 24 |
| Finished | Sep 24 02:14:45 PM UTC 24 |
| Peak memory | 227812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50653496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.50653496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.594986149 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 16891076 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 02:14:38 PM UTC 24 |
| Finished | Sep 24 02:14:41 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594986149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.594986149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.2551589154 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 83549205 ps |
| CPU time | 1.33 seconds |
| Started | Sep 24 02:14:36 PM UTC 24 |
| Finished | Sep 24 02:14:39 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551589154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2551589154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.471009034 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 40200699 ps |
| CPU time | 3.29 seconds |
| Started | Sep 24 02:14:41 PM UTC 24 |
| Finished | Sep 24 02:14:45 PM UTC 24 |
| Peak memory | 234792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471009034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.471009034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/6.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.2763535931 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 38120895 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 02:15:27 PM UTC 24 |
| Finished | Sep 24 02:15:30 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763535931 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2763535931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.3794867746 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1545406040 ps |
| CPU time | 25.25 seconds |
| Started | Sep 24 02:15:16 PM UTC 24 |
| Finished | Sep 24 02:15:42 PM UTC 24 |
| Peak memory | 245340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794867746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3794867746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.2108067548 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 51664681 ps |
| CPU time | 1.04 seconds |
| Started | Sep 24 02:14:57 PM UTC 24 |
| Finished | Sep 24 02:14:59 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108067548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2108067548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.2865027208 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 9689621748 ps |
| CPU time | 135.5 seconds |
| Started | Sep 24 02:15:22 PM UTC 24 |
| Finished | Sep 24 02:17:41 PM UTC 24 |
| Peak memory | 249828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865027208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2865027208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1156910240 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 36743561533 ps |
| CPU time | 426.52 seconds |
| Started | Sep 24 02:15:23 PM UTC 24 |
| Finished | Sep 24 02:22:36 PM UTC 24 |
| Peak memory | 261928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156910240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.1156910240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.4063777812 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 1648651727 ps |
| CPU time | 8.85 seconds |
| Started | Sep 24 02:15:19 PM UTC 24 |
| Finished | Sep 24 02:15:29 PM UTC 24 |
| Peak memory | 235224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063777812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.4063777812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.1516479297 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1758705683 ps |
| CPU time | 17.39 seconds |
| Started | Sep 24 02:15:21 PM UTC 24 |
| Finished | Sep 24 02:15:39 PM UTC 24 |
| Peak memory | 245348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516479297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.1516479297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.1484594193 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 359028512 ps |
| CPU time | 9.32 seconds |
| Started | Sep 24 02:15:10 PM UTC 24 |
| Finished | Sep 24 02:15:21 PM UTC 24 |
| Peak memory | 245360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484594193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1484594193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.3186217343 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 224715864 ps |
| CPU time | 8.82 seconds |
| Started | Sep 24 02:15:11 PM UTC 24 |
| Finished | Sep 24 02:15:21 PM UTC 24 |
| Peak memory | 244212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186217343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3186217343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.3328709235 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 25573595 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 02:14:59 PM UTC 24 |
| Finished | Sep 24 02:15:01 PM UTC 24 |
| Peak memory | 228256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328709235 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mem_parity.3328709235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3297234246 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 1027026729 ps |
| CPU time | 9.73 seconds |
| Started | Sep 24 02:15:09 PM UTC 24 |
| Finished | Sep 24 02:15:20 PM UTC 24 |
| Peak memory | 245484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297234246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.3297234246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3899541229 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 709621148 ps |
| CPU time | 9.45 seconds |
| Started | Sep 24 02:15:09 PM UTC 24 |
| Finished | Sep 24 02:15:20 PM UTC 24 |
| Peak memory | 235172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899541229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3899541229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3380993257 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 948277658 ps |
| CPU time | 14.77 seconds |
| Started | Sep 24 02:15:21 PM UTC 24 |
| Finished | Sep 24 02:15:37 PM UTC 24 |
| Peak memory | 231652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380993257 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.3380993257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.2410976371 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 2370963172 ps |
| CPU time | 11.87 seconds |
| Started | Sep 24 02:15:02 PM UTC 24 |
| Finished | Sep 24 02:15:15 PM UTC 24 |
| Peak memory | 227804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410976371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2410976371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.2338380683 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 303233817 ps |
| CPU time | 3.28 seconds |
| Started | Sep 24 02:15:00 PM UTC 24 |
| Finished | Sep 24 02:15:04 PM UTC 24 |
| Peak memory | 217312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338380683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2338380683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.1619712137 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 214742661 ps |
| CPU time | 3.43 seconds |
| Started | Sep 24 02:15:08 PM UTC 24 |
| Finished | Sep 24 02:15:13 PM UTC 24 |
| Peak memory | 227740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619712137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1619712137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.695349091 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 250463849 ps |
| CPU time | 1.68 seconds |
| Started | Sep 24 02:15:05 PM UTC 24 |
| Finished | Sep 24 02:15:08 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695349091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.695349091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.194658668 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 4700583960 ps |
| CPU time | 11.57 seconds |
| Started | Sep 24 02:15:14 PM UTC 24 |
| Finished | Sep 24 02:15:26 PM UTC 24 |
| Peak memory | 235304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194658668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.194658668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/7.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.3719580576 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 40166446 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 02:15:56 PM UTC 24 |
| Finished | Sep 24 02:15:58 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719580576 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3719580576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.2550379219 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 975898809 ps |
| CPU time | 18.02 seconds |
| Started | Sep 24 02:15:42 PM UTC 24 |
| Finished | Sep 24 02:16:02 PM UTC 24 |
| Peak memory | 235232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550379219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2550379219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.987443744 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 76238581 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 02:15:29 PM UTC 24 |
| Finished | Sep 24 02:15:32 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987443744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.987443744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.3577463398 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 136878145620 ps |
| CPU time | 318.56 seconds |
| Started | Sep 24 02:15:50 PM UTC 24 |
| Finished | Sep 24 02:21:13 PM UTC 24 |
| Peak memory | 278304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577463398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3577463398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.1993495661 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 18657509966 ps |
| CPU time | 39.82 seconds |
| Started | Sep 24 02:15:55 PM UTC 24 |
| Finished | Sep 24 02:16:36 PM UTC 24 |
| Peak memory | 229940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993495661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.1993495661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.4145857688 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1022647530 ps |
| CPU time | 9.4 seconds |
| Started | Sep 24 02:15:44 PM UTC 24 |
| Finished | Sep 24 02:15:54 PM UTC 24 |
| Peak memory | 235184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145857688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.4145857688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.3821995565 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 24209002804 ps |
| CPU time | 57.24 seconds |
| Started | Sep 24 02:15:46 PM UTC 24 |
| Finished | Sep 24 02:16:45 PM UTC 24 |
| Peak memory | 261860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821995565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.3821995565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.1471153030 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 492160225 ps |
| CPU time | 11.97 seconds |
| Started | Sep 24 02:15:39 PM UTC 24 |
| Finished | Sep 24 02:15:52 PM UTC 24 |
| Peak memory | 245340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471153030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1471153030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.4174386159 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 1250367954 ps |
| CPU time | 13.58 seconds |
| Started | Sep 24 02:15:40 PM UTC 24 |
| Finished | Sep 24 02:15:55 PM UTC 24 |
| Peak memory | 245348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174386159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.4174386159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.1121643778 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 43699945 ps |
| CPU time | 1.6 seconds |
| Started | Sep 24 02:15:31 PM UTC 24 |
| Finished | Sep 24 02:15:33 PM UTC 24 |
| Peak memory | 228256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121643778 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mem_parity.1121643778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.3976455851 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 387581879 ps |
| CPU time | 10.04 seconds |
| Started | Sep 24 02:15:38 PM UTC 24 |
| Finished | Sep 24 02:15:49 PM UTC 24 |
| Peak memory | 245360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976455851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.3976455851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2889894386 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 230052682 ps |
| CPU time | 4.53 seconds |
| Started | Sep 24 02:15:36 PM UTC 24 |
| Finished | Sep 24 02:15:41 PM UTC 24 |
| Peak memory | 235152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889894386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2889894386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.2999207597 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 14236760282 ps |
| CPU time | 12.12 seconds |
| Started | Sep 24 02:15:47 PM UTC 24 |
| Finished | Sep 24 02:16:00 PM UTC 24 |
| Peak memory | 234068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999207597 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.2999207597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.904881146 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 6758496705 ps |
| CPU time | 42.6 seconds |
| Started | Sep 24 02:15:31 PM UTC 24 |
| Finished | Sep 24 02:16:15 PM UTC 24 |
| Peak memory | 229920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904881146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.904881146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.2117696300 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 20434194008 ps |
| CPU time | 21.97 seconds |
| Started | Sep 24 02:15:31 PM UTC 24 |
| Finished | Sep 24 02:15:54 PM UTC 24 |
| Peak memory | 229364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117696300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2117696300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.1519357757 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 139763026 ps |
| CPU time | 4.03 seconds |
| Started | Sep 24 02:15:34 PM UTC 24 |
| Finished | Sep 24 02:15:39 PM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519357757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1519357757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3145094829 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 23287536 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 02:15:33 PM UTC 24 |
| Finished | Sep 24 02:15:35 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145094829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3145094829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.3488844168 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 277969013 ps |
| CPU time | 3.13 seconds |
| Started | Sep 24 02:15:40 PM UTC 24 |
| Finished | Sep 24 02:15:44 PM UTC 24 |
| Peak memory | 235080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488844168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3488844168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/8.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.591045203 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 43306520 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 02:16:34 PM UTC 24 |
| Finished | Sep 24 02:16:36 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591045203 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.591045203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.4088351783 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1879184511 ps |
| CPU time | 19 seconds |
| Started | Sep 24 02:16:16 PM UTC 24 |
| Finished | Sep 24 02:16:37 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088351783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.4088351783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.376420079 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 64112513 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 02:15:59 PM UTC 24 |
| Finished | Sep 24 02:16:01 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376420079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.376420079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.3149958874 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 888195862 ps |
| CPU time | 14.77 seconds |
| Started | Sep 24 02:16:25 PM UTC 24 |
| Finished | Sep 24 02:16:41 PM UTC 24 |
| Peak memory | 251492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149958874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3149958874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.2305903375 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 17631414775 ps |
| CPU time | 149.79 seconds |
| Started | Sep 24 02:16:26 PM UTC 24 |
| Finished | Sep 24 02:18:58 PM UTC 24 |
| Peak memory | 278312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305903375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2305903375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.884646408 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 57402074938 ps |
| CPU time | 261.29 seconds |
| Started | Sep 24 02:16:32 PM UTC 24 |
| Finished | Sep 24 02:20:58 PM UTC 24 |
| Peak memory | 268084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884646408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.884646408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.1870600250 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 1971629517 ps |
| CPU time | 13.74 seconds |
| Started | Sep 24 02:16:18 PM UTC 24 |
| Finished | Sep 24 02:16:34 PM UTC 24 |
| Peak memory | 235180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870600250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1870600250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.2313967623 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 164871282681 ps |
| CPU time | 612.71 seconds |
| Started | Sep 24 02:16:21 PM UTC 24 |
| Finished | Sep 24 02:26:42 PM UTC 24 |
| Peak memory | 266028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313967623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.2313967623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.2736729308 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 617683358 ps |
| CPU time | 12.82 seconds |
| Started | Sep 24 02:16:10 PM UTC 24 |
| Finished | Sep 24 02:16:24 PM UTC 24 |
| Peak memory | 245360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736729308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2736729308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.2621428055 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 3989450454 ps |
| CPU time | 34.95 seconds |
| Started | Sep 24 02:16:11 PM UTC 24 |
| Finished | Sep 24 02:16:48 PM UTC 24 |
| Peak memory | 251616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621428055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2621428055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.3270950113 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 187920728 ps |
| CPU time | 1.69 seconds |
| Started | Sep 24 02:16:01 PM UTC 24 |
| Finished | Sep 24 02:16:04 PM UTC 24 |
| Peak memory | 228256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270950113 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mem_parity.3270950113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1115115761 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 2941825907 ps |
| CPU time | 11.91 seconds |
| Started | Sep 24 02:16:08 PM UTC 24 |
| Finished | Sep 24 02:16:21 PM UTC 24 |
| Peak memory | 251564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115115761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.1115115761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.2109510564 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 339932139 ps |
| CPU time | 9 seconds |
| Started | Sep 24 02:16:07 PM UTC 24 |
| Finished | Sep 24 02:16:17 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109510564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2109510564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.1321010049 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 995814677 ps |
| CPU time | 11.78 seconds |
| Started | Sep 24 02:16:23 PM UTC 24 |
| Finished | Sep 24 02:16:36 PM UTC 24 |
| Peak memory | 233700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321010049 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.1321010049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.3654537196 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 63355621 ps |
| CPU time | 1.89 seconds |
| Started | Sep 24 02:16:32 PM UTC 24 |
| Finished | Sep 24 02:16:35 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654537196 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.3654537196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.970504664 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 516038830 ps |
| CPU time | 6.19 seconds |
| Started | Sep 24 02:16:02 PM UTC 24 |
| Finished | Sep 24 02:16:10 PM UTC 24 |
| Peak memory | 227820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970504664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.970504664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.1011291560 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1248549060 ps |
| CPU time | 2.91 seconds |
| Started | Sep 24 02:16:02 PM UTC 24 |
| Finished | Sep 24 02:16:06 PM UTC 24 |
| Peak memory | 217312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011291560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1011291560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.2173133035 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 38810200 ps |
| CPU time | 1.55 seconds |
| Started | Sep 24 02:16:07 PM UTC 24 |
| Finished | Sep 24 02:16:09 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173133035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2173133035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1545015504 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 17040700 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 02:16:05 PM UTC 24 |
| Finished | Sep 24 02:16:07 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545015504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1545015504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.446632819 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 430737848 ps |
| CPU time | 9.85 seconds |
| Started | Sep 24 02:16:14 PM UTC 24 |
| Finished | Sep 24 02:16:25 PM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446632819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.446632819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/9.spi_device_upload/latest |
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