| T830 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.1376354760 |
|
|
Sep 24 02:31:17 PM UTC 24 |
Sep 24 02:31:51 PM UTC 24 |
43865474371 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_upload.1628181151 |
|
|
Sep 24 02:31:25 PM UTC 24 |
Sep 24 02:31:51 PM UTC 24 |
3273669888 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.1652811544 |
|
|
Sep 24 02:31:19 PM UTC 24 |
Sep 24 02:31:52 PM UTC 24 |
9466905848 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_rw.1839369197 |
|
|
Sep 24 02:31:49 PM UTC 24 |
Sep 24 02:31:52 PM UTC 24 |
144695321 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.2892565797 |
|
|
Sep 24 02:31:50 PM UTC 24 |
Sep 24 02:31:54 PM UTC 24 |
616824241 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.2465480752 |
|
|
Sep 24 02:31:43 PM UTC 24 |
Sep 24 02:31:56 PM UTC 24 |
5085336090 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/21.spi_device_stress_all.718360716 |
|
|
Sep 24 02:23:15 PM UTC 24 |
Sep 24 02:31:58 PM UTC 24 |
476711008951 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_intercept.1246925774 |
|
|
Sep 24 02:31:51 PM UTC 24 |
Sep 24 02:31:58 PM UTC 24 |
269046423 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.3795295288 |
|
|
Sep 24 02:30:49 PM UTC 24 |
Sep 24 02:31:58 PM UTC 24 |
15161629365 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.3420110140 |
|
|
Sep 24 02:31:52 PM UTC 24 |
Sep 24 02:32:01 PM UTC 24 |
291178847 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.4101342199 |
|
|
Sep 24 02:31:49 PM UTC 24 |
Sep 24 02:32:06 PM UTC 24 |
676694243 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.2046017729 |
|
|
Sep 24 02:31:54 PM UTC 24 |
Sep 24 02:32:07 PM UTC 24 |
1149379867 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.1998998172 |
|
|
Sep 24 02:32:02 PM UTC 24 |
Sep 24 02:32:09 PM UTC 24 |
1140022590 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.3071464708 |
|
|
Sep 24 02:32:07 PM UTC 24 |
Sep 24 02:32:09 PM UTC 24 |
13956878 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.2659673947 |
|
|
Sep 24 02:32:07 PM UTC 24 |
Sep 24 02:32:10 PM UTC 24 |
44123864 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.3881331795 |
|
|
Sep 24 02:31:43 PM UTC 24 |
Sep 24 02:32:10 PM UTC 24 |
7856920742 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.4199988943 |
|
|
Sep 24 02:31:59 PM UTC 24 |
Sep 24 02:32:11 PM UTC 24 |
1193557764 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.204637182 |
|
|
Sep 24 02:32:10 PM UTC 24 |
Sep 24 02:32:13 PM UTC 24 |
23738954 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.3323213723 |
|
|
Sep 24 02:33:15 PM UTC 24 |
Sep 24 02:34:03 PM UTC 24 |
2185473145 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.1372797048 |
|
|
Sep 24 02:31:59 PM UTC 24 |
Sep 24 02:32:15 PM UTC 24 |
980422912 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.3784847645 |
|
|
Sep 24 02:32:12 PM UTC 24 |
Sep 24 02:32:15 PM UTC 24 |
54578995 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.1869775991 |
|
|
Sep 24 02:28:29 PM UTC 24 |
Sep 24 02:32:16 PM UTC 24 |
43381947736 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.829183726 |
|
|
Sep 24 02:27:43 PM UTC 24 |
Sep 24 02:32:17 PM UTC 24 |
20277259093 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.344799641 |
|
|
Sep 24 02:31:20 PM UTC 24 |
Sep 24 02:32:18 PM UTC 24 |
12165115597 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.658343201 |
|
|
Sep 24 02:32:14 PM UTC 24 |
Sep 24 02:32:18 PM UTC 24 |
71847664 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.2899889949 |
|
|
Sep 24 02:31:36 PM UTC 24 |
Sep 24 02:32:22 PM UTC 24 |
1196748108 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.1900254508 |
|
|
Sep 24 02:32:16 PM UTC 24 |
Sep 24 02:32:22 PM UTC 24 |
204275659 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.4281849225 |
|
|
Sep 24 02:31:52 PM UTC 24 |
Sep 24 02:32:24 PM UTC 24 |
21070795175 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.2909262830 |
|
|
Sep 24 02:32:10 PM UTC 24 |
Sep 24 02:32:24 PM UTC 24 |
757683419 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_intercept.2204525584 |
|
|
Sep 24 02:31:23 PM UTC 24 |
Sep 24 02:32:24 PM UTC 24 |
28396957549 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.350617152 |
|
|
Sep 24 02:32:16 PM UTC 24 |
Sep 24 02:32:24 PM UTC 24 |
1351007478 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.1823460594 |
|
|
Sep 24 02:32:25 PM UTC 24 |
Sep 24 02:32:27 PM UTC 24 |
16585739 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.1644496780 |
|
|
Sep 24 02:32:25 PM UTC 24 |
Sep 24 02:32:27 PM UTC 24 |
31865415 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.847846968 |
|
|
Sep 24 02:32:28 PM UTC 24 |
Sep 24 02:32:30 PM UTC 24 |
11249939 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.2606521319 |
|
|
Sep 24 02:32:28 PM UTC 24 |
Sep 24 02:32:30 PM UTC 24 |
238784428 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.680531406 |
|
|
Sep 24 02:32:10 PM UTC 24 |
Sep 24 02:32:33 PM UTC 24 |
1573574848 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.207544342 |
|
|
Sep 24 02:32:18 PM UTC 24 |
Sep 24 02:32:34 PM UTC 24 |
8304438175 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.2419246575 |
|
|
Sep 24 02:32:13 PM UTC 24 |
Sep 24 02:32:35 PM UTC 24 |
32983403802 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.4091842210 |
|
|
Sep 24 02:25:59 PM UTC 24 |
Sep 24 02:32:36 PM UTC 24 |
44088009008 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.2361173254 |
|
|
Sep 24 02:32:17 PM UTC 24 |
Sep 24 02:32:36 PM UTC 24 |
3502264410 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.1630418788 |
|
|
Sep 24 02:32:31 PM UTC 24 |
Sep 24 02:32:37 PM UTC 24 |
333457065 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.3248778056 |
|
|
Sep 24 02:32:31 PM UTC 24 |
Sep 24 02:32:37 PM UTC 24 |
330688498 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.1162535366 |
|
|
Sep 24 02:32:34 PM UTC 24 |
Sep 24 02:32:38 PM UTC 24 |
115297356 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.3051237668 |
|
|
Sep 24 02:32:25 PM UTC 24 |
Sep 24 02:32:41 PM UTC 24 |
2100915202 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.1705576060 |
|
|
Sep 24 02:32:15 PM UTC 24 |
Sep 24 02:32:42 PM UTC 24 |
2321679163 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.3998576831 |
|
|
Sep 24 02:32:38 PM UTC 24 |
Sep 24 02:32:44 PM UTC 24 |
360357027 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.151886682 |
|
|
Sep 24 02:30:49 PM UTC 24 |
Sep 24 02:32:44 PM UTC 24 |
20513277897 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.904762429 |
|
|
Sep 24 02:32:39 PM UTC 24 |
Sep 24 02:32:45 PM UTC 24 |
83092446 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.1105179051 |
|
|
Sep 24 02:32:34 PM UTC 24 |
Sep 24 02:32:46 PM UTC 24 |
15994056909 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.1537154970 |
|
|
Sep 24 02:32:37 PM UTC 24 |
Sep 24 02:32:47 PM UTC 24 |
3890027053 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.2092874658 |
|
|
Sep 24 02:32:46 PM UTC 24 |
Sep 24 02:32:48 PM UTC 24 |
16708606 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.1560163121 |
|
|
Sep 24 02:32:47 PM UTC 24 |
Sep 24 02:32:49 PM UTC 24 |
50441841 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.1359089974 |
|
|
Sep 24 02:32:50 PM UTC 24 |
Sep 24 02:32:52 PM UTC 24 |
19680551 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.1474413428 |
|
|
Sep 24 02:24:36 PM UTC 24 |
Sep 24 02:32:55 PM UTC 24 |
54327261444 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.3080704661 |
|
|
Sep 24 02:32:53 PM UTC 24 |
Sep 24 02:32:57 PM UTC 24 |
71221431 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.3277699656 |
|
|
Sep 24 02:32:37 PM UTC 24 |
Sep 24 02:32:58 PM UTC 24 |
13120565954 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.4293014401 |
|
|
Sep 24 02:32:48 PM UTC 24 |
Sep 24 02:32:59 PM UTC 24 |
3053494207 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.3263742561 |
|
|
Sep 24 02:32:16 PM UTC 24 |
Sep 24 02:33:01 PM UTC 24 |
4096785729 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.124703883 |
|
|
Sep 24 02:29:34 PM UTC 24 |
Sep 24 02:33:06 PM UTC 24 |
223400375933 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.3119748448 |
|
|
Sep 24 02:33:02 PM UTC 24 |
Sep 24 02:33:08 PM UTC 24 |
305427035 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.899359868 |
|
|
Sep 24 02:32:58 PM UTC 24 |
Sep 24 02:33:10 PM UTC 24 |
409988306 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.126035185 |
|
|
Sep 24 02:32:56 PM UTC 24 |
Sep 24 02:33:13 PM UTC 24 |
5454273393 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.4290116913 |
|
|
Sep 24 02:32:49 PM UTC 24 |
Sep 24 02:33:14 PM UTC 24 |
3081536759 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.3831029665 |
|
|
Sep 24 02:32:57 PM UTC 24 |
Sep 24 02:33:17 PM UTC 24 |
2724102359 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.2100256777 |
|
|
Sep 24 02:33:07 PM UTC 24 |
Sep 24 02:33:18 PM UTC 24 |
318467630 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.1655294700 |
|
|
Sep 24 02:32:59 PM UTC 24 |
Sep 24 02:33:18 PM UTC 24 |
5164858752 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.147198268 |
|
|
Sep 24 02:33:14 PM UTC 24 |
Sep 24 02:33:21 PM UTC 24 |
438262344 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.4106346573 |
|
|
Sep 24 02:33:09 PM UTC 24 |
Sep 24 02:33:24 PM UTC 24 |
482265083 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.1150251882 |
|
|
Sep 24 02:33:22 PM UTC 24 |
Sep 24 02:33:25 PM UTC 24 |
28855625 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.3869925625 |
|
|
Sep 24 02:31:57 PM UTC 24 |
Sep 24 02:33:25 PM UTC 24 |
13633466417 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.1976487372 |
|
|
Sep 24 02:30:20 PM UTC 24 |
Sep 24 02:33:26 PM UTC 24 |
24244923877 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.1718750215 |
|
|
Sep 24 02:33:25 PM UTC 24 |
Sep 24 02:33:27 PM UTC 24 |
46519362 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.2851836490 |
|
|
Sep 24 02:33:27 PM UTC 24 |
Sep 24 02:33:29 PM UTC 24 |
59547581 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.3812838199 |
|
|
Sep 24 02:33:28 PM UTC 24 |
Sep 24 02:33:31 PM UTC 24 |
222611648 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.4141752333 |
|
|
Sep 24 02:33:26 PM UTC 24 |
Sep 24 02:33:35 PM UTC 24 |
528372106 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.28277823 |
|
|
Sep 24 02:33:30 PM UTC 24 |
Sep 24 02:33:37 PM UTC 24 |
2068915656 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.2843964966 |
|
|
Sep 24 02:31:34 PM UTC 24 |
Sep 24 02:33:37 PM UTC 24 |
13310230179 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.1280044858 |
|
|
Sep 24 02:27:23 PM UTC 24 |
Sep 24 02:33:40 PM UTC 24 |
158133088779 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2977283025 |
|
|
Sep 24 02:33:32 PM UTC 24 |
Sep 24 02:33:40 PM UTC 24 |
292338529 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.3721084750 |
|
|
Sep 24 02:32:41 PM UTC 24 |
Sep 24 02:33:43 PM UTC 24 |
50845229626 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.276381969 |
|
|
Sep 24 02:28:47 PM UTC 24 |
Sep 24 02:33:43 PM UTC 24 |
90428248868 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.2515109512 |
|
|
Sep 24 02:33:40 PM UTC 24 |
Sep 24 02:33:45 PM UTC 24 |
52552837 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.1004039829 |
|
|
Sep 24 02:32:44 PM UTC 24 |
Sep 24 02:33:48 PM UTC 24 |
6518185989 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.2829070115 |
|
|
Sep 24 02:33:38 PM UTC 24 |
Sep 24 02:33:49 PM UTC 24 |
682462810 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.992796954 |
|
|
Sep 24 02:32:19 PM UTC 24 |
Sep 24 02:33:49 PM UTC 24 |
23182668647 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.2610475164 |
|
|
Sep 24 02:33:41 PM UTC 24 |
Sep 24 02:33:50 PM UTC 24 |
865316719 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.154010610 |
|
|
Sep 24 02:31:10 PM UTC 24 |
Sep 24 02:33:53 PM UTC 24 |
24167410018 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.3318957588 |
|
|
Sep 24 02:33:51 PM UTC 24 |
Sep 24 02:33:53 PM UTC 24 |
34566484 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.2713485616 |
|
|
Sep 24 02:33:53 PM UTC 24 |
Sep 24 02:33:56 PM UTC 24 |
33673691 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.1763256983 |
|
|
Sep 24 02:33:54 PM UTC 24 |
Sep 24 02:33:58 PM UTC 24 |
102611308 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.3573753084 |
|
|
Sep 24 02:33:38 PM UTC 24 |
Sep 24 02:33:59 PM UTC 24 |
1799431065 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.1989468048 |
|
|
Sep 24 02:33:57 PM UTC 24 |
Sep 24 02:33:59 PM UTC 24 |
27787485 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.736232704 |
|
|
Sep 24 02:33:45 PM UTC 24 |
Sep 24 02:33:59 PM UTC 24 |
847795161 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.4253191753 |
|
|
Sep 24 02:33:59 PM UTC 24 |
Sep 24 02:34:02 PM UTC 24 |
59210504 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/19.spi_device_stress_all.4134334641 |
|
|
Sep 24 02:22:07 PM UTC 24 |
Sep 24 02:34:03 PM UTC 24 |
408372093579 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.2840441520 |
|
|
Sep 24 02:34:00 PM UTC 24 |
Sep 24 02:34:04 PM UTC 24 |
269035154 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.880827205 |
|
|
Sep 24 02:34:00 PM UTC 24 |
Sep 24 02:34:05 PM UTC 24 |
45843208 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.4071911750 |
|
|
Sep 24 02:33:36 PM UTC 24 |
Sep 24 02:34:06 PM UTC 24 |
7292266312 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.3956171550 |
|
|
Sep 24 02:31:36 PM UTC 24 |
Sep 24 02:34:07 PM UTC 24 |
14688856868 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_all.1691945891 |
|
|
Sep 24 02:30:18 PM UTC 24 |
Sep 24 02:35:04 PM UTC 24 |
29613209629 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.3925471871 |
|
|
Sep 24 02:34:00 PM UTC 24 |
Sep 24 02:34:09 PM UTC 24 |
1217140699 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2712810221 |
|
|
Sep 24 02:35:00 PM UTC 24 |
Sep 24 02:35:03 PM UTC 24 |
54230750 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.1645684801 |
|
|
Sep 24 02:32:36 PM UTC 24 |
Sep 24 02:34:09 PM UTC 24 |
9073870561 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.3201304485 |
|
|
Sep 24 02:30:49 PM UTC 24 |
Sep 24 02:34:12 PM UTC 24 |
43281156532 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.2181687775 |
|
|
Sep 24 02:34:04 PM UTC 24 |
Sep 24 02:34:14 PM UTC 24 |
777735590 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.90729073 |
|
|
Sep 24 02:34:08 PM UTC 24 |
Sep 24 02:34:14 PM UTC 24 |
293854798 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.1689422111 |
|
|
Sep 24 02:34:15 PM UTC 24 |
Sep 24 02:34:17 PM UTC 24 |
40662874 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.1045617039 |
|
|
Sep 24 02:34:15 PM UTC 24 |
Sep 24 02:34:17 PM UTC 24 |
22059262 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.715347980 |
|
|
Sep 24 02:33:26 PM UTC 24 |
Sep 24 02:34:18 PM UTC 24 |
12333269759 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.3011844834 |
|
|
Sep 24 02:32:24 PM UTC 24 |
Sep 24 02:34:19 PM UTC 24 |
10830149834 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.1327817937 |
|
|
Sep 24 02:28:49 PM UTC 24 |
Sep 24 02:34:19 PM UTC 24 |
140324368789 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.2209540246 |
|
|
Sep 24 02:32:38 PM UTC 24 |
Sep 24 02:34:21 PM UTC 24 |
35460272798 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.3001048415 |
|
|
Sep 24 02:34:19 PM UTC 24 |
Sep 24 02:34:21 PM UTC 24 |
75407383 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.887500295 |
|
|
Sep 24 02:31:35 PM UTC 24 |
Sep 24 02:34:21 PM UTC 24 |
10599874115 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.227583338 |
|
|
Sep 24 02:28:30 PM UTC 24 |
Sep 24 02:34:21 PM UTC 24 |
324665302896 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.2998706681 |
|
|
Sep 24 02:34:19 PM UTC 24 |
Sep 24 02:34:21 PM UTC 24 |
88603396 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.3907216134 |
|
|
Sep 24 02:32:18 PM UTC 24 |
Sep 24 02:34:24 PM UTC 24 |
9849441581 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.4046094150 |
|
|
Sep 24 02:30:51 PM UTC 24 |
Sep 24 02:34:26 PM UTC 24 |
67584110289 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.2186553280 |
|
|
Sep 24 02:34:02 PM UTC 24 |
Sep 24 02:34:27 PM UTC 24 |
1902044742 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.3937132397 |
|
|
Sep 24 02:32:00 PM UTC 24 |
Sep 24 02:34:29 PM UTC 24 |
4692309920 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.1332692771 |
|
|
Sep 24 02:34:22 PM UTC 24 |
Sep 24 02:34:30 PM UTC 24 |
305140064 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.438755662 |
|
|
Sep 24 02:34:21 PM UTC 24 |
Sep 24 02:34:30 PM UTC 24 |
11555369488 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.3743554231 |
|
|
Sep 24 02:34:18 PM UTC 24 |
Sep 24 02:34:30 PM UTC 24 |
1319921608 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.612905674 |
|
|
Sep 24 02:34:20 PM UTC 24 |
Sep 24 02:34:32 PM UTC 24 |
4304188376 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.3928309121 |
|
|
Sep 24 02:34:22 PM UTC 24 |
Sep 24 02:34:33 PM UTC 24 |
765764470 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.3752705794 |
|
|
Sep 24 02:34:32 PM UTC 24 |
Sep 24 02:34:34 PM UTC 24 |
14570218 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.479891847 |
|
|
Sep 24 02:34:22 PM UTC 24 |
Sep 24 02:34:34 PM UTC 24 |
860158297 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.1239998241 |
|
|
Sep 24 02:34:33 PM UTC 24 |
Sep 24 02:34:35 PM UTC 24 |
28236242 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.1876903361 |
|
|
Sep 24 02:33:50 PM UTC 24 |
Sep 24 02:34:36 PM UTC 24 |
7059905112 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.2888054924 |
|
|
Sep 24 02:30:01 PM UTC 24 |
Sep 24 02:34:36 PM UTC 24 |
54051249796 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.1373623038 |
|
|
Sep 24 02:34:35 PM UTC 24 |
Sep 24 02:34:38 PM UTC 24 |
248824497 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.549713363 |
|
|
Sep 24 02:34:22 PM UTC 24 |
Sep 24 02:34:39 PM UTC 24 |
842901860 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.1086801577 |
|
|
Sep 24 02:33:56 PM UTC 24 |
Sep 24 02:34:40 PM UTC 24 |
20615908105 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.2655882319 |
|
|
Sep 24 02:34:37 PM UTC 24 |
Sep 24 02:34:41 PM UTC 24 |
223122719 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.2589089813 |
|
|
Sep 24 02:34:35 PM UTC 24 |
Sep 24 02:34:42 PM UTC 24 |
118519786 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.324708605 |
|
|
Sep 24 02:33:46 PM UTC 24 |
Sep 24 02:34:43 PM UTC 24 |
3414273444 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.737384155 |
|
|
Sep 24 02:35:00 PM UTC 24 |
Sep 24 02:35:05 PM UTC 24 |
374929879 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.1866849014 |
|
|
Sep 24 02:34:37 PM UTC 24 |
Sep 24 02:34:43 PM UTC 24 |
825152169 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.3855730068 |
|
|
Sep 24 02:34:39 PM UTC 24 |
Sep 24 02:34:44 PM UTC 24 |
980445202 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.741313859 |
|
|
Sep 24 02:35:04 PM UTC 24 |
Sep 24 02:35:09 PM UTC 24 |
138324852 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.4025456302 |
|
|
Sep 24 02:34:04 PM UTC 24 |
Sep 24 02:34:44 PM UTC 24 |
12579201851 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.2862539203 |
|
|
Sep 24 02:34:24 PM UTC 24 |
Sep 24 02:34:44 PM UTC 24 |
6802688798 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.135703500 |
|
|
Sep 24 02:34:28 PM UTC 24 |
Sep 24 02:34:45 PM UTC 24 |
1380771514 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.109843177 |
|
|
Sep 24 02:34:43 PM UTC 24 |
Sep 24 02:34:46 PM UTC 24 |
16803258 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.2996327424 |
|
|
Sep 24 02:34:41 PM UTC 24 |
Sep 24 02:34:47 PM UTC 24 |
61496021 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.2162033470 |
|
|
Sep 24 02:34:45 PM UTC 24 |
Sep 24 02:34:47 PM UTC 24 |
16096530 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.813728552 |
|
|
Sep 24 02:34:45 PM UTC 24 |
Sep 24 02:34:47 PM UTC 24 |
85439754 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.1259638919 |
|
|
Sep 24 02:34:40 PM UTC 24 |
Sep 24 02:34:48 PM UTC 24 |
432972635 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.797350699 |
|
|
Sep 24 02:32:43 PM UTC 24 |
Sep 24 02:34:49 PM UTC 24 |
103041353353 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.1685780449 |
|
|
Sep 24 02:34:34 PM UTC 24 |
Sep 24 02:34:49 PM UTC 24 |
3288293376 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.2518113995 |
|
|
Sep 24 02:34:42 PM UTC 24 |
Sep 24 02:34:50 PM UTC 24 |
201302670 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.3247306683 |
|
|
Sep 24 02:34:47 PM UTC 24 |
Sep 24 02:34:50 PM UTC 24 |
213271451 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.3527680950 |
|
|
Sep 24 02:34:48 PM UTC 24 |
Sep 24 02:34:51 PM UTC 24 |
61483267 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.4196515996 |
|
|
Sep 24 02:34:05 PM UTC 24 |
Sep 24 02:34:52 PM UTC 24 |
9335861243 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.1243836171 |
|
|
Sep 24 02:34:50 PM UTC 24 |
Sep 24 02:34:54 PM UTC 24 |
253743535 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.4201457343 |
|
|
Sep 24 02:34:18 PM UTC 24 |
Sep 24 02:34:55 PM UTC 24 |
37997591469 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.2686233434 |
|
|
Sep 24 02:34:43 PM UTC 24 |
Sep 24 02:34:56 PM UTC 24 |
1083137791 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.5794190 |
|
|
Sep 24 02:34:51 PM UTC 24 |
Sep 24 02:34:56 PM UTC 24 |
62848798 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.4207475557 |
|
|
Sep 24 02:34:51 PM UTC 24 |
Sep 24 02:34:57 PM UTC 24 |
2169487193 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.1843037328 |
|
|
Sep 24 02:33:18 PM UTC 24 |
Sep 24 02:34:58 PM UTC 24 |
6883253831 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.1748044702 |
|
|
Sep 24 02:34:56 PM UTC 24 |
Sep 24 02:34:58 PM UTC 24 |
22876100 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.3204165752 |
|
|
Sep 24 02:21:32 PM UTC 24 |
Sep 24 02:34:58 PM UTC 24 |
57704145154 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.1760969103 |
|
|
Sep 24 02:34:46 PM UTC 24 |
Sep 24 02:34:58 PM UTC 24 |
3565033382 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.37698470 |
|
|
Sep 24 02:34:53 PM UTC 24 |
Sep 24 02:34:59 PM UTC 24 |
963379781 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.2764060119 |
|
|
Sep 24 02:34:37 PM UTC 24 |
Sep 24 02:34:59 PM UTC 24 |
16199247847 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.1520926850 |
|
|
Sep 24 02:34:57 PM UTC 24 |
Sep 24 02:35:01 PM UTC 24 |
621939504 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.4111781119 |
|
|
Sep 24 02:34:59 PM UTC 24 |
Sep 24 02:35:02 PM UTC 24 |
23524860 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.2034690972 |
|
|
Sep 24 02:35:00 PM UTC 24 |
Sep 24 02:35:03 PM UTC 24 |
85102322 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.1868838355 |
|
|
Sep 24 02:35:00 PM UTC 24 |
Sep 24 02:35:03 PM UTC 24 |
16622379 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.3320465410 |
|
|
Sep 24 02:34:50 PM UTC 24 |
Sep 24 02:35:03 PM UTC 24 |
1774014247 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2124362016 |
|
|
Sep 24 02:34:48 PM UTC 24 |
Sep 24 02:35:03 PM UTC 24 |
5909335813 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.2950546086 |
|
|
Sep 24 02:29:38 PM UTC 24 |
Sep 24 02:35:09 PM UTC 24 |
494808100790 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.2724444017 |
|
|
Sep 24 02:34:34 PM UTC 24 |
Sep 24 02:35:10 PM UTC 24 |
1630325009 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.2662169849 |
|
|
Sep 24 02:34:46 PM UTC 24 |
Sep 24 02:35:10 PM UTC 24 |
31485206934 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2379334342 |
|
|
Sep 24 02:34:55 PM UTC 24 |
Sep 24 02:35:10 PM UTC 24 |
4219816139 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.2370454617 |
|
|
Sep 24 02:35:05 PM UTC 24 |
Sep 24 02:35:10 PM UTC 24 |
96535551 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.4213769845 |
|
|
Sep 24 02:34:28 PM UTC 24 |
Sep 24 02:35:13 PM UTC 24 |
26234432618 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.850202879 |
|
|
Sep 24 02:35:11 PM UTC 24 |
Sep 24 02:35:13 PM UTC 24 |
14557146 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.1799725106 |
|
|
Sep 24 02:33:50 PM UTC 24 |
Sep 24 02:35:21 PM UTC 24 |
9762423645 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.2527570418 |
|
|
Sep 24 02:35:04 PM UTC 24 |
Sep 24 02:35:22 PM UTC 24 |
17427631133 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.989766964 |
|
|
Sep 24 02:35:02 PM UTC 24 |
Sep 24 02:35:22 PM UTC 24 |
3494923507 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.1272336019 |
|
|
Sep 24 02:35:04 PM UTC 24 |
Sep 24 02:35:22 PM UTC 24 |
424961182 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.1137406567 |
|
|
Sep 24 02:34:31 PM UTC 24 |
Sep 24 02:35:24 PM UTC 24 |
11898287102 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.3893745386 |
|
|
Sep 24 02:33:11 PM UTC 24 |
Sep 24 02:35:25 PM UTC 24 |
11564500533 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.818946602 |
|
|
Sep 24 02:35:06 PM UTC 24 |
Sep 24 02:35:26 PM UTC 24 |
6623965478 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.2997879869 |
|
|
Sep 24 02:35:00 PM UTC 24 |
Sep 24 02:35:26 PM UTC 24 |
5449629743 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.2990394000 |
|
|
Sep 24 02:31:09 PM UTC 24 |
Sep 24 02:35:27 PM UTC 24 |
28423366118 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.2425066484 |
|
|
Sep 24 02:35:05 PM UTC 24 |
Sep 24 02:35:30 PM UTC 24 |
7561776025 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.3502442776 |
|
|
Sep 24 02:34:50 PM UTC 24 |
Sep 24 02:35:30 PM UTC 24 |
2944503034 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.4039086574 |
|
|
Sep 24 02:33:49 PM UTC 24 |
Sep 24 02:35:33 PM UTC 24 |
10892780921 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.4245792716 |
|
|
Sep 24 02:35:04 PM UTC 24 |
Sep 24 02:35:33 PM UTC 24 |
4865027054 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.4072652382 |
|
|
Sep 24 02:34:22 PM UTC 24 |
Sep 24 02:35:36 PM UTC 24 |
13518563183 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.1243155832 |
|
|
Sep 24 02:34:10 PM UTC 24 |
Sep 24 02:35:43 PM UTC 24 |
9281840262 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.1046765410 |
|
|
Sep 24 02:33:18 PM UTC 24 |
Sep 24 02:35:47 PM UTC 24 |
13025105868 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.2725685914 |
|
|
Sep 24 02:34:08 PM UTC 24 |
Sep 24 02:35:49 PM UTC 24 |
37756712959 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.2565592575 |
|
|
Sep 24 02:32:23 PM UTC 24 |
Sep 24 02:35:53 PM UTC 24 |
12422005271 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.3963177705 |
|
|
Sep 24 02:34:31 PM UTC 24 |
Sep 24 02:36:00 PM UTC 24 |
36468027027 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.1268763652 |
|
|
Sep 24 02:31:12 PM UTC 24 |
Sep 24 02:36:04 PM UTC 24 |
19968310097 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.3477556205 |
|
|
Sep 24 02:30:46 PM UTC 24 |
Sep 24 02:36:12 PM UTC 24 |
35106290263 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.1295385177 |
|
|
Sep 24 02:35:06 PM UTC 24 |
Sep 24 02:36:13 PM UTC 24 |
12862418974 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.1130655942 |
|
|
Sep 24 02:32:25 PM UTC 24 |
Sep 24 02:36:32 PM UTC 24 |
46731586578 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.572790386 |
|
|
Sep 24 02:34:45 PM UTC 24 |
Sep 24 02:37:00 PM UTC 24 |
7336216755 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.380757403 |
|
|
Sep 24 02:34:11 PM UTC 24 |
Sep 24 02:37:00 PM UTC 24 |
43788459262 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.3636910934 |
|
|
Sep 24 02:33:44 PM UTC 24 |
Sep 24 02:37:17 PM UTC 24 |
104147042975 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.3919503244 |
|
|
Sep 24 02:34:56 PM UTC 24 |
Sep 24 02:37:24 PM UTC 24 |
49324646637 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.1039739138 |
|
|
Sep 24 02:24:40 PM UTC 24 |
Sep 24 02:37:26 PM UTC 24 |
120562268504 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.2834895323 |
|
|
Sep 24 02:35:10 PM UTC 24 |
Sep 24 02:37:37 PM UTC 24 |
53623784036 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3963199261 |
|
|
Sep 24 02:34:44 PM UTC 24 |
Sep 24 02:37:39 PM UTC 24 |
244824070268 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.3866047589 |
|
|
Sep 24 02:35:11 PM UTC 24 |
Sep 24 02:37:44 PM UTC 24 |
11460681891 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.1385053852 |
|
|
Sep 24 02:33:18 PM UTC 24 |
Sep 24 02:37:46 PM UTC 24 |
367101017675 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.2773768951 |
|
|
Sep 24 02:34:06 PM UTC 24 |
Sep 24 02:37:57 PM UTC 24 |
25868810429 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.1253215047 |
|
|
Sep 24 02:34:43 PM UTC 24 |
Sep 24 02:38:01 PM UTC 24 |
78781239606 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.938984511 |
|
|
Sep 24 02:34:53 PM UTC 24 |
Sep 24 02:38:51 PM UTC 24 |
439757638081 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.2488791863 |
|
|
Sep 24 02:31:12 PM UTC 24 |
Sep 24 02:38:55 PM UTC 24 |
41721261241 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.1205315017 |
|
|
Sep 24 02:34:13 PM UTC 24 |
Sep 24 02:39:02 PM UTC 24 |
55446129597 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.3072741828 |
|
|
Sep 24 02:32:44 PM UTC 24 |
Sep 24 02:39:02 PM UTC 24 |
34876616437 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.1334866135 |
|
|
Sep 24 02:26:59 PM UTC 24 |
Sep 24 02:39:06 PM UTC 24 |
250164602122 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.4254709297 |
|
|
Sep 24 02:32:07 PM UTC 24 |
Sep 24 02:39:38 PM UTC 24 |
493102009025 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.539843783 |
|
|
Sep 24 02:34:30 PM UTC 24 |
Sep 24 02:39:52 PM UTC 24 |
133177456516 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.3781310275 |
|
|
Sep 24 02:34:56 PM UTC 24 |
Sep 24 02:40:26 PM UTC 24 |
37321470377 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.3486395316 |
|
|
Sep 24 02:35:10 PM UTC 24 |
Sep 24 02:41:01 PM UTC 24 |
84816382991 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.307063291 |
|
|
Sep 24 02:29:14 PM UTC 24 |
Sep 24 02:41:22 PM UTC 24 |
179721927491 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.963472289 |
|
|
Sep 24 02:35:11 PM UTC 24 |
Sep 24 02:41:22 PM UTC 24 |
57974875436 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.1133125404 |
|
|
Sep 24 02:30:02 PM UTC 24 |
Sep 24 02:41:39 PM UTC 24 |
58358521377 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.2488132688 |
|
|
Sep 24 02:34:45 PM UTC 24 |
Sep 24 02:48:20 PM UTC 24 |
81886677473 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.404190977 |
|
|
Sep 24 02:35:14 PM UTC 24 |
Sep 24 02:35:17 PM UTC 24 |
11313747 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.2612158535 |
|
|
Sep 24 02:35:11 PM UTC 24 |
Sep 24 02:35:19 PM UTC 24 |
65935352 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2161146104 |
|
|
Sep 24 02:35:18 PM UTC 24 |
Sep 24 02:35:20 PM UTC 24 |
12863838 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3382288334 |
|
|
Sep 24 02:35:13 PM UTC 24 |
Sep 24 02:35:23 PM UTC 24 |
889394151 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2771231898 |
|
|
Sep 24 02:35:21 PM UTC 24 |
Sep 24 02:35:23 PM UTC 24 |
36437701 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.2954839751 |
|
|
Sep 24 02:35:20 PM UTC 24 |
Sep 24 02:35:24 PM UTC 24 |
43650465 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.536008996 |
|
|
Sep 24 02:35:22 PM UTC 24 |
Sep 24 02:35:26 PM UTC 24 |
281455555 ps |
| T1038 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3339526805 |
|
|
Sep 24 02:35:24 PM UTC 24 |
Sep 24 02:35:27 PM UTC 24 |
17304721 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4072709845 |
|
|
Sep 24 02:35:23 PM UTC 24 |
Sep 24 02:35:27 PM UTC 24 |
116126730 ps |
| T1039 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1951533152 |
|
|
Sep 24 02:35:27 PM UTC 24 |
Sep 24 02:35:29 PM UTC 24 |
19311555 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1841640328 |
|
|
Sep 24 02:35:24 PM UTC 24 |
Sep 24 02:35:30 PM UTC 24 |
78592748 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.502682723 |
|
|
Sep 24 02:35:27 PM UTC 24 |
Sep 24 02:35:30 PM UTC 24 |
147124497 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.587073495 |
|
|
Sep 24 02:35:24 PM UTC 24 |
Sep 24 02:35:31 PM UTC 24 |
193333274 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1403226774 |
|
|
Sep 24 02:35:27 PM UTC 24 |
Sep 24 02:35:31 PM UTC 24 |
793401992 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.1241904997 |
|
|
Sep 24 02:35:28 PM UTC 24 |
Sep 24 02:35:32 PM UTC 24 |
104459300 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.762286245 |
|
|
Sep 24 02:35:28 PM UTC 24 |
Sep 24 02:35:32 PM UTC 24 |
38346556 ps |
| T1040 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.2198552806 |
|
|
Sep 24 02:35:31 PM UTC 24 |
Sep 24 02:35:34 PM UTC 24 |
17651107 ps |
| T1041 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.3311417550 |
|
|
Sep 24 02:35:31 PM UTC 24 |
Sep 24 02:35:34 PM UTC 24 |
32073430 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.2165842974 |
|
|
Sep 24 02:35:30 PM UTC 24 |
Sep 24 02:35:34 PM UTC 24 |
219087915 ps |
| T1042 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3197365148 |
|
|
Sep 24 02:35:32 PM UTC 24 |
Sep 24 02:35:34 PM UTC 24 |
27710388 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1018614389 |
|
|
Sep 24 02:35:29 PM UTC 24 |
Sep 24 02:35:35 PM UTC 24 |
184866370 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.817611307 |
|
|
Sep 24 02:35:32 PM UTC 24 |
Sep 24 02:35:36 PM UTC 24 |
28859124 ps |
| T1043 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.3836488767 |
|
|
Sep 24 02:36:02 PM UTC 24 |
Sep 24 02:36:05 PM UTC 24 |
23558529 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.1904464844 |
|
|
Sep 24 02:35:33 PM UTC 24 |
Sep 24 02:35:37 PM UTC 24 |
250429586 ps |
| T1044 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.3059130200 |
|
|
Sep 24 02:35:35 PM UTC 24 |
Sep 24 02:35:37 PM UTC 24 |
32726747 ps |