Line Coverage for Module :
spid_upload
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 109 | 109 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 143 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 206 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 234 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 241 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 246 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 251 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
| ALWAYS | 256 | 6 | 6 | 100.00 |
| ALWAYS | 262 | 3 | 3 | 100.00 |
| ALWAYS | 268 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 307 | 1 | 1 | 100.00 |
| ALWAYS | 322 | 3 | 3 | 100.00 |
| ALWAYS | 346 | 10 | 10 | 100.00 |
| ALWAYS | 367 | 8 | 8 | 100.00 |
| ALWAYS | 390 | 8 | 8 | 100.00 |
| ALWAYS | 408 | 6 | 6 | 100.00 |
| ALWAYS | 418 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
| ALWAYS | 428 | 3 | 3 | 100.00 |
| ALWAYS | 438 | 26 | 26 | 100.00 |
| CONT_ASSIGN | 570 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 577 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 578 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 579 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 580 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 630 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 637 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 638 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 639 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 640 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 707 | 1 | 1 | 100.00 |
133 spi_mode_e unused_spi_mode;
134 1/1 assign unused_spi_mode = spi_mode_i;
Tests: T1 T2 T3
135
136 sel_datapath_e unused_sel_dp;
137 1/1 assign unused_sel_dp = sel_dp_i;
Tests: T1 T2 T3
138
139 assign p2s_valid_o = 1'b 0;
140 assign p2s_data_o = '0;
141
142 logic unused_p2s_sent;
143 1/1 assign unused_p2s_sent = p2s_sent_i;
Tests: T1 T2 T3
144
145 ////////////////
146 // Definition //
147 ////////////////
148 typedef enum int unsigned {
149 SramCmdFifo = 0,
150 SramAddrFifo = 1,
151 SramPayload = 2
152 } sramintf_e;
153 localparam int unsigned NumSramIntf = 3;
154
155 typedef enum logic [1:0] {
156 StIdle,
157 StAddress,
158 StPayload
159 } st_e;
160 st_e st_q, st_d;
161
162 ////////////
163 // Signal //
164 ////////////
165
166 // SRAM access (to SRAM Arbiter)
167 logic [NumSramIntf-1:0] sck_sram_req;
168 logic [NumSramIntf-1:0] sck_sram_gnt;
169 logic [NumSramIntf-1:0] sck_sram_write;
170 logic [SramAw-1:0] sck_sram_addr [NumSramIntf];
171 logic [SramDw-1:0] sck_sram_wdata [NumSramIntf];
172 logic [SramDw-1:0] sck_sram_wmask [NumSramIntf];
173 logic [NumSramIntf-1:0] sck_sram_rvalid; // not used
174 logic [SramDw-1:0] sck_sram_rdata [NumSramIntf]; // not used
175 logic [1:0] sck_sram_rerror [NumSramIntf]; // not used
176
177 logic [NumSramIntf-2:0] sys_sram_req;
178 logic [NumSramIntf-2:0] sys_sram_gnt;
179 logic [NumSramIntf-2:0] sys_sram_write;
180 logic [SramAw-1:0] sys_sram_addr [NumSramIntf-1];
181 logic [SramDw-1:0] sys_sram_wdata [NumSramIntf-1];
182 logic [SramDw-1:0] sys_sram_wmask [NumSramIntf-1];
183 logic [NumSramIntf-2:0] sys_sram_rvalid; // not used
184 logic [SramDw-1:0] sys_sram_rdata [NumSramIntf-1]; // not used
185 logic [1:0] sys_sram_rerror [NumSramIntf-1]; // not used
186
187 logic cmdfifo_wvalid;
188 logic cmdfifo_wready; // Assume always ready
189 logic [15:0] cmdfifo_wdata ;
190 logic [CmdPtrW-1:0] cmdfifo_depth; // Write side depth to check if FIFO empty
191
192 // cmdfifo_depth is used in assertion not in the logic.
193 logic unused_cmdfifo_depth;
194 1/1 assign unused_cmdfifo_depth = ^cmdfifo_depth;
Tests: T1 T2 T3
195
196 logic addrfifo_wvalid;
197 logic addrfifo_wready; // Assume always ready
198 logic [31:0] addrfifo_wdata ;
199
200 logic payload_wvalid;
201 logic payload_wready; // Assume always ready
202 logic [7:0] payload_wdata ;
203
204 // Unused wready
205 logic unused_fifo_wready;
206 1/1 assign unused_fifo_wready = ^{cmdfifo_wready, addrfifo_wready, payload_wready};
Tests: T1 T2 T3
207
208 // Simplified command info
209 addr_mode_e cmdinfo_addr_mode;
210 logic cmdinfo_addr_en, cmdinfo_addr_4b_en;
211
212 logic unused_cmdinfo;
213 1/1 assign unused_cmdinfo = ^{
Tests: T1 T2 T3
214 cmd_only_info_i.valid, // cmdparse checks the valid bit
215 cmd_only_info_i.addr_swap_en,
216 cmd_only_info_i.dummy_en,
217 cmd_only_info_i.dummy_size,
218 cmd_only_info_i.mbyte_en,
219 cmd_only_info_i.opcode,
220 cmd_only_info_i.payload_dir,
221 cmd_only_info_i.payload_en,
222 cmd_only_info_i.payload_swap_en,
223 cmd_only_info_i.read_pipeline_mode,
224 cmd_only_info_i.upload
225 };
226
227 // Address latch
228 logic addr_update, addr_shift;
229 logic [31:0] address_q, address_d;
230 logic [AddrCntW-1:0] addrcnt;
231
232 // unused
233 logic unused_cmdinfo_idx;
234 1/1 assign unused_cmdinfo_idx = ^cmd_only_info_idx_i;
Tests: T1 T2 T3
235
236 //////////////
237 // Datapath //
238 //////////////
239
240 // Command info process
241 1/1 assign cmdinfo_addr_mode = get_addr_mode(cmd_only_info_i.addr_mode, cmd_sync_cfg_addr_4b_en_i);
Tests: T1 T2 T3
242 1/1 assign cmdinfo_addr_en = cmdinfo_addr_mode != AddrDisabled;
Tests: T1 T2 T3
243
244 1/1 assign cmdinfo_addr_4b_en = cmdinfo_addr_mode == Addr4B;
Tests: T1 T2 T3
245
246 1/1 assign cmdfifo_wdata = { cmdinfo_addr_4b_en,
Tests: T1 T2 T3
247 cmd_sync_status_wel_i,
248 cmd_sync_status_busy_i,
249 5'h00,
250 s2p_byte_i};
251 1/1 assign addrfifo_wdata = address_d;
Tests: T1 T2 T3
252 1/1 assign payload_wdata = s2p_byte_i;
Tests: T1 T2 T3
253
254 // Address counter
255 always_ff @(posedge clk_i or negedge rst_ni) begin
256 2/2 if (!rst_ni) addrcnt <= '0;
Tests: T1 T2 T3 | T1 T2 T3
257 2/2 else if (addr_update) addrcnt <= cmdinfo_addr_4b_en ? 5'd 31 : 5'd 23;
Tests: T7 T8 T9 | T19 T32 T54
258 2/2 else if (addr_shift) addrcnt <= addrcnt - 5'd 1;
Tests: T7 T8 T9 | T19 T32 T54
MISSING_ELSE
259 end
260
261 always_comb begin
262 1/1 address_d = address_q;
Tests: T1 T2 T3
263 1/1 if (addr_shift) begin
Tests: T1 T2 T3
264 1/1 address_d = {address_q[23:0], s2p_byte_i};
Tests: T19 T32 T54
265 end
MISSING_ELSE
266 end
267 always_ff @(posedge clk_i or negedge rst_ni) begin
268 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
269 1/1 address_q <= '0;
Tests: T1 T2 T3
270 1/1 end else if (s2p_valid_i && addr_shift) begin
Tests: T7 T8 T9
271 1/1 address_q <= address_d;
Tests: T19 T32 T54
272 end
MISSING_ELSE
273 end
274
275 // sys_cmdfifo_not_empty_o -> sys_cmdfifo_set_o
276 //
277 // The signal is generated from SCK domain write fifo depth signal. The
278 // reason is to delay the interrupt. If the notempty interrupt comes from
279 // the CMDFIFO directly, then SW waits the SPI transaction to be completed
280 // in order to get the correct address and payload.
281 //
282 // cmdfifo_depth (SCK) is a registered signal. So, it becomes notempty after
283 // 8th beat of the SCK. The CSb as a clock latches the signal to be != 0,
284 // then sys_cmdfifo_set signal let SYS_CLK latch the notempty signal.
285 // Because CSb as a clock is synchronous with SCK, there is no CDC issue
286 // here. Please check the chip Synopsys Design Constraints (SDC) file.
287 //
288 // The case to be considered: If two commands are back-to-back and uploaded
289 // into the CMDFIFO. Then, if SW pops the first one, the notempty keeps
290 // high. The edge detector could not catch the change.
291 //
292 // To resolve the issue describe above, the notempty interrupt @ SCK catches
293 // the current transaction only. It means that the notempty becomes one if
294 // the FIFO is empty and becomes notempty. If the FIFO is not empty and
295 // the logic pushes one more to the FIFO, it does not generate event
296 // signal.
297 //
298 // In the SYS_CLK, logics see the event. If it is high, the logic generates
299 // a pulse to set the interrupt (along with the status). So that the SW can
300 // get the event.
301
302 logic sck_cmdfifo_set, sys_cmdfifo_set;
303 `ASSERT(CmdFifoPush_A,
304 cmdfifo_wvalid && cmdfifo_wready |=> cmdfifo_depth != 0,
305 clk_i, !sys_rst_ni)
306
307 1/1 assign sck_cmdfifo_set = cmdfifo_wvalid && cmdfifo_wready;
Tests: T1 T2 T3
308
309 spid_csb_sync u_sys_cmdfifo_set (
310 .clk_i (sys_clk_i),
311 .rst_ni (sys_rst_ni),
312 .sck_i (clk_i),
313 .sck_pulse_en_i (sck_cmdfifo_set),
314 .csb_i (clk_csb_i),
315 .csb_deasserted_pulse_o (sys_cmdfifo_set)
316 );
317
318 // This block is merely to align INTR_STATE updates with the payload FIFO
319 // depth updates, so the interrupt doesn't appear a cycle before the related
320 // upload data.
321 always_ff @(posedge sys_clk_i or negedge sys_rst_ni) begin
322 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
323 1/1 sys_cmdfifo_set_o <= 1'b0;
Tests: T1 T2 T3
324 end else begin
325 1/1 sys_cmdfifo_set_o <= sys_cmdfifo_set;
Tests: T1 T2 T3
326 end
327 end
328
329 // payloadptr manage: spid_fifo2sram_adapter's fifoptr (wdepth) is reset by
330 // CSb everytime. the written payload size should be visible to SW even CSb
331 // is de-asserted.
332 //
333 // payloadptr maintains the pointer inside the Payload buffer (256B
334 // currently). If the host system issues equal to or more than 256B of the
335 // size, the payload_max is set to 1 then SW will sees always PayloadByte
336 // value from the CSR. Inside the HW, SPI_DEVICE keeps storing the incoming
337 // bytes into the payload buffer as a circular FIFO manner. The payload
338 // start index CSR represents the next pointer inside the buffer IFF the
339 // payload buffer is full. If it has not been received the full payload, the
340 // start index is 0, which means SW should read from 0.
341 logic payloadptr_inc, payloadptr_clr;
342 logic [PayloadIdxW-1:0] payloadptr;
343 // Indicate the payload reached the max value (PayloadByte)
344 logic payload_max;
345 always_ff @(posedge clk_i or negedge sys_rst_ni) begin
346 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
347 1/1 payload_max <= 1'b 0;
Tests: T1 T2 T3
348 1/1 payloadptr <= '0;
Tests: T1 T2 T3
349 1/1 end else if (payloadptr_clr) begin
Tests: T4 T5 T6
350 1/1 payloadptr <= '0;
Tests: T19 T32 T54
351 1/1 payload_max <= 1'b 0;
Tests: T19 T32 T54
352 1/1 end else if (payloadptr_inc) begin
Tests: T4 T5 T6
353 1/1 if (payloadptr == PayloadIdxW'(PayloadByte-1)) begin
Tests: T19 T32 T54
354 // payloadptr reached max
355 1/1 payload_max <= 1'b 1;
Tests: T19 T32 T54
356 end
MISSING_ELSE
357 1/1 payloadptr <= payloadptr + PayloadIdxW'(1);
Tests: T19 T32 T54
358 end
MISSING_ELSE
359 end
360
361 // Synchronize to the sys_clk when CSb deasserted
362 logic sys_payloadptr_clr_posedge;
363
364 // To trigger the payload buffer update event, the payload_depth should be
365 // reset when new upload command comes.
366 always_ff @(posedge sys_clk_i or negedge sys_rst_ni) begin
367 2/2 if (!sys_rst_ni) sys_payload_depth_o <= '0;
Tests: T1 T2 T3 | T1 T2 T3
368 2/2 else if (sys_payloadptr_clr_posedge) sys_payload_depth_o <= '0;
Tests: T1 T2 T3 | T19 T32 T54
369 1/1 else if (sys_cmdfifo_set && payload_max) begin
Tests: T1 T2 T3
370 1/1 sys_payload_depth_o <= PayloadPtrW'(PayloadByte);
Tests: T19 T32 T54
371 1/1 end else if (sys_cmdfifo_set && !payload_max) begin
Tests: T1 T2 T3
372 1/1 sys_payload_depth_o <= PayloadPtrW'(payloadptr);
Tests: T19 T32 T54
373 end
MISSING_ELSE
374 end
375
376 // payloadptr_clr --> sys domain
377 prim_pulse_sync u_payloadptr_clr_psync (
378 // source clock domain
379 .clk_src_i (clk_i),
380 .rst_src_ni (sys_rst_ni),
381 .src_pulse_i (payloadptr_clr),
382 // destination clock domain
383 .clk_dst_i (sys_clk_i),
384 .rst_dst_ni (sys_rst_ni),
385 .dst_pulse_o (sys_payloadptr_clr_posedge)
386 );
387
388 // Latch payloadptr @ CSb events
389 always_ff @(posedge sys_clk_i or negedge sys_rst_ni) begin
390 2/2 if (!sys_rst_ni) sys_payload_start_idx_o <= '0;
Tests: T1 T2 T3 | T1 T2 T3
391 2/2 else if (sys_payloadptr_clr_posedge) sys_payload_start_idx_o <= '0;
Tests: T1 T2 T3 | T19 T32 T54
392 1/1 else if (sys_cmdfifo_set && payload_max) begin
Tests: T1 T2 T3
393 // Payload reached the max, need to tell SW the exact location SW shoul
394 // read
395 1/1 sys_payload_start_idx_o <= payloadptr;
Tests: T19 T32 T54
396 1/1 end else if (sys_cmdfifo_set && !payload_max) begin
Tests: T1 T2 T3
397 // Payload buffer has not been reached to the max, the start index
398 // should be 0 for SW to read from the first of the buffer.
399 1/1 sys_payload_start_idx_o <= '0;
Tests: T19 T32 T54
400 end
MISSING_ELSE
401 end
402
403 // Overflow event
404 // When the SPI host system issues more than 256B payload, HW stores the
405 // overflow event in SCK then notify to SW when CSb is deasserted
406 logic event_payload_overflow;
407 always_ff @(posedge clk_i or negedge sys_rst_ni) begin
408 2/2 if (!sys_rst_ni) event_payload_overflow <= 1'b 0;
Tests: T1 T2 T3 | T1 T2 T3
409 2/2 else if (payloadptr_clr) event_payload_overflow <= 1'b 0;
Tests: T4 T5 T6 | T19 T32 T54
410 1/1 else if (payloadptr_inc && payload_max) begin
Tests: T4 T5 T6
411 1/1 event_payload_overflow <= 1'b 1;
Tests: T32 T54 T49
412 end
MISSING_ELSE
413 end
414
415 // Sync to SYSCLK when CSb release. Edge detection on the spi_device top
416 logic sys_event_payload_overflow;
417 always_ff @(posedge sys_clk_i or negedge sys_rst_ni) begin
418 2/2 if (!sys_rst_ni) sys_event_payload_overflow <= 1'b 0;
Tests: T1 T2 T3 | T1 T2 T3
419 2/2 else if (sys_payloadptr_clr_posedge) sys_event_payload_overflow <= 1'b 0;
Tests: T1 T2 T3 | T19 T32 T54
420 1/1 else if (sys_cmdfifo_set) begin
Tests: T1 T2 T3
421 1/1 sys_event_payload_overflow <= event_payload_overflow;
Tests: T19 T32 T54
422 end
MISSING_ELSE
423 end
424
425 1/1 assign sys_payload_overflow_o = sys_event_payload_overflow;
Tests: T1 T2 T3
426
427 always_ff @(posedge clk_i or negedge rst_ni) begin
428 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
429 1/1 st_q <= StIdle;
Tests: T1 T2 T3
430 end else begin
431 1/1 st_q <= st_d;
Tests: T7 T8 T9
432 end
433 end
434
435
436 // State Machine runs in SCK domain
437 always_comb begin
438 1/1 st_d = st_q;
Tests: T1 T2 T3
439
440 1/1 cmdfifo_wvalid = 1'b 0;
Tests: T1 T2 T3
441 1/1 addrfifo_wvalid = 1'b 0;
Tests: T1 T2 T3
442 1/1 payload_wvalid = 1'b 0;
Tests: T1 T2 T3
443
444 1/1 addr_update = 1'b 0;
Tests: T1 T2 T3
445 1/1 addr_shift = 1'b 0;
Tests: T1 T2 T3
446
447 1/1 set_busy_o = 1'b 0;
Tests: T1 T2 T3
448
449 1/1 payloadptr_clr = 1'b 0;
Tests: T1 T2 T3
450 1/1 payloadptr_inc = 1'b 0;
Tests: T1 T2 T3
451
452 1/1 unique case (st_q)
Tests: T1 T2 T3
453 StIdle: begin
454 1/1 if (s2p_valid_i && cmd_only_sel_dp_i == DpUpload) begin
Tests: T1 T2 T3
455 1/1 if (cmdinfo_addr_en) begin
Tests: T19 T32 T54
456 1/1 st_d = StAddress;
Tests: T19 T32 T54
457
458 // Address process (determines 32bit or 24bit)
459 1/1 addr_update = 1'b 1;
Tests: T19 T32 T54
460 end else begin
461 1/1 st_d = StPayload;
Tests: T32 T54 T49
462 end
463
464 // Upload to SRAM right away.
465 1/1 cmdfifo_wvalid = 1'b 1;
Tests: T19 T32 T54
466
467 // Assume cmdfifo_wready is 1 always (need to add assumption)
468
469 1/1 if (cmd_only_info_i.busy) begin
Tests: T19 T32 T54
470 // Set BUSY
471 1/1 set_busy_o = 1'b 1;
Tests: T19 T32 T54
472 end
==> MISSING_ELSE
473
474 // Clear payload counter
475 1/1 payloadptr_clr = 1'b 1;
Tests: T19 T32 T54
476
477 end
MISSING_ELSE
478 end
479
480 StAddress: begin
481 1/1 addr_shift = 1'b 1;
Tests: T19 T32 T54
482
483 1/1 if (addrcnt == '0) begin
Tests: T19 T32 T54
484 1/1 st_d = StPayload;
Tests: T19 T32 T54
485
486 1/1 addrfifo_wvalid = 1'b 1;
Tests: T19 T32 T54
487 end
MISSING_ELSE
488 end
489
490 StPayload: begin
491 // TERMINAL_STATE
492 1/1 if (s2p_valid_i) begin
Tests: T19 T32 T54
493 1/1 payload_wvalid = 1'b 1;
Tests: T19 T32 T54
494 1/1 payloadptr_inc = 1'b 1;
Tests: T19 T32 T54
495 end
MISSING_ELSE
496
497 // ASSUME payload_wready == 1'b1
498 end
499
500 default: begin
501 st_d = StIdle;
502 end
503 endcase
504 end
505
506 //////////////
507 // Instance //
508 //////////////
509
510 // FIFO reset:
511 // To maintain the pointer on read/ write side same, the FIFO uses
512 // sys_rst_ni rather than rst_ni for the write port. The pointer is
513 // maintained throughout the SPI transactions (CSb assertion/ de-assertion).
514 //
515 // As sys_rst_ni is not synchronized to the external clock, the sys_rst_ni
516 // should be de-asserted when SPI line is in idle (CSb == 1).
517
518 // CmdFifo
519 prim_fifo_async_sram_adapter #(
520 .Width (CmdFifoWidth),
521 .Depth (CmdFifoDepth),
522 .SramAw (SramAw),
523 .SramDw (SramDw),
524 .SramBaseAddr (CmdFifoBaseAddr)
525 ) u_cmdfifo (
526 .clk_wr_i (clk_i),
527 .rst_wr_ni (sys_rst_ni),
528 .wvalid_i (cmdfifo_wvalid),
529 .wready_o (cmdfifo_wready),
530 .wdata_i (cmdfifo_wdata ),
531 .wdepth_o (cmdfifo_depth),
532
533 .clk_rd_i (sys_clk_i),
534 .rst_rd_ni (sys_rst_ni),
535 .rvalid_o (sys_cmdfifo_rvalid_o),
536 .rready_i (sys_cmdfifo_rready_i),
537 .rdata_o (sys_cmdfifo_rdata_o),
538 .rdepth_o (sys_cmdfifo_depth_o),
539
540 .r_full_o (sys_cmdfifo_full_o),
541 // Not directly use `notempty` as an interrupt. Rather generated from the
542 // upload logic to delay the cmdfifo_notempty interrupt.
543 // See #11871
544 .r_notempty_o (sys_cmdfifo_notempty_o),
545
546 .w_full_o (),
547
548 .w_sram_req_o (sck_sram_req [SramCmdFifo]),
549 .w_sram_gnt_i (sck_sram_gnt [SramCmdFifo]),
550 .w_sram_write_o (sck_sram_write [SramCmdFifo]),
551 .w_sram_addr_o (sck_sram_addr [SramCmdFifo]),
552 .w_sram_wdata_o (sck_sram_wdata [SramCmdFifo]),
553 .w_sram_wmask_o (sck_sram_wmask [SramCmdFifo]),
554 .w_sram_rvalid_i (sck_sram_rvalid [SramCmdFifo]),
555 .w_sram_rdata_i (sck_sram_rdata [SramCmdFifo]),
556 .w_sram_rerror_i (sck_sram_rerror [SramCmdFifo]),
557
558 .r_sram_req_o (sys_sram_req [SramCmdFifo]),
559 .r_sram_gnt_i (sys_sram_gnt [SramCmdFifo]),
560 .r_sram_write_o (sys_sram_write [SramCmdFifo]),
561 .r_sram_addr_o (sys_sram_addr [SramCmdFifo]),
562 .r_sram_wdata_o (sys_sram_wdata [SramCmdFifo]),
563 .r_sram_wmask_o (sys_sram_wmask [SramCmdFifo]),
564 .r_sram_rvalid_i (sys_sram_rvalid [SramCmdFifo]),
565 .r_sram_rdata_i (sys_sram_rdata [SramCmdFifo]),
566 .r_sram_rerror_i (sys_sram_rerror [SramCmdFifo])
567 );
568
569 // Connect to sys_cmdfifo_sram_o/_i
570 1/1 assign sys_cmdfifo_sram_o = '{
Tests: T1 T2 T3
571 req: sys_sram_req [SramCmdFifo],
572 we: sys_sram_write [SramCmdFifo],
573 addr: sys_sram_addr [SramCmdFifo],
574 wdata: sys_sram_wdata [SramCmdFifo],
575 wstrb: sram_mask2strb(sys_sram_wmask [SramCmdFifo])
576 };
577 1/1 assign sys_sram_rvalid [SramCmdFifo] = sys_cmdfifo_sram_i.rvalid;
Tests: T1 T2 T3
578 1/1 assign sys_sram_rdata [SramCmdFifo] = sys_cmdfifo_sram_i.rdata ;
Tests: T3 T6 T25
579 1/1 assign sys_sram_rerror [SramCmdFifo] = sys_cmdfifo_sram_i.rerror;
Tests: T1 T2 T3
580 1/1 assign sys_sram_gnt [SramCmdFifo] = sys_cmdfifo_gnt_i;
Tests: T1 T2 T3
581
582 // AddrFifo
583 prim_fifo_async_sram_adapter #(
584 .Width (AddrFifoWidth),
585 .Depth (AddrFifoDepth),
586 .SramAw (SramAw),
587 .SramDw (SramDw),
588 .SramBaseAddr (AddrFifoBaseAddr)
589 ) u_addrfifo (
590 .clk_wr_i (clk_i),
591 .rst_wr_ni (sys_rst_ni),
592 .wvalid_i (addrfifo_wvalid),
593 .wready_o (addrfifo_wready),
594 .wdata_i (addrfifo_wdata ),
595 .wdepth_o (),
596
597 .clk_rd_i (sys_clk_i),
598 .rst_rd_ni (sys_rst_ni),
599 .rvalid_o (sys_addrfifo_rvalid_o),
600 .rready_i (sys_addrfifo_rready_i),
601 .rdata_o (sys_addrfifo_rdata_o),
602 .rdepth_o (sys_addrfifo_depth_o),
603
604 .r_full_o (sys_addrfifo_full_o),
605 .r_notempty_o (sys_addrfifo_notempty_o),
606
607 .w_full_o (),
608
609 .w_sram_req_o (sck_sram_req [SramAddrFifo]),
610 .w_sram_gnt_i (sck_sram_gnt [SramAddrFifo]),
611 .w_sram_write_o (sck_sram_write [SramAddrFifo]),
612 .w_sram_addr_o (sck_sram_addr [SramAddrFifo]),
613 .w_sram_wdata_o (sck_sram_wdata [SramAddrFifo]),
614 .w_sram_wmask_o (sck_sram_wmask [SramAddrFifo]),
615 .w_sram_rvalid_i (sck_sram_rvalid [SramAddrFifo]),
616 .w_sram_rdata_i (sck_sram_rdata [SramAddrFifo]),
617 .w_sram_rerror_i (sck_sram_rerror [SramAddrFifo]),
618
619 .r_sram_req_o (sys_sram_req [SramAddrFifo]),
620 .r_sram_gnt_i (sys_sram_gnt [SramAddrFifo]),
621 .r_sram_write_o (sys_sram_write [SramAddrFifo]),
622 .r_sram_addr_o (sys_sram_addr [SramAddrFifo]),
623 .r_sram_wdata_o (sys_sram_wdata [SramAddrFifo]),
624 .r_sram_wmask_o (sys_sram_wmask [SramAddrFifo]),
625 .r_sram_rvalid_i (sys_sram_rvalid [SramAddrFifo]),
626 .r_sram_rdata_i (sys_sram_rdata [SramAddrFifo]),
627 .r_sram_rerror_i (sys_sram_rerror [SramAddrFifo])
628 );
629 // Connect to sys_addrfifo_sram_o/_i
630 1/1 assign sys_addrfifo_sram_o = '{
Tests: T1 T2 T3
631 req: sys_sram_req [SramAddrFifo],
632 we: sys_sram_write [SramAddrFifo],
633 addr: sys_sram_addr [SramAddrFifo],
634 wdata: sys_sram_wdata [SramAddrFifo],
635 wstrb: sram_mask2strb(sys_sram_wmask [SramAddrFifo])
636 };
637 1/1 assign sys_sram_rvalid [SramAddrFifo] = sys_addrfifo_sram_i.rvalid;
Tests: T1 T2 T3
638 1/1 assign sys_sram_rdata [SramAddrFifo] = sys_addrfifo_sram_i.rdata ;
Tests: T3 T6 T25
639 1/1 assign sys_sram_rerror [SramAddrFifo] = sys_addrfifo_sram_i.rerror;
Tests: T1 T2 T3
640 1/1 assign sys_sram_gnt [SramAddrFifo] = sys_addrfifo_gnt_i;
Tests: T1 T2 T3
641
642 // Payload Buffer
643 spid_fifo2sram_adapter #(
644 .FifoWidth (SpiByte),
645 .FifoDepth (PayloadByte),
646
647 .SramAw (SramAw),
648 .SramDw (SramDw),
649 .SramBaseAddr (PayloadBaseAddr),
650
651 // CFG
652 .EnPack (1'b1)
653 ) u_payload_buffer (
654 .clk_i,
655 .rst_ni,
656 .clr_i (1'b0),
657
658 .wvalid_i (payload_wvalid),
659 .wready_o (payload_wready),
660 .wdata_i (payload_wdata ),
661
662 // Does not use wdepth from the buffer as it is reset by CSb.
663 .wdepth_o (),
664
665 .sram_req_o (sck_sram_req [SramPayload]),
666 .sram_gnt_i (sck_sram_gnt [SramPayload]),
667 .sram_write_o (sck_sram_write [SramPayload]),
668 .sram_addr_o (sck_sram_addr [SramPayload]),
669 .sram_wdata_o (sck_sram_wdata [SramPayload]),
670 .sram_wmask_o (sck_sram_wmask [SramPayload]),
671 .sram_rvalid_i (sck_sram_rvalid [SramPayload]),
672 .sram_rdata_i (sck_sram_rdata [SramPayload]),
673 .sram_rerror_i (sck_sram_rerror [SramPayload])
674 );
675
676 // SramArbiter
677 logic [SramDw-1:0] sram_wmask;
678 prim_sram_arbiter #(
679 .N (NumSramIntf),
680 .SramDw (SramDw),
681 .SramAw (SramAw),
682 .EnMask (1'b 1)
683 ) u_arbiter (
684 .clk_i,
685 .rst_ni,
686
687 .req_i (sck_sram_req),
688 .req_addr_i (sck_sram_addr),
689 .req_write_i (sck_sram_write),
690 .req_wdata_i (sck_sram_wdata),
691 .req_wmask_i (sck_sram_wmask),
692 .gnt_o (sck_sram_gnt),
693
694 .rsp_rvalid_o (sck_sram_rvalid), // not used
695 .rsp_rdata_o (sck_sram_rdata), // not used
696 .rsp_error_o (sck_sram_rerror),
697
698 .sram_req_o (sck_sram_o.req),
699 .sram_addr_o (sck_sram_o.addr),
700 .sram_write_o (sck_sram_o.we),
701 .sram_wdata_o (sck_sram_o.wdata),
702 .sram_wmask_o (sram_wmask),
703 .sram_rvalid_i (sck_sram_i.rvalid),
704 .sram_rdata_i (sck_sram_i.rdata),
705 .sram_rerror_i (sck_sram_i.rerror)
706 );
707 1/1 assign sck_sram_o.wstrb = sram_mask2strb(sram_wmask);
Tests: T1 T2 T3
Cond Coverage for Module :
spid_upload
| Total | Covered | Percent |
|---|
| Conditions | 36 | 31 | 86.11 |
| Logical | 36 | 31 | 86.11 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 242
EXPRESSION (cmdinfo_addr_mode != AddrDisabled)
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 244
EXPRESSION (cmdinfo_addr_mode == Addr4B)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 257
EXPRESSION (cmdinfo_addr_4b_en ? 5'd31 : 5'd23)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T19,T32,T49 |
| 1 | Covered | T19,T54,T49 |
LINE 270
EXPRESSION (s2p_valid_i && addr_shift)
-----1----- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T19,T32,T54 |
| 1 | 0 | Covered | T7,T8,T9 |
| 1 | 1 | Covered | T19,T32,T54 |
LINE 307
EXPRESSION (cmdfifo_wvalid && cmdfifo_wready)
-------1------ -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T19,T32,T54 |
LINE 353
EXPRESSION (payloadptr == 8'((PayloadByte - 1)))
------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T19,T32,T54 |
| 1 | Covered | T19,T32,T54 |
LINE 369
EXPRESSION (sys_cmdfifo_set && payload_max)
-------1------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T19,T32,T54 |
| 1 | 0 | Covered | T19,T32,T54 |
| 1 | 1 | Covered | T19,T32,T54 |
LINE 371
EXPRESSION (sys_cmdfifo_set && ((!payload_max)))
-------1------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T19,T32,T54 |
LINE 392
EXPRESSION (sys_cmdfifo_set && payload_max)
-------1------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T19,T32,T54 |
| 1 | 0 | Covered | T19,T32,T54 |
| 1 | 1 | Covered | T19,T32,T54 |
LINE 396
EXPRESSION (sys_cmdfifo_set && ((!payload_max)))
-------1------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T19,T32,T54 |
LINE 410
EXPRESSION (payloadptr_inc && payload_max)
-------1------ -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T19,T32,T54 |
| 1 | 0 | Covered | T19,T32,T54 |
| 1 | 1 | Covered | T32,T54,T49 |
LINE 454
EXPRESSION (s2p_valid_i && (cmd_only_sel_dp_i == DpUpload))
-----1----- ---------------2---------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T7,T8,T9 |
| 1 | 1 | Covered | T19,T32,T54 |
LINE 454
SUB-EXPRESSION (cmd_only_sel_dp_i == DpUpload)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T19,T32,T54 |
LINE 483
EXPRESSION (addrcnt == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T19,T32,T54 |
| 1 | Covered | T19,T32,T54 |
FSM Coverage for Module :
spid_upload
Summary for FSM :: st_q
| Total | Covered | Percent | |
| States |
3 |
3 |
100.00 |
(Not included in score) |
| Transitions |
3 |
3 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: st_q
| states | Line No. | Covered | Tests |
| StAddress |
456 |
Covered |
T19,T32,T54 |
| StIdle |
453 |
Covered |
T1,T2,T3 |
| StPayload |
461 |
Covered |
T19,T32,T54 |
| transitions | Line No. | Covered | Tests |
| StAddress->StPayload |
484 |
Covered |
T19,T32,T54 |
| StIdle->StAddress |
456 |
Covered |
T19,T32,T54 |
| StIdle->StPayload |
461 |
Covered |
T32,T54,T49 |
Branch Coverage for Module :
spid_upload
| Line No. | Total | Covered | Percent |
| Branches |
|
47 |
45 |
95.74 |
| IF |
256 |
5 |
5 |
100.00 |
| IF |
263 |
2 |
2 |
100.00 |
| IF |
268 |
3 |
3 |
100.00 |
| IF |
322 |
2 |
2 |
100.00 |
| IF |
346 |
5 |
5 |
100.00 |
| IF |
367 |
5 |
5 |
100.00 |
| IF |
390 |
5 |
5 |
100.00 |
| IF |
408 |
4 |
4 |
100.00 |
| IF |
418 |
4 |
4 |
100.00 |
| IF |
428 |
2 |
2 |
100.00 |
| CASE |
452 |
10 |
8 |
80.00 |
256 if (!rst_ni) addrcnt <= '0;
-1-
==>
257 else if (addr_update) addrcnt <= cmdinfo_addr_4b_en ? 5'd 31 : 5'd 23;
-2- -3-
==>
==>
258 else if (addr_shift) addrcnt <= addrcnt - 5'd 1;
-4-
==>
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
1 |
- |
Covered |
T19,T54,T49 |
| 0 |
1 |
0 |
- |
Covered |
T19,T32,T49 |
| 0 |
0 |
- |
1 |
Covered |
T19,T32,T54 |
| 0 |
0 |
- |
0 |
Covered |
T7,T8,T9 |
263 if (addr_shift) begin
-1-
264 address_d = {address_q[23:0], s2p_byte_i};
==>
265 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T19,T32,T54 |
| 0 |
Covered |
T1,T2,T3 |
268 if (!rst_ni) begin
-1-
269 address_q <= '0;
==>
270 end else if (s2p_valid_i && addr_shift) begin
-2-
271 address_q <= address_d;
==>
272 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T19,T32,T54 |
| 0 |
0 |
Covered |
T7,T8,T9 |
322 if (!sys_rst_ni) begin
-1-
323 sys_cmdfifo_set_o <= 1'b0;
==>
324 end else begin
325 sys_cmdfifo_set_o <= sys_cmdfifo_set;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
346 if (!sys_rst_ni) begin
-1-
347 payload_max <= 1'b 0;
==>
348 payloadptr <= '0;
349 end else if (payloadptr_clr) begin
-2-
350 payloadptr <= '0;
==>
351 payload_max <= 1'b 0;
352 end else if (payloadptr_inc) begin
-3-
353 if (payloadptr == PayloadIdxW'(PayloadByte-1)) begin
-4-
354 // payloadptr reached max
355 payload_max <= 1'b 1;
==>
356 end
MISSING_ELSE
==>
357 payloadptr <= payloadptr + PayloadIdxW'(1);
358 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
Covered |
T19,T32,T54 |
| 0 |
0 |
1 |
1 |
Covered |
T19,T32,T54 |
| 0 |
0 |
1 |
0 |
Covered |
T19,T32,T54 |
| 0 |
0 |
0 |
- |
Covered |
T4,T5,T6 |
367 if (!sys_rst_ni) sys_payload_depth_o <= '0;
-1-
==>
368 else if (sys_payloadptr_clr_posedge) sys_payload_depth_o <= '0;
-2-
==>
369 else if (sys_cmdfifo_set && payload_max) begin
-3-
370 sys_payload_depth_o <= PayloadPtrW'(PayloadByte);
==>
371 end else if (sys_cmdfifo_set && !payload_max) begin
-4-
372 sys_payload_depth_o <= PayloadPtrW'(payloadptr);
==>
373 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
Covered |
T19,T32,T54 |
| 0 |
0 |
1 |
- |
Covered |
T19,T32,T54 |
| 0 |
0 |
0 |
1 |
Covered |
T19,T32,T54 |
| 0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
390 if (!sys_rst_ni) sys_payload_start_idx_o <= '0;
-1-
==>
391 else if (sys_payloadptr_clr_posedge) sys_payload_start_idx_o <= '0;
-2-
==>
392 else if (sys_cmdfifo_set && payload_max) begin
-3-
393 // Payload reached the max, need to tell SW the exact location SW shoul
394 // read
395 sys_payload_start_idx_o <= payloadptr;
==>
396 end else if (sys_cmdfifo_set && !payload_max) begin
-4-
397 // Payload buffer has not been reached to the max, the start index
398 // should be 0 for SW to read from the first of the buffer.
399 sys_payload_start_idx_o <= '0;
==>
400 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
Covered |
T19,T32,T54 |
| 0 |
0 |
1 |
- |
Covered |
T19,T32,T54 |
| 0 |
0 |
0 |
1 |
Covered |
T19,T32,T54 |
| 0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
408 if (!sys_rst_ni) event_payload_overflow <= 1'b 0;
-1-
==>
409 else if (payloadptr_clr) event_payload_overflow <= 1'b 0;
-2-
==>
410 else if (payloadptr_inc && payload_max) begin
-3-
411 event_payload_overflow <= 1'b 1;
==>
412 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T19,T32,T54 |
| 0 |
0 |
1 |
Covered |
T32,T54,T49 |
| 0 |
0 |
0 |
Covered |
T4,T5,T6 |
418 if (!sys_rst_ni) sys_event_payload_overflow <= 1'b 0;
-1-
==>
419 else if (sys_payloadptr_clr_posedge) sys_event_payload_overflow <= 1'b 0;
-2-
==>
420 else if (sys_cmdfifo_set) begin
-3-
421 sys_event_payload_overflow <= event_payload_overflow;
==>
422 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T19,T32,T54 |
| 0 |
0 |
1 |
Covered |
T19,T32,T54 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
428 if (!rst_ni) begin
-1-
429 st_q <= StIdle;
==>
430 end else begin
431 st_q <= st_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T7,T8,T9 |
452 unique case (st_q)
-1-
453 StIdle: begin
454 if (s2p_valid_i && cmd_only_sel_dp_i == DpUpload) begin
-2-
455 if (cmdinfo_addr_en) begin
-3-
456 st_d = StAddress;
==>
457
458 // Address process (determines 32bit or 24bit)
459 addr_update = 1'b 1;
460 end else begin
461 st_d = StPayload;
==>
462 end
463
464 // Upload to SRAM right away.
465 cmdfifo_wvalid = 1'b 1;
466
467 // Assume cmdfifo_wready is 1 always (need to add assumption)
468
469 if (cmd_only_info_i.busy) begin
-4-
470 // Set BUSY
471 set_busy_o = 1'b 1;
==>
472 end
MISSING_ELSE
==>
473
474 // Clear payload counter
475 payloadptr_clr = 1'b 1;
476
477 end
MISSING_ELSE
==>
478 end
479
480 StAddress: begin
481 addr_shift = 1'b 1;
482
483 if (addrcnt == '0) begin
-5-
484 st_d = StPayload;
==>
485
486 addrfifo_wvalid = 1'b 1;
487 end
MISSING_ELSE
==>
488 end
489
490 StPayload: begin
491 // TERMINAL_STATE
492 if (s2p_valid_i) begin
-6-
493 payload_wvalid = 1'b 1;
==>
494 payloadptr_inc = 1'b 1;
495 end
MISSING_ELSE
==>
496
497 // ASSUME payload_wready == 1'b1
498 end
499
500 default: begin
501 st_d = StIdle;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
| StIdle |
1 |
1 |
- |
- |
- |
Covered |
T19,T32,T54 |
| StIdle |
1 |
0 |
- |
- |
- |
Covered |
T32,T54,T49 |
| StIdle |
1 |
- |
1 |
- |
- |
Covered |
T19,T32,T54 |
| StIdle |
1 |
- |
0 |
- |
- |
Not Covered |
|
| StIdle |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| StAddress |
- |
- |
- |
1 |
- |
Covered |
T19,T32,T54 |
| StAddress |
- |
- |
- |
0 |
- |
Covered |
T19,T32,T54 |
| StPayload |
- |
- |
- |
- |
1 |
Covered |
T19,T32,T54 |
| StPayload |
- |
- |
- |
- |
0 |
Covered |
T19,T32,T54 |
| default |
- |
- |
- |
- |
- |
Not Covered |
|
Assert Coverage for Module :
spid_upload
Assertion Details
AddrFifoNeverFull_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
146533180 |
1591 |
0 |
0 |
| T19 |
54696 |
2 |
0 |
0 |
| T23 |
0 |
4 |
0 |
0 |
| T29 |
95700 |
0 |
0 |
0 |
| T30 |
277088 |
0 |
0 |
0 |
| T32 |
305619 |
5 |
0 |
0 |
| T33 |
1343 |
0 |
0 |
0 |
| T34 |
3433 |
0 |
0 |
0 |
| T36 |
0 |
5 |
0 |
0 |
| T45 |
15496 |
0 |
0 |
0 |
| T46 |
0 |
14 |
0 |
0 |
| T47 |
0 |
7 |
0 |
0 |
| T49 |
0 |
7 |
0 |
0 |
| T50 |
0 |
6 |
0 |
0 |
| T51 |
108824 |
0 |
0 |
0 |
| T54 |
0 |
7 |
0 |
0 |
| T55 |
2080 |
0 |
0 |
0 |
| T56 |
61949 |
0 |
0 |
0 |
| T81 |
0 |
6 |
0 |
0 |
CmdFifoNeverFull_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
146533180 |
2141 |
0 |
0 |
| T19 |
54696 |
2 |
0 |
0 |
| T23 |
0 |
7 |
0 |
0 |
| T29 |
95700 |
0 |
0 |
0 |
| T30 |
277088 |
0 |
0 |
0 |
| T32 |
305619 |
6 |
0 |
0 |
| T33 |
1343 |
0 |
0 |
0 |
| T34 |
3433 |
0 |
0 |
0 |
| T36 |
0 |
10 |
0 |
0 |
| T45 |
15496 |
0 |
0 |
0 |
| T46 |
0 |
16 |
0 |
0 |
| T47 |
0 |
7 |
0 |
0 |
| T49 |
0 |
8 |
0 |
0 |
| T50 |
0 |
9 |
0 |
0 |
| T51 |
108824 |
0 |
0 |
0 |
| T54 |
0 |
10 |
0 |
0 |
| T55 |
2080 |
0 |
0 |
0 |
| T56 |
61949 |
0 |
0 |
0 |
| T81 |
0 |
13 |
0 |
0 |
CmdFifoPush_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
146533180 |
2141 |
0 |
0 |
| T19 |
54696 |
2 |
0 |
0 |
| T23 |
0 |
7 |
0 |
0 |
| T29 |
95700 |
0 |
0 |
0 |
| T30 |
277088 |
0 |
0 |
0 |
| T32 |
305619 |
6 |
0 |
0 |
| T33 |
1343 |
0 |
0 |
0 |
| T34 |
3433 |
0 |
0 |
0 |
| T36 |
0 |
10 |
0 |
0 |
| T45 |
15496 |
0 |
0 |
0 |
| T46 |
0 |
16 |
0 |
0 |
| T47 |
0 |
7 |
0 |
0 |
| T49 |
0 |
8 |
0 |
0 |
| T50 |
0 |
9 |
0 |
0 |
| T51 |
108824 |
0 |
0 |
0 |
| T54 |
0 |
10 |
0 |
0 |
| T55 |
2080 |
0 |
0 |
0 |
| T56 |
61949 |
0 |
0 |
0 |
| T81 |
0 |
13 |
0 |
0 |
FifosOnlyOneValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
146533180 |
119952536 |
0 |
0 |
| T7 |
31058 |
31058 |
0 |
0 |
| T8 |
10480 |
10480 |
0 |
0 |
| T9 |
8888 |
8888 |
0 |
0 |
| T10 |
109671 |
0 |
0 |
0 |
| T11 |
14640 |
14640 |
0 |
0 |
| T12 |
5392 |
5392 |
0 |
0 |
| T13 |
93908 |
93738 |
0 |
0 |
| T14 |
16979 |
16979 |
0 |
0 |
| T17 |
0 |
2128 |
0 |
0 |
| T18 |
0 |
96 |
0 |
0 |
| T19 |
0 |
54621 |
0 |
0 |
| T26 |
1159 |
0 |
0 |
0 |
| T27 |
3656 |
0 |
0 |
0 |
PayloadNeverFull_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
146533180 |
802631 |
0 |
0 |
| T19 |
54696 |
260 |
0 |
0 |
| T23 |
0 |
2223 |
0 |
0 |
| T29 |
95700 |
0 |
0 |
0 |
| T30 |
277088 |
0 |
0 |
0 |
| T32 |
305619 |
1634 |
0 |
0 |
| T33 |
1343 |
0 |
0 |
0 |
| T34 |
3433 |
0 |
0 |
0 |
| T36 |
0 |
6648 |
0 |
0 |
| T45 |
15496 |
0 |
0 |
0 |
| T46 |
0 |
2215 |
0 |
0 |
| T47 |
0 |
5582 |
0 |
0 |
| T49 |
0 |
1444 |
0 |
0 |
| T50 |
0 |
2215 |
0 |
0 |
| T51 |
108824 |
0 |
0 |
0 |
| T54 |
0 |
4050 |
0 |
0 |
| T55 |
2080 |
0 |
0 |
0 |
| T56 |
61949 |
0 |
0 |
0 |
| T81 |
0 |
1849 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_upload
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 109 | 109 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 143 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 206 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 213 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 234 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 241 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 246 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 251 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
| ALWAYS | 256 | 6 | 6 | 100.00 |
| ALWAYS | 262 | 3 | 3 | 100.00 |
| ALWAYS | 268 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 307 | 1 | 1 | 100.00 |
| ALWAYS | 322 | 3 | 3 | 100.00 |
| ALWAYS | 346 | 10 | 10 | 100.00 |
| ALWAYS | 367 | 8 | 8 | 100.00 |
| ALWAYS | 390 | 8 | 8 | 100.00 |
| ALWAYS | 408 | 6 | 6 | 100.00 |
| ALWAYS | 418 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
| ALWAYS | 428 | 3 | 3 | 100.00 |
| ALWAYS | 438 | 26 | 26 | 100.00 |
| CONT_ASSIGN | 570 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 577 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 578 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 579 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 580 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 630 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 637 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 638 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 639 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 640 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 707 | 1 | 1 | 100.00 |
133 spi_mode_e unused_spi_mode;
134 1/1 assign unused_spi_mode = spi_mode_i;
Tests: T1 T2 T3
135
136 sel_datapath_e unused_sel_dp;
137 1/1 assign unused_sel_dp = sel_dp_i;
Tests: T1 T2 T3
138
139 assign p2s_valid_o = 1'b 0;
140 assign p2s_data_o = '0;
141
142 logic unused_p2s_sent;
143 1/1 assign unused_p2s_sent = p2s_sent_i;
Tests: T1 T2 T3
144
145 ////////////////
146 // Definition //
147 ////////////////
148 typedef enum int unsigned {
149 SramCmdFifo = 0,
150 SramAddrFifo = 1,
151 SramPayload = 2
152 } sramintf_e;
153 localparam int unsigned NumSramIntf = 3;
154
155 typedef enum logic [1:0] {
156 StIdle,
157 StAddress,
158 StPayload
159 } st_e;
160 st_e st_q, st_d;
161
162 ////////////
163 // Signal //
164 ////////////
165
166 // SRAM access (to SRAM Arbiter)
167 logic [NumSramIntf-1:0] sck_sram_req;
168 logic [NumSramIntf-1:0] sck_sram_gnt;
169 logic [NumSramIntf-1:0] sck_sram_write;
170 logic [SramAw-1:0] sck_sram_addr [NumSramIntf];
171 logic [SramDw-1:0] sck_sram_wdata [NumSramIntf];
172 logic [SramDw-1:0] sck_sram_wmask [NumSramIntf];
173 logic [NumSramIntf-1:0] sck_sram_rvalid; // not used
174 logic [SramDw-1:0] sck_sram_rdata [NumSramIntf]; // not used
175 logic [1:0] sck_sram_rerror [NumSramIntf]; // not used
176
177 logic [NumSramIntf-2:0] sys_sram_req;
178 logic [NumSramIntf-2:0] sys_sram_gnt;
179 logic [NumSramIntf-2:0] sys_sram_write;
180 logic [SramAw-1:0] sys_sram_addr [NumSramIntf-1];
181 logic [SramDw-1:0] sys_sram_wdata [NumSramIntf-1];
182 logic [SramDw-1:0] sys_sram_wmask [NumSramIntf-1];
183 logic [NumSramIntf-2:0] sys_sram_rvalid; // not used
184 logic [SramDw-1:0] sys_sram_rdata [NumSramIntf-1]; // not used
185 logic [1:0] sys_sram_rerror [NumSramIntf-1]; // not used
186
187 logic cmdfifo_wvalid;
188 logic cmdfifo_wready; // Assume always ready
189 logic [15:0] cmdfifo_wdata ;
190 logic [CmdPtrW-1:0] cmdfifo_depth; // Write side depth to check if FIFO empty
191
192 // cmdfifo_depth is used in assertion not in the logic.
193 logic unused_cmdfifo_depth;
194 1/1 assign unused_cmdfifo_depth = ^cmdfifo_depth;
Tests: T1 T2 T3
195
196 logic addrfifo_wvalid;
197 logic addrfifo_wready; // Assume always ready
198 logic [31:0] addrfifo_wdata ;
199
200 logic payload_wvalid;
201 logic payload_wready; // Assume always ready
202 logic [7:0] payload_wdata ;
203
204 // Unused wready
205 logic unused_fifo_wready;
206 1/1 assign unused_fifo_wready = ^{cmdfifo_wready, addrfifo_wready, payload_wready};
Tests: T1 T2 T3
207
208 // Simplified command info
209 addr_mode_e cmdinfo_addr_mode;
210 logic cmdinfo_addr_en, cmdinfo_addr_4b_en;
211
212 logic unused_cmdinfo;
213 1/1 assign unused_cmdinfo = ^{
Tests: T1 T2 T3
214 cmd_only_info_i.valid, // cmdparse checks the valid bit
215 cmd_only_info_i.addr_swap_en,
216 cmd_only_info_i.dummy_en,
217 cmd_only_info_i.dummy_size,
218 cmd_only_info_i.mbyte_en,
219 cmd_only_info_i.opcode,
220 cmd_only_info_i.payload_dir,
221 cmd_only_info_i.payload_en,
222 cmd_only_info_i.payload_swap_en,
223 cmd_only_info_i.read_pipeline_mode,
224 cmd_only_info_i.upload
225 };
226
227 // Address latch
228 logic addr_update, addr_shift;
229 logic [31:0] address_q, address_d;
230 logic [AddrCntW-1:0] addrcnt;
231
232 // unused
233 logic unused_cmdinfo_idx;
234 1/1 assign unused_cmdinfo_idx = ^cmd_only_info_idx_i;
Tests: T1 T2 T3
235
236 //////////////
237 // Datapath //
238 //////////////
239
240 // Command info process
241 1/1 assign cmdinfo_addr_mode = get_addr_mode(cmd_only_info_i.addr_mode, cmd_sync_cfg_addr_4b_en_i);
Tests: T1 T2 T3
242 1/1 assign cmdinfo_addr_en = cmdinfo_addr_mode != AddrDisabled;
Tests: T1 T2 T3
243
244 1/1 assign cmdinfo_addr_4b_en = cmdinfo_addr_mode == Addr4B;
Tests: T1 T2 T3
245
246 1/1 assign cmdfifo_wdata = { cmdinfo_addr_4b_en,
Tests: T1 T2 T3
247 cmd_sync_status_wel_i,
248 cmd_sync_status_busy_i,
249 5'h00,
250 s2p_byte_i};
251 1/1 assign addrfifo_wdata = address_d;
Tests: T1 T2 T3
252 1/1 assign payload_wdata = s2p_byte_i;
Tests: T1 T2 T3
253
254 // Address counter
255 always_ff @(posedge clk_i or negedge rst_ni) begin
256 2/2 if (!rst_ni) addrcnt <= '0;
Tests: T1 T2 T3 | T1 T2 T3
257 2/2 else if (addr_update) addrcnt <= cmdinfo_addr_4b_en ? 5'd 31 : 5'd 23;
Tests: T7 T8 T9 | T19 T32 T54
258 2/2 else if (addr_shift) addrcnt <= addrcnt - 5'd 1;
Tests: T7 T8 T9 | T19 T32 T54
MISSING_ELSE
259 end
260
261 always_comb begin
262 1/1 address_d = address_q;
Tests: T1 T2 T3
263 1/1 if (addr_shift) begin
Tests: T1 T2 T3
264 1/1 address_d = {address_q[23:0], s2p_byte_i};
Tests: T19 T32 T54
265 end
MISSING_ELSE
266 end
267 always_ff @(posedge clk_i or negedge rst_ni) begin
268 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
269 1/1 address_q <= '0;
Tests: T1 T2 T3
270 1/1 end else if (s2p_valid_i && addr_shift) begin
Tests: T7 T8 T9
271 1/1 address_q <= address_d;
Tests: T19 T32 T54
272 end
MISSING_ELSE
273 end
274
275 // sys_cmdfifo_not_empty_o -> sys_cmdfifo_set_o
276 //
277 // The signal is generated from SCK domain write fifo depth signal. The
278 // reason is to delay the interrupt. If the notempty interrupt comes from
279 // the CMDFIFO directly, then SW waits the SPI transaction to be completed
280 // in order to get the correct address and payload.
281 //
282 // cmdfifo_depth (SCK) is a registered signal. So, it becomes notempty after
283 // 8th beat of the SCK. The CSb as a clock latches the signal to be != 0,
284 // then sys_cmdfifo_set signal let SYS_CLK latch the notempty signal.
285 // Because CSb as a clock is synchronous with SCK, there is no CDC issue
286 // here. Please check the chip Synopsys Design Constraints (SDC) file.
287 //
288 // The case to be considered: If two commands are back-to-back and uploaded
289 // into the CMDFIFO. Then, if SW pops the first one, the notempty keeps
290 // high. The edge detector could not catch the change.
291 //
292 // To resolve the issue describe above, the notempty interrupt @ SCK catches
293 // the current transaction only. It means that the notempty becomes one if
294 // the FIFO is empty and becomes notempty. If the FIFO is not empty and
295 // the logic pushes one more to the FIFO, it does not generate event
296 // signal.
297 //
298 // In the SYS_CLK, logics see the event. If it is high, the logic generates
299 // a pulse to set the interrupt (along with the status). So that the SW can
300 // get the event.
301
302 logic sck_cmdfifo_set, sys_cmdfifo_set;
303 `ASSERT(CmdFifoPush_A,
304 cmdfifo_wvalid && cmdfifo_wready |=> cmdfifo_depth != 0,
305 clk_i, !sys_rst_ni)
306
307 1/1 assign sck_cmdfifo_set = cmdfifo_wvalid && cmdfifo_wready;
Tests: T1 T2 T3
308
309 spid_csb_sync u_sys_cmdfifo_set (
310 .clk_i (sys_clk_i),
311 .rst_ni (sys_rst_ni),
312 .sck_i (clk_i),
313 .sck_pulse_en_i (sck_cmdfifo_set),
314 .csb_i (clk_csb_i),
315 .csb_deasserted_pulse_o (sys_cmdfifo_set)
316 );
317
318 // This block is merely to align INTR_STATE updates with the payload FIFO
319 // depth updates, so the interrupt doesn't appear a cycle before the related
320 // upload data.
321 always_ff @(posedge sys_clk_i or negedge sys_rst_ni) begin
322 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
323 1/1 sys_cmdfifo_set_o <= 1'b0;
Tests: T1 T2 T3
324 end else begin
325 1/1 sys_cmdfifo_set_o <= sys_cmdfifo_set;
Tests: T1 T2 T3
326 end
327 end
328
329 // payloadptr manage: spid_fifo2sram_adapter's fifoptr (wdepth) is reset by
330 // CSb everytime. the written payload size should be visible to SW even CSb
331 // is de-asserted.
332 //
333 // payloadptr maintains the pointer inside the Payload buffer (256B
334 // currently). If the host system issues equal to or more than 256B of the
335 // size, the payload_max is set to 1 then SW will sees always PayloadByte
336 // value from the CSR. Inside the HW, SPI_DEVICE keeps storing the incoming
337 // bytes into the payload buffer as a circular FIFO manner. The payload
338 // start index CSR represents the next pointer inside the buffer IFF the
339 // payload buffer is full. If it has not been received the full payload, the
340 // start index is 0, which means SW should read from 0.
341 logic payloadptr_inc, payloadptr_clr;
342 logic [PayloadIdxW-1:0] payloadptr;
343 // Indicate the payload reached the max value (PayloadByte)
344 logic payload_max;
345 always_ff @(posedge clk_i or negedge sys_rst_ni) begin
346 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
347 1/1 payload_max <= 1'b 0;
Tests: T1 T2 T3
348 1/1 payloadptr <= '0;
Tests: T1 T2 T3
349 1/1 end else if (payloadptr_clr) begin
Tests: T4 T5 T6
350 1/1 payloadptr <= '0;
Tests: T19 T32 T54
351 1/1 payload_max <= 1'b 0;
Tests: T19 T32 T54
352 1/1 end else if (payloadptr_inc) begin
Tests: T4 T5 T6
353 1/1 if (payloadptr == PayloadIdxW'(PayloadByte-1)) begin
Tests: T19 T32 T54
354 // payloadptr reached max
355 1/1 payload_max <= 1'b 1;
Tests: T19 T32 T54
356 end
MISSING_ELSE
357 1/1 payloadptr <= payloadptr + PayloadIdxW'(1);
Tests: T19 T32 T54
358 end
MISSING_ELSE
359 end
360
361 // Synchronize to the sys_clk when CSb deasserted
362 logic sys_payloadptr_clr_posedge;
363
364 // To trigger the payload buffer update event, the payload_depth should be
365 // reset when new upload command comes.
366 always_ff @(posedge sys_clk_i or negedge sys_rst_ni) begin
367 2/2 if (!sys_rst_ni) sys_payload_depth_o <= '0;
Tests: T1 T2 T3 | T1 T2 T3
368 2/2 else if (sys_payloadptr_clr_posedge) sys_payload_depth_o <= '0;
Tests: T1 T2 T3 | T19 T32 T54
369 1/1 else if (sys_cmdfifo_set && payload_max) begin
Tests: T1 T2 T3
370 1/1 sys_payload_depth_o <= PayloadPtrW'(PayloadByte);
Tests: T19 T32 T54
371 1/1 end else if (sys_cmdfifo_set && !payload_max) begin
Tests: T1 T2 T3
372 1/1 sys_payload_depth_o <= PayloadPtrW'(payloadptr);
Tests: T19 T32 T54
373 end
MISSING_ELSE
374 end
375
376 // payloadptr_clr --> sys domain
377 prim_pulse_sync u_payloadptr_clr_psync (
378 // source clock domain
379 .clk_src_i (clk_i),
380 .rst_src_ni (sys_rst_ni),
381 .src_pulse_i (payloadptr_clr),
382 // destination clock domain
383 .clk_dst_i (sys_clk_i),
384 .rst_dst_ni (sys_rst_ni),
385 .dst_pulse_o (sys_payloadptr_clr_posedge)
386 );
387
388 // Latch payloadptr @ CSb events
389 always_ff @(posedge sys_clk_i or negedge sys_rst_ni) begin
390 2/2 if (!sys_rst_ni) sys_payload_start_idx_o <= '0;
Tests: T1 T2 T3 | T1 T2 T3
391 2/2 else if (sys_payloadptr_clr_posedge) sys_payload_start_idx_o <= '0;
Tests: T1 T2 T3 | T19 T32 T54
392 1/1 else if (sys_cmdfifo_set && payload_max) begin
Tests: T1 T2 T3
393 // Payload reached the max, need to tell SW the exact location SW shoul
394 // read
395 1/1 sys_payload_start_idx_o <= payloadptr;
Tests: T19 T32 T54
396 1/1 end else if (sys_cmdfifo_set && !payload_max) begin
Tests: T1 T2 T3
397 // Payload buffer has not been reached to the max, the start index
398 // should be 0 for SW to read from the first of the buffer.
399 1/1 sys_payload_start_idx_o <= '0;
Tests: T19 T32 T54
400 end
MISSING_ELSE
401 end
402
403 // Overflow event
404 // When the SPI host system issues more than 256B payload, HW stores the
405 // overflow event in SCK then notify to SW when CSb is deasserted
406 logic event_payload_overflow;
407 always_ff @(posedge clk_i or negedge sys_rst_ni) begin
408 2/2 if (!sys_rst_ni) event_payload_overflow <= 1'b 0;
Tests: T1 T2 T3 | T1 T2 T3
409 2/2 else if (payloadptr_clr) event_payload_overflow <= 1'b 0;
Tests: T4 T5 T6 | T19 T32 T54
410 1/1 else if (payloadptr_inc && payload_max) begin
Tests: T4 T5 T6
411 1/1 event_payload_overflow <= 1'b 1;
Tests: T32 T54 T49
412 end
MISSING_ELSE
413 end
414
415 // Sync to SYSCLK when CSb release. Edge detection on the spi_device top
416 logic sys_event_payload_overflow;
417 always_ff @(posedge sys_clk_i or negedge sys_rst_ni) begin
418 2/2 if (!sys_rst_ni) sys_event_payload_overflow <= 1'b 0;
Tests: T1 T2 T3 | T1 T2 T3
419 2/2 else if (sys_payloadptr_clr_posedge) sys_event_payload_overflow <= 1'b 0;
Tests: T1 T2 T3 | T19 T32 T54
420 1/1 else if (sys_cmdfifo_set) begin
Tests: T1 T2 T3
421 1/1 sys_event_payload_overflow <= event_payload_overflow;
Tests: T19 T32 T54
422 end
MISSING_ELSE
423 end
424
425 1/1 assign sys_payload_overflow_o = sys_event_payload_overflow;
Tests: T1 T2 T3
426
427 always_ff @(posedge clk_i or negedge rst_ni) begin
428 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
429 1/1 st_q <= StIdle;
Tests: T1 T2 T3
430 end else begin
431 1/1 st_q <= st_d;
Tests: T7 T8 T9
432 end
433 end
434
435
436 // State Machine runs in SCK domain
437 always_comb begin
438 1/1 st_d = st_q;
Tests: T1 T2 T3
439
440 1/1 cmdfifo_wvalid = 1'b 0;
Tests: T1 T2 T3
441 1/1 addrfifo_wvalid = 1'b 0;
Tests: T1 T2 T3
442 1/1 payload_wvalid = 1'b 0;
Tests: T1 T2 T3
443
444 1/1 addr_update = 1'b 0;
Tests: T1 T2 T3
445 1/1 addr_shift = 1'b 0;
Tests: T1 T2 T3
446
447 1/1 set_busy_o = 1'b 0;
Tests: T1 T2 T3
448
449 1/1 payloadptr_clr = 1'b 0;
Tests: T1 T2 T3
450 1/1 payloadptr_inc = 1'b 0;
Tests: T1 T2 T3
451
452 1/1 unique case (st_q)
Tests: T1 T2 T3
453 StIdle: begin
454 1/1 if (s2p_valid_i && cmd_only_sel_dp_i == DpUpload) begin
Tests: T1 T2 T3
455 1/1 if (cmdinfo_addr_en) begin
Tests: T19 T32 T54
456 1/1 st_d = StAddress;
Tests: T19 T32 T54
457
458 // Address process (determines 32bit or 24bit)
459 1/1 addr_update = 1'b 1;
Tests: T19 T32 T54
460 end else begin
461 1/1 st_d = StPayload;
Tests: T32 T54 T49
462 end
463
464 // Upload to SRAM right away.
465 1/1 cmdfifo_wvalid = 1'b 1;
Tests: T19 T32 T54
466
467 // Assume cmdfifo_wready is 1 always (need to add assumption)
468
469 1/1 if (cmd_only_info_i.busy) begin
Tests: T19 T32 T54
470 // Set BUSY
471 1/1 set_busy_o = 1'b 1;
Tests: T19 T32 T54
472 end
==> MISSING_ELSE
473
474 // Clear payload counter
475 1/1 payloadptr_clr = 1'b 1;
Tests: T19 T32 T54
476
477 end
MISSING_ELSE
478 end
479
480 StAddress: begin
481 1/1 addr_shift = 1'b 1;
Tests: T19 T32 T54
482
483 1/1 if (addrcnt == '0) begin
Tests: T19 T32 T54
484 1/1 st_d = StPayload;
Tests: T19 T32 T54
485
486 1/1 addrfifo_wvalid = 1'b 1;
Tests: T19 T32 T54
487 end
MISSING_ELSE
488 end
489
490 StPayload: begin
491 // TERMINAL_STATE
492 1/1 if (s2p_valid_i) begin
Tests: T19 T32 T54
493 1/1 payload_wvalid = 1'b 1;
Tests: T19 T32 T54
494 1/1 payloadptr_inc = 1'b 1;
Tests: T19 T32 T54
495 end
MISSING_ELSE
496
497 // ASSUME payload_wready == 1'b1
498 end
499
500 default: begin
501 st_d = StIdle;
502 end
503 endcase
504 end
505
506 //////////////
507 // Instance //
508 //////////////
509
510 // FIFO reset:
511 // To maintain the pointer on read/ write side same, the FIFO uses
512 // sys_rst_ni rather than rst_ni for the write port. The pointer is
513 // maintained throughout the SPI transactions (CSb assertion/ de-assertion).
514 //
515 // As sys_rst_ni is not synchronized to the external clock, the sys_rst_ni
516 // should be de-asserted when SPI line is in idle (CSb == 1).
517
518 // CmdFifo
519 prim_fifo_async_sram_adapter #(
520 .Width (CmdFifoWidth),
521 .Depth (CmdFifoDepth),
522 .SramAw (SramAw),
523 .SramDw (SramDw),
524 .SramBaseAddr (CmdFifoBaseAddr)
525 ) u_cmdfifo (
526 .clk_wr_i (clk_i),
527 .rst_wr_ni (sys_rst_ni),
528 .wvalid_i (cmdfifo_wvalid),
529 .wready_o (cmdfifo_wready),
530 .wdata_i (cmdfifo_wdata ),
531 .wdepth_o (cmdfifo_depth),
532
533 .clk_rd_i (sys_clk_i),
534 .rst_rd_ni (sys_rst_ni),
535 .rvalid_o (sys_cmdfifo_rvalid_o),
536 .rready_i (sys_cmdfifo_rready_i),
537 .rdata_o (sys_cmdfifo_rdata_o),
538 .rdepth_o (sys_cmdfifo_depth_o),
539
540 .r_full_o (sys_cmdfifo_full_o),
541 // Not directly use `notempty` as an interrupt. Rather generated from the
542 // upload logic to delay the cmdfifo_notempty interrupt.
543 // See #11871
544 .r_notempty_o (sys_cmdfifo_notempty_o),
545
546 .w_full_o (),
547
548 .w_sram_req_o (sck_sram_req [SramCmdFifo]),
549 .w_sram_gnt_i (sck_sram_gnt [SramCmdFifo]),
550 .w_sram_write_o (sck_sram_write [SramCmdFifo]),
551 .w_sram_addr_o (sck_sram_addr [SramCmdFifo]),
552 .w_sram_wdata_o (sck_sram_wdata [SramCmdFifo]),
553 .w_sram_wmask_o (sck_sram_wmask [SramCmdFifo]),
554 .w_sram_rvalid_i (sck_sram_rvalid [SramCmdFifo]),
555 .w_sram_rdata_i (sck_sram_rdata [SramCmdFifo]),
556 .w_sram_rerror_i (sck_sram_rerror [SramCmdFifo]),
557
558 .r_sram_req_o (sys_sram_req [SramCmdFifo]),
559 .r_sram_gnt_i (sys_sram_gnt [SramCmdFifo]),
560 .r_sram_write_o (sys_sram_write [SramCmdFifo]),
561 .r_sram_addr_o (sys_sram_addr [SramCmdFifo]),
562 .r_sram_wdata_o (sys_sram_wdata [SramCmdFifo]),
563 .r_sram_wmask_o (sys_sram_wmask [SramCmdFifo]),
564 .r_sram_rvalid_i (sys_sram_rvalid [SramCmdFifo]),
565 .r_sram_rdata_i (sys_sram_rdata [SramCmdFifo]),
566 .r_sram_rerror_i (sys_sram_rerror [SramCmdFifo])
567 );
568
569 // Connect to sys_cmdfifo_sram_o/_i
570 1/1 assign sys_cmdfifo_sram_o = '{
Tests: T1 T2 T3
571 req: sys_sram_req [SramCmdFifo],
572 we: sys_sram_write [SramCmdFifo],
573 addr: sys_sram_addr [SramCmdFifo],
574 wdata: sys_sram_wdata [SramCmdFifo],
575 wstrb: sram_mask2strb(sys_sram_wmask [SramCmdFifo])
576 };
577 1/1 assign sys_sram_rvalid [SramCmdFifo] = sys_cmdfifo_sram_i.rvalid;
Tests: T1 T2 T3
578 1/1 assign sys_sram_rdata [SramCmdFifo] = sys_cmdfifo_sram_i.rdata ;
Tests: T3 T6 T25
579 1/1 assign sys_sram_rerror [SramCmdFifo] = sys_cmdfifo_sram_i.rerror;
Tests: T1 T2 T3
580 1/1 assign sys_sram_gnt [SramCmdFifo] = sys_cmdfifo_gnt_i;
Tests: T1 T2 T3
581
582 // AddrFifo
583 prim_fifo_async_sram_adapter #(
584 .Width (AddrFifoWidth),
585 .Depth (AddrFifoDepth),
586 .SramAw (SramAw),
587 .SramDw (SramDw),
588 .SramBaseAddr (AddrFifoBaseAddr)
589 ) u_addrfifo (
590 .clk_wr_i (clk_i),
591 .rst_wr_ni (sys_rst_ni),
592 .wvalid_i (addrfifo_wvalid),
593 .wready_o (addrfifo_wready),
594 .wdata_i (addrfifo_wdata ),
595 .wdepth_o (),
596
597 .clk_rd_i (sys_clk_i),
598 .rst_rd_ni (sys_rst_ni),
599 .rvalid_o (sys_addrfifo_rvalid_o),
600 .rready_i (sys_addrfifo_rready_i),
601 .rdata_o (sys_addrfifo_rdata_o),
602 .rdepth_o (sys_addrfifo_depth_o),
603
604 .r_full_o (sys_addrfifo_full_o),
605 .r_notempty_o (sys_addrfifo_notempty_o),
606
607 .w_full_o (),
608
609 .w_sram_req_o (sck_sram_req [SramAddrFifo]),
610 .w_sram_gnt_i (sck_sram_gnt [SramAddrFifo]),
611 .w_sram_write_o (sck_sram_write [SramAddrFifo]),
612 .w_sram_addr_o (sck_sram_addr [SramAddrFifo]),
613 .w_sram_wdata_o (sck_sram_wdata [SramAddrFifo]),
614 .w_sram_wmask_o (sck_sram_wmask [SramAddrFifo]),
615 .w_sram_rvalid_i (sck_sram_rvalid [SramAddrFifo]),
616 .w_sram_rdata_i (sck_sram_rdata [SramAddrFifo]),
617 .w_sram_rerror_i (sck_sram_rerror [SramAddrFifo]),
618
619 .r_sram_req_o (sys_sram_req [SramAddrFifo]),
620 .r_sram_gnt_i (sys_sram_gnt [SramAddrFifo]),
621 .r_sram_write_o (sys_sram_write [SramAddrFifo]),
622 .r_sram_addr_o (sys_sram_addr [SramAddrFifo]),
623 .r_sram_wdata_o (sys_sram_wdata [SramAddrFifo]),
624 .r_sram_wmask_o (sys_sram_wmask [SramAddrFifo]),
625 .r_sram_rvalid_i (sys_sram_rvalid [SramAddrFifo]),
626 .r_sram_rdata_i (sys_sram_rdata [SramAddrFifo]),
627 .r_sram_rerror_i (sys_sram_rerror [SramAddrFifo])
628 );
629 // Connect to sys_addrfifo_sram_o/_i
630 1/1 assign sys_addrfifo_sram_o = '{
Tests: T1 T2 T3
631 req: sys_sram_req [SramAddrFifo],
632 we: sys_sram_write [SramAddrFifo],
633 addr: sys_sram_addr [SramAddrFifo],
634 wdata: sys_sram_wdata [SramAddrFifo],
635 wstrb: sram_mask2strb(sys_sram_wmask [SramAddrFifo])
636 };
637 1/1 assign sys_sram_rvalid [SramAddrFifo] = sys_addrfifo_sram_i.rvalid;
Tests: T1 T2 T3
638 1/1 assign sys_sram_rdata [SramAddrFifo] = sys_addrfifo_sram_i.rdata ;
Tests: T3 T6 T25
639 1/1 assign sys_sram_rerror [SramAddrFifo] = sys_addrfifo_sram_i.rerror;
Tests: T1 T2 T3
640 1/1 assign sys_sram_gnt [SramAddrFifo] = sys_addrfifo_gnt_i;
Tests: T1 T2 T3
641
642 // Payload Buffer
643 spid_fifo2sram_adapter #(
644 .FifoWidth (SpiByte),
645 .FifoDepth (PayloadByte),
646
647 .SramAw (SramAw),
648 .SramDw (SramDw),
649 .SramBaseAddr (PayloadBaseAddr),
650
651 // CFG
652 .EnPack (1'b1)
653 ) u_payload_buffer (
654 .clk_i,
655 .rst_ni,
656 .clr_i (1'b0),
657
658 .wvalid_i (payload_wvalid),
659 .wready_o (payload_wready),
660 .wdata_i (payload_wdata ),
661
662 // Does not use wdepth from the buffer as it is reset by CSb.
663 .wdepth_o (),
664
665 .sram_req_o (sck_sram_req [SramPayload]),
666 .sram_gnt_i (sck_sram_gnt [SramPayload]),
667 .sram_write_o (sck_sram_write [SramPayload]),
668 .sram_addr_o (sck_sram_addr [SramPayload]),
669 .sram_wdata_o (sck_sram_wdata [SramPayload]),
670 .sram_wmask_o (sck_sram_wmask [SramPayload]),
671 .sram_rvalid_i (sck_sram_rvalid [SramPayload]),
672 .sram_rdata_i (sck_sram_rdata [SramPayload]),
673 .sram_rerror_i (sck_sram_rerror [SramPayload])
674 );
675
676 // SramArbiter
677 logic [SramDw-1:0] sram_wmask;
678 prim_sram_arbiter #(
679 .N (NumSramIntf),
680 .SramDw (SramDw),
681 .SramAw (SramAw),
682 .EnMask (1'b 1)
683 ) u_arbiter (
684 .clk_i,
685 .rst_ni,
686
687 .req_i (sck_sram_req),
688 .req_addr_i (sck_sram_addr),
689 .req_write_i (sck_sram_write),
690 .req_wdata_i (sck_sram_wdata),
691 .req_wmask_i (sck_sram_wmask),
692 .gnt_o (sck_sram_gnt),
693
694 .rsp_rvalid_o (sck_sram_rvalid), // not used
695 .rsp_rdata_o (sck_sram_rdata), // not used
696 .rsp_error_o (sck_sram_rerror),
697
698 .sram_req_o (sck_sram_o.req),
699 .sram_addr_o (sck_sram_o.addr),
700 .sram_write_o (sck_sram_o.we),
701 .sram_wdata_o (sck_sram_o.wdata),
702 .sram_wmask_o (sram_wmask),
703 .sram_rvalid_i (sck_sram_i.rvalid),
704 .sram_rdata_i (sck_sram_i.rdata),
705 .sram_rerror_i (sck_sram_i.rerror)
706 );
707 1/1 assign sck_sram_o.wstrb = sram_mask2strb(sram_wmask);
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_upload
| Total | Covered | Percent |
|---|
| Conditions | 32 | 31 | 96.88 |
| Logical | 32 | 31 | 96.88 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 242
EXPRESSION (cmdinfo_addr_mode != AddrDisabled)
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 244
EXPRESSION (cmdinfo_addr_mode == Addr4B)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 257
EXPRESSION (cmdinfo_addr_4b_en ? 5'd31 : 5'd23)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T19,T32,T49 |
| 1 | Covered | T19,T54,T49 |
LINE 270
EXPRESSION (s2p_valid_i && addr_shift)
-----1----- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T19,T32,T54 |
| 1 | 0 | Covered | T7,T8,T9 |
| 1 | 1 | Covered | T19,T32,T54 |
LINE 307
EXPRESSION (cmdfifo_wvalid && cmdfifo_wready)
-------1------ -------2------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T19,T32,T54 |
LINE 353
EXPRESSION (payloadptr == 8'((PayloadByte - 1)))
------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T19,T32,T54 |
| 1 | Covered | T19,T32,T54 |
LINE 369
EXPRESSION (sys_cmdfifo_set && payload_max)
-------1------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T19,T32,T54 |
| 1 | 0 | Covered | T19,T32,T54 |
| 1 | 1 | Covered | T19,T32,T54 |
LINE 371
EXPRESSION (sys_cmdfifo_set && ((!payload_max)))
-------1------- --------2-------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T19,T32,T54 |
LINE 392
EXPRESSION (sys_cmdfifo_set && payload_max)
-------1------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T19,T32,T54 |
| 1 | 0 | Covered | T19,T32,T54 |
| 1 | 1 | Covered | T19,T32,T54 |
LINE 396
EXPRESSION (sys_cmdfifo_set && ((!payload_max)))
-------1------- --------2-------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T19,T32,T54 |
LINE 410
EXPRESSION (payloadptr_inc && payload_max)
-------1------ -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T19,T32,T54 |
| 1 | 0 | Covered | T19,T32,T54 |
| 1 | 1 | Covered | T32,T54,T49 |
LINE 454
EXPRESSION (s2p_valid_i && (cmd_only_sel_dp_i == DpUpload))
-----1----- ---------------2---------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Covered | T7,T8,T9 |
| 1 | 1 | Covered | T19,T32,T54 |
LINE 454
SUB-EXPRESSION (cmd_only_sel_dp_i == DpUpload)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T19,T32,T54 |
LINE 483
EXPRESSION (addrcnt == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T19,T32,T54 |
| 1 | Covered | T19,T32,T54 |
FSM Coverage for Instance : tb.dut.u_upload
Summary for FSM :: st_q
| Total | Covered | Percent | |
| States |
3 |
3 |
100.00 |
(Not included in score) |
| Transitions |
3 |
3 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: st_q
| states | Line No. | Covered | Tests |
| StAddress |
456 |
Covered |
T19,T32,T54 |
| StIdle |
453 |
Covered |
T1,T2,T3 |
| StPayload |
461 |
Covered |
T19,T32,T54 |
| transitions | Line No. | Covered | Tests |
| StAddress->StPayload |
484 |
Covered |
T19,T32,T54 |
| StIdle->StAddress |
456 |
Covered |
T19,T32,T54 |
| StIdle->StPayload |
461 |
Covered |
T32,T54,T49 |
Branch Coverage for Instance : tb.dut.u_upload
| Line No. | Total | Covered | Percent |
| Branches |
|
47 |
45 |
95.74 |
| IF |
256 |
5 |
5 |
100.00 |
| IF |
263 |
2 |
2 |
100.00 |
| IF |
268 |
3 |
3 |
100.00 |
| IF |
322 |
2 |
2 |
100.00 |
| IF |
346 |
5 |
5 |
100.00 |
| IF |
367 |
5 |
5 |
100.00 |
| IF |
390 |
5 |
5 |
100.00 |
| IF |
408 |
4 |
4 |
100.00 |
| IF |
418 |
4 |
4 |
100.00 |
| IF |
428 |
2 |
2 |
100.00 |
| CASE |
452 |
10 |
8 |
80.00 |
256 if (!rst_ni) addrcnt <= '0;
-1-
==>
257 else if (addr_update) addrcnt <= cmdinfo_addr_4b_en ? 5'd 31 : 5'd 23;
-2- -3-
==>
==>
258 else if (addr_shift) addrcnt <= addrcnt - 5'd 1;
-4-
==>
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
1 |
- |
Covered |
T19,T54,T49 |
| 0 |
1 |
0 |
- |
Covered |
T19,T32,T49 |
| 0 |
0 |
- |
1 |
Covered |
T19,T32,T54 |
| 0 |
0 |
- |
0 |
Covered |
T7,T8,T9 |
263 if (addr_shift) begin
-1-
264 address_d = {address_q[23:0], s2p_byte_i};
==>
265 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T19,T32,T54 |
| 0 |
Covered |
T1,T2,T3 |
268 if (!rst_ni) begin
-1-
269 address_q <= '0;
==>
270 end else if (s2p_valid_i && addr_shift) begin
-2-
271 address_q <= address_d;
==>
272 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T19,T32,T54 |
| 0 |
0 |
Covered |
T7,T8,T9 |
322 if (!sys_rst_ni) begin
-1-
323 sys_cmdfifo_set_o <= 1'b0;
==>
324 end else begin
325 sys_cmdfifo_set_o <= sys_cmdfifo_set;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
346 if (!sys_rst_ni) begin
-1-
347 payload_max <= 1'b 0;
==>
348 payloadptr <= '0;
349 end else if (payloadptr_clr) begin
-2-
350 payloadptr <= '0;
==>
351 payload_max <= 1'b 0;
352 end else if (payloadptr_inc) begin
-3-
353 if (payloadptr == PayloadIdxW'(PayloadByte-1)) begin
-4-
354 // payloadptr reached max
355 payload_max <= 1'b 1;
==>
356 end
MISSING_ELSE
==>
357 payloadptr <= payloadptr + PayloadIdxW'(1);
358 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
Covered |
T19,T32,T54 |
| 0 |
0 |
1 |
1 |
Covered |
T19,T32,T54 |
| 0 |
0 |
1 |
0 |
Covered |
T19,T32,T54 |
| 0 |
0 |
0 |
- |
Covered |
T4,T5,T6 |
367 if (!sys_rst_ni) sys_payload_depth_o <= '0;
-1-
==>
368 else if (sys_payloadptr_clr_posedge) sys_payload_depth_o <= '0;
-2-
==>
369 else if (sys_cmdfifo_set && payload_max) begin
-3-
370 sys_payload_depth_o <= PayloadPtrW'(PayloadByte);
==>
371 end else if (sys_cmdfifo_set && !payload_max) begin
-4-
372 sys_payload_depth_o <= PayloadPtrW'(payloadptr);
==>
373 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
Covered |
T19,T32,T54 |
| 0 |
0 |
1 |
- |
Covered |
T19,T32,T54 |
| 0 |
0 |
0 |
1 |
Covered |
T19,T32,T54 |
| 0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
390 if (!sys_rst_ni) sys_payload_start_idx_o <= '0;
-1-
==>
391 else if (sys_payloadptr_clr_posedge) sys_payload_start_idx_o <= '0;
-2-
==>
392 else if (sys_cmdfifo_set && payload_max) begin
-3-
393 // Payload reached the max, need to tell SW the exact location SW shoul
394 // read
395 sys_payload_start_idx_o <= payloadptr;
==>
396 end else if (sys_cmdfifo_set && !payload_max) begin
-4-
397 // Payload buffer has not been reached to the max, the start index
398 // should be 0 for SW to read from the first of the buffer.
399 sys_payload_start_idx_o <= '0;
==>
400 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
Covered |
T19,T32,T54 |
| 0 |
0 |
1 |
- |
Covered |
T19,T32,T54 |
| 0 |
0 |
0 |
1 |
Covered |
T19,T32,T54 |
| 0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
408 if (!sys_rst_ni) event_payload_overflow <= 1'b 0;
-1-
==>
409 else if (payloadptr_clr) event_payload_overflow <= 1'b 0;
-2-
==>
410 else if (payloadptr_inc && payload_max) begin
-3-
411 event_payload_overflow <= 1'b 1;
==>
412 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T19,T32,T54 |
| 0 |
0 |
1 |
Covered |
T32,T54,T49 |
| 0 |
0 |
0 |
Covered |
T4,T5,T6 |
418 if (!sys_rst_ni) sys_event_payload_overflow <= 1'b 0;
-1-
==>
419 else if (sys_payloadptr_clr_posedge) sys_event_payload_overflow <= 1'b 0;
-2-
==>
420 else if (sys_cmdfifo_set) begin
-3-
421 sys_event_payload_overflow <= event_payload_overflow;
==>
422 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T19,T32,T54 |
| 0 |
0 |
1 |
Covered |
T19,T32,T54 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
428 if (!rst_ni) begin
-1-
429 st_q <= StIdle;
==>
430 end else begin
431 st_q <= st_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T7,T8,T9 |
452 unique case (st_q)
-1-
453 StIdle: begin
454 if (s2p_valid_i && cmd_only_sel_dp_i == DpUpload) begin
-2-
455 if (cmdinfo_addr_en) begin
-3-
456 st_d = StAddress;
==>
457
458 // Address process (determines 32bit or 24bit)
459 addr_update = 1'b 1;
460 end else begin
461 st_d = StPayload;
==>
462 end
463
464 // Upload to SRAM right away.
465 cmdfifo_wvalid = 1'b 1;
466
467 // Assume cmdfifo_wready is 1 always (need to add assumption)
468
469 if (cmd_only_info_i.busy) begin
-4-
470 // Set BUSY
471 set_busy_o = 1'b 1;
==>
472 end
MISSING_ELSE
==>
473
474 // Clear payload counter
475 payloadptr_clr = 1'b 1;
476
477 end
MISSING_ELSE
==>
478 end
479
480 StAddress: begin
481 addr_shift = 1'b 1;
482
483 if (addrcnt == '0) begin
-5-
484 st_d = StPayload;
==>
485
486 addrfifo_wvalid = 1'b 1;
487 end
MISSING_ELSE
==>
488 end
489
490 StPayload: begin
491 // TERMINAL_STATE
492 if (s2p_valid_i) begin
-6-
493 payload_wvalid = 1'b 1;
==>
494 payloadptr_inc = 1'b 1;
495 end
MISSING_ELSE
==>
496
497 // ASSUME payload_wready == 1'b1
498 end
499
500 default: begin
501 st_d = StIdle;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
| StIdle |
1 |
1 |
- |
- |
- |
Covered |
T19,T32,T54 |
| StIdle |
1 |
0 |
- |
- |
- |
Covered |
T32,T54,T49 |
| StIdle |
1 |
- |
1 |
- |
- |
Covered |
T19,T32,T54 |
| StIdle |
1 |
- |
0 |
- |
- |
Not Covered |
|
| StIdle |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| StAddress |
- |
- |
- |
1 |
- |
Covered |
T19,T32,T54 |
| StAddress |
- |
- |
- |
0 |
- |
Covered |
T19,T32,T54 |
| StPayload |
- |
- |
- |
- |
1 |
Covered |
T19,T32,T54 |
| StPayload |
- |
- |
- |
- |
0 |
Covered |
T19,T32,T54 |
| default |
- |
- |
- |
- |
- |
Not Covered |
|
Assert Coverage for Instance : tb.dut.u_upload
Assertion Details
AddrFifoNeverFull_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
146533180 |
1591 |
0 |
0 |
| T19 |
54696 |
2 |
0 |
0 |
| T23 |
0 |
4 |
0 |
0 |
| T29 |
95700 |
0 |
0 |
0 |
| T30 |
277088 |
0 |
0 |
0 |
| T32 |
305619 |
5 |
0 |
0 |
| T33 |
1343 |
0 |
0 |
0 |
| T34 |
3433 |
0 |
0 |
0 |
| T36 |
0 |
5 |
0 |
0 |
| T45 |
15496 |
0 |
0 |
0 |
| T46 |
0 |
14 |
0 |
0 |
| T47 |
0 |
7 |
0 |
0 |
| T49 |
0 |
7 |
0 |
0 |
| T50 |
0 |
6 |
0 |
0 |
| T51 |
108824 |
0 |
0 |
0 |
| T54 |
0 |
7 |
0 |
0 |
| T55 |
2080 |
0 |
0 |
0 |
| T56 |
61949 |
0 |
0 |
0 |
| T81 |
0 |
6 |
0 |
0 |
CmdFifoNeverFull_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
146533180 |
2141 |
0 |
0 |
| T19 |
54696 |
2 |
0 |
0 |
| T23 |
0 |
7 |
0 |
0 |
| T29 |
95700 |
0 |
0 |
0 |
| T30 |
277088 |
0 |
0 |
0 |
| T32 |
305619 |
6 |
0 |
0 |
| T33 |
1343 |
0 |
0 |
0 |
| T34 |
3433 |
0 |
0 |
0 |
| T36 |
0 |
10 |
0 |
0 |
| T45 |
15496 |
0 |
0 |
0 |
| T46 |
0 |
16 |
0 |
0 |
| T47 |
0 |
7 |
0 |
0 |
| T49 |
0 |
8 |
0 |
0 |
| T50 |
0 |
9 |
0 |
0 |
| T51 |
108824 |
0 |
0 |
0 |
| T54 |
0 |
10 |
0 |
0 |
| T55 |
2080 |
0 |
0 |
0 |
| T56 |
61949 |
0 |
0 |
0 |
| T81 |
0 |
13 |
0 |
0 |
CmdFifoPush_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
146533180 |
2141 |
0 |
0 |
| T19 |
54696 |
2 |
0 |
0 |
| T23 |
0 |
7 |
0 |
0 |
| T29 |
95700 |
0 |
0 |
0 |
| T30 |
277088 |
0 |
0 |
0 |
| T32 |
305619 |
6 |
0 |
0 |
| T33 |
1343 |
0 |
0 |
0 |
| T34 |
3433 |
0 |
0 |
0 |
| T36 |
0 |
10 |
0 |
0 |
| T45 |
15496 |
0 |
0 |
0 |
| T46 |
0 |
16 |
0 |
0 |
| T47 |
0 |
7 |
0 |
0 |
| T49 |
0 |
8 |
0 |
0 |
| T50 |
0 |
9 |
0 |
0 |
| T51 |
108824 |
0 |
0 |
0 |
| T54 |
0 |
10 |
0 |
0 |
| T55 |
2080 |
0 |
0 |
0 |
| T56 |
61949 |
0 |
0 |
0 |
| T81 |
0 |
13 |
0 |
0 |
FifosOnlyOneValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
146533180 |
119952536 |
0 |
0 |
| T7 |
31058 |
31058 |
0 |
0 |
| T8 |
10480 |
10480 |
0 |
0 |
| T9 |
8888 |
8888 |
0 |
0 |
| T10 |
109671 |
0 |
0 |
0 |
| T11 |
14640 |
14640 |
0 |
0 |
| T12 |
5392 |
5392 |
0 |
0 |
| T13 |
93908 |
93738 |
0 |
0 |
| T14 |
16979 |
16979 |
0 |
0 |
| T17 |
0 |
2128 |
0 |
0 |
| T18 |
0 |
96 |
0 |
0 |
| T19 |
0 |
54621 |
0 |
0 |
| T26 |
1159 |
0 |
0 |
0 |
| T27 |
3656 |
0 |
0 |
0 |
PayloadNeverFull_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
146533180 |
802631 |
0 |
0 |
| T19 |
54696 |
260 |
0 |
0 |
| T23 |
0 |
2223 |
0 |
0 |
| T29 |
95700 |
0 |
0 |
0 |
| T30 |
277088 |
0 |
0 |
0 |
| T32 |
305619 |
1634 |
0 |
0 |
| T33 |
1343 |
0 |
0 |
0 |
| T34 |
3433 |
0 |
0 |
0 |
| T36 |
0 |
6648 |
0 |
0 |
| T45 |
15496 |
0 |
0 |
0 |
| T46 |
0 |
2215 |
0 |
0 |
| T47 |
0 |
5582 |
0 |
0 |
| T49 |
0 |
1444 |
0 |
0 |
| T50 |
0 |
2215 |
0 |
0 |
| T51 |
108824 |
0 |
0 |
0 |
| T54 |
0 |
4050 |
0 |
0 |
| T55 |
2080 |
0 |
0 |
0 |
| T56 |
61949 |
0 |
0 |
0 |
| T81 |
0 |
1849 |
0 |
0 |