Module Definition
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Module : prim_pulse_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_flash_readbuf_flip_pulse_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_upload.u_payloadptr_clr_psync 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.10 95.20 93.48 97.84 93.55 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.10 95.20 93.48 97.84 93.55 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.52 100.00 96.88 100.00 95.74 100.00 u_upload


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00


30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 
Cond Coverage for Module : prim_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT12,T14,T19
10CoveredT12,T14,T19
11CoveredT12,T14,T19 

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T14,T19
10CoveredT12,T14,T19
11CoveredT12,T14,T19
Branch Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00 



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6 



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Module : prim_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1253222097 2619 0 0
SrcPulseCheck_M 439599540 2619 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1253222097 2619 0 0
T12 27966 3 0 0
T13 197306 0 0 0
T14 74160 7 0 0
T15 14450 0 0 0
T16 1956 0 0 0
T19 343247 2 0 0
T20 9204 0 0 0
T23 0 7 0 0
T24 2806 0 0 0
T25 5362 0 0 0
T26 10944 0 0 0
T27 17990 0 0 0
T29 659427 0 0 0
T30 287568 0 0 0
T31 1304 0 0 0
T32 0 6 0 0
T36 0 10 0 0
T40 5944 0 0 0
T45 53808 7 0 0
T46 0 16 0 0
T47 0 7 0 0
T49 0 8 0 0
T50 0 9 0 0
T51 438789 0 0 0
T52 0 7 0 0
T54 0 10 0 0
T55 19691 0 0 0
T56 503990 0 0 0
T81 0 13 0 0
T83 1308 0 0 0
T102 0 4 0 0
T126 0 7 0 0
T138 0 9 0 0
T152 0 7 0 0
T153 0 6 0 0
T154 0 7 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 439599540 2619 0 0
T12 10784 3 0 0
T13 187816 0 0 0
T14 33958 7 0 0
T17 4256 0 0 0
T18 192 0 0 0
T19 164088 2 0 0
T23 0 7 0 0
T26 2318 0 0 0
T27 7312 0 0 0
T28 446474 0 0 0
T29 95700 0 0 0
T30 277088 0 0 0
T32 305619 6 0 0
T33 1343 0 0 0
T34 3433 0 0 0
T36 0 10 0 0
T45 15496 7 0 0
T46 0 16 0 0
T47 0 7 0 0
T49 0 8 0 0
T50 0 9 0 0
T51 108824 0 0 0
T52 0 7 0 0
T54 0 10 0 0
T55 6240 0 0 0
T56 61949 0 0 0
T81 0 13 0 0
T102 0 4 0 0
T126 0 7 0 0
T138 0 9 0 0
T152 0 7 0 0
T153 0 6 0 0
T154 0 7 0 0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00


30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT12,T14,T45
10CoveredT12,T14,T45
11CoveredT12,T14,T45 

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T14,T45
10CoveredT12,T14,T45
11CoveredT12,T14,T45
Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00 



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6 



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 417740699 171 0 0
SrcPulseCheck_M 146533180 171 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 417740699 171 0 0
T12 13983 2 0 0
T13 98653 0 0 0
T14 37080 2 0 0
T15 7225 0 0 0
T16 978 0 0 0
T24 1403 0 0 0
T25 2681 0 0 0
T26 5472 0 0 0
T27 8995 0 0 0
T40 2972 0 0 0
T45 0 4 0 0
T52 0 2 0 0
T102 0 2 0 0
T126 0 2 0 0
T138 0 5 0 0
T152 0 2 0 0
T153 0 3 0 0
T154 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 146533180 171 0 0
T12 5392 2 0 0
T13 93908 0 0 0
T14 16979 2 0 0
T17 2128 0 0 0
T18 96 0 0 0
T19 54696 0 0 0
T26 1159 0 0 0
T27 3656 0 0 0
T28 223237 0 0 0
T45 0 4 0 0
T52 0 2 0 0
T55 2080 0 0 0
T102 0 2 0 0
T126 0 2 0 0
T138 0 5 0 0
T152 0 2 0 0
T153 0 3 0 0
T154 0 2 0 0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00


30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT12,T14,T45
10CoveredT12,T14,T45
11CoveredT14,T45,T52 

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T14,T45
10CoveredT14,T45,T52
11CoveredT12,T14,T45
Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00 



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6 



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 417740699 307 0 0
SrcPulseCheck_M 146533180 307 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 417740699 307 0 0
T12 13983 1 0 0
T13 98653 0 0 0
T14 37080 5 0 0
T15 7225 0 0 0
T16 978 0 0 0
T24 1403 0 0 0
T25 2681 0 0 0
T26 5472 0 0 0
T27 8995 0 0 0
T40 2972 0 0 0
T45 0 3 0 0
T52 0 5 0 0
T102 0 2 0 0
T126 0 5 0 0
T138 0 4 0 0
T152 0 5 0 0
T153 0 3 0 0
T154 0 5 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 146533180 307 0 0
T12 5392 1 0 0
T13 93908 0 0 0
T14 16979 5 0 0
T17 2128 0 0 0
T18 96 0 0 0
T19 54696 0 0 0
T26 1159 0 0 0
T27 3656 0 0 0
T28 223237 0 0 0
T45 0 3 0 0
T52 0 5 0 0
T55 2080 0 0 0
T102 0 2 0 0
T126 0 5 0 0
T138 0 4 0 0
T152 0 5 0 0
T153 0 3 0 0
T154 0 5 0 0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00


30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT19,T32,T54
10CoveredT19,T32,T54
11CoveredT19,T32,T54 

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT19,T32,T54
10CoveredT19,T32,T54
11CoveredT19,T32,T54
Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00 



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6 



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 417740699 2141 0 0
SrcPulseCheck_M 146533180 2141 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 417740699 2141 0 0
T19 343247 2 0 0
T20 9204 0 0 0
T23 0 7 0 0
T29 659427 0 0 0
T30 287568 0 0 0
T31 1304 0 0 0
T32 0 6 0 0
T36 0 10 0 0
T45 53808 0 0 0
T46 0 16 0 0
T47 0 7 0 0
T49 0 8 0 0
T50 0 9 0 0
T51 438789 0 0 0
T54 0 10 0 0
T55 19691 0 0 0
T56 503990 0 0 0
T81 0 13 0 0
T83 1308 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 146533180 2141 0 0
T19 54696 2 0 0
T23 0 7 0 0
T29 95700 0 0 0
T30 277088 0 0 0
T32 305619 6 0 0
T33 1343 0 0 0
T34 3433 0 0 0
T36 0 10 0 0
T45 15496 0 0 0
T46 0 16 0 0
T47 0 7 0 0
T49 0 8 0 0
T50 0 9 0 0
T51 108824 0 0 0
T54 0 10 0 0
T55 2080 0 0 0
T56 61949 0 0 0
T81 0 13 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%