| T437 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.936143125 |
|
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Oct 09 04:02:19 PM UTC 24 |
Oct 09 04:03:08 PM UTC 24 |
8393184615 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_cfg_cmd.1153019150 |
|
|
Oct 09 04:03:02 PM UTC 24 |
Oct 09 04:03:10 PM UTC 24 |
285509306 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_all.1399033559 |
|
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Oct 09 04:02:46 PM UTC 24 |
Oct 09 04:03:13 PM UTC 24 |
3533649190 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.2277270920 |
|
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Oct 09 04:01:54 PM UTC 24 |
Oct 09 04:03:19 PM UTC 24 |
25326020685 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_upload.1745183419 |
|
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Oct 09 04:02:58 PM UTC 24 |
Oct 09 04:03:20 PM UTC 24 |
8613877937 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.1713910213 |
|
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Oct 09 04:03:09 PM UTC 24 |
Oct 09 04:03:21 PM UTC 24 |
590077115 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_alert_test.3880570049 |
|
|
Oct 09 04:03:21 PM UTC 24 |
Oct 09 04:03:24 PM UTC 24 |
13333276 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_csb_read.2373180969 |
|
|
Oct 09 04:03:23 PM UTC 24 |
Oct 09 04:03:25 PM UTC 24 |
15522700 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mem_parity.600915284 |
|
|
Oct 09 04:03:25 PM UTC 24 |
Oct 09 04:03:28 PM UTC 24 |
15013598 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode.1696646429 |
|
|
Oct 09 04:03:04 PM UTC 24 |
Oct 09 04:03:32 PM UTC 24 |
771013168 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mailbox.438008428 |
|
|
Oct 09 04:02:54 PM UTC 24 |
Oct 09 04:03:32 PM UTC 24 |
3059564963 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.1983548637 |
|
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Oct 09 03:57:50 PM UTC 24 |
Oct 09 04:03:33 PM UTC 24 |
199646960287 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_rw.3379578901 |
|
|
Oct 09 04:03:33 PM UTC 24 |
Oct 09 04:03:35 PM UTC 24 |
22875699 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.2954221996 |
|
|
Oct 09 04:03:33 PM UTC 24 |
Oct 09 04:03:36 PM UTC 24 |
36112739 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.312193984 |
|
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Oct 09 04:03:26 PM UTC 24 |
Oct 09 04:03:40 PM UTC 24 |
3802607262 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_intercept.2343176476 |
|
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Oct 09 04:03:36 PM UTC 24 |
Oct 09 04:03:41 PM UTC 24 |
61572505 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.2727120007 |
|
|
Oct 09 04:03:36 PM UTC 24 |
Oct 09 04:03:41 PM UTC 24 |
176881105 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.2163492250 |
|
|
Oct 09 04:03:09 PM UTC 24 |
Oct 09 04:03:45 PM UTC 24 |
998001153 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_cfg_cmd.2578399320 |
|
|
Oct 09 04:03:43 PM UTC 24 |
Oct 09 04:03:47 PM UTC 24 |
105998114 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode.1833885805 |
|
|
Oct 09 04:03:46 PM UTC 24 |
Oct 09 04:03:55 PM UTC 24 |
693459691 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.2483898179 |
|
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Oct 09 04:03:34 PM UTC 24 |
Oct 09 04:03:59 PM UTC 24 |
4204157531 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_upload.1874653471 |
|
|
Oct 09 04:03:42 PM UTC 24 |
Oct 09 04:03:59 PM UTC 24 |
2532259557 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.1374510977 |
|
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Oct 09 04:03:55 PM UTC 24 |
Oct 09 04:04:04 PM UTC 24 |
1382144835 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_all.71202303 |
|
|
Oct 09 04:02:27 PM UTC 24 |
Oct 09 04:04:05 PM UTC 24 |
31354686872 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.2857562893 |
|
|
Oct 09 04:00:25 PM UTC 24 |
Oct 09 04:04:06 PM UTC 24 |
63940344408 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_alert_test.460343374 |
|
|
Oct 09 04:04:05 PM UTC 24 |
Oct 09 04:04:07 PM UTC 24 |
21942707 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_csb_read.693654655 |
|
|
Oct 09 04:04:06 PM UTC 24 |
Oct 09 04:04:09 PM UTC 24 |
45113043 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mem_parity.3355657873 |
|
|
Oct 09 04:04:07 PM UTC 24 |
Oct 09 04:04:10 PM UTC 24 |
145675462 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.1589636309 |
|
|
Oct 09 04:04:11 PM UTC 24 |
Oct 09 04:04:13 PM UTC 24 |
107920868 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.2156668074 |
|
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Oct 09 04:02:27 PM UTC 24 |
Oct 09 04:04:18 PM UTC 24 |
4041335249 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_rw.2489358838 |
|
|
Oct 09 04:04:12 PM UTC 24 |
Oct 09 04:04:19 PM UTC 24 |
187284578 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_all.2264989488 |
|
|
Oct 09 04:03:29 PM UTC 24 |
Oct 09 04:04:25 PM UTC 24 |
91523844550 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.2864611662 |
|
|
Oct 09 04:02:27 PM UTC 24 |
Oct 09 04:04:26 PM UTC 24 |
57990985701 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.2312946026 |
|
|
Oct 09 04:04:09 PM UTC 24 |
Oct 09 04:04:29 PM UTC 24 |
3612360189 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_intercept.3565930213 |
|
|
Oct 09 04:04:19 PM UTC 24 |
Oct 09 04:04:32 PM UTC 24 |
2378886935 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.429372955 |
|
|
Oct 09 04:04:18 PM UTC 24 |
Oct 09 04:04:34 PM UTC 24 |
4445389959 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_upload.632209206 |
|
|
Oct 09 04:04:28 PM UTC 24 |
Oct 09 04:04:35 PM UTC 24 |
443004091 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.2037377284 |
|
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Oct 09 04:02:12 PM UTC 24 |
Oct 09 04:04:36 PM UTC 24 |
11258492138 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.1976738687 |
|
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Oct 09 04:04:36 PM UTC 24 |
Oct 09 04:04:43 PM UTC 24 |
192653621 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_all.570379726 |
|
|
Oct 09 04:04:10 PM UTC 24 |
Oct 09 04:04:44 PM UTC 24 |
5024643998 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_cfg_cmd.762430790 |
|
|
Oct 09 04:04:31 PM UTC 24 |
Oct 09 04:04:48 PM UTC 24 |
7214590411 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.306178897 |
|
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Oct 09 04:04:14 PM UTC 24 |
Oct 09 04:04:51 PM UTC 24 |
60732286999 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_stress_all.3790550103 |
|
|
Oct 09 04:04:49 PM UTC 24 |
Oct 09 04:04:51 PM UTC 24 |
44081561 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.4128034345 |
|
|
Oct 09 04:02:36 PM UTC 24 |
Oct 09 04:04:52 PM UTC 24 |
42340834545 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_alert_test.3203921519 |
|
|
Oct 09 04:04:52 PM UTC 24 |
Oct 09 04:04:54 PM UTC 24 |
13224969 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_csb_read.1933122922 |
|
|
Oct 09 04:04:52 PM UTC 24 |
Oct 09 04:04:55 PM UTC 24 |
46923791 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode.1750074320 |
|
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Oct 09 04:04:33 PM UTC 24 |
Oct 09 04:04:55 PM UTC 24 |
4869463300 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mem_parity.11043559 |
|
|
Oct 09 04:04:53 PM UTC 24 |
Oct 09 04:04:56 PM UTC 24 |
98982893 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_all.2768248241 |
|
|
Oct 09 04:04:55 PM UTC 24 |
Oct 09 04:04:58 PM UTC 24 |
11896277 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.1780027219 |
|
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Oct 09 04:04:55 PM UTC 24 |
Oct 09 04:04:58 PM UTC 24 |
19420098 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_rw.1476775323 |
|
|
Oct 09 04:04:57 PM UTC 24 |
Oct 09 04:04:59 PM UTC 24 |
37098829 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.3159463407 |
|
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Oct 09 04:00:52 PM UTC 24 |
Oct 09 04:05:00 PM UTC 24 |
144230596003 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mailbox.2521771557 |
|
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Oct 09 04:03:41 PM UTC 24 |
Oct 09 04:05:00 PM UTC 24 |
51180318700 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mailbox.867787769 |
|
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Oct 09 04:04:26 PM UTC 24 |
Oct 09 04:05:05 PM UTC 24 |
3910912793 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_intercept.4123186011 |
|
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Oct 09 04:05:00 PM UTC 24 |
Oct 09 04:05:07 PM UTC 24 |
429749439 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mailbox.2514871560 |
|
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Oct 09 04:05:00 PM UTC 24 |
Oct 09 04:05:09 PM UTC 24 |
867214752 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.1159673226 |
|
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Oct 09 04:05:08 PM UTC 24 |
Oct 09 04:05:10 PM UTC 24 |
18867894 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.2015902306 |
|
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Oct 09 04:00:21 PM UTC 24 |
Oct 09 04:05:11 PM UTC 24 |
21967363710 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode.343632628 |
|
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Oct 09 04:05:07 PM UTC 24 |
Oct 09 04:05:11 PM UTC 24 |
60159905 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.523877074 |
|
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Oct 09 04:04:59 PM UTC 24 |
Oct 09 04:05:12 PM UTC 24 |
994884165 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.1811392601 |
|
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Oct 09 04:04:59 PM UTC 24 |
Oct 09 04:05:14 PM UTC 24 |
2847582606 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.2477739168 |
|
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Oct 09 04:04:01 PM UTC 24 |
Oct 09 04:05:15 PM UTC 24 |
7118275595 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.2304677309 |
|
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Oct 09 04:03:48 PM UTC 24 |
Oct 09 04:05:15 PM UTC 24 |
12223800357 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_upload.2866470154 |
|
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Oct 09 04:05:01 PM UTC 24 |
Oct 09 04:05:15 PM UTC 24 |
1474127094 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_alert_test.3851812874 |
|
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Oct 09 04:05:14 PM UTC 24 |
Oct 09 04:05:16 PM UTC 24 |
24561284 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_csb_read.4145946995 |
|
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Oct 09 04:05:15 PM UTC 24 |
Oct 09 04:05:17 PM UTC 24 |
79805887 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_cfg_cmd.3000213495 |
|
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Oct 09 04:05:07 PM UTC 24 |
Oct 09 04:05:18 PM UTC 24 |
3236657611 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.3252682470 |
|
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Oct 09 04:05:16 PM UTC 24 |
Oct 09 04:05:18 PM UTC 24 |
56674595 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mem_parity.3509841922 |
|
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Oct 09 04:05:16 PM UTC 24 |
Oct 09 04:05:18 PM UTC 24 |
198479065 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_rw.243003544 |
|
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Oct 09 04:05:17 PM UTC 24 |
Oct 09 04:05:22 PM UTC 24 |
502880108 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_intercept.3075176879 |
|
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Oct 09 04:05:20 PM UTC 24 |
Oct 09 04:05:24 PM UTC 24 |
150314980 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.3464189501 |
|
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Oct 09 04:05:18 PM UTC 24 |
Oct 09 04:05:25 PM UTC 24 |
1192987461 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_all.618121334 |
|
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Oct 09 04:05:16 PM UTC 24 |
Oct 09 04:05:26 PM UTC 24 |
6689201540 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_all.4127573278 |
|
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Oct 09 04:03:56 PM UTC 24 |
Oct 09 04:05:26 PM UTC 24 |
4992506191 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.1614198354 |
|
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Oct 09 04:05:16 PM UTC 24 |
Oct 09 04:05:26 PM UTC 24 |
1729962400 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.1684471910 |
|
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Oct 09 04:05:10 PM UTC 24 |
Oct 09 04:05:30 PM UTC 24 |
1221923849 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.2265303770 |
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Oct 09 04:04:55 PM UTC 24 |
Oct 09 04:05:30 PM UTC 24 |
10055873062 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_cfg_cmd.2959324319 |
|
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Oct 09 04:05:26 PM UTC 24 |
Oct 09 04:05:30 PM UTC 24 |
516673361 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.1942815459 |
|
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Oct 09 04:03:11 PM UTC 24 |
Oct 09 04:05:32 PM UTC 24 |
8242363524 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.3082153309 |
|
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Oct 09 04:04:35 PM UTC 24 |
Oct 09 04:05:34 PM UTC 24 |
8218863019 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_upload.3781443021 |
|
|
Oct 09 04:05:25 PM UTC 24 |
Oct 09 04:05:36 PM UTC 24 |
1741283991 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_alert_test.3391302990 |
|
|
Oct 09 04:05:35 PM UTC 24 |
Oct 09 04:05:37 PM UTC 24 |
21350236 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_csb_read.540623402 |
|
|
Oct 09 04:05:37 PM UTC 24 |
Oct 09 04:05:39 PM UTC 24 |
85601130 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_all.2260261942 |
|
|
Oct 09 04:05:11 PM UTC 24 |
Oct 09 04:05:40 PM UTC 24 |
865445418 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.750091477 |
|
|
Oct 09 04:05:27 PM UTC 24 |
Oct 09 04:05:40 PM UTC 24 |
408059813 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mem_parity.3958083976 |
|
|
Oct 09 04:05:38 PM UTC 24 |
Oct 09 04:05:41 PM UTC 24 |
341463903 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2439728391 |
|
|
Oct 09 03:58:26 PM UTC 24 |
Oct 09 04:05:43 PM UTC 24 |
38708310880 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_rw.1899293126 |
|
|
Oct 09 04:05:42 PM UTC 24 |
Oct 09 04:05:44 PM UTC 24 |
11390145 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode.2572001104 |
|
|
Oct 09 04:05:27 PM UTC 24 |
Oct 09 04:05:44 PM UTC 24 |
967983375 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.3501507018 |
|
|
Oct 09 04:05:42 PM UTC 24 |
Oct 09 04:05:44 PM UTC 24 |
199010917 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_intercept.560072769 |
|
|
Oct 09 04:05:45 PM UTC 24 |
Oct 09 04:05:49 PM UTC 24 |
69234300 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.863915313 |
|
|
Oct 09 04:05:40 PM UTC 24 |
Oct 09 04:05:52 PM UTC 24 |
2505885828 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.846158665 |
|
|
Oct 09 03:59:43 PM UTC 24 |
Oct 09 04:05:52 PM UTC 24 |
156033962619 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mailbox.2391466026 |
|
|
Oct 09 04:05:23 PM UTC 24 |
Oct 09 04:05:52 PM UTC 24 |
2900400110 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.3570072274 |
|
|
Oct 09 04:01:50 PM UTC 24 |
Oct 09 04:05:55 PM UTC 24 |
66326912934 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_upload.3576452998 |
|
|
Oct 09 04:05:46 PM UTC 24 |
Oct 09 04:05:56 PM UTC 24 |
3032392575 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.3817354475 |
|
|
Oct 09 04:05:19 PM UTC 24 |
Oct 09 04:05:56 PM UTC 24 |
17786894624 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_cfg_cmd.2721251215 |
|
|
Oct 09 04:05:50 PM UTC 24 |
Oct 09 04:06:00 PM UTC 24 |
1190326962 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.145431273 |
|
|
Oct 09 04:05:54 PM UTC 24 |
Oct 09 04:06:00 PM UTC 24 |
1038140919 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.1338977031 |
|
|
Oct 09 04:00:56 PM UTC 24 |
Oct 09 04:06:01 PM UTC 24 |
45265260245 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_alert_test.1551283126 |
|
|
Oct 09 04:06:00 PM UTC 24 |
Oct 09 04:06:02 PM UTC 24 |
28815036 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_csb_read.778846921 |
|
|
Oct 09 04:06:00 PM UTC 24 |
Oct 09 04:06:03 PM UTC 24 |
16284699 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.2988468643 |
|
|
Oct 09 04:06:00 PM UTC 24 |
Oct 09 04:06:03 PM UTC 24 |
116264221 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_all.3811798455 |
|
|
Oct 09 04:05:40 PM UTC 24 |
Oct 09 04:06:04 PM UTC 24 |
11912289867 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mem_parity.336142734 |
|
|
Oct 09 04:06:02 PM UTC 24 |
Oct 09 04:06:04 PM UTC 24 |
32932576 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.2380568148 |
|
|
Oct 09 04:05:45 PM UTC 24 |
Oct 09 04:06:04 PM UTC 24 |
1833044991 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_all.996368218 |
|
|
Oct 09 04:06:04 PM UTC 24 |
Oct 09 04:06:06 PM UTC 24 |
35351363 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.1322448747 |
|
|
Oct 09 04:06:04 PM UTC 24 |
Oct 09 04:06:06 PM UTC 24 |
41561841 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_rw.1016338046 |
|
|
Oct 09 04:06:05 PM UTC 24 |
Oct 09 04:06:09 PM UTC 24 |
175045164 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.3456995723 |
|
|
Oct 09 04:06:05 PM UTC 24 |
Oct 09 04:06:10 PM UTC 24 |
114321207 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_intercept.4178637161 |
|
|
Oct 09 04:06:07 PM UTC 24 |
Oct 09 04:06:12 PM UTC 24 |
107065785 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_upload.3380445395 |
|
|
Oct 09 04:06:10 PM UTC 24 |
Oct 09 04:06:14 PM UTC 24 |
54372790 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.867530935 |
|
|
Oct 09 04:06:04 PM UTC 24 |
Oct 09 04:06:14 PM UTC 24 |
1994502292 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.232503583 |
|
|
Oct 09 04:05:45 PM UTC 24 |
Oct 09 04:06:15 PM UTC 24 |
15691768367 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.3153685188 |
|
|
Oct 09 04:00:57 PM UTC 24 |
Oct 09 04:06:15 PM UTC 24 |
23578577898 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.2057385472 |
|
|
Oct 09 04:06:05 PM UTC 24 |
Oct 09 04:06:16 PM UTC 24 |
601055090 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.2549242520 |
|
|
Oct 09 04:05:32 PM UTC 24 |
Oct 09 04:06:18 PM UTC 24 |
2744909941 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mailbox.1293237457 |
|
|
Oct 09 04:06:08 PM UTC 24 |
Oct 09 04:06:20 PM UTC 24 |
271420554 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.1358177495 |
|
|
Oct 09 04:06:15 PM UTC 24 |
Oct 09 04:06:22 PM UTC 24 |
874358160 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode.2193446638 |
|
|
Oct 09 04:06:13 PM UTC 24 |
Oct 09 04:06:23 PM UTC 24 |
672605896 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_alert_test.3058301601 |
|
|
Oct 09 04:06:21 PM UTC 24 |
Oct 09 04:06:24 PM UTC 24 |
47478538 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_csb_read.551185234 |
|
|
Oct 09 04:06:23 PM UTC 24 |
Oct 09 04:06:26 PM UTC 24 |
122888580 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.1086934417 |
|
|
Oct 09 04:04:00 PM UTC 24 |
Oct 09 04:06:28 PM UTC 24 |
32824438593 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.3472148091 |
|
|
Oct 09 04:06:26 PM UTC 24 |
Oct 09 04:06:29 PM UTC 24 |
140902787 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_rw.3760520016 |
|
|
Oct 09 04:06:28 PM UTC 24 |
Oct 09 04:06:31 PM UTC 24 |
44349003 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.1305938088 |
|
|
Oct 09 04:01:57 PM UTC 24 |
Oct 09 04:06:31 PM UTC 24 |
22232275115 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mailbox.3921824718 |
|
|
Oct 09 04:05:45 PM UTC 24 |
Oct 09 04:06:32 PM UTC 24 |
13567291052 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.2977169544 |
|
|
Oct 09 04:06:24 PM UTC 24 |
Oct 09 04:06:32 PM UTC 24 |
2240769170 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.3822408940 |
|
|
Oct 09 04:06:15 PM UTC 24 |
Oct 09 04:06:33 PM UTC 24 |
7773521606 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_all.3423609030 |
|
|
Oct 09 04:04:37 PM UTC 24 |
Oct 09 04:06:36 PM UTC 24 |
10966654258 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.1135107972 |
|
|
Oct 09 03:56:40 PM UTC 24 |
Oct 09 04:06:37 PM UTC 24 |
238975236221 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_cfg_cmd.3830043599 |
|
|
Oct 09 04:06:11 PM UTC 24 |
Oct 09 04:06:37 PM UTC 24 |
6399324440 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_mailbox.1089548681 |
|
|
Oct 09 04:06:33 PM UTC 24 |
Oct 09 04:06:39 PM UTC 24 |
450500017 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_upload.1582131241 |
|
|
Oct 09 04:06:33 PM UTC 24 |
Oct 09 04:06:41 PM UTC 24 |
7772252771 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.3130920380 |
|
|
Oct 09 04:06:32 PM UTC 24 |
Oct 09 04:06:41 PM UTC 24 |
1190622757 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_cfg_cmd.1427122734 |
|
|
Oct 09 04:06:34 PM UTC 24 |
Oct 09 04:06:42 PM UTC 24 |
276845699 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.942943084 |
|
|
Oct 09 04:06:30 PM UTC 24 |
Oct 09 04:06:45 PM UTC 24 |
524020486 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.2310399407 |
|
|
Oct 09 04:06:38 PM UTC 24 |
Oct 09 04:06:46 PM UTC 24 |
562759779 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_alert_test.1949191604 |
|
|
Oct 09 04:06:43 PM UTC 24 |
Oct 09 04:06:46 PM UTC 24 |
21890665 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_intercept.2800319164 |
|
|
Oct 09 04:06:33 PM UTC 24 |
Oct 09 04:06:47 PM UTC 24 |
2707383178 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_csb_read.587671887 |
|
|
Oct 09 04:06:46 PM UTC 24 |
Oct 09 04:06:48 PM UTC 24 |
14892631 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode.3420760659 |
|
|
Oct 09 04:06:36 PM UTC 24 |
Oct 09 04:06:49 PM UTC 24 |
1789671296 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.892645166 |
|
|
Oct 09 04:06:48 PM UTC 24 |
Oct 09 04:06:50 PM UTC 24 |
84764388 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.3234551614 |
|
|
Oct 09 04:05:54 PM UTC 24 |
Oct 09 04:06:52 PM UTC 24 |
4968357140 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_rw.623591858 |
|
|
Oct 09 04:06:49 PM UTC 24 |
Oct 09 04:06:53 PM UTC 24 |
1053192719 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.2135988946 |
|
|
Oct 09 04:06:49 PM UTC 24 |
Oct 09 04:06:53 PM UTC 24 |
259598296 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.1323022664 |
|
|
Oct 09 04:04:44 PM UTC 24 |
Oct 09 04:06:54 PM UTC 24 |
68136338649 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.2719495785 |
|
|
Oct 09 04:06:47 PM UTC 24 |
Oct 09 04:06:55 PM UTC 24 |
1134119593 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode.1095596810 |
|
|
Oct 09 04:05:52 PM UTC 24 |
Oct 09 04:07:00 PM UTC 24 |
3968821078 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_all.561440012 |
|
|
Oct 09 04:05:31 PM UTC 24 |
Oct 09 04:07:06 PM UTC 24 |
7600904746 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_cfg_cmd.2285728385 |
|
|
Oct 09 04:06:55 PM UTC 24 |
Oct 09 04:07:06 PM UTC 24 |
469165340 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.1132948667 |
|
|
Oct 09 04:01:25 PM UTC 24 |
Oct 09 04:07:07 PM UTC 24 |
42684857346 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2466254666 |
|
|
Oct 09 04:05:12 PM UTC 24 |
Oct 09 04:07:08 PM UTC 24 |
19672067538 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_all.433206884 |
|
|
Oct 09 04:06:24 PM UTC 24 |
Oct 09 04:07:10 PM UTC 24 |
15416002797 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_all.1053493280 |
|
|
Oct 09 04:05:56 PM UTC 24 |
Oct 09 04:07:13 PM UTC 24 |
7665814010 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_stress_all.1093398055 |
|
|
Oct 09 04:07:11 PM UTC 24 |
Oct 09 04:07:13 PM UTC 24 |
55173982 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.2438068111 |
|
|
Oct 09 04:05:32 PM UTC 24 |
Oct 09 04:07:14 PM UTC 24 |
6319453721 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_upload.3391394736 |
|
|
Oct 09 04:06:54 PM UTC 24 |
Oct 09 04:07:15 PM UTC 24 |
11176218897 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.2466877611 |
|
|
Oct 09 04:07:07 PM UTC 24 |
Oct 09 04:07:15 PM UTC 24 |
2200974669 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_alert_test.628623924 |
|
|
Oct 09 04:07:14 PM UTC 24 |
Oct 09 04:07:16 PM UTC 24 |
25650768 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_csb_read.3833000466 |
|
|
Oct 09 04:07:14 PM UTC 24 |
Oct 09 04:07:16 PM UTC 24 |
31666119 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.3565452545 |
|
|
Oct 09 04:07:16 PM UTC 24 |
Oct 09 04:07:18 PM UTC 24 |
70515342 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_rw.2451119948 |
|
|
Oct 09 04:07:17 PM UTC 24 |
Oct 09 04:07:20 PM UTC 24 |
79746568 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.3345313345 |
|
|
Oct 09 04:04:45 PM UTC 24 |
Oct 09 04:07:25 PM UTC 24 |
5803803336 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_mailbox.1227410379 |
|
|
Oct 09 04:06:53 PM UTC 24 |
Oct 09 04:07:28 PM UTC 24 |
1178947000 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.3983377285 |
|
|
Oct 09 04:07:17 PM UTC 24 |
Oct 09 04:07:28 PM UTC 24 |
932009034 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.3712935890 |
|
|
Oct 09 04:07:19 PM UTC 24 |
Oct 09 04:07:30 PM UTC 24 |
602113555 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.1646971911 |
|
|
Oct 09 04:07:15 PM UTC 24 |
Oct 09 04:07:30 PM UTC 24 |
8538476694 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_mailbox.3593090577 |
|
|
Oct 09 04:07:26 PM UTC 24 |
Oct 09 04:07:31 PM UTC 24 |
345333779 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.2500158839 |
|
|
Oct 09 04:05:12 PM UTC 24 |
Oct 09 04:07:32 PM UTC 24 |
208879951903 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_stress_all.2010983171 |
|
|
Oct 09 04:06:43 PM UTC 24 |
Oct 09 04:07:32 PM UTC 24 |
2449812410 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_intercept.469201433 |
|
|
Oct 09 04:06:52 PM UTC 24 |
Oct 09 04:07:34 PM UTC 24 |
13169376240 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.3167466948 |
|
|
Oct 09 04:07:31 PM UTC 24 |
Oct 09 04:07:36 PM UTC 24 |
114168752 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_intercept.3450829721 |
|
|
Oct 09 04:07:21 PM UTC 24 |
Oct 09 04:07:38 PM UTC 24 |
1654597218 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_alert_test.2441604797 |
|
|
Oct 09 04:07:37 PM UTC 24 |
Oct 09 04:07:39 PM UTC 24 |
26180722 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.3751760271 |
|
|
Oct 09 04:06:51 PM UTC 24 |
Oct 09 04:07:40 PM UTC 24 |
20025225191 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_csb_read.3239482385 |
|
|
Oct 09 04:07:39 PM UTC 24 |
Oct 09 04:07:41 PM UTC 24 |
38696741 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_all.181896136 |
|
|
Oct 09 04:06:47 PM UTC 24 |
Oct 09 04:07:42 PM UTC 24 |
6471369271 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.2322613345 |
|
|
Oct 09 04:07:42 PM UTC 24 |
Oct 09 04:07:45 PM UTC 24 |
32502148 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode.2658177348 |
|
|
Oct 09 04:06:56 PM UTC 24 |
Oct 09 04:07:45 PM UTC 24 |
12369009997 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.2656131055 |
|
|
Oct 09 04:05:27 PM UTC 24 |
Oct 09 04:07:45 PM UTC 24 |
56792449746 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_rw.808807007 |
|
|
Oct 09 04:07:43 PM UTC 24 |
Oct 09 04:07:45 PM UTC 24 |
82144006 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.3864293677 |
|
|
Oct 09 03:57:57 PM UTC 24 |
Oct 09 04:07:50 PM UTC 24 |
40939318547 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_all.3317838326 |
|
|
Oct 09 04:07:07 PM UTC 24 |
Oct 09 04:07:50 PM UTC 24 |
7483214060 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.765659071 |
|
|
Oct 09 04:07:40 PM UTC 24 |
Oct 09 04:07:51 PM UTC 24 |
3273191529 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.3120032851 |
|
|
Oct 09 04:06:17 PM UTC 24 |
Oct 09 04:07:52 PM UTC 24 |
23175793984 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode.3771178227 |
|
|
Oct 09 04:07:29 PM UTC 24 |
Oct 09 04:07:52 PM UTC 24 |
1432715586 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_intercept.1723064013 |
|
|
Oct 09 04:07:46 PM UTC 24 |
Oct 09 04:07:54 PM UTC 24 |
539231097 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_upload.559550864 |
|
|
Oct 09 04:07:29 PM UTC 24 |
Oct 09 04:07:54 PM UTC 24 |
21863272210 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_upload.753604206 |
|
|
Oct 09 04:07:51 PM UTC 24 |
Oct 09 04:07:56 PM UTC 24 |
92605458 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_cfg_cmd.2474333318 |
|
|
Oct 09 04:07:29 PM UTC 24 |
Oct 09 04:07:58 PM UTC 24 |
3349173656 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.3763562432 |
|
|
Oct 09 04:07:46 PM UTC 24 |
Oct 09 04:07:59 PM UTC 24 |
1122933797 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_all.2846714310 |
|
|
Oct 09 04:07:16 PM UTC 24 |
Oct 09 04:07:59 PM UTC 24 |
23155604871 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode.62610200 |
|
|
Oct 09 04:07:52 PM UTC 24 |
Oct 09 04:08:00 PM UTC 24 |
1105337910 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_cfg_cmd.157503803 |
|
|
Oct 09 04:07:51 PM UTC 24 |
Oct 09 04:08:02 PM UTC 24 |
815846168 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_alert_test.2944467954 |
|
|
Oct 09 04:08:00 PM UTC 24 |
Oct 09 04:08:02 PM UTC 24 |
102210390 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_csb_read.1607869766 |
|
|
Oct 09 04:08:00 PM UTC 24 |
Oct 09 04:08:03 PM UTC 24 |
17428964 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.2805490783 |
|
|
Oct 09 04:08:04 PM UTC 24 |
Oct 09 04:08:06 PM UTC 24 |
39946535 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_mailbox.2088967630 |
|
|
Oct 09 04:07:46 PM UTC 24 |
Oct 09 04:08:06 PM UTC 24 |
3290607940 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_rw.943677706 |
|
|
Oct 09 04:08:04 PM UTC 24 |
Oct 09 04:08:07 PM UTC 24 |
153745591 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.3495007381 |
|
|
Oct 09 04:06:42 PM UTC 24 |
Oct 09 04:08:08 PM UTC 24 |
29715606574 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.2093657391 |
|
|
Oct 09 04:07:01 PM UTC 24 |
Oct 09 04:08:09 PM UTC 24 |
2336730295 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.2671857420 |
|
|
Oct 09 04:08:07 PM UTC 24 |
Oct 09 04:08:11 PM UTC 24 |
62181987 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_all.2063992806 |
|
|
Oct 09 04:07:40 PM UTC 24 |
Oct 09 04:08:14 PM UTC 24 |
13011511798 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.3399811202 |
|
|
Oct 09 04:07:55 PM UTC 24 |
Oct 09 04:08:14 PM UTC 24 |
9500761250 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.255579216 |
|
|
Oct 09 04:07:54 PM UTC 24 |
Oct 09 04:08:18 PM UTC 24 |
1843432470 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.3149666861 |
|
|
Oct 09 04:06:38 PM UTC 24 |
Oct 09 04:08:18 PM UTC 24 |
4531443763 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_cfg_cmd.3458142814 |
|
|
Oct 09 04:08:12 PM UTC 24 |
Oct 09 04:08:18 PM UTC 24 |
756206268 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.4199093372 |
|
|
Oct 09 04:08:01 PM UTC 24 |
Oct 09 04:08:23 PM UTC 24 |
9553037121 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_intercept.1265720469 |
|
|
Oct 09 04:08:08 PM UTC 24 |
Oct 09 04:08:23 PM UTC 24 |
1569394424 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_all.3124906807 |
|
|
Oct 09 04:06:40 PM UTC 24 |
Oct 09 04:08:26 PM UTC 24 |
143793605540 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.4095237581 |
|
|
Oct 09 04:08:19 PM UTC 24 |
Oct 09 04:08:26 PM UTC 24 |
168607290 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_alert_test.3208432508 |
|
|
Oct 09 04:08:26 PM UTC 24 |
Oct 09 04:08:28 PM UTC 24 |
13572262 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.280266603 |
|
|
Oct 09 04:07:46 PM UTC 24 |
Oct 09 04:08:28 PM UTC 24 |
8895133655 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.3853114162 |
|
|
Oct 09 04:05:57 PM UTC 24 |
Oct 09 04:08:29 PM UTC 24 |
9868020199 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_csb_read.28018653 |
|
|
Oct 09 04:08:27 PM UTC 24 |
Oct 09 04:08:30 PM UTC 24 |
17236663 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.2348428234 |
|
|
Oct 09 04:08:16 PM UTC 24 |
Oct 09 04:08:30 PM UTC 24 |
392408079 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.1732425890 |
|
|
Oct 09 04:08:29 PM UTC 24 |
Oct 09 04:08:31 PM UTC 24 |
67082123 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.3419170438 |
|
|
Oct 09 04:08:30 PM UTC 24 |
Oct 09 04:08:32 PM UTC 24 |
76091883 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.3174773952 |
|
|
Oct 09 04:07:57 PM UTC 24 |
Oct 09 04:08:33 PM UTC 24 |
1565372476 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_rw.1509123008 |
|
|
Oct 09 04:08:31 PM UTC 24 |
Oct 09 04:08:34 PM UTC 24 |
182670999 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.361961873 |
|
|
Oct 09 04:08:14 PM UTC 24 |
Oct 09 04:08:35 PM UTC 24 |
1627576363 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_upload.638805711 |
|
|
Oct 09 04:08:34 PM UTC 24 |
Oct 09 04:08:38 PM UTC 24 |
586032617 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_mailbox.3913390047 |
|
|
Oct 09 04:08:34 PM UTC 24 |
Oct 09 04:08:39 PM UTC 24 |
300794425 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_upload.3622048525 |
|
|
Oct 09 04:08:09 PM UTC 24 |
Oct 09 04:08:40 PM UTC 24 |
10599596216 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_all.4162689460 |
|
|
Oct 09 04:08:30 PM UTC 24 |
Oct 09 04:08:40 PM UTC 24 |
1033175130 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_cfg_cmd.3024143070 |
|
|
Oct 09 04:08:36 PM UTC 24 |
Oct 09 04:08:43 PM UTC 24 |
199577053 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.1954456860 |
|
|
Oct 09 04:07:33 PM UTC 24 |
Oct 09 04:08:44 PM UTC 24 |
8017899920 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_intercept.2417773755 |
|
|
Oct 09 04:08:33 PM UTC 24 |
Oct 09 04:08:45 PM UTC 24 |
3991783632 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.1486336573 |
|
|
Oct 09 04:08:40 PM UTC 24 |
Oct 09 04:08:46 PM UTC 24 |
502160920 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_all.4025357554 |
|
|
Oct 09 04:08:03 PM UTC 24 |
Oct 09 04:08:47 PM UTC 24 |
4236694841 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_alert_test.424613180 |
|
|
Oct 09 04:08:46 PM UTC 24 |
Oct 09 04:08:49 PM UTC 24 |
34394923 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_csb_read.1144536863 |
|
|
Oct 09 04:08:48 PM UTC 24 |
Oct 09 04:08:50 PM UTC 24 |
26239097 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.579961796 |
|
|
Oct 09 04:08:31 PM UTC 24 |
Oct 09 04:08:53 PM UTC 24 |
43963193613 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.3623124320 |
|
|
Oct 09 04:08:51 PM UTC 24 |
Oct 09 04:08:53 PM UTC 24 |
214191265 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.3886731510 |
|
|
Oct 09 04:08:32 PM UTC 24 |
Oct 09 04:08:54 PM UTC 24 |
7508668788 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_rw.3124333908 |
|
|
Oct 09 04:08:54 PM UTC 24 |
Oct 09 04:08:57 PM UTC 24 |
391770184 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.17447339 |
|
|
Oct 09 04:06:17 PM UTC 24 |
Oct 09 04:08:58 PM UTC 24 |
10729068821 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.1990269386 |
|
|
Oct 09 04:07:08 PM UTC 24 |
Oct 09 04:08:58 PM UTC 24 |
8531689248 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.766138005 |
|
|
Oct 09 04:08:19 PM UTC 24 |
Oct 09 04:08:58 PM UTC 24 |
2426816350 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.1881465249 |
|
|
Oct 09 04:08:07 PM UTC 24 |
Oct 09 04:08:59 PM UTC 24 |
23490679315 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.1079196915 |
|
|
Oct 09 04:07:35 PM UTC 24 |
Oct 09 04:09:01 PM UTC 24 |
11615337501 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.577535048 |
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|
Oct 09 04:08:48 PM UTC 24 |
Oct 09 04:09:02 PM UTC 24 |
8985407628 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.673588729 |
|
|
Oct 09 04:08:44 PM UTC 24 |
Oct 09 04:09:03 PM UTC 24 |
3752758267 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_csb_read.4130720065 |
|
|
Oct 09 04:09:35 PM UTC 24 |
Oct 09 04:09:37 PM UTC 24 |
46893698 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode.4150162202 |
|
|
Oct 09 04:09:00 PM UTC 24 |
Oct 09 04:09:05 PM UTC 24 |
797960868 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.1047575888 |
|
|
Oct 09 04:08:54 PM UTC 24 |
Oct 09 04:09:05 PM UTC 24 |
1145908212 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.721061294 |
|
|
Oct 09 04:08:54 PM UTC 24 |
Oct 09 04:09:08 PM UTC 24 |
1027468635 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.4070824070 |
|
|
Oct 09 04:09:07 PM UTC 24 |
Oct 09 04:09:09 PM UTC 24 |
165834295 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_alert_test.3333248702 |
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|
Oct 09 04:09:08 PM UTC 24 |
Oct 09 04:09:10 PM UTC 24 |
33867821 ps |