| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.77 | 98.70 | 96.92 | 99.01 | 89.36 | 98.59 | 95.56 | 99.26 |
| T1033 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.1486546867 | Oct 09 12:16:58 PM UTC 24 | Oct 09 12:17:00 PM UTC 24 | 31710420 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3588748828 | Oct 09 12:16:55 PM UTC 24 | Oct 09 12:17:01 PM UTC 24 | 217024976 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.3209369215 | Oct 09 12:16:59 PM UTC 24 | Oct 09 12:17:01 PM UTC 24 | 70938867 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1915960742 | Oct 09 12:16:57 PM UTC 24 | Oct 09 12:17:03 PM UTC 24 | 115075257 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.1595281167 | Oct 09 12:16:41 PM UTC 24 | Oct 09 12:17:03 PM UTC 24 | 5490150239 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3372500271 | Oct 09 12:17:01 PM UTC 24 | Oct 09 12:17:04 PM UTC 24 | 59300632 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.146295584 | Oct 09 12:17:01 PM UTC 24 | Oct 09 12:17:04 PM UTC 24 | 474244559 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.2926957044 | Oct 09 12:17:01 PM UTC 24 | Oct 09 12:17:05 PM UTC 24 | 154389239 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.1779209617 | Oct 09 12:16:50 PM UTC 24 | Oct 09 12:17:05 PM UTC 24 | 548565757 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.2985044514 | Oct 09 12:16:57 PM UTC 24 | Oct 09 12:17:05 PM UTC 24 | 287217761 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.2228155305 | Oct 09 12:16:57 PM UTC 24 | Oct 09 12:17:07 PM UTC 24 | 3100688053 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.251834494 | Oct 09 12:17:31 PM UTC 24 | Oct 09 12:17:34 PM UTC 24 | 11603637 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.658600789 | Oct 09 12:16:44 PM UTC 24 | Oct 09 12:17:08 PM UTC 24 | 636667559 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.2755557124 | Oct 09 12:17:06 PM UTC 24 | Oct 09 12:17:08 PM UTC 24 | 15822622 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.3989459802 | Oct 09 12:17:06 PM UTC 24 | Oct 09 12:17:08 PM UTC 24 | 11794082 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.1044593105 | Oct 09 12:17:06 PM UTC 24 | Oct 09 12:17:09 PM UTC 24 | 37998831 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1335840622 | Oct 09 12:16:54 PM UTC 24 | Oct 09 12:17:10 PM UTC 24 | 185830680 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3167584288 | Oct 09 12:17:08 PM UTC 24 | Oct 09 12:17:11 PM UTC 24 | 65961972 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.3709013576 | Oct 09 12:17:05 PM UTC 24 | Oct 09 12:17:11 PM UTC 24 | 531113333 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.178445662 | Oct 09 12:17:05 PM UTC 24 | Oct 09 12:17:11 PM UTC 24 | 162394204 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4075647097 | Oct 09 12:17:05 PM UTC 24 | Oct 09 12:17:12 PM UTC 24 | 834297899 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.1726677113 | Oct 09 12:17:09 PM UTC 24 | Oct 09 12:17:13 PM UTC 24 | 28426434 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.264526729 | Oct 09 12:17:11 PM UTC 24 | Oct 09 12:17:14 PM UTC 24 | 240066715 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.1712650778 | Oct 09 12:17:13 PM UTC 24 | Oct 09 12:17:15 PM UTC 24 | 12845762 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.3559436660 | Oct 09 12:17:12 PM UTC 24 | Oct 09 12:17:15 PM UTC 24 | 156482155 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1638489166 | Oct 09 12:17:12 PM UTC 24 | Oct 09 12:17:15 PM UTC 24 | 51332288 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.1881520985 | Oct 09 12:17:13 PM UTC 24 | Oct 09 12:17:16 PM UTC 24 | 321697354 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.3604599765 | Oct 09 12:16:44 PM UTC 24 | Oct 09 12:17:17 PM UTC 24 | 2179131604 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.863111018 | Oct 09 12:17:16 PM UTC 24 | Oct 09 12:17:19 PM UTC 24 | 34039905 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.1087412490 | Oct 09 12:17:15 PM UTC 24 | Oct 09 12:17:20 PM UTC 24 | 502866483 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2870260626 | Oct 09 12:17:14 PM UTC 24 | Oct 09 12:17:20 PM UTC 24 | 115996975 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2409560343 | Oct 09 12:16:44 PM UTC 24 | Oct 09 12:17:20 PM UTC 24 | 2466110753 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.2346168269 | Oct 09 12:17:05 PM UTC 24 | Oct 09 12:17:21 PM UTC 24 | 405779439 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.488343800 | Oct 09 12:17:17 PM UTC 24 | Oct 09 12:17:21 PM UTC 24 | 332287554 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1308860293 | Oct 09 12:17:18 PM UTC 24 | Oct 09 12:17:21 PM UTC 24 | 107957751 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.597281557 | Oct 09 12:17:15 PM UTC 24 | Oct 09 12:17:21 PM UTC 24 | 127353081 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.918127739 | Oct 09 12:17:18 PM UTC 24 | Oct 09 12:17:22 PM UTC 24 | 92482777 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.3351897230 | Oct 09 12:17:21 PM UTC 24 | Oct 09 12:17:23 PM UTC 24 | 56554664 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.4090333398 | Oct 09 12:16:54 PM UTC 24 | Oct 09 12:17:25 PM UTC 24 | 327542335 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.720405203 | Oct 09 12:17:22 PM UTC 24 | Oct 09 12:17:25 PM UTC 24 | 12479588 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.2566297224 | Oct 09 12:17:21 PM UTC 24 | Oct 09 12:17:25 PM UTC 24 | 80649987 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.1808310692 | Oct 09 12:17:05 PM UTC 24 | Oct 09 12:17:25 PM UTC 24 | 220985492 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2655642795 | Oct 09 12:17:22 PM UTC 24 | Oct 09 12:17:27 PM UTC 24 | 104469904 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.1435830974 | Oct 09 12:17:20 PM UTC 24 | Oct 09 12:17:28 PM UTC 24 | 218887802 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.2493216706 | Oct 09 12:17:26 PM UTC 24 | Oct 09 12:17:29 PM UTC 24 | 24794702 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.867264939 | Oct 09 12:17:22 PM UTC 24 | Oct 09 12:17:29 PM UTC 24 | 349787466 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.178176947 | Oct 09 12:17:22 PM UTC 24 | Oct 09 12:17:29 PM UTC 24 | 65274931 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.1541563388 | Oct 09 12:17:24 PM UTC 24 | Oct 09 12:17:29 PM UTC 24 | 94450044 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.1854028604 | Oct 09 12:17:28 PM UTC 24 | Oct 09 12:17:30 PM UTC 24 | 17027352 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.419859730 | Oct 09 12:16:47 PM UTC 24 | Oct 09 12:17:31 PM UTC 24 | 7219180947 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.404080023 | Oct 09 12:17:12 PM UTC 24 | Oct 09 12:17:32 PM UTC 24 | 2872238090 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2497434565 | Oct 09 12:17:26 PM UTC 24 | Oct 09 12:17:32 PM UTC 24 | 319693840 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4088667221 | Oct 09 12:17:26 PM UTC 24 | Oct 09 12:17:32 PM UTC 24 | 163699859 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.938374926 | Oct 09 12:17:02 PM UTC 24 | Oct 09 12:17:34 PM UTC 24 | 1952523734 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.2452399612 | Oct 09 12:17:09 PM UTC 24 | Oct 09 12:17:35 PM UTC 24 | 2697369785 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3058896503 | Oct 09 12:17:30 PM UTC 24 | Oct 09 12:17:35 PM UTC 24 | 832522515 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.633694477 | Oct 09 12:17:33 PM UTC 24 | Oct 09 12:17:36 PM UTC 24 | 141181239 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.479769291 | Oct 09 12:17:30 PM UTC 24 | Oct 09 12:17:36 PM UTC 24 | 207505880 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.94319275 | Oct 09 12:17:32 PM UTC 24 | Oct 09 12:17:36 PM UTC 24 | 28164645 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.1551377090 | Oct 09 12:17:35 PM UTC 24 | Oct 09 12:17:37 PM UTC 24 | 22825512 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.105633441 | Oct 09 12:17:16 PM UTC 24 | Oct 09 12:17:37 PM UTC 24 | 613675790 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2911656924 | Oct 09 12:17:33 PM UTC 24 | Oct 09 12:17:38 PM UTC 24 | 78495769 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.2995875677 | Oct 09 12:17:34 PM UTC 24 | Oct 09 12:17:38 PM UTC 24 | 63446354 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.2421185105 | Oct 09 12:17:35 PM UTC 24 | Oct 09 12:17:38 PM UTC 24 | 82808200 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1908833665 | Oct 09 12:17:30 PM UTC 24 | Oct 09 12:17:38 PM UTC 24 | 841247584 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.3450634206 | Oct 09 12:17:36 PM UTC 24 | Oct 09 12:17:39 PM UTC 24 | 96303446 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.2654965931 | Oct 09 12:17:27 PM UTC 24 | Oct 09 12:17:39 PM UTC 24 | 289275496 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3620097285 | Oct 09 12:17:09 PM UTC 24 | Oct 09 12:17:39 PM UTC 24 | 369940725 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.139131125 | Oct 09 12:17:36 PM UTC 24 | Oct 09 12:17:40 PM UTC 24 | 517865549 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.3959554448 | Oct 09 12:17:39 PM UTC 24 | Oct 09 12:17:41 PM UTC 24 | 40273489 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3497459377 | Oct 09 12:17:36 PM UTC 24 | Oct 09 12:17:41 PM UTC 24 | 175620464 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1676562610 | Oct 09 12:17:35 PM UTC 24 | Oct 09 12:17:41 PM UTC 24 | 661704778 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.215949613 | Oct 09 12:17:21 PM UTC 24 | Oct 09 12:17:41 PM UTC 24 | 4233741158 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.3597700337 | Oct 09 12:17:37 PM UTC 24 | Oct 09 12:17:42 PM UTC 24 | 73099116 ps | ||
| T1081 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.188804249 | Oct 09 12:17:59 PM UTC 24 | Oct 09 12:18:01 PM UTC 24 | 63257608 ps | ||
| T1082 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3356339927 | Oct 09 12:17:39 PM UTC 24 | Oct 09 12:17:42 PM UTC 24 | 47003837 ps | ||
| T1083 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1467307668 | Oct 09 12:17:39 PM UTC 24 | Oct 09 12:17:42 PM UTC 24 | 240918916 ps | ||
| T1084 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.620078341 | Oct 09 12:17:39 PM UTC 24 | Oct 09 12:17:43 PM UTC 24 | 151715488 ps | ||
| T1085 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.3913461104 | Oct 09 12:17:40 PM UTC 24 | Oct 09 12:17:44 PM UTC 24 | 62298691 ps | ||
| T1086 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.27939229 | Oct 09 12:17:39 PM UTC 24 | Oct 09 12:17:44 PM UTC 24 | 192166811 ps | ||
| T1087 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.1822252887 | Oct 09 12:17:42 PM UTC 24 | Oct 09 12:17:45 PM UTC 24 | 13109574 ps | ||
| T1088 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2883903070 | Oct 09 12:17:40 PM UTC 24 | Oct 09 12:17:45 PM UTC 24 | 80191082 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3389873272 | Oct 09 12:17:30 PM UTC 24 | Oct 09 12:17:45 PM UTC 24 | 395482016 ps | ||
| T1089 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.3583486906 | Oct 09 12:17:42 PM UTC 24 | Oct 09 12:17:45 PM UTC 24 | 125153386 ps | ||
| T1090 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2288331293 | Oct 09 12:17:40 PM UTC 24 | Oct 09 12:17:45 PM UTC 24 | 895231053 ps | ||
| T1091 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.4038702141 | Oct 09 12:17:44 PM UTC 24 | Oct 09 12:17:46 PM UTC 24 | 21202284 ps | ||
| T1092 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2244041851 | Oct 09 12:17:43 PM UTC 24 | Oct 09 12:17:47 PM UTC 24 | 36566834 ps | ||
| T1093 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1394953537 | Oct 09 12:17:42 PM UTC 24 | Oct 09 12:17:47 PM UTC 24 | 214236170 ps | ||
| T1094 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.1735452148 | Oct 09 12:17:44 PM UTC 24 | Oct 09 12:17:48 PM UTC 24 | 62885851 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.3528446457 | Oct 09 12:17:22 PM UTC 24 | Oct 09 12:17:48 PM UTC 24 | 310866515 ps | ||
| T1095 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.1256132496 | Oct 09 12:17:46 PM UTC 24 | Oct 09 12:17:49 PM UTC 24 | 12543792 ps | ||
| T1096 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2818057176 | Oct 09 12:17:45 PM UTC 24 | Oct 09 12:17:49 PM UTC 24 | 307443686 ps | ||
| T1097 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.546769646 | Oct 09 12:17:43 PM UTC 24 | Oct 09 12:17:49 PM UTC 24 | 137548597 ps | ||
| T1098 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.3554582515 | Oct 09 12:17:41 PM UTC 24 | Oct 09 12:17:50 PM UTC 24 | 307782591 ps | ||
| T1099 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1638218557 | Oct 09 12:17:46 PM UTC 24 | Oct 09 12:17:50 PM UTC 24 | 56321529 ps | ||
| T1100 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.3710861003 | Oct 09 12:17:59 PM UTC 24 | Oct 09 12:18:01 PM UTC 24 | 39762835 ps | ||
| T1101 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2728487564 | Oct 09 12:17:48 PM UTC 24 | Oct 09 12:17:51 PM UTC 24 | 38158264 ps | ||
| T1102 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3258616187 | Oct 09 12:17:45 PM UTC 24 | Oct 09 12:17:51 PM UTC 24 | 520351177 ps | ||
| T1103 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.878743488 | Oct 09 12:17:49 PM UTC 24 | Oct 09 12:17:51 PM UTC 24 | 13638623 ps | ||
| T1104 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.2410793735 | Oct 09 12:17:46 PM UTC 24 | Oct 09 12:17:51 PM UTC 24 | 92574319 ps | ||
| T1105 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.2315412708 | Oct 09 12:17:39 PM UTC 24 | Oct 09 12:17:51 PM UTC 24 | 205726319 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.1376096139 | Oct 09 12:17:48 PM UTC 24 | Oct 09 12:17:52 PM UTC 24 | 38906287 ps | ||
| T1106 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.830245401 | Oct 09 12:17:49 PM UTC 24 | Oct 09 12:17:52 PM UTC 24 | 173297445 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.3042531481 | Oct 09 12:17:46 PM UTC 24 | Oct 09 12:17:53 PM UTC 24 | 555554661 ps | ||
| T1107 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4251412992 | Oct 09 12:17:50 PM UTC 24 | Oct 09 12:17:54 PM UTC 24 | 92164990 ps | ||
| T1108 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.2198446200 | Oct 09 12:17:51 PM UTC 24 | Oct 09 12:17:54 PM UTC 24 | 15287138 ps | ||
| T1109 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.3895474069 | Oct 09 12:17:51 PM UTC 24 | Oct 09 12:17:55 PM UTC 24 | 58916832 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.617346853 | Oct 09 12:17:34 PM UTC 24 | Oct 09 12:17:55 PM UTC 24 | 1309579649 ps | ||
| T1110 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.3183913682 | Oct 09 12:17:53 PM UTC 24 | Oct 09 12:17:55 PM UTC 24 | 14292026 ps | ||
| T1111 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1028112984 | Oct 09 12:17:50 PM UTC 24 | Oct 09 12:17:55 PM UTC 24 | 43375358 ps | ||
| T1112 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.727802966 | Oct 09 12:17:36 PM UTC 24 | Oct 09 12:17:56 PM UTC 24 | 318084648 ps | ||
| T1113 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.1359008112 | Oct 09 12:17:50 PM UTC 24 | Oct 09 12:17:57 PM UTC 24 | 186210421 ps | ||
| T1114 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2739652312 | Oct 09 12:17:51 PM UTC 24 | Oct 09 12:17:57 PM UTC 24 | 406226286 ps | ||
| T1115 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.2992570712 | Oct 09 12:17:53 PM UTC 24 | Oct 09 12:17:57 PM UTC 24 | 29823153 ps | ||
| T1116 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.963390553 | Oct 09 12:17:51 PM UTC 24 | Oct 09 12:17:57 PM UTC 24 | 321282450 ps | ||
| T1117 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.3975214405 | Oct 09 12:17:55 PM UTC 24 | Oct 09 12:17:58 PM UTC 24 | 41476314 ps | ||
| T1118 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.3074772514 | Oct 09 12:17:55 PM UTC 24 | Oct 09 12:17:58 PM UTC 24 | 33873942 ps | ||
| T1119 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.1970655055 | Oct 09 12:17:43 PM UTC 24 | Oct 09 12:17:58 PM UTC 24 | 647432515 ps | ||
| T1120 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.4034060744 | Oct 09 12:17:56 PM UTC 24 | Oct 09 12:17:58 PM UTC 24 | 48161676 ps | ||
| T1121 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1515155564 | Oct 09 12:17:56 PM UTC 24 | Oct 09 12:17:59 PM UTC 24 | 18293228 ps | ||
| T1122 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.1900555662 | Oct 09 12:17:56 PM UTC 24 | Oct 09 12:17:59 PM UTC 24 | 39508601 ps | ||
| T1123 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3763614096 | Oct 09 12:17:54 PM UTC 24 | Oct 09 12:17:59 PM UTC 24 | 39416991 ps | ||
| T1124 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.4110047121 | Oct 09 12:17:49 PM UTC 24 | Oct 09 12:17:59 PM UTC 24 | 387514064 ps | ||
| T1125 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.113813645 | Oct 09 12:17:53 PM UTC 24 | Oct 09 12:17:59 PM UTC 24 | 435259671 ps | ||
| T1126 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.3745301254 | Oct 09 12:17:56 PM UTC 24 | Oct 09 12:17:59 PM UTC 24 | 17699445 ps | ||
| T1127 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.2223305728 | Oct 09 12:17:58 PM UTC 24 | Oct 09 12:18:00 PM UTC 24 | 18016090 ps | ||
| T1128 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.2482010767 | Oct 09 12:17:58 PM UTC 24 | Oct 09 12:18:00 PM UTC 24 | 19166026 ps | ||
| T1129 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.189125179 | Oct 09 12:17:58 PM UTC 24 | Oct 09 12:18:00 PM UTC 24 | 11158532 ps | ||
| T1130 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.2252920804 | Oct 09 12:17:58 PM UTC 24 | Oct 09 12:18:00 PM UTC 24 | 17921664 ps | ||
| T1131 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.573062028 | Oct 09 12:17:59 PM UTC 24 | Oct 09 12:18:01 PM UTC 24 | 56510962 ps | ||
| T1132 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.2423382086 | Oct 09 12:17:59 PM UTC 24 | Oct 09 12:18:01 PM UTC 24 | 13627566 ps | ||
| T1133 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.3203772112 | Oct 09 12:17:59 PM UTC 24 | Oct 09 12:18:01 PM UTC 24 | 53802478 ps | ||
| T1134 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.20677721 | Oct 09 12:18:00 PM UTC 24 | Oct 09 12:18:02 PM UTC 24 | 16612042 ps | ||
| T1135 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.1147027880 | Oct 09 12:17:53 PM UTC 24 | Oct 09 12:18:02 PM UTC 24 | 5027817776 ps | ||
| T1136 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.2713071585 | Oct 09 12:18:00 PM UTC 24 | Oct 09 12:18:02 PM UTC 24 | 36733378 ps | ||
| T1137 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.3811440654 | Oct 09 12:18:00 PM UTC 24 | Oct 09 12:18:02 PM UTC 24 | 17025851 ps | ||
| T1138 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.816409137 | Oct 09 12:18:00 PM UTC 24 | Oct 09 12:18:02 PM UTC 24 | 72196451 ps | ||
| T1139 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.163405656 | Oct 09 12:18:00 PM UTC 24 | Oct 09 12:18:02 PM UTC 24 | 25877547 ps | ||
| T1140 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.517055020 | Oct 09 12:18:00 PM UTC 24 | Oct 09 12:18:02 PM UTC 24 | 11952984 ps | ||
| T1141 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.3150411935 | Oct 09 12:18:00 PM UTC 24 | Oct 09 12:18:03 PM UTC 24 | 31349961 ps | ||
| T1142 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.1701158204 | Oct 09 12:17:50 PM UTC 24 | Oct 09 12:18:03 PM UTC 24 | 1446893739 ps | ||
| T1143 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.2146025875 | Oct 09 12:18:02 PM UTC 24 | Oct 09 12:18:04 PM UTC 24 | 16697703 ps | ||
| T1144 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.488629378 | Oct 09 12:18:02 PM UTC 24 | Oct 09 12:18:04 PM UTC 24 | 10658080 ps | ||
| T1145 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.1171590513 | Oct 09 12:18:02 PM UTC 24 | Oct 09 12:18:04 PM UTC 24 | 18054491 ps | ||
| T1146 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.3121469545 | Oct 09 12:18:02 PM UTC 24 | Oct 09 12:18:04 PM UTC 24 | 46115973 ps | ||
| T1147 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.714686468 | Oct 09 12:18:02 PM UTC 24 | Oct 09 12:18:04 PM UTC 24 | 13304706 ps | ||
| T1148 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.1087450567 | Oct 09 12:18:02 PM UTC 24 | Oct 09 12:18:04 PM UTC 24 | 16351310 ps | ||
| T1149 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.3144133159 | Oct 09 12:18:02 PM UTC 24 | Oct 09 12:18:04 PM UTC 24 | 17296451 ps | ||
| T1150 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.1377287702 | Oct 09 12:18:02 PM UTC 24 | Oct 09 12:18:04 PM UTC 24 | 18984577 ps | ||
| T1151 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.3304276671 | Oct 09 12:17:46 PM UTC 24 | Oct 09 12:18:10 PM UTC 24 | 2600722621 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.3937186570 | Oct 09 12:17:53 PM UTC 24 | Oct 09 12:18:17 PM UTC 24 | 1311503532 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.717615708 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 573077823 ps |
| CPU time | 8.68 seconds |
| Started | Oct 09 03:53:48 PM UTC 24 |
| Finished | Oct 09 03:53:58 PM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717615708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.717615708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.3097892839 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 13333731374 ps |
| CPU time | 63.47 seconds |
| Started | Oct 09 03:54:06 PM UTC 24 |
| Finished | Oct 09 03:55:11 PM UTC 24 |
| Peak memory | 263820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097892839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3097892839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.4198864506 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 7045084599 ps |
| CPU time | 133.47 seconds |
| Started | Oct 09 03:55:44 PM UTC 24 |
| Finished | Oct 09 03:58:00 PM UTC 24 |
| Peak memory | 265868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198864506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.4198864506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.1375494061 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 50456068744 ps |
| CPU time | 522.65 seconds |
| Started | Oct 09 03:54:12 PM UTC 24 |
| Finished | Oct 09 04:03:02 PM UTC 24 |
| Peak memory | 265940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375494061 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.1375494061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.1185481561 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1318050630 ps |
| CPU time | 22.57 seconds |
| Started | Oct 09 03:54:25 PM UTC 24 |
| Finished | Oct 09 03:54:49 PM UTC 24 |
| Peak memory | 231776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185481561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1185481561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.1595281167 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 5490150239 ps |
| CPU time | 20.24 seconds |
| Started | Oct 09 12:16:41 PM UTC 24 |
| Finished | Oct 09 12:17:03 PM UTC 24 |
| Peak memory | 225128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595281167 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.1595281167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.3457015935 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 11909567966 ps |
| CPU time | 95.38 seconds |
| Started | Oct 09 03:53:59 PM UTC 24 |
| Finished | Oct 09 03:55:36 PM UTC 24 |
| Peak memory | 265748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457015935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.3457015935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.176422985 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 25638421 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 03:53:26 PM UTC 24 |
| Finished | Oct 09 03:53:29 PM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176422985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.176422985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.2545899083 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10431028572 ps |
| CPU time | 151.2 seconds |
| Started | Oct 09 03:55:48 PM UTC 24 |
| Finished | Oct 09 03:58:22 PM UTC 24 |
| Peak memory | 274008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545899083 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.2545899083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.3345313345 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 5803803336 ps |
| CPU time | 157.73 seconds |
| Started | Oct 09 04:04:45 PM UTC 24 |
| Finished | Oct 09 04:07:25 PM UTC 24 |
| Peak memory | 282188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345313345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.3345313345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.2386029087 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 141263611 ps |
| CPU time | 5.81 seconds |
| Started | Oct 09 03:53:59 PM UTC 24 |
| Finished | Oct 09 03:54:06 PM UTC 24 |
| Peak memory | 245452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386029087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2386029087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.2171640991 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 9622168322 ps |
| CPU time | 148.99 seconds |
| Started | Oct 09 03:57:52 PM UTC 24 |
| Finished | Oct 09 04:00:24 PM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171640991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2171640991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.1703320777 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 717976151 ps |
| CPU time | 5.53 seconds |
| Started | Oct 09 12:16:40 PM UTC 24 |
| Finished | Oct 09 12:16:47 PM UTC 24 |
| Peak memory | 227324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703320777 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1703320777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2694328048 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 14576710255 ps |
| CPU time | 150.76 seconds |
| Started | Oct 09 04:00:11 PM UTC 24 |
| Finished | Oct 09 04:02:45 PM UTC 24 |
| Peak memory | 275996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694328048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.2694328048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.1983548637 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 199646960287 ps |
| CPU time | 338.49 seconds |
| Started | Oct 09 03:57:50 PM UTC 24 |
| Finished | Oct 09 04:03:33 PM UTC 24 |
| Peak memory | 276052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983548637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1983548637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.3425683892 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 75297431 ps |
| CPU time | 1.85 seconds |
| Started | Oct 09 03:54:19 PM UTC 24 |
| Finished | Oct 09 03:54:21 PM UTC 24 |
| Peak memory | 257636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425683892 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3425683892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.1360428426 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 7558506040 ps |
| CPU time | 59.81 seconds |
| Started | Oct 09 03:59:08 PM UTC 24 |
| Finished | Oct 09 04:00:10 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360428426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.1360428426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.914865416 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 26158628911 ps |
| CPU time | 190.27 seconds |
| Started | Oct 09 03:58:23 PM UTC 24 |
| Finished | Oct 09 04:01:37 PM UTC 24 |
| Peak memory | 278028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914865416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.914865416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1686723383 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 42156879 ps |
| CPU time | 2.04 seconds |
| Started | Oct 09 12:16:54 PM UTC 24 |
| Finished | Oct 09 12:16:57 PM UTC 24 |
| Peak memory | 225184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686723383 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.1686723383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.1132948667 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 42684857346 ps |
| CPU time | 337.42 seconds |
| Started | Oct 09 04:01:25 PM UTC 24 |
| Finished | Oct 09 04:07:07 PM UTC 24 |
| Peak memory | 284232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132948667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1132948667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2439728391 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 38708310880 ps |
| CPU time | 431.69 seconds |
| Started | Oct 09 03:58:26 PM UTC 24 |
| Finished | Oct 09 04:05:43 PM UTC 24 |
| Peak memory | 278168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439728391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.2439728391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.4086728978 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 18306777454 ps |
| CPU time | 111.63 seconds |
| Started | Oct 09 03:56:40 PM UTC 24 |
| Finished | Oct 09 03:58:34 PM UTC 24 |
| Peak memory | 261900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086728978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.4086728978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.2881568566 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 27390432 ps |
| CPU time | 1.53 seconds |
| Started | Oct 09 03:55:54 PM UTC 24 |
| Finished | Oct 09 03:55:56 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881568566 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_parity.2881568566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.896146060 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 191829257255 ps |
| CPU time | 453.38 seconds |
| Started | Oct 09 03:55:05 PM UTC 24 |
| Finished | Oct 09 04:02:44 PM UTC 24 |
| Peak memory | 280212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896146060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.896146060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.17447339 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 10729068821 ps |
| CPU time | 158.15 seconds |
| Started | Oct 09 04:06:17 PM UTC 24 |
| Finished | Oct 09 04:08:58 PM UTC 24 |
| Peak memory | 280268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17447339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.17447339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.1338977031 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 45265260245 ps |
| CPU time | 300.17 seconds |
| Started | Oct 09 04:00:56 PM UTC 24 |
| Finished | Oct 09 04:06:01 PM UTC 24 |
| Peak memory | 267916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338977031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.1338977031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.2572507005 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 6888598667 ps |
| CPU time | 21.13 seconds |
| Started | Oct 09 03:54:53 PM UTC 24 |
| Finished | Oct 09 03:55:16 PM UTC 24 |
| Peak memory | 233704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572507005 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.2572507005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.1079196915 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 11615337501 ps |
| CPU time | 84.55 seconds |
| Started | Oct 09 04:07:35 PM UTC 24 |
| Finished | Oct 09 04:09:01 PM UTC 24 |
| Peak memory | 263744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079196915 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.1079196915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/22.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.2912831290 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 16635351182 ps |
| CPU time | 162.6 seconds |
| Started | Oct 09 03:54:59 PM UTC 24 |
| Finished | Oct 09 03:57:44 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912831290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2912831290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.2656131055 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 56792449746 ps |
| CPU time | 135.3 seconds |
| Started | Oct 09 04:05:27 PM UTC 24 |
| Finished | Oct 09 04:07:45 PM UTC 24 |
| Peak memory | 278024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656131055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.2656131055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.607898814 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 14334719 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 03:54:21 PM UTC 24 |
| Finished | Oct 09 03:54:23 PM UTC 24 |
| Peak memory | 214840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607898814 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.607898814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.2015902306 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 21967363710 ps |
| CPU time | 285.35 seconds |
| Started | Oct 09 04:00:21 PM UTC 24 |
| Finished | Oct 09 04:05:11 PM UTC 24 |
| Peak memory | 278164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015902306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2015902306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.3937186570 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 1311503532 ps |
| CPU time | 22.49 seconds |
| Started | Oct 09 12:17:53 PM UTC 24 |
| Finished | Oct 09 12:18:17 PM UTC 24 |
| Peak memory | 233128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937186570 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.3937186570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.1500479788 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 44490471623 ps |
| CPU time | 543.07 seconds |
| Started | Oct 09 04:01:33 PM UTC 24 |
| Finished | Oct 09 04:10:44 PM UTC 24 |
| Peak memory | 282368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500479788 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.1500479788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.2438068111 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 6319453721 ps |
| CPU time | 100.49 seconds |
| Started | Oct 09 04:05:32 PM UTC 24 |
| Finished | Oct 09 04:07:14 PM UTC 24 |
| Peak memory | 261700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438068111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.2438068111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.3302283013 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 57141747271 ps |
| CPU time | 152.97 seconds |
| Started | Oct 09 04:14:17 PM UTC 24 |
| Finished | Oct 09 04:16:52 PM UTC 24 |
| Peak memory | 267916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302283013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3302283013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3195242096 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 17602022981 ps |
| CPU time | 28.92 seconds |
| Started | Oct 09 03:53:30 PM UTC 24 |
| Finished | Oct 09 03:54:00 PM UTC 24 |
| Peak memory | 227668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195242096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3195242096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode.4182915339 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1103240781 ps |
| CPU time | 33.5 seconds |
| Started | Oct 09 04:08:36 PM UTC 24 |
| Finished | Oct 09 04:09:11 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182915339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4182915339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/25.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1908833665 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 841247584 ps |
| CPU time | 6.72 seconds |
| Started | Oct 09 12:17:30 PM UTC 24 |
| Finished | Oct 09 12:17:38 PM UTC 24 |
| Peak memory | 227256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908833665 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.1908833665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.3604599765 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 2179131604 ps |
| CPU time | 31.04 seconds |
| Started | Oct 09 12:16:44 PM UTC 24 |
| Finished | Oct 09 12:17:17 PM UTC 24 |
| Peak memory | 227324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604599765 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.3604599765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.4112817594 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 90407173498 ps |
| CPU time | 191.36 seconds |
| Started | Oct 09 03:54:58 PM UTC 24 |
| Finished | Oct 09 03:58:12 PM UTC 24 |
| Peak memory | 265808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112817594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.4112817594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.1624895317 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 5294167241 ps |
| CPU time | 50.1 seconds |
| Started | Oct 09 04:01:52 PM UTC 24 |
| Finished | Oct 09 04:02:44 PM UTC 24 |
| Peak memory | 261840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624895317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1624895317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.2291317947 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 242300750958 ps |
| CPU time | 752.32 seconds |
| Started | Oct 09 04:03:14 PM UTC 24 |
| Finished | Oct 09 04:15:56 PM UTC 24 |
| Peak memory | 261780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291317947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.2291317947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.1061305179 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1547286688 ps |
| CPU time | 37.14 seconds |
| Started | Oct 09 04:10:22 PM UTC 24 |
| Finished | Oct 09 04:11:01 PM UTC 24 |
| Peak memory | 235012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061305179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1061305179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.4128651624 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1632061348 ps |
| CPU time | 65.84 seconds |
| Started | Oct 09 04:14:17 PM UTC 24 |
| Finished | Oct 09 04:15:24 PM UTC 24 |
| Peak memory | 261656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128651624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.4128651624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/45.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.3749435729 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 84143950620 ps |
| CPU time | 327.94 seconds |
| Started | Oct 09 03:54:51 PM UTC 24 |
| Finished | Oct 09 04:00:24 PM UTC 24 |
| Peak memory | 261716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749435729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.3749435729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.2257372381 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 5250091916 ps |
| CPU time | 19.99 seconds |
| Started | Oct 09 03:54:43 PM UTC 24 |
| Finished | Oct 09 03:55:04 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257372381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2257372381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.2461403369 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 12507798154 ps |
| CPU time | 71.11 seconds |
| Started | Oct 09 04:01:22 PM UTC 24 |
| Finished | Oct 09 04:02:35 PM UTC 24 |
| Peak memory | 261776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461403369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.2461403369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.2277270920 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 25326020685 ps |
| CPU time | 82.47 seconds |
| Started | Oct 09 04:01:54 PM UTC 24 |
| Finished | Oct 09 04:03:19 PM UTC 24 |
| Peak memory | 261704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277270920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2277270920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_stress_all.982275739 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 15257680196 ps |
| CPU time | 241.88 seconds |
| Started | Oct 09 04:05:33 PM UTC 24 |
| Finished | Oct 09 04:09:39 PM UTC 24 |
| Peak memory | 265928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982275739 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.982275739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.3906223820 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 509116997 ps |
| CPU time | 19.01 seconds |
| Started | Oct 09 03:55:28 PM UTC 24 |
| Finished | Oct 09 03:55:48 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906223820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3906223820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.910733815 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 63544711922 ps |
| CPU time | 347.62 seconds |
| Started | Oct 09 04:09:07 PM UTC 24 |
| Finished | Oct 09 04:14:59 PM UTC 24 |
| Peak memory | 278092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910733815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.910733815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode.4150162202 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 797960868 ps |
| CPU time | 4.28 seconds |
| Started | Oct 09 04:09:00 PM UTC 24 |
| Finished | Oct 09 04:09:05 PM UTC 24 |
| Peak memory | 245140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150162202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.4150162202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/26.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode.82994750 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 266783566 ps |
| CPU time | 5.58 seconds |
| Started | Oct 09 04:09:44 PM UTC 24 |
| Finished | Oct 09 04:09:51 PM UTC 24 |
| Peak memory | 235140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82994750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.82994750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/29.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.274442788 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1974471812 ps |
| CPU time | 10.26 seconds |
| Started | Oct 09 03:53:36 PM UTC 24 |
| Finished | Oct 09 03:53:48 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274442788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.274442788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.139131125 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 517865549 ps |
| CPU time | 2.28 seconds |
| Started | Oct 09 12:17:36 PM UTC 24 |
| Finished | Oct 09 12:17:40 PM UTC 24 |
| Peak memory | 227172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139131125 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.139131125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.617346853 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1309579649 ps |
| CPU time | 19.84 seconds |
| Started | Oct 09 12:17:34 PM UTC 24 |
| Finished | Oct 09 12:17:55 PM UTC 24 |
| Peak memory | 226980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617346853 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.617346853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.105633441 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 613675790 ps |
| CPU time | 19.44 seconds |
| Started | Oct 09 12:17:16 PM UTC 24 |
| Finished | Oct 09 12:17:37 PM UTC 24 |
| Peak memory | 225080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105633441 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.105633441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.3119642053 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4804165062 ps |
| CPU time | 111.15 seconds |
| Started | Oct 09 04:07:34 PM UTC 24 |
| Finished | Oct 09 04:09:27 PM UTC 24 |
| Peak memory | 278144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119642053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.3119642053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.658600789 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 636667559 ps |
| CPU time | 22.68 seconds |
| Started | Oct 09 12:16:44 PM UTC 24 |
| Finished | Oct 09 12:17:08 PM UTC 24 |
| Peak memory | 225000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658600789 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.658600789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2409560343 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 2466110753 ps |
| CPU time | 34.8 seconds |
| Started | Oct 09 12:16:44 PM UTC 24 |
| Finished | Oct 09 12:17:20 PM UTC 24 |
| Peak memory | 224972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409560343 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.2409560343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2924133842 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 67327930 ps |
| CPU time | 1.62 seconds |
| Started | Oct 09 12:16:42 PM UTC 24 |
| Finished | Oct 09 12:16:45 PM UTC 24 |
| Peak memory | 214136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924133842 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.2924133842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2509145695 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 46046784 ps |
| CPU time | 2.63 seconds |
| Started | Oct 09 12:16:44 PM UTC 24 |
| Finished | Oct 09 12:16:48 PM UTC 24 |
| Peak memory | 225284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2509145695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2509145695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3307455069 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 68678074 ps |
| CPU time | 2.67 seconds |
| Started | Oct 09 12:16:42 PM UTC 24 |
| Finished | Oct 09 12:16:46 PM UTC 24 |
| Peak memory | 225080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307455069 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3307455069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.1898658176 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 25598260 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 12:16:42 PM UTC 24 |
| Finished | Oct 09 12:16:44 PM UTC 24 |
| Peak memory | 212688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898658176 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1898658176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.3232368835 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 72626392 ps |
| CPU time | 3.03 seconds |
| Started | Oct 09 12:16:42 PM UTC 24 |
| Finished | Oct 09 12:16:46 PM UTC 24 |
| Peak memory | 225072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232368835 -assert nopostp roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.3232368835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2030362849 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 13675719 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 12:16:42 PM UTC 24 |
| Finished | Oct 09 12:16:44 PM UTC 24 |
| Peak memory | 212676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030362849 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.2030362849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1692657791 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 255412115 ps |
| CPU time | 2.68 seconds |
| Started | Oct 09 12:16:44 PM UTC 24 |
| Finished | Oct 09 12:16:48 PM UTC 24 |
| Peak memory | 227040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692657791 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstanding.1692657791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2026432019 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 225930652 ps |
| CPU time | 10.11 seconds |
| Started | Oct 09 12:16:48 PM UTC 24 |
| Finished | Oct 09 12:17:00 PM UTC 24 |
| Peak memory | 225204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026432019 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.2026432019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.419859730 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 7219180947 ps |
| CPU time | 41.91 seconds |
| Started | Oct 09 12:16:47 PM UTC 24 |
| Finished | Oct 09 12:17:31 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419859730 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.419859730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2783875492 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 17217242 ps |
| CPU time | 1.43 seconds |
| Started | Oct 09 12:16:47 PM UTC 24 |
| Finished | Oct 09 12:16:50 PM UTC 24 |
| Peak memory | 214312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783875492 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.2783875492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.951282633 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 108674411 ps |
| CPU time | 3.73 seconds |
| Started | Oct 09 12:16:49 PM UTC 24 |
| Finished | Oct 09 12:16:54 PM UTC 24 |
| Peak memory | 229168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=951282633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.951282633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2399349307 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 105920322 ps |
| CPU time | 2.58 seconds |
| Started | Oct 09 12:16:47 PM UTC 24 |
| Finished | Oct 09 12:16:51 PM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399349307 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2399349307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.4060777320 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 17284251 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 12:16:45 PM UTC 24 |
| Finished | Oct 09 12:16:48 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060777320 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.4060777320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.3203838434 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 61234036 ps |
| CPU time | 1.94 seconds |
| Started | Oct 09 12:16:46 PM UTC 24 |
| Finished | Oct 09 12:16:49 PM UTC 24 |
| Peak memory | 223884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203838434 -assert nopostp roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.3203838434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1708573437 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 27982035 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 12:16:45 PM UTC 24 |
| Finished | Oct 09 12:16:47 PM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708573437 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.1708573437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3859236568 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 200841856 ps |
| CPU time | 5.74 seconds |
| Started | Oct 09 12:16:49 PM UTC 24 |
| Finished | Oct 09 12:16:55 PM UTC 24 |
| Peak memory | 225048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859236568 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstanding.3859236568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1101908553 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 182798611 ps |
| CPU time | 2.91 seconds |
| Started | Oct 09 12:16:44 PM UTC 24 |
| Finished | Oct 09 12:16:48 PM UTC 24 |
| Peak memory | 227380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101908553 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1101908553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2911656924 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 78495769 ps |
| CPU time | 4.06 seconds |
| Started | Oct 09 12:17:33 PM UTC 24 |
| Finished | Oct 09 12:17:38 PM UTC 24 |
| Peak memory | 229096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2911656924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2911656924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.94319275 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 28164645 ps |
| CPU time | 2.61 seconds |
| Started | Oct 09 12:17:32 PM UTC 24 |
| Finished | Oct 09 12:17:36 PM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94319275 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.94319275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.251834494 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 11603637 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 12:17:31 PM UTC 24 |
| Finished | Oct 09 12:17:34 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251834494 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.251834494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.633694477 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 141181239 ps |
| CPU time | 2.1 seconds |
| Started | Oct 09 12:17:33 PM UTC 24 |
| Finished | Oct 09 12:17:36 PM UTC 24 |
| Peak memory | 224944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633694477 -assert nopost proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstanding.633694477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3389873272 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 395482016 ps |
| CPU time | 13.31 seconds |
| Started | Oct 09 12:17:30 PM UTC 24 |
| Finished | Oct 09 12:17:45 PM UTC 24 |
| Peak memory | 225208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389873272 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.3389873272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3497459377 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 175620464 ps |
| CPU time | 3.61 seconds |
| Started | Oct 09 12:17:36 PM UTC 24 |
| Finished | Oct 09 12:17:41 PM UTC 24 |
| Peak memory | 227188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3497459377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3497459377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.2421185105 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 82808200 ps |
| CPU time | 1.83 seconds |
| Started | Oct 09 12:17:35 PM UTC 24 |
| Finished | Oct 09 12:17:38 PM UTC 24 |
| Peak memory | 213608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421185105 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.2421185105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.1551377090 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 22825512 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 12:17:35 PM UTC 24 |
| Finished | Oct 09 12:17:37 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551377090 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.1551377090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1676562610 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 661704778 ps |
| CPU time | 4.96 seconds |
| Started | Oct 09 12:17:35 PM UTC 24 |
| Finished | Oct 09 12:17:41 PM UTC 24 |
| Peak memory | 225216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676562610 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstanding.1676562610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.2995875677 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 63446354 ps |
| CPU time | 3.08 seconds |
| Started | Oct 09 12:17:34 PM UTC 24 |
| Finished | Oct 09 12:17:38 PM UTC 24 |
| Peak memory | 225160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995875677 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.2995875677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3356339927 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 47003837 ps |
| CPU time | 2.21 seconds |
| Started | Oct 09 12:17:39 PM UTC 24 |
| Finished | Oct 09 12:17:42 PM UTC 24 |
| Peak memory | 227124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3356339927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3356339927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.3597700337 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 73099116 ps |
| CPU time | 3.08 seconds |
| Started | Oct 09 12:17:37 PM UTC 24 |
| Finished | Oct 09 12:17:42 PM UTC 24 |
| Peak memory | 225212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597700337 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.3597700337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.3450634206 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 96303446 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 12:17:36 PM UTC 24 |
| Finished | Oct 09 12:17:39 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450634206 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.3450634206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1467307668 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 240918916 ps |
| CPU time | 2.47 seconds |
| Started | Oct 09 12:17:39 PM UTC 24 |
| Finished | Oct 09 12:17:42 PM UTC 24 |
| Peak memory | 224940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467307668 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstanding.1467307668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.727802966 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 318084648 ps |
| CPU time | 18.66 seconds |
| Started | Oct 09 12:17:36 PM UTC 24 |
| Finished | Oct 09 12:17:56 PM UTC 24 |
| Peak memory | 225248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727802966 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.727802966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2883903070 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 80191082 ps |
| CPU time | 3.63 seconds |
| Started | Oct 09 12:17:40 PM UTC 24 |
| Finished | Oct 09 12:17:45 PM UTC 24 |
| Peak memory | 227268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2883903070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2883903070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.27939229 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 192166811 ps |
| CPU time | 3.9 seconds |
| Started | Oct 09 12:17:39 PM UTC 24 |
| Finished | Oct 09 12:17:44 PM UTC 24 |
| Peak memory | 225268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27939229 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.27939229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.3959554448 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 40273489 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 12:17:39 PM UTC 24 |
| Finished | Oct 09 12:17:41 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959554448 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.3959554448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2288331293 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 895231053 ps |
| CPU time | 3.96 seconds |
| Started | Oct 09 12:17:40 PM UTC 24 |
| Finished | Oct 09 12:17:45 PM UTC 24 |
| Peak memory | 224996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288331293 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstanding.2288331293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.620078341 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 151715488 ps |
| CPU time | 3.26 seconds |
| Started | Oct 09 12:17:39 PM UTC 24 |
| Finished | Oct 09 12:17:43 PM UTC 24 |
| Peak memory | 227412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620078341 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.620078341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.2315412708 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 205726319 ps |
| CPU time | 11.36 seconds |
| Started | Oct 09 12:17:39 PM UTC 24 |
| Finished | Oct 09 12:17:51 PM UTC 24 |
| Peak memory | 225252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315412708 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.2315412708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2244041851 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 36566834 ps |
| CPU time | 3.64 seconds |
| Started | Oct 09 12:17:43 PM UTC 24 |
| Finished | Oct 09 12:17:47 PM UTC 24 |
| Peak memory | 229292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2244041851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2244041851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.3583486906 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 125153386 ps |
| CPU time | 1.7 seconds |
| Started | Oct 09 12:17:42 PM UTC 24 |
| Finished | Oct 09 12:17:45 PM UTC 24 |
| Peak memory | 213608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583486906 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.3583486906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.1822252887 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 13109574 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 12:17:42 PM UTC 24 |
| Finished | Oct 09 12:17:45 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822252887 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.1822252887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1394953537 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 214236170 ps |
| CPU time | 3.79 seconds |
| Started | Oct 09 12:17:42 PM UTC 24 |
| Finished | Oct 09 12:17:47 PM UTC 24 |
| Peak memory | 224968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394953537 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstanding.1394953537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.3913461104 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 62298691 ps |
| CPU time | 2.68 seconds |
| Started | Oct 09 12:17:40 PM UTC 24 |
| Finished | Oct 09 12:17:44 PM UTC 24 |
| Peak memory | 225132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913461104 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.3913461104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.3554582515 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 307782591 ps |
| CPU time | 7.79 seconds |
| Started | Oct 09 12:17:41 PM UTC 24 |
| Finished | Oct 09 12:17:50 PM UTC 24 |
| Peak memory | 224940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554582515 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.3554582515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3258616187 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 520351177 ps |
| CPU time | 4.75 seconds |
| Started | Oct 09 12:17:45 PM UTC 24 |
| Finished | Oct 09 12:17:51 PM UTC 24 |
| Peak memory | 229240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3258616187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3258616187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.1735452148 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 62885851 ps |
| CPU time | 2.63 seconds |
| Started | Oct 09 12:17:44 PM UTC 24 |
| Finished | Oct 09 12:17:48 PM UTC 24 |
| Peak memory | 225008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735452148 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.1735452148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.4038702141 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 21202284 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 12:17:44 PM UTC 24 |
| Finished | Oct 09 12:17:46 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038702141 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.4038702141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2818057176 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 307443686 ps |
| CPU time | 2.8 seconds |
| Started | Oct 09 12:17:45 PM UTC 24 |
| Finished | Oct 09 12:17:49 PM UTC 24 |
| Peak memory | 224996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818057176 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstanding.2818057176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.546769646 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 137548597 ps |
| CPU time | 5.23 seconds |
| Started | Oct 09 12:17:43 PM UTC 24 |
| Finished | Oct 09 12:17:49 PM UTC 24 |
| Peak memory | 225344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546769646 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.546769646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.1970655055 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 647432515 ps |
| CPU time | 14.03 seconds |
| Started | Oct 09 12:17:43 PM UTC 24 |
| Finished | Oct 09 12:17:58 PM UTC 24 |
| Peak memory | 227004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970655055 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.1970655055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2728487564 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 38158264 ps |
| CPU time | 2.12 seconds |
| Started | Oct 09 12:17:48 PM UTC 24 |
| Finished | Oct 09 12:17:51 PM UTC 24 |
| Peak memory | 227124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2728487564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2728487564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.2410793735 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 92574319 ps |
| CPU time | 3.35 seconds |
| Started | Oct 09 12:17:46 PM UTC 24 |
| Finished | Oct 09 12:17:51 PM UTC 24 |
| Peak memory | 225192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410793735 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.2410793735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.1256132496 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 12543792 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 12:17:46 PM UTC 24 |
| Finished | Oct 09 12:17:49 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256132496 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.1256132496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1638218557 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 56321529 ps |
| CPU time | 2.47 seconds |
| Started | Oct 09 12:17:46 PM UTC 24 |
| Finished | Oct 09 12:17:50 PM UTC 24 |
| Peak memory | 225208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638218557 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstanding.1638218557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.3042531481 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 555554661 ps |
| CPU time | 5.05 seconds |
| Started | Oct 09 12:17:46 PM UTC 24 |
| Finished | Oct 09 12:17:53 PM UTC 24 |
| Peak memory | 225160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042531481 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.3042531481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.3304276671 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 2600722621 ps |
| CPU time | 21.99 seconds |
| Started | Oct 09 12:17:46 PM UTC 24 |
| Finished | Oct 09 12:18:10 PM UTC 24 |
| Peak memory | 227176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304276671 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.3304276671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4251412992 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 92164990 ps |
| CPU time | 2.39 seconds |
| Started | Oct 09 12:17:50 PM UTC 24 |
| Finished | Oct 09 12:17:54 PM UTC 24 |
| Peak memory | 227048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4251412992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.4251412992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.830245401 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 173297445 ps |
| CPU time | 1.87 seconds |
| Started | Oct 09 12:17:49 PM UTC 24 |
| Finished | Oct 09 12:17:52 PM UTC 24 |
| Peak memory | 223844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830245401 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.830245401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.878743488 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 13638623 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 12:17:49 PM UTC 24 |
| Finished | Oct 09 12:17:51 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878743488 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.878743488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1028112984 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 43375358 ps |
| CPU time | 4 seconds |
| Started | Oct 09 12:17:50 PM UTC 24 |
| Finished | Oct 09 12:17:55 PM UTC 24 |
| Peak memory | 225136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028112984 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstanding.1028112984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.1376096139 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 38906287 ps |
| CPU time | 2.93 seconds |
| Started | Oct 09 12:17:48 PM UTC 24 |
| Finished | Oct 09 12:17:52 PM UTC 24 |
| Peak memory | 227268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376096139 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.1376096139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.4110047121 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 387514064 ps |
| CPU time | 8.61 seconds |
| Started | Oct 09 12:17:49 PM UTC 24 |
| Finished | Oct 09 12:17:59 PM UTC 24 |
| Peak memory | 225080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110047121 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.4110047121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2739652312 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 406226286 ps |
| CPU time | 3.7 seconds |
| Started | Oct 09 12:17:51 PM UTC 24 |
| Finished | Oct 09 12:17:57 PM UTC 24 |
| Peak memory | 229240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2739652312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2739652312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.3895474069 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 58916832 ps |
| CPU time | 1.77 seconds |
| Started | Oct 09 12:17:51 PM UTC 24 |
| Finished | Oct 09 12:17:55 PM UTC 24 |
| Peak memory | 213608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895474069 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.3895474069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.2198446200 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 15287138 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 12:17:51 PM UTC 24 |
| Finished | Oct 09 12:17:54 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198446200 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.2198446200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.963390553 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 321282450 ps |
| CPU time | 4.01 seconds |
| Started | Oct 09 12:17:51 PM UTC 24 |
| Finished | Oct 09 12:17:57 PM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963390553 -assert nopost proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstanding.963390553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.1359008112 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 186210421 ps |
| CPU time | 5.27 seconds |
| Started | Oct 09 12:17:50 PM UTC 24 |
| Finished | Oct 09 12:17:57 PM UTC 24 |
| Peak memory | 225476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359008112 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.1359008112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.1701158204 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 1446893739 ps |
| CPU time | 11.59 seconds |
| Started | Oct 09 12:17:50 PM UTC 24 |
| Finished | Oct 09 12:18:03 PM UTC 24 |
| Peak memory | 227056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701158204 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.1701158204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3763614096 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 39416991 ps |
| CPU time | 2.87 seconds |
| Started | Oct 09 12:17:54 PM UTC 24 |
| Finished | Oct 09 12:17:59 PM UTC 24 |
| Peak memory | 229172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3763614096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3763614096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.2992570712 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 29823153 ps |
| CPU time | 2.67 seconds |
| Started | Oct 09 12:17:53 PM UTC 24 |
| Finished | Oct 09 12:17:57 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992570712 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.2992570712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.3183913682 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 14292026 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 12:17:53 PM UTC 24 |
| Finished | Oct 09 12:17:55 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183913682 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.3183913682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.113813645 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 435259671 ps |
| CPU time | 4.27 seconds |
| Started | Oct 09 12:17:53 PM UTC 24 |
| Finished | Oct 09 12:17:59 PM UTC 24 |
| Peak memory | 225256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113813645 -assert nopost proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstanding.113813645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.1147027880 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 5027817776 ps |
| CPU time | 7.99 seconds |
| Started | Oct 09 12:17:53 PM UTC 24 |
| Finished | Oct 09 12:18:02 PM UTC 24 |
| Peak memory | 227324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147027880 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.1147027880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.4090333398 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 327542335 ps |
| CPU time | 28.73 seconds |
| Started | Oct 09 12:16:54 PM UTC 24 |
| Finished | Oct 09 12:17:25 PM UTC 24 |
| Peak memory | 214756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090333398 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.4090333398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1335840622 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 185830680 ps |
| CPU time | 14.57 seconds |
| Started | Oct 09 12:16:54 PM UTC 24 |
| Finished | Oct 09 12:17:10 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335840622 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.1335840622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1915960742 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 115075257 ps |
| CPU time | 5.35 seconds |
| Started | Oct 09 12:16:57 PM UTC 24 |
| Finished | Oct 09 12:17:03 PM UTC 24 |
| Peak memory | 229372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1915960742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1915960742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.2853052473 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 98543849 ps |
| CPU time | 2.59 seconds |
| Started | Oct 09 12:16:54 PM UTC 24 |
| Finished | Oct 09 12:16:58 PM UTC 24 |
| Peak memory | 225008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853052473 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2853052473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.1028262990 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 18991012 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 12:16:51 PM UTC 24 |
| Finished | Oct 09 12:16:53 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028262990 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1028262990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.3768350792 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 56985236 ps |
| CPU time | 2.52 seconds |
| Started | Oct 09 12:16:52 PM UTC 24 |
| Finished | Oct 09 12:16:56 PM UTC 24 |
| Peak memory | 225316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768350792 -assert nopostp roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.3768350792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.1970649832 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 12131206 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 12:16:51 PM UTC 24 |
| Finished | Oct 09 12:16:53 PM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970649832 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.1970649832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3588748828 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 217024976 ps |
| CPU time | 3.97 seconds |
| Started | Oct 09 12:16:55 PM UTC 24 |
| Finished | Oct 09 12:17:01 PM UTC 24 |
| Peak memory | 224984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588748828 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstanding.3588748828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.1828568533 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 336385836 ps |
| CPU time | 2.91 seconds |
| Started | Oct 09 12:16:49 PM UTC 24 |
| Finished | Oct 09 12:16:53 PM UTC 24 |
| Peak memory | 227324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828568533 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1828568533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.1779209617 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 548565757 ps |
| CPU time | 13.71 seconds |
| Started | Oct 09 12:16:50 PM UTC 24 |
| Finished | Oct 09 12:17:05 PM UTC 24 |
| Peak memory | 225000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779209617 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.1779209617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.3074772514 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 33873942 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 12:17:55 PM UTC 24 |
| Finished | Oct 09 12:17:58 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074772514 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.3074772514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/20.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.3975214405 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 41476314 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 12:17:55 PM UTC 24 |
| Finished | Oct 09 12:17:58 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975214405 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.3975214405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/21.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.4034060744 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 48161676 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 12:17:56 PM UTC 24 |
| Finished | Oct 09 12:17:58 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034060744 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.4034060744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/22.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1515155564 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 18293228 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 12:17:56 PM UTC 24 |
| Finished | Oct 09 12:17:59 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515155564 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.1515155564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/23.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.1900555662 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 39508601 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 12:17:56 PM UTC 24 |
| Finished | Oct 09 12:17:59 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900555662 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.1900555662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/24.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.3745301254 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 17699445 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 12:17:56 PM UTC 24 |
| Finished | Oct 09 12:17:59 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745301254 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.3745301254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/25.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.189125179 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 11158532 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 12:17:58 PM UTC 24 |
| Finished | Oct 09 12:18:00 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189125179 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.189125179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/26.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.2223305728 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 18016090 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 12:17:58 PM UTC 24 |
| Finished | Oct 09 12:18:00 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223305728 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.2223305728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/27.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.2252920804 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 17921664 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 12:17:58 PM UTC 24 |
| Finished | Oct 09 12:18:00 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252920804 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.2252920804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/28.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.2482010767 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 19166026 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 12:17:58 PM UTC 24 |
| Finished | Oct 09 12:18:00 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482010767 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.2482010767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/29.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.1808310692 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 220985492 ps |
| CPU time | 19.22 seconds |
| Started | Oct 09 12:17:05 PM UTC 24 |
| Finished | Oct 09 12:17:25 PM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808310692 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.1808310692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.938374926 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 1952523734 ps |
| CPU time | 29.8 seconds |
| Started | Oct 09 12:17:02 PM UTC 24 |
| Finished | Oct 09 12:17:34 PM UTC 24 |
| Peak memory | 224936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938374926 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.938374926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3372500271 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 59300632 ps |
| CPU time | 1.43 seconds |
| Started | Oct 09 12:17:01 PM UTC 24 |
| Finished | Oct 09 12:17:04 PM UTC 24 |
| Peak memory | 214312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372500271 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.3372500271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.178445662 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 162394204 ps |
| CPU time | 5.48 seconds |
| Started | Oct 09 12:17:05 PM UTC 24 |
| Finished | Oct 09 12:17:11 PM UTC 24 |
| Peak memory | 229372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=178445662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.178445662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.146295584 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 474244559 ps |
| CPU time | 1.77 seconds |
| Started | Oct 09 12:17:01 PM UTC 24 |
| Finished | Oct 09 12:17:04 PM UTC 24 |
| Peak memory | 215652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146295584 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.146295584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.1486546867 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 31710420 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 12:16:58 PM UTC 24 |
| Finished | Oct 09 12:17:00 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486546867 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1486546867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.2926957044 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 154389239 ps |
| CPU time | 2.43 seconds |
| Started | Oct 09 12:17:01 PM UTC 24 |
| Finished | Oct 09 12:17:05 PM UTC 24 |
| Peak memory | 225000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926957044 -assert nopostp roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.2926957044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.3209369215 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 70938867 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 12:16:59 PM UTC 24 |
| Finished | Oct 09 12:17:01 PM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209369215 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.3209369215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4075647097 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 834297899 ps |
| CPU time | 6.05 seconds |
| Started | Oct 09 12:17:05 PM UTC 24 |
| Finished | Oct 09 12:17:12 PM UTC 24 |
| Peak memory | 225048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075647097 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstanding.4075647097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.2985044514 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 287217761 ps |
| CPU time | 7.15 seconds |
| Started | Oct 09 12:16:57 PM UTC 24 |
| Finished | Oct 09 12:17:05 PM UTC 24 |
| Peak memory | 225080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985044514 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2985044514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.2228155305 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 3100688053 ps |
| CPU time | 9.16 seconds |
| Started | Oct 09 12:16:57 PM UTC 24 |
| Finished | Oct 09 12:17:07 PM UTC 24 |
| Peak memory | 227032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228155305 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.2228155305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.573062028 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 56510962 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 12:17:59 PM UTC 24 |
| Finished | Oct 09 12:18:01 PM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573062028 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.573062028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/30.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.188804249 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 63257608 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 12:17:59 PM UTC 24 |
| Finished | Oct 09 12:18:01 PM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188804249 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.188804249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/31.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.3710861003 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 39762835 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 12:17:59 PM UTC 24 |
| Finished | Oct 09 12:18:01 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710861003 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.3710861003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/32.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.2423382086 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 13627566 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 12:17:59 PM UTC 24 |
| Finished | Oct 09 12:18:01 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423382086 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.2423382086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/33.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.3203772112 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 53802478 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 12:17:59 PM UTC 24 |
| Finished | Oct 09 12:18:01 PM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203772112 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.3203772112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/34.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.20677721 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 16612042 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 12:18:00 PM UTC 24 |
| Finished | Oct 09 12:18:02 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20677721 -assert nopostproc +UVM_TESTNAME=spi _device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.20677721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/35.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.2713071585 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 36733378 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 12:18:00 PM UTC 24 |
| Finished | Oct 09 12:18:02 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713071585 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.2713071585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/36.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.3811440654 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 17025851 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 12:18:00 PM UTC 24 |
| Finished | Oct 09 12:18:02 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811440654 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.3811440654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/37.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.163405656 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 25877547 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 12:18:00 PM UTC 24 |
| Finished | Oct 09 12:18:02 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163405656 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.163405656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/38.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.816409137 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 72196451 ps |
| CPU time | 0.96 seconds |
| Started | Oct 09 12:18:00 PM UTC 24 |
| Finished | Oct 09 12:18:02 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816409137 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.816409137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/39.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.2452399612 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 2697369785 ps |
| CPU time | 23.91 seconds |
| Started | Oct 09 12:17:09 PM UTC 24 |
| Finished | Oct 09 12:17:35 PM UTC 24 |
| Peak memory | 225332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452399612 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.2452399612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3620097285 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 369940725 ps |
| CPU time | 28 seconds |
| Started | Oct 09 12:17:09 PM UTC 24 |
| Finished | Oct 09 12:17:39 PM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620097285 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.3620097285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3167584288 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 65961972 ps |
| CPU time | 1.64 seconds |
| Started | Oct 09 12:17:08 PM UTC 24 |
| Finished | Oct 09 12:17:11 PM UTC 24 |
| Peak memory | 225928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167584288 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.3167584288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1638489166 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 51332288 ps |
| CPU time | 2.62 seconds |
| Started | Oct 09 12:17:12 PM UTC 24 |
| Finished | Oct 09 12:17:15 PM UTC 24 |
| Peak memory | 227176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1638489166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1638489166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.1726677113 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 28426434 ps |
| CPU time | 2.51 seconds |
| Started | Oct 09 12:17:09 PM UTC 24 |
| Finished | Oct 09 12:17:13 PM UTC 24 |
| Peak memory | 214956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726677113 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1726677113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.3989459802 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 11794082 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 12:17:06 PM UTC 24 |
| Finished | Oct 09 12:17:08 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989459802 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3989459802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.1044593105 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 37998831 ps |
| CPU time | 1.92 seconds |
| Started | Oct 09 12:17:06 PM UTC 24 |
| Finished | Oct 09 12:17:09 PM UTC 24 |
| Peak memory | 223884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044593105 -assert nopostp roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.1044593105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.2755557124 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 15822622 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 12:17:06 PM UTC 24 |
| Finished | Oct 09 12:17:08 PM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755557124 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.2755557124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.264526729 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 240066715 ps |
| CPU time | 2.6 seconds |
| Started | Oct 09 12:17:11 PM UTC 24 |
| Finished | Oct 09 12:17:14 PM UTC 24 |
| Peak memory | 224992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264526729 -assert nopost proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstanding.264526729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.3709013576 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 531113333 ps |
| CPU time | 4.98 seconds |
| Started | Oct 09 12:17:05 PM UTC 24 |
| Finished | Oct 09 12:17:11 PM UTC 24 |
| Peak memory | 227188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709013576 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3709013576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.2346168269 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 405779439 ps |
| CPU time | 14.33 seconds |
| Started | Oct 09 12:17:05 PM UTC 24 |
| Finished | Oct 09 12:17:21 PM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346168269 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.2346168269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.3150411935 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 31349961 ps |
| CPU time | 1.02 seconds |
| Started | Oct 09 12:18:00 PM UTC 24 |
| Finished | Oct 09 12:18:03 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150411935 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.3150411935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/40.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.517055020 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 11952984 ps |
| CPU time | 0.93 seconds |
| Started | Oct 09 12:18:00 PM UTC 24 |
| Finished | Oct 09 12:18:02 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517055020 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.517055020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/41.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.2146025875 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 16697703 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 12:18:02 PM UTC 24 |
| Finished | Oct 09 12:18:04 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146025875 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.2146025875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/42.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.488629378 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 10658080 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 12:18:02 PM UTC 24 |
| Finished | Oct 09 12:18:04 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488629378 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.488629378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/43.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.1171590513 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 18054491 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 12:18:02 PM UTC 24 |
| Finished | Oct 09 12:18:04 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171590513 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.1171590513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/44.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.3121469545 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 46115973 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 12:18:02 PM UTC 24 |
| Finished | Oct 09 12:18:04 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121469545 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.3121469545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/45.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.3144133159 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 17296451 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 12:18:02 PM UTC 24 |
| Finished | Oct 09 12:18:04 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144133159 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.3144133159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/46.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.1087450567 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 16351310 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 12:18:02 PM UTC 24 |
| Finished | Oct 09 12:18:04 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087450567 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.1087450567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/47.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.1377287702 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 18984577 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 12:18:02 PM UTC 24 |
| Finished | Oct 09 12:18:04 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377287702 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.1377287702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/48.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.714686468 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 13304706 ps |
| CPU time | 0.96 seconds |
| Started | Oct 09 12:18:02 PM UTC 24 |
| Finished | Oct 09 12:18:04 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714686468 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.714686468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/49.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.597281557 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 127353081 ps |
| CPU time | 5.01 seconds |
| Started | Oct 09 12:17:15 PM UTC 24 |
| Finished | Oct 09 12:17:21 PM UTC 24 |
| Peak memory | 229192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=597281557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.597281557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.1881520985 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 321697354 ps |
| CPU time | 2.54 seconds |
| Started | Oct 09 12:17:13 PM UTC 24 |
| Finished | Oct 09 12:17:16 PM UTC 24 |
| Peak memory | 225196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881520985 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1881520985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.1712650778 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 12845762 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 12:17:13 PM UTC 24 |
| Finished | Oct 09 12:17:15 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712650778 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1712650778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2870260626 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 115996975 ps |
| CPU time | 4.88 seconds |
| Started | Oct 09 12:17:14 PM UTC 24 |
| Finished | Oct 09 12:17:20 PM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870260626 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstanding.2870260626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.3559436660 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 156482155 ps |
| CPU time | 2.3 seconds |
| Started | Oct 09 12:17:12 PM UTC 24 |
| Finished | Oct 09 12:17:15 PM UTC 24 |
| Peak memory | 225352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559436660 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3559436660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.404080023 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 2872238090 ps |
| CPU time | 18.66 seconds |
| Started | Oct 09 12:17:12 PM UTC 24 |
| Finished | Oct 09 12:17:32 PM UTC 24 |
| Peak memory | 233356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404080023 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.404080023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.918127739 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 92482777 ps |
| CPU time | 2.76 seconds |
| Started | Oct 09 12:17:18 PM UTC 24 |
| Finished | Oct 09 12:17:22 PM UTC 24 |
| Peak memory | 225276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=918127739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.918127739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.488343800 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 332287554 ps |
| CPU time | 2.97 seconds |
| Started | Oct 09 12:17:17 PM UTC 24 |
| Finished | Oct 09 12:17:21 PM UTC 24 |
| Peak memory | 225028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488343800 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.488343800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.863111018 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 34039905 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 12:17:16 PM UTC 24 |
| Finished | Oct 09 12:17:19 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863111018 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.863111018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1308860293 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 107957751 ps |
| CPU time | 2.6 seconds |
| Started | Oct 09 12:17:18 PM UTC 24 |
| Finished | Oct 09 12:17:21 PM UTC 24 |
| Peak memory | 225200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308860293 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstanding.1308860293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.1087412490 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 502866483 ps |
| CPU time | 3.11 seconds |
| Started | Oct 09 12:17:15 PM UTC 24 |
| Finished | Oct 09 12:17:20 PM UTC 24 |
| Peak memory | 227180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087412490 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1087412490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2655642795 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 104469904 ps |
| CPU time | 3.5 seconds |
| Started | Oct 09 12:17:22 PM UTC 24 |
| Finished | Oct 09 12:17:27 PM UTC 24 |
| Peak memory | 227372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2655642795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2655642795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.2566297224 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 80649987 ps |
| CPU time | 2.97 seconds |
| Started | Oct 09 12:17:21 PM UTC 24 |
| Finished | Oct 09 12:17:25 PM UTC 24 |
| Peak memory | 225144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566297224 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2566297224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.3351897230 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 56554664 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 12:17:21 PM UTC 24 |
| Finished | Oct 09 12:17:23 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351897230 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3351897230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.867264939 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 349787466 ps |
| CPU time | 5.63 seconds |
| Started | Oct 09 12:17:22 PM UTC 24 |
| Finished | Oct 09 12:17:29 PM UTC 24 |
| Peak memory | 225016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867264939 -assert nopost proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstanding.867264939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.1435830974 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 218887802 ps |
| CPU time | 7.01 seconds |
| Started | Oct 09 12:17:20 PM UTC 24 |
| Finished | Oct 09 12:17:28 PM UTC 24 |
| Peak memory | 227260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435830974 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1435830974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.215949613 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 4233741158 ps |
| CPU time | 19.21 seconds |
| Started | Oct 09 12:17:21 PM UTC 24 |
| Finished | Oct 09 12:17:41 PM UTC 24 |
| Peak memory | 225012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215949613 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.215949613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2497434565 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 319693840 ps |
| CPU time | 5.07 seconds |
| Started | Oct 09 12:17:26 PM UTC 24 |
| Finished | Oct 09 12:17:32 PM UTC 24 |
| Peak memory | 228452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2497434565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2497434565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.1541563388 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 94450044 ps |
| CPU time | 3.85 seconds |
| Started | Oct 09 12:17:24 PM UTC 24 |
| Finished | Oct 09 12:17:29 PM UTC 24 |
| Peak memory | 225256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541563388 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1541563388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.720405203 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 12479588 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 12:17:22 PM UTC 24 |
| Finished | Oct 09 12:17:25 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720405203 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.720405203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4088667221 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 163699859 ps |
| CPU time | 5.48 seconds |
| Started | Oct 09 12:17:26 PM UTC 24 |
| Finished | Oct 09 12:17:32 PM UTC 24 |
| Peak memory | 224364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088667221 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstanding.4088667221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.178176947 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 65274931 ps |
| CPU time | 5.58 seconds |
| Started | Oct 09 12:17:22 PM UTC 24 |
| Finished | Oct 09 12:17:29 PM UTC 24 |
| Peak memory | 225152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178176947 -assert nopostproc +UVM_TESTNAME=sp i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.178176947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.3528446457 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 310866515 ps |
| CPU time | 24.82 seconds |
| Started | Oct 09 12:17:22 PM UTC 24 |
| Finished | Oct 09 12:17:48 PM UTC 24 |
| Peak memory | 225064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528446457 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.3528446457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3058896503 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 832522515 ps |
| CPU time | 3.65 seconds |
| Started | Oct 09 12:17:30 PM UTC 24 |
| Finished | Oct 09 12:17:35 PM UTC 24 |
| Peak memory | 227332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3058896503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3058896503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.3883313059 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 69171304 ps |
| CPU time | 2.97 seconds |
| Started | Oct 09 12:17:29 PM UTC 24 |
| Finished | Oct 09 12:17:33 PM UTC 24 |
| Peak memory | 214704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883313059 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3883313059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.1854028604 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 17027352 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 12:17:28 PM UTC 24 |
| Finished | Oct 09 12:17:30 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854028604 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1854028604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.479769291 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 207505880 ps |
| CPU time | 4.51 seconds |
| Started | Oct 09 12:17:30 PM UTC 24 |
| Finished | Oct 09 12:17:36 PM UTC 24 |
| Peak memory | 225072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479769291 -assert nopost proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstanding.479769291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.2493216706 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 24794702 ps |
| CPU time | 1.91 seconds |
| Started | Oct 09 12:17:26 PM UTC 24 |
| Finished | Oct 09 12:17:29 PM UTC 24 |
| Peak memory | 226024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493216706 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2493216706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.2654965931 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 289275496 ps |
| CPU time | 10.69 seconds |
| Started | Oct 09 12:17:27 PM UTC 24 |
| Finished | Oct 09 12:17:39 PM UTC 24 |
| Peak memory | 233244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654965931 -assert nopostproc +UV M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.2654965931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.251879324 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 71785249 ps |
| CPU time | 5.65 seconds |
| Started | Oct 09 03:53:54 PM UTC 24 |
| Finished | Oct 09 03:54:01 PM UTC 24 |
| Peak memory | 245184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251879324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.251879324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.3395767869 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 64606014 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 03:53:23 PM UTC 24 |
| Finished | Oct 09 03:53:26 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395767869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3395767869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.1468956522 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3538550602 ps |
| CPU time | 46.63 seconds |
| Started | Oct 09 03:54:02 PM UTC 24 |
| Finished | Oct 09 03:54:50 PM UTC 24 |
| Peak memory | 247440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468956522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1468956522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.649899116 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 14378522356 ps |
| CPU time | 59.06 seconds |
| Started | Oct 09 03:54:07 PM UTC 24 |
| Finished | Oct 09 03:55:08 PM UTC 24 |
| Peak memory | 245388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649899116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.649899116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.1895763763 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 20894744833 ps |
| CPU time | 63 seconds |
| Started | Oct 09 03:53:52 PM UTC 24 |
| Finished | Oct 09 03:54:57 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895763763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1895763763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.2904679441 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 18605603 ps |
| CPU time | 1.57 seconds |
| Started | Oct 09 03:53:26 PM UTC 24 |
| Finished | Oct 09 03:53:29 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904679441 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_parity.2904679441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.114261137 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 157185209 ps |
| CPU time | 4.73 seconds |
| Started | Oct 09 03:53:46 PM UTC 24 |
| Finished | Oct 09 03:53:52 PM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114261137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.114261137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.1116109403 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2317675689 ps |
| CPU time | 9.78 seconds |
| Started | Oct 09 03:54:01 PM UTC 24 |
| Finished | Oct 09 03:54:12 PM UTC 24 |
| Peak memory | 233648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116109403 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.1116109403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.1348905652 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4083058550 ps |
| CPU time | 14.3 seconds |
| Started | Oct 09 03:53:30 PM UTC 24 |
| Finished | Oct 09 03:53:45 PM UTC 24 |
| Peak memory | 227740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348905652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1348905652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.3732148728 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 11521875 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 03:53:33 PM UTC 24 |
| Finished | Oct 09 03:53:35 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732148728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3732148728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.2349938739 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 12842900 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 03:53:30 PM UTC 24 |
| Finished | Oct 09 03:53:32 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349938739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2349938739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.3123525522 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1038437066 ps |
| CPU time | 12.25 seconds |
| Started | Oct 09 03:53:52 PM UTC 24 |
| Finished | Oct 09 03:54:06 PM UTC 24 |
| Peak memory | 245060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123525522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3123525522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/0.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.936454451 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 13371254 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 03:55:08 PM UTC 24 |
| Finished | Oct 09 03:55:11 PM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936454451 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.936454451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1132541561 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 200946222 ps |
| CPU time | 4.79 seconds |
| Started | Oct 09 03:54:47 PM UTC 24 |
| Finished | Oct 09 03:54:53 PM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132541561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1132541561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.117889166 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 40871309 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 03:54:22 PM UTC 24 |
| Finished | Oct 09 03:54:24 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117889166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.117889166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.697905620 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 2152416751 ps |
| CPU time | 15.9 seconds |
| Started | Oct 09 03:54:50 PM UTC 24 |
| Finished | Oct 09 03:55:07 PM UTC 24 |
| Peak memory | 235152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697905620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.697905620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.1316744586 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 138497757 ps |
| CPU time | 3.36 seconds |
| Started | Oct 09 03:54:38 PM UTC 24 |
| Finished | Oct 09 03:54:42 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316744586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1316744586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.3825405431 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 7337743104 ps |
| CPU time | 63.9 seconds |
| Started | Oct 09 03:54:40 PM UTC 24 |
| Finished | Oct 09 03:55:45 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825405431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3825405431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.338510606 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 26836134 ps |
| CPU time | 1.61 seconds |
| Started | Oct 09 03:54:22 PM UTC 24 |
| Finished | Oct 09 03:54:25 PM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338510606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_parity.338510606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.287005786 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 431016091 ps |
| CPU time | 4.32 seconds |
| Started | Oct 09 03:54:34 PM UTC 24 |
| Finished | Oct 09 03:54:39 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287005786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.287005786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.1957325475 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 29750210 ps |
| CPU time | 3.56 seconds |
| Started | Oct 09 03:54:32 PM UTC 24 |
| Finished | Oct 09 03:54:37 PM UTC 24 |
| Peak memory | 244876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957325475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1957325475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.955923705 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 242267621 ps |
| CPU time | 1.36 seconds |
| Started | Oct 09 03:55:06 PM UTC 24 |
| Finished | Oct 09 03:55:08 PM UTC 24 |
| Peak memory | 257640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955923705 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.955923705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.169795094 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 337054640427 ps |
| CPU time | 1972.46 seconds |
| Started | Oct 09 03:55:06 PM UTC 24 |
| Finished | Oct 09 04:28:22 PM UTC 24 |
| Peak memory | 296708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169795094 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.169795094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.533370925 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 27476428106 ps |
| CPU time | 31.02 seconds |
| Started | Oct 09 03:54:24 PM UTC 24 |
| Finished | Oct 09 03:54:56 PM UTC 24 |
| Peak memory | 227624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533370925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.533370925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.1647224125 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 642641145 ps |
| CPU time | 2.54 seconds |
| Started | Oct 09 03:54:28 PM UTC 24 |
| Finished | Oct 09 03:54:32 PM UTC 24 |
| Peak memory | 227676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647224125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1647224125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.2539781199 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 54745806 ps |
| CPU time | 1.52 seconds |
| Started | Oct 09 03:54:25 PM UTC 24 |
| Finished | Oct 09 03:54:28 PM UTC 24 |
| Peak memory | 214856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539781199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2539781199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/1.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.3808630884 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 22592693 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 04:01:34 PM UTC 24 |
| Finished | Oct 09 04:01:36 PM UTC 24 |
| Peak memory | 214840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808630884 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.3808630884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.3053205034 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 1045181239 ps |
| CPU time | 11.19 seconds |
| Started | Oct 09 04:01:20 PM UTC 24 |
| Finished | Oct 09 04:01:32 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053205034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3053205034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.927531095 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 26082135 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 04:01:00 PM UTC 24 |
| Finished | Oct 09 04:01:02 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927531095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.927531095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.3112030050 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 28932728425 ps |
| CPU time | 14.83 seconds |
| Started | Oct 09 04:01:30 PM UTC 24 |
| Finished | Oct 09 04:01:46 PM UTC 24 |
| Peak memory | 229672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112030050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3112030050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.1025347556 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 3200987366 ps |
| CPU time | 29.38 seconds |
| Started | Oct 09 04:01:32 PM UTC 24 |
| Finished | Oct 09 04:02:02 PM UTC 24 |
| Peak memory | 229920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025347556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.1025347556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.1930065688 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 2294069170 ps |
| CPU time | 47.22 seconds |
| Started | Oct 09 04:01:22 PM UTC 24 |
| Finished | Oct 09 04:02:11 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930065688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1930065688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.2607579992 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 213775890 ps |
| CPU time | 8.67 seconds |
| Started | Oct 09 04:01:14 PM UTC 24 |
| Finished | Oct 09 04:01:24 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607579992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2607579992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.1264489147 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1872511500 ps |
| CPU time | 27.66 seconds |
| Started | Oct 09 04:01:16 PM UTC 24 |
| Finished | Oct 09 04:01:45 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264489147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1264489147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.4264237039 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 32659180 ps |
| CPU time | 1.7 seconds |
| Started | Oct 09 04:01:01 PM UTC 24 |
| Finished | Oct 09 04:01:03 PM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264237039 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mem_parity.4264237039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.4123504204 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 8794224067 ps |
| CPU time | 8.19 seconds |
| Started | Oct 09 04:01:11 PM UTC 24 |
| Finished | Oct 09 04:01:21 PM UTC 24 |
| Peak memory | 251340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123504204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.4123504204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.2795002377 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 535510515 ps |
| CPU time | 12.9 seconds |
| Started | Oct 09 04:01:07 PM UTC 24 |
| Finished | Oct 09 04:01:21 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795002377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2795002377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.1101546727 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 3788905022 ps |
| CPU time | 16.02 seconds |
| Started | Oct 09 04:01:24 PM UTC 24 |
| Finished | Oct 09 04:01:42 PM UTC 24 |
| Peak memory | 233760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101546727 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.1101546727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.4065563064 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 1528164838 ps |
| CPU time | 9.06 seconds |
| Started | Oct 09 04:01:03 PM UTC 24 |
| Finished | Oct 09 04:01:13 PM UTC 24 |
| Peak memory | 227624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065563064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.4065563064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.163233601 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 11929095185 ps |
| CPU time | 15.81 seconds |
| Started | Oct 09 04:01:02 PM UTC 24 |
| Finished | Oct 09 04:01:19 PM UTC 24 |
| Peak memory | 227560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163233601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.163233601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.1175822336 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 112379498 ps |
| CPU time | 2.13 seconds |
| Started | Oct 09 04:01:07 PM UTC 24 |
| Finished | Oct 09 04:01:10 PM UTC 24 |
| Peak memory | 227556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175822336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1175822336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.2185967665 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 68863848 ps |
| CPU time | 1.45 seconds |
| Started | Oct 09 04:01:04 PM UTC 24 |
| Finished | Oct 09 04:01:06 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185967665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2185967665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.1884300737 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 6965054408 ps |
| CPU time | 10.85 seconds |
| Started | Oct 09 04:01:19 PM UTC 24 |
| Finished | Oct 09 04:01:31 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884300737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1884300737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/10.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.3328584714 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 55580299 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 04:02:01 PM UTC 24 |
| Finished | Oct 09 04:02:03 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328584714 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.3328584714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.57869472 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 238155656 ps |
| CPU time | 3.9 seconds |
| Started | Oct 09 04:01:47 PM UTC 24 |
| Finished | Oct 09 04:01:52 PM UTC 24 |
| Peak memory | 235012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57869472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.57869472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.2741595426 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 13021662 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 04:01:37 PM UTC 24 |
| Finished | Oct 09 04:01:39 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741595426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2741595426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.1305938088 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 22232275115 ps |
| CPU time | 270.24 seconds |
| Started | Oct 09 04:01:57 PM UTC 24 |
| Finished | Oct 09 04:06:31 PM UTC 24 |
| Peak memory | 267844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305938088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.1305938088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.3281667787 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 471206358 ps |
| CPU time | 11.71 seconds |
| Started | Oct 09 04:01:49 PM UTC 24 |
| Finished | Oct 09 04:02:02 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281667787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3281667787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.3570072274 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 66326912934 ps |
| CPU time | 240.23 seconds |
| Started | Oct 09 04:01:50 PM UTC 24 |
| Finished | Oct 09 04:05:55 PM UTC 24 |
| Peak memory | 284172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570072274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.3570072274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.2517034393 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 2845506135 ps |
| CPU time | 16.34 seconds |
| Started | Oct 09 04:01:45 PM UTC 24 |
| Finished | Oct 09 04:02:02 PM UTC 24 |
| Peak memory | 245388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517034393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2517034393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.1034716324 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 29728629 ps |
| CPU time | 3.27 seconds |
| Started | Oct 09 04:01:46 PM UTC 24 |
| Finished | Oct 09 04:01:50 PM UTC 24 |
| Peak memory | 244880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034716324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1034716324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.267289663 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 33903216 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 04:01:38 PM UTC 24 |
| Finished | Oct 09 04:01:40 PM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267289663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mem_parity.267289663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.3711118155 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 75421034 ps |
| CPU time | 3.31 seconds |
| Started | Oct 09 04:01:45 PM UTC 24 |
| Finished | Oct 09 04:01:49 PM UTC 24 |
| Peak memory | 244936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711118155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.3711118155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.1215675905 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 160437457 ps |
| CPU time | 2.41 seconds |
| Started | Oct 09 04:01:43 PM UTC 24 |
| Finished | Oct 09 04:01:46 PM UTC 24 |
| Peak memory | 245388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215675905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1215675905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.621730080 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 427240881 ps |
| CPU time | 7.33 seconds |
| Started | Oct 09 04:01:51 PM UTC 24 |
| Finished | Oct 09 04:02:00 PM UTC 24 |
| Peak memory | 231460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621730080 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.621730080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.785419207 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 285801947744 ps |
| CPU time | 462.31 seconds |
| Started | Oct 09 04:01:59 PM UTC 24 |
| Finished | Oct 09 04:09:47 PM UTC 24 |
| Peak memory | 278156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785419207 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.785419207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.1521000557 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 2357449157 ps |
| CPU time | 13.73 seconds |
| Started | Oct 09 04:01:41 PM UTC 24 |
| Finished | Oct 09 04:01:56 PM UTC 24 |
| Peak memory | 227752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521000557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1521000557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3374925155 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 357597165 ps |
| CPU time | 2.67 seconds |
| Started | Oct 09 04:01:40 PM UTC 24 |
| Finished | Oct 09 04:01:44 PM UTC 24 |
| Peak memory | 217184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374925155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3374925155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.359798616 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 160591097 ps |
| CPU time | 4.6 seconds |
| Started | Oct 09 04:01:42 PM UTC 24 |
| Finished | Oct 09 04:01:48 PM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359798616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.359798616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.2895619766 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 54282433 ps |
| CPU time | 1.3 seconds |
| Started | Oct 09 04:01:41 PM UTC 24 |
| Finished | Oct 09 04:01:44 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895619766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2895619766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.2062434826 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 1876871021 ps |
| CPU time | 9.92 seconds |
| Started | Oct 09 04:01:47 PM UTC 24 |
| Finished | Oct 09 04:01:58 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062434826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2062434826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/11.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.1345055924 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 37897287 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 04:02:37 PM UTC 24 |
| Finished | Oct 09 04:02:39 PM UTC 24 |
| Peak memory | 214840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345055924 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.1345055924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.2646601688 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 2186729645 ps |
| CPU time | 7.42 seconds |
| Started | Oct 09 04:02:17 PM UTC 24 |
| Finished | Oct 09 04:02:26 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646601688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2646601688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.76562298 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 55439331 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 04:02:03 PM UTC 24 |
| Finished | Oct 09 04:02:05 PM UTC 24 |
| Peak memory | 214856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76562298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.76562298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_all.71202303 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 31354686872 ps |
| CPU time | 95.84 seconds |
| Started | Oct 09 04:02:27 PM UTC 24 |
| Finished | Oct 09 04:04:05 PM UTC 24 |
| Peak memory | 261704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71202303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.71202303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.2864611662 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 57990985701 ps |
| CPU time | 117.13 seconds |
| Started | Oct 09 04:02:27 PM UTC 24 |
| Finished | Oct 09 04:04:26 PM UTC 24 |
| Peak memory | 261704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864611662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2864611662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.2156668074 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 4041335249 ps |
| CPU time | 108.44 seconds |
| Started | Oct 09 04:02:27 PM UTC 24 |
| Finished | Oct 09 04:04:18 PM UTC 24 |
| Peak memory | 274056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156668074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.2156668074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.58549682 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 163508527 ps |
| CPU time | 6.39 seconds |
| Started | Oct 09 04:02:18 PM UTC 24 |
| Finished | Oct 09 04:02:26 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58549682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.58549682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.936143125 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 8393184615 ps |
| CPU time | 48.31 seconds |
| Started | Oct 09 04:02:19 PM UTC 24 |
| Finished | Oct 09 04:03:08 PM UTC 24 |
| Peak memory | 261776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936143125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.936143125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.3150753758 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 457703238 ps |
| CPU time | 5.3 seconds |
| Started | Oct 09 04:02:11 PM UTC 24 |
| Finished | Oct 09 04:02:18 PM UTC 24 |
| Peak memory | 242088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150753758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3150753758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.2037377284 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 11258492138 ps |
| CPU time | 141.35 seconds |
| Started | Oct 09 04:02:12 PM UTC 24 |
| Finished | Oct 09 04:04:36 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037377284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2037377284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.1097616505 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 121239522 ps |
| CPU time | 1.56 seconds |
| Started | Oct 09 04:02:03 PM UTC 24 |
| Finished | Oct 09 04:02:06 PM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097616505 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mem_parity.1097616505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.2879960101 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 255896273 ps |
| CPU time | 6.44 seconds |
| Started | Oct 09 04:02:10 PM UTC 24 |
| Finished | Oct 09 04:02:18 PM UTC 24 |
| Peak memory | 235036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879960101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.2879960101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1545052469 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1194516040 ps |
| CPU time | 7.07 seconds |
| Started | Oct 09 04:02:07 PM UTC 24 |
| Finished | Oct 09 04:02:15 PM UTC 24 |
| Peak memory | 245388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545052469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1545052469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.1265356881 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 8460292147 ps |
| CPU time | 26.45 seconds |
| Started | Oct 09 04:02:23 PM UTC 24 |
| Finished | Oct 09 04:02:51 PM UTC 24 |
| Peak memory | 231460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265356881 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.1265356881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.4128034345 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 42340834545 ps |
| CPU time | 133.29 seconds |
| Started | Oct 09 04:02:36 PM UTC 24 |
| Finished | Oct 09 04:04:52 PM UTC 24 |
| Peak memory | 249428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128034345 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.4128034345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.815689334 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 3662749815 ps |
| CPU time | 30.26 seconds |
| Started | Oct 09 04:02:04 PM UTC 24 |
| Finished | Oct 09 04:02:36 PM UTC 24 |
| Peak memory | 231776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815689334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.815689334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.4021669869 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 11789557 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 04:02:03 PM UTC 24 |
| Finished | Oct 09 04:02:05 PM UTC 24 |
| Peak memory | 214856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021669869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.4021669869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.440769344 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 41218211 ps |
| CPU time | 1.45 seconds |
| Started | Oct 09 04:02:07 PM UTC 24 |
| Finished | Oct 09 04:02:09 PM UTC 24 |
| Peak memory | 214976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440769344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.440769344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.2490476350 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 118746642 ps |
| CPU time | 1.39 seconds |
| Started | Oct 09 04:02:07 PM UTC 24 |
| Finished | Oct 09 04:02:09 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490476350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2490476350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.3770796640 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 2070371693 ps |
| CPU time | 4.13 seconds |
| Started | Oct 09 04:02:16 PM UTC 24 |
| Finished | Oct 09 04:02:21 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770796640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3770796640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/12.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_alert_test.3880570049 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 13333276 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 04:03:21 PM UTC 24 |
| Finished | Oct 09 04:03:24 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880570049 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.3880570049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_cfg_cmd.1153019150 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 285509306 ps |
| CPU time | 6.77 seconds |
| Started | Oct 09 04:03:02 PM UTC 24 |
| Finished | Oct 09 04:03:10 PM UTC 24 |
| Peak memory | 235088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153019150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1153019150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.607221104 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 17595984 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 04:02:40 PM UTC 24 |
| Finished | Oct 09 04:02:43 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607221104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.607221104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.1551282296 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 88798929874 ps |
| CPU time | 363.21 seconds |
| Started | Oct 09 04:03:10 PM UTC 24 |
| Finished | Oct 09 04:09:18 PM UTC 24 |
| Peak memory | 276180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551282296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1551282296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.1942815459 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 8242363524 ps |
| CPU time | 138.12 seconds |
| Started | Oct 09 04:03:11 PM UTC 24 |
| Finished | Oct 09 04:05:32 PM UTC 24 |
| Peak memory | 278144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942815459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1942815459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode.1696646429 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 771013168 ps |
| CPU time | 26.69 seconds |
| Started | Oct 09 04:03:04 PM UTC 24 |
| Finished | Oct 09 04:03:32 PM UTC 24 |
| Peak memory | 263628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696646429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1696646429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.2163492250 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 998001153 ps |
| CPU time | 34.78 seconds |
| Started | Oct 09 04:03:09 PM UTC 24 |
| Finished | Oct 09 04:03:45 PM UTC 24 |
| Peak memory | 261640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163492250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.2163492250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_intercept.3509509645 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 274392752 ps |
| CPU time | 5.33 seconds |
| Started | Oct 09 04:02:51 PM UTC 24 |
| Finished | Oct 09 04:02:58 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509509645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3509509645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mailbox.438008428 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 3059564963 ps |
| CPU time | 36.36 seconds |
| Started | Oct 09 04:02:54 PM UTC 24 |
| Finished | Oct 09 04:03:32 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438008428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.438008428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.1063861816 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 40775246 ps |
| CPU time | 1.61 seconds |
| Started | Oct 09 04:02:43 PM UTC 24 |
| Finished | Oct 09 04:02:46 PM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063861816 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mem_parity.1063861816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.3579967906 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 4908824033 ps |
| CPU time | 15.79 seconds |
| Started | Oct 09 04:02:51 PM UTC 24 |
| Finished | Oct 09 04:03:08 PM UTC 24 |
| Peak memory | 235088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579967906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.3579967906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.1565235935 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 57158004 ps |
| CPU time | 3.79 seconds |
| Started | Oct 09 04:02:49 PM UTC 24 |
| Finished | Oct 09 04:02:54 PM UTC 24 |
| Peak memory | 234952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565235935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1565235935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.1713910213 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 590077115 ps |
| CPU time | 11.51 seconds |
| Started | Oct 09 04:03:09 PM UTC 24 |
| Finished | Oct 09 04:03:21 PM UTC 24 |
| Peak memory | 231400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713910213 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.1713910213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.2016355638 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 249984092711 ps |
| CPU time | 583.38 seconds |
| Started | Oct 09 04:03:20 PM UTC 24 |
| Finished | Oct 09 04:13:11 PM UTC 24 |
| Peak memory | 265860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016355638 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.2016355638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_all.1399033559 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 3533649190 ps |
| CPU time | 25.92 seconds |
| Started | Oct 09 04:02:46 PM UTC 24 |
| Finished | Oct 09 04:03:13 PM UTC 24 |
| Peak memory | 227752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399033559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1399033559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.1799441247 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 4289455031 ps |
| CPU time | 16.66 seconds |
| Started | Oct 09 04:02:45 PM UTC 24 |
| Finished | Oct 09 04:03:02 PM UTC 24 |
| Peak memory | 227808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799441247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1799441247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.1231846673 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 61873225 ps |
| CPU time | 2.08 seconds |
| Started | Oct 09 04:02:47 PM UTC 24 |
| Finished | Oct 09 04:02:50 PM UTC 24 |
| Peak memory | 217384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231846673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1231846673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.3754501094 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 103481727 ps |
| CPU time | 1.52 seconds |
| Started | Oct 09 04:02:46 PM UTC 24 |
| Finished | Oct 09 04:02:48 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754501094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3754501094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_upload.1745183419 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 8613877937 ps |
| CPU time | 20.35 seconds |
| Started | Oct 09 04:02:58 PM UTC 24 |
| Finished | Oct 09 04:03:20 PM UTC 24 |
| Peak memory | 235212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745183419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1745183419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/13.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_alert_test.460343374 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 21942707 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 04:04:05 PM UTC 24 |
| Finished | Oct 09 04:04:07 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460343374 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.460343374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_cfg_cmd.2578399320 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 105998114 ps |
| CPU time | 3.24 seconds |
| Started | Oct 09 04:03:43 PM UTC 24 |
| Finished | Oct 09 04:03:47 PM UTC 24 |
| Peak memory | 245140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578399320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2578399320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_csb_read.2373180969 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 15522700 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 04:03:23 PM UTC 24 |
| Finished | Oct 09 04:03:25 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373180969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2373180969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_all.4127573278 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 4992506191 ps |
| CPU time | 87.49 seconds |
| Started | Oct 09 04:03:56 PM UTC 24 |
| Finished | Oct 09 04:05:26 PM UTC 24 |
| Peak memory | 276112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127573278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.4127573278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.1092774109 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 250048701924 ps |
| CPU time | 377.42 seconds |
| Started | Oct 09 04:04:00 PM UTC 24 |
| Finished | Oct 09 04:10:22 PM UTC 24 |
| Peak memory | 278152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092774109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1092774109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.1086934417 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 32824438593 ps |
| CPU time | 145.22 seconds |
| Started | Oct 09 04:04:00 PM UTC 24 |
| Finished | Oct 09 04:06:28 PM UTC 24 |
| Peak memory | 278340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086934417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.1086934417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode.1833885805 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 693459691 ps |
| CPU time | 7.33 seconds |
| Started | Oct 09 04:03:46 PM UTC 24 |
| Finished | Oct 09 04:03:55 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833885805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1833885805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.2304677309 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 12223800357 ps |
| CPU time | 84.54 seconds |
| Started | Oct 09 04:03:48 PM UTC 24 |
| Finished | Oct 09 04:05:15 PM UTC 24 |
| Peak memory | 261640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304677309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.2304677309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_intercept.2343176476 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 61572505 ps |
| CPU time | 3.42 seconds |
| Started | Oct 09 04:03:36 PM UTC 24 |
| Finished | Oct 09 04:03:41 PM UTC 24 |
| Peak memory | 244872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343176476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2343176476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mailbox.2521771557 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 51180318700 ps |
| CPU time | 77.52 seconds |
| Started | Oct 09 04:03:41 PM UTC 24 |
| Finished | Oct 09 04:05:00 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521771557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2521771557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mem_parity.600915284 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 15013598 ps |
| CPU time | 1.54 seconds |
| Started | Oct 09 04:03:25 PM UTC 24 |
| Finished | Oct 09 04:03:28 PM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600915284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mem_parity.600915284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.2727120007 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 176881105 ps |
| CPU time | 3.99 seconds |
| Started | Oct 09 04:03:36 PM UTC 24 |
| Finished | Oct 09 04:03:41 PM UTC 24 |
| Peak memory | 234488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727120007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.2727120007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.2483898179 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 4204157531 ps |
| CPU time | 22.85 seconds |
| Started | Oct 09 04:03:34 PM UTC 24 |
| Finished | Oct 09 04:03:59 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483898179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2483898179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.1374510977 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 1382144835 ps |
| CPU time | 7.97 seconds |
| Started | Oct 09 04:03:55 PM UTC 24 |
| Finished | Oct 09 04:04:04 PM UTC 24 |
| Peak memory | 231396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374510977 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.1374510977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.2477739168 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 7118275595 ps |
| CPU time | 71.52 seconds |
| Started | Oct 09 04:04:01 PM UTC 24 |
| Finished | Oct 09 04:05:15 PM UTC 24 |
| Peak memory | 247372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477739168 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.2477739168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_all.2264989488 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 91523844550 ps |
| CPU time | 54.66 seconds |
| Started | Oct 09 04:03:29 PM UTC 24 |
| Finished | Oct 09 04:04:25 PM UTC 24 |
| Peak memory | 227740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264989488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2264989488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.312193984 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 3802607262 ps |
| CPU time | 13.09 seconds |
| Started | Oct 09 04:03:26 PM UTC 24 |
| Finished | Oct 09 04:03:40 PM UTC 24 |
| Peak memory | 227760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312193984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.312193984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_rw.3379578901 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 22875699 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 04:03:33 PM UTC 24 |
| Finished | Oct 09 04:03:35 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379578901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3379578901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.2954221996 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 36112739 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 04:03:33 PM UTC 24 |
| Finished | Oct 09 04:03:36 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954221996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2954221996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_upload.1874653471 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 2532259557 ps |
| CPU time | 16.21 seconds |
| Started | Oct 09 04:03:42 PM UTC 24 |
| Finished | Oct 09 04:03:59 PM UTC 24 |
| Peak memory | 233772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874653471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1874653471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/14.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_alert_test.3203921519 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 13224969 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 04:04:52 PM UTC 24 |
| Finished | Oct 09 04:04:54 PM UTC 24 |
| Peak memory | 214840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203921519 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.3203921519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_cfg_cmd.762430790 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 7214590411 ps |
| CPU time | 15.85 seconds |
| Started | Oct 09 04:04:31 PM UTC 24 |
| Finished | Oct 09 04:04:48 PM UTC 24 |
| Peak memory | 235076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762430790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.762430790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_csb_read.693654655 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 45113043 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 04:04:06 PM UTC 24 |
| Finished | Oct 09 04:04:09 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693654655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.693654655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_all.3423609030 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 10966654258 ps |
| CPU time | 116.16 seconds |
| Started | Oct 09 04:04:37 PM UTC 24 |
| Finished | Oct 09 04:06:36 PM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423609030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3423609030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.1323022664 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 68136338649 ps |
| CPU time | 126.56 seconds |
| Started | Oct 09 04:04:44 PM UTC 24 |
| Finished | Oct 09 04:06:54 PM UTC 24 |
| Peak memory | 267848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323022664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1323022664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode.1750074320 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 4869463300 ps |
| CPU time | 20.5 seconds |
| Started | Oct 09 04:04:33 PM UTC 24 |
| Finished | Oct 09 04:04:55 PM UTC 24 |
| Peak memory | 261720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750074320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1750074320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.3082153309 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 8218863019 ps |
| CPU time | 56.89 seconds |
| Started | Oct 09 04:04:35 PM UTC 24 |
| Finished | Oct 09 04:05:34 PM UTC 24 |
| Peak memory | 263756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082153309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.3082153309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_intercept.3565930213 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 2378886935 ps |
| CPU time | 11.01 seconds |
| Started | Oct 09 04:04:19 PM UTC 24 |
| Finished | Oct 09 04:04:32 PM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565930213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3565930213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mailbox.867787769 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 3910912793 ps |
| CPU time | 37.34 seconds |
| Started | Oct 09 04:04:26 PM UTC 24 |
| Finished | Oct 09 04:05:05 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867787769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.867787769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mem_parity.3355657873 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 145675462 ps |
| CPU time | 1.57 seconds |
| Started | Oct 09 04:04:07 PM UTC 24 |
| Finished | Oct 09 04:04:10 PM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355657873 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mem_parity.3355657873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.429372955 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 4445389959 ps |
| CPU time | 14.24 seconds |
| Started | Oct 09 04:04:18 PM UTC 24 |
| Finished | Oct 09 04:04:34 PM UTC 24 |
| Peak memory | 245392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429372955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.429372955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.306178897 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 60732286999 ps |
| CPU time | 35.28 seconds |
| Started | Oct 09 04:04:14 PM UTC 24 |
| Finished | Oct 09 04:04:51 PM UTC 24 |
| Peak memory | 245332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306178897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.306178897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.1976738687 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 192653621 ps |
| CPU time | 6 seconds |
| Started | Oct 09 04:04:36 PM UTC 24 |
| Finished | Oct 09 04:04:43 PM UTC 24 |
| Peak memory | 233768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976738687 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.1976738687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_stress_all.3790550103 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 44081561 ps |
| CPU time | 1.51 seconds |
| Started | Oct 09 04:04:49 PM UTC 24 |
| Finished | Oct 09 04:04:51 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790550103 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.3790550103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_all.570379726 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 5024643998 ps |
| CPU time | 32.48 seconds |
| Started | Oct 09 04:04:10 PM UTC 24 |
| Finished | Oct 09 04:04:44 PM UTC 24 |
| Peak memory | 227616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570379726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.570379726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.2312946026 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 3612360189 ps |
| CPU time | 19.56 seconds |
| Started | Oct 09 04:04:09 PM UTC 24 |
| Finished | Oct 09 04:04:29 PM UTC 24 |
| Peak memory | 227680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312946026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2312946026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_rw.2489358838 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 187284578 ps |
| CPU time | 5.55 seconds |
| Started | Oct 09 04:04:12 PM UTC 24 |
| Finished | Oct 09 04:04:19 PM UTC 24 |
| Peak memory | 227688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489358838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2489358838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.1589636309 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 107920868 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 04:04:11 PM UTC 24 |
| Finished | Oct 09 04:04:13 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589636309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1589636309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_upload.632209206 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 443004091 ps |
| CPU time | 6.24 seconds |
| Started | Oct 09 04:04:28 PM UTC 24 |
| Finished | Oct 09 04:04:35 PM UTC 24 |
| Peak memory | 235004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632209206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.632209206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/15.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_alert_test.3851812874 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 24561284 ps |
| CPU time | 0.96 seconds |
| Started | Oct 09 04:05:14 PM UTC 24 |
| Finished | Oct 09 04:05:16 PM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851812874 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.3851812874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_cfg_cmd.3000213495 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 3236657611 ps |
| CPU time | 9.52 seconds |
| Started | Oct 09 04:05:07 PM UTC 24 |
| Finished | Oct 09 04:05:18 PM UTC 24 |
| Peak memory | 235084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000213495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3000213495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_csb_read.1933122922 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 46923791 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 04:04:52 PM UTC 24 |
| Finished | Oct 09 04:04:55 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933122922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1933122922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_all.2260261942 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 865445418 ps |
| CPU time | 27.27 seconds |
| Started | Oct 09 04:05:11 PM UTC 24 |
| Finished | Oct 09 04:05:40 PM UTC 24 |
| Peak memory | 245392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260261942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2260261942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.2500158839 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 208879951903 ps |
| CPU time | 137.26 seconds |
| Started | Oct 09 04:05:12 PM UTC 24 |
| Finished | Oct 09 04:07:32 PM UTC 24 |
| Peak memory | 263760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500158839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2500158839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2466254666 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 19672067538 ps |
| CPU time | 113.11 seconds |
| Started | Oct 09 04:05:12 PM UTC 24 |
| Finished | Oct 09 04:07:08 PM UTC 24 |
| Peak memory | 263816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466254666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.2466254666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode.343632628 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 60159905 ps |
| CPU time | 3.21 seconds |
| Started | Oct 09 04:05:07 PM UTC 24 |
| Finished | Oct 09 04:05:11 PM UTC 24 |
| Peak memory | 245188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343632628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.343632628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.1159673226 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 18867894 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 04:05:08 PM UTC 24 |
| Finished | Oct 09 04:05:10 PM UTC 24 |
| Peak memory | 225964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159673226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.1159673226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_intercept.4123186011 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 429749439 ps |
| CPU time | 5.73 seconds |
| Started | Oct 09 04:05:00 PM UTC 24 |
| Finished | Oct 09 04:05:07 PM UTC 24 |
| Peak memory | 235148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123186011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4123186011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mailbox.2514871560 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 867214752 ps |
| CPU time | 7.93 seconds |
| Started | Oct 09 04:05:00 PM UTC 24 |
| Finished | Oct 09 04:05:09 PM UTC 24 |
| Peak memory | 245256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514871560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2514871560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mem_parity.11043559 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 98982893 ps |
| CPU time | 1.73 seconds |
| Started | Oct 09 04:04:53 PM UTC 24 |
| Finished | Oct 09 04:04:56 PM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11043559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mem_parity.11043559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.1811392601 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2847582606 ps |
| CPU time | 14.23 seconds |
| Started | Oct 09 04:04:59 PM UTC 24 |
| Finished | Oct 09 04:05:14 PM UTC 24 |
| Peak memory | 251596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811392601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.1811392601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.523877074 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 994884165 ps |
| CPU time | 12.06 seconds |
| Started | Oct 09 04:04:59 PM UTC 24 |
| Finished | Oct 09 04:05:12 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523877074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.523877074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.1684471910 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 1221923849 ps |
| CPU time | 18.7 seconds |
| Started | Oct 09 04:05:10 PM UTC 24 |
| Finished | Oct 09 04:05:30 PM UTC 24 |
| Peak memory | 233568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684471910 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.1684471910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.282993567 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 33241299309 ps |
| CPU time | 434.73 seconds |
| Started | Oct 09 04:05:14 PM UTC 24 |
| Finished | Oct 09 04:12:34 PM UTC 24 |
| Peak memory | 284296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282993567 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.282993567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_all.2768248241 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 11896277 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 04:04:55 PM UTC 24 |
| Finished | Oct 09 04:04:58 PM UTC 24 |
| Peak memory | 214856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768248241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2768248241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.2265303770 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 10055873062 ps |
| CPU time | 33.25 seconds |
| Started | Oct 09 04:04:55 PM UTC 24 |
| Finished | Oct 09 04:05:30 PM UTC 24 |
| Peak memory | 227876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265303770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2265303770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_rw.1476775323 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 37098829 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 04:04:57 PM UTC 24 |
| Finished | Oct 09 04:04:59 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476775323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1476775323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.1780027219 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 19420098 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 04:04:55 PM UTC 24 |
| Finished | Oct 09 04:04:58 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780027219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1780027219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_upload.2866470154 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1474127094 ps |
| CPU time | 12.44 seconds |
| Started | Oct 09 04:05:01 PM UTC 24 |
| Finished | Oct 09 04:05:15 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866470154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2866470154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/16.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_alert_test.3391302990 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 21350236 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 04:05:35 PM UTC 24 |
| Finished | Oct 09 04:05:37 PM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391302990 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.3391302990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_cfg_cmd.2959324319 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 516673361 ps |
| CPU time | 3.24 seconds |
| Started | Oct 09 04:05:26 PM UTC 24 |
| Finished | Oct 09 04:05:30 PM UTC 24 |
| Peak memory | 233692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959324319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2959324319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_csb_read.4145946995 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 79805887 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 04:05:15 PM UTC 24 |
| Finished | Oct 09 04:05:17 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145946995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.4145946995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_all.561440012 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 7600904746 ps |
| CPU time | 92.36 seconds |
| Started | Oct 09 04:05:31 PM UTC 24 |
| Finished | Oct 09 04:07:06 PM UTC 24 |
| Peak memory | 278036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561440012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.561440012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.2549242520 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 2744909941 ps |
| CPU time | 44.78 seconds |
| Started | Oct 09 04:05:32 PM UTC 24 |
| Finished | Oct 09 04:06:18 PM UTC 24 |
| Peak memory | 263752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549242520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2549242520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode.2572001104 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 967983375 ps |
| CPU time | 15.85 seconds |
| Started | Oct 09 04:05:27 PM UTC 24 |
| Finished | Oct 09 04:05:44 PM UTC 24 |
| Peak memory | 235096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572001104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2572001104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_intercept.3075176879 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 150314980 ps |
| CPU time | 3.36 seconds |
| Started | Oct 09 04:05:20 PM UTC 24 |
| Finished | Oct 09 04:05:24 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075176879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3075176879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mailbox.2391466026 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 2900400110 ps |
| CPU time | 28.06 seconds |
| Started | Oct 09 04:05:23 PM UTC 24 |
| Finished | Oct 09 04:05:52 PM UTC 24 |
| Peak memory | 261640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391466026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2391466026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mem_parity.3509841922 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 198479065 ps |
| CPU time | 1.57 seconds |
| Started | Oct 09 04:05:16 PM UTC 24 |
| Finished | Oct 09 04:05:18 PM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509841922 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mem_parity.3509841922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.3817354475 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 17786894624 ps |
| CPU time | 35.05 seconds |
| Started | Oct 09 04:05:19 PM UTC 24 |
| Finished | Oct 09 04:05:56 PM UTC 24 |
| Peak memory | 261644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817354475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.3817354475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.3464189501 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 1192987461 ps |
| CPU time | 5.76 seconds |
| Started | Oct 09 04:05:18 PM UTC 24 |
| Finished | Oct 09 04:05:25 PM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464189501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3464189501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.750091477 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 408059813 ps |
| CPU time | 11.67 seconds |
| Started | Oct 09 04:05:27 PM UTC 24 |
| Finished | Oct 09 04:05:40 PM UTC 24 |
| Peak memory | 233696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750091477 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.750091477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_all.618121334 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 6689201540 ps |
| CPU time | 8.49 seconds |
| Started | Oct 09 04:05:16 PM UTC 24 |
| Finished | Oct 09 04:05:26 PM UTC 24 |
| Peak memory | 227680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618121334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.618121334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.1614198354 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 1729962400 ps |
| CPU time | 8.99 seconds |
| Started | Oct 09 04:05:16 PM UTC 24 |
| Finished | Oct 09 04:05:26 PM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614198354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1614198354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_rw.243003544 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 502880108 ps |
| CPU time | 3.9 seconds |
| Started | Oct 09 04:05:17 PM UTC 24 |
| Finished | Oct 09 04:05:22 PM UTC 24 |
| Peak memory | 227556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243003544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.243003544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.3252682470 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 56674595 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 04:05:16 PM UTC 24 |
| Finished | Oct 09 04:05:18 PM UTC 24 |
| Peak memory | 214856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252682470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3252682470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_upload.3781443021 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 1741283991 ps |
| CPU time | 10.26 seconds |
| Started | Oct 09 04:05:25 PM UTC 24 |
| Finished | Oct 09 04:05:36 PM UTC 24 |
| Peak memory | 245396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781443021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3781443021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/17.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_alert_test.1551283126 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 28815036 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 04:06:00 PM UTC 24 |
| Finished | Oct 09 04:06:02 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551283126 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.1551283126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_cfg_cmd.2721251215 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1190326962 ps |
| CPU time | 8.12 seconds |
| Started | Oct 09 04:05:50 PM UTC 24 |
| Finished | Oct 09 04:06:00 PM UTC 24 |
| Peak memory | 234968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721251215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2721251215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_csb_read.540623402 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 85601130 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 04:05:37 PM UTC 24 |
| Finished | Oct 09 04:05:39 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540623402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.540623402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_all.1053493280 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 7665814010 ps |
| CPU time | 74.96 seconds |
| Started | Oct 09 04:05:56 PM UTC 24 |
| Finished | Oct 09 04:07:13 PM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053493280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1053493280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.3853114162 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 9868020199 ps |
| CPU time | 149.3 seconds |
| Started | Oct 09 04:05:57 PM UTC 24 |
| Finished | Oct 09 04:08:29 PM UTC 24 |
| Peak memory | 278148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853114162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3853114162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.451292337 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 203222197811 ps |
| CPU time | 521.58 seconds |
| Started | Oct 09 04:05:57 PM UTC 24 |
| Finished | Oct 09 04:14:45 PM UTC 24 |
| Peak memory | 267852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451292337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.451292337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode.1095596810 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 3968821078 ps |
| CPU time | 65.66 seconds |
| Started | Oct 09 04:05:52 PM UTC 24 |
| Finished | Oct 09 04:07:00 PM UTC 24 |
| Peak memory | 245456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095596810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1095596810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.3234551614 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 4968357140 ps |
| CPU time | 56.62 seconds |
| Started | Oct 09 04:05:54 PM UTC 24 |
| Finished | Oct 09 04:06:52 PM UTC 24 |
| Peak memory | 261644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234551614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.3234551614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_intercept.560072769 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 69234300 ps |
| CPU time | 3.05 seconds |
| Started | Oct 09 04:05:45 PM UTC 24 |
| Finished | Oct 09 04:05:49 PM UTC 24 |
| Peak memory | 234680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560072769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.560072769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mailbox.3921824718 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 13567291052 ps |
| CPU time | 45.41 seconds |
| Started | Oct 09 04:05:45 PM UTC 24 |
| Finished | Oct 09 04:06:32 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921824718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3921824718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mem_parity.3958083976 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 341463903 ps |
| CPU time | 1.55 seconds |
| Started | Oct 09 04:05:38 PM UTC 24 |
| Finished | Oct 09 04:05:41 PM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958083976 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mem_parity.3958083976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.232503583 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 15691768367 ps |
| CPU time | 29.1 seconds |
| Started | Oct 09 04:05:45 PM UTC 24 |
| Finished | Oct 09 04:06:15 PM UTC 24 |
| Peak memory | 245396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232503583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.232503583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.2380568148 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1833044991 ps |
| CPU time | 18.25 seconds |
| Started | Oct 09 04:05:45 PM UTC 24 |
| Finished | Oct 09 04:06:04 PM UTC 24 |
| Peak memory | 261772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380568148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2380568148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.145431273 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1038140919 ps |
| CPU time | 5.11 seconds |
| Started | Oct 09 04:05:54 PM UTC 24 |
| Finished | Oct 09 04:06:00 PM UTC 24 |
| Peak memory | 231516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145431273 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.145431273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.2988468643 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 116264221 ps |
| CPU time | 1.44 seconds |
| Started | Oct 09 04:06:00 PM UTC 24 |
| Finished | Oct 09 04:06:03 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988468643 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.2988468643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_all.3811798455 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 11912289867 ps |
| CPU time | 21.89 seconds |
| Started | Oct 09 04:05:40 PM UTC 24 |
| Finished | Oct 09 04:06:04 PM UTC 24 |
| Peak memory | 227688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811798455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3811798455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.863915313 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 2505885828 ps |
| CPU time | 10.53 seconds |
| Started | Oct 09 04:05:40 PM UTC 24 |
| Finished | Oct 09 04:05:52 PM UTC 24 |
| Peak memory | 227568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863915313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.863915313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_rw.1899293126 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 11390145 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 04:05:42 PM UTC 24 |
| Finished | Oct 09 04:05:44 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899293126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1899293126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.3501507018 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 199010917 ps |
| CPU time | 1.69 seconds |
| Started | Oct 09 04:05:42 PM UTC 24 |
| Finished | Oct 09 04:05:44 PM UTC 24 |
| Peak memory | 214860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501507018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3501507018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_upload.3576452998 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 3032392575 ps |
| CPU time | 8.21 seconds |
| Started | Oct 09 04:05:46 PM UTC 24 |
| Finished | Oct 09 04:05:56 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576452998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3576452998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/18.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_alert_test.3058301601 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 47478538 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 04:06:21 PM UTC 24 |
| Finished | Oct 09 04:06:24 PM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058301601 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.3058301601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_cfg_cmd.3830043599 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 6399324440 ps |
| CPU time | 24.77 seconds |
| Started | Oct 09 04:06:11 PM UTC 24 |
| Finished | Oct 09 04:06:37 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830043599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3830043599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_csb_read.778846921 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 16284699 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 04:06:00 PM UTC 24 |
| Finished | Oct 09 04:06:03 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778846921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.778846921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_all.4277719507 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 21640670958 ps |
| CPU time | 224.46 seconds |
| Started | Oct 09 04:06:16 PM UTC 24 |
| Finished | Oct 09 04:10:05 PM UTC 24 |
| Peak memory | 261648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277719507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.4277719507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.3120032851 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 23175793984 ps |
| CPU time | 92.79 seconds |
| Started | Oct 09 04:06:17 PM UTC 24 |
| Finished | Oct 09 04:07:52 PM UTC 24 |
| Peak memory | 261704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120032851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.3120032851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode.2193446638 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 672605896 ps |
| CPU time | 9.27 seconds |
| Started | Oct 09 04:06:13 PM UTC 24 |
| Finished | Oct 09 04:06:23 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193446638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2193446638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.3822408940 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 7773521606 ps |
| CPU time | 16.51 seconds |
| Started | Oct 09 04:06:15 PM UTC 24 |
| Finished | Oct 09 04:06:33 PM UTC 24 |
| Peak memory | 235216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822408940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.3822408940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_intercept.4178637161 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 107065785 ps |
| CPU time | 4.48 seconds |
| Started | Oct 09 04:06:07 PM UTC 24 |
| Finished | Oct 09 04:06:12 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178637161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.4178637161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mailbox.1293237457 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 271420554 ps |
| CPU time | 11.71 seconds |
| Started | Oct 09 04:06:08 PM UTC 24 |
| Finished | Oct 09 04:06:20 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293237457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1293237457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mem_parity.336142734 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 32932576 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 04:06:02 PM UTC 24 |
| Finished | Oct 09 04:06:04 PM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336142734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mem_parity.336142734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.3456995723 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 114321207 ps |
| CPU time | 3.17 seconds |
| Started | Oct 09 04:06:05 PM UTC 24 |
| Finished | Oct 09 04:06:10 PM UTC 24 |
| Peak memory | 245332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456995723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.3456995723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.2057385472 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 601055090 ps |
| CPU time | 9.48 seconds |
| Started | Oct 09 04:06:05 PM UTC 24 |
| Finished | Oct 09 04:06:16 PM UTC 24 |
| Peak memory | 245140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057385472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2057385472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.1358177495 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 874358160 ps |
| CPU time | 5.72 seconds |
| Started | Oct 09 04:06:15 PM UTC 24 |
| Finished | Oct 09 04:06:22 PM UTC 24 |
| Peak memory | 229416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358177495 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.1358177495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_stress_all.1697281466 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 29262881146 ps |
| CPU time | 190.61 seconds |
| Started | Oct 09 04:06:19 PM UTC 24 |
| Finished | Oct 09 04:09:33 PM UTC 24 |
| Peak memory | 267916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697281466 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.1697281466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_all.996368218 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 35351363 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 04:06:04 PM UTC 24 |
| Finished | Oct 09 04:06:06 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996368218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.996368218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.867530935 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 1994502292 ps |
| CPU time | 9.45 seconds |
| Started | Oct 09 04:06:04 PM UTC 24 |
| Finished | Oct 09 04:06:14 PM UTC 24 |
| Peak memory | 227676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867530935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.867530935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_rw.1016338046 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 175045164 ps |
| CPU time | 3.11 seconds |
| Started | Oct 09 04:06:05 PM UTC 24 |
| Finished | Oct 09 04:06:09 PM UTC 24 |
| Peak memory | 227936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016338046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1016338046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.1322448747 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 41561841 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 04:06:04 PM UTC 24 |
| Finished | Oct 09 04:06:06 PM UTC 24 |
| Peak memory | 214856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322448747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1322448747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_upload.3380445395 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 54372790 ps |
| CPU time | 3.35 seconds |
| Started | Oct 09 04:06:10 PM UTC 24 |
| Finished | Oct 09 04:06:14 PM UTC 24 |
| Peak memory | 234640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380445395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3380445395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/19.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.1458091081 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 21225242 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 03:55:50 PM UTC 24 |
| Finished | Oct 09 03:55:52 PM UTC 24 |
| Peak memory | 214840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458091081 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1458091081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.1486749578 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 494963618 ps |
| CPU time | 6.99 seconds |
| Started | Oct 09 03:55:21 PM UTC 24 |
| Finished | Oct 09 03:55:30 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486749578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1486749578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.2990822191 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 52227808 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 03:55:08 PM UTC 24 |
| Finished | Oct 09 03:55:10 PM UTC 24 |
| Peak memory | 214972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990822191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2990822191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.1866073525 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 34991707198 ps |
| CPU time | 213.11 seconds |
| Started | Oct 09 03:55:44 PM UTC 24 |
| Finished | Oct 09 03:59:21 PM UTC 24 |
| Peak memory | 263760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866073525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1866073525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.4168719329 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 24707030440 ps |
| CPU time | 236.6 seconds |
| Started | Oct 09 03:55:46 PM UTC 24 |
| Finished | Oct 09 03:59:46 PM UTC 24 |
| Peak memory | 263768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168719329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.4168719329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.3641251126 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 49141657097 ps |
| CPU time | 276.71 seconds |
| Started | Oct 09 03:55:31 PM UTC 24 |
| Finished | Oct 09 04:00:12 PM UTC 24 |
| Peak memory | 261716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641251126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.3641251126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.1675256723 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 38168430900 ps |
| CPU time | 41.06 seconds |
| Started | Oct 09 03:55:16 PM UTC 24 |
| Finished | Oct 09 03:55:59 PM UTC 24 |
| Peak memory | 235084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675256723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1675256723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.1803120751 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 3407717014 ps |
| CPU time | 37.45 seconds |
| Started | Oct 09 03:55:17 PM UTC 24 |
| Finished | Oct 09 03:55:56 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803120751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1803120751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.559028328 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 45236340 ps |
| CPU time | 1.45 seconds |
| Started | Oct 09 03:55:09 PM UTC 24 |
| Finished | Oct 09 03:55:12 PM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559028328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_parity.559028328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.3782445779 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 762047606 ps |
| CPU time | 2.99 seconds |
| Started | Oct 09 03:55:15 PM UTC 24 |
| Finished | Oct 09 03:55:19 PM UTC 24 |
| Peak memory | 233512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782445779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.3782445779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.122549673 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 688652128 ps |
| CPU time | 6.26 seconds |
| Started | Oct 09 03:55:13 PM UTC 24 |
| Finished | Oct 09 03:55:20 PM UTC 24 |
| Peak memory | 235156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122549673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.122549673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.2730329698 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 103637709 ps |
| CPU time | 5.22 seconds |
| Started | Oct 09 03:55:37 PM UTC 24 |
| Finished | Oct 09 03:55:43 PM UTC 24 |
| Peak memory | 233784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730329698 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.2730329698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.2419786980 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 159471580 ps |
| CPU time | 2.02 seconds |
| Started | Oct 09 03:55:49 PM UTC 24 |
| Finished | Oct 09 03:55:52 PM UTC 24 |
| Peak memory | 258388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419786980 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2419786980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.2314771049 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 17563903187 ps |
| CPU time | 34.42 seconds |
| Started | Oct 09 03:55:12 PM UTC 24 |
| Finished | Oct 09 03:55:47 PM UTC 24 |
| Peak memory | 227688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314771049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2314771049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.1844013908 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 6117139268 ps |
| CPU time | 16.15 seconds |
| Started | Oct 09 03:55:09 PM UTC 24 |
| Finished | Oct 09 03:55:27 PM UTC 24 |
| Peak memory | 227580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844013908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1844013908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.1002751629 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 147919830 ps |
| CPU time | 1.72 seconds |
| Started | Oct 09 03:55:13 PM UTC 24 |
| Finished | Oct 09 03:55:16 PM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002751629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1002751629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.3924398330 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 75155402 ps |
| CPU time | 1.5 seconds |
| Started | Oct 09 03:55:12 PM UTC 24 |
| Finished | Oct 09 03:55:14 PM UTC 24 |
| Peak memory | 214856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924398330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3924398330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.3160575715 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 5725922094 ps |
| CPU time | 21.69 seconds |
| Started | Oct 09 03:55:20 PM UTC 24 |
| Finished | Oct 09 03:55:43 PM UTC 24 |
| Peak memory | 245392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160575715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3160575715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/2.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_alert_test.1949191604 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 21890665 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 04:06:43 PM UTC 24 |
| Finished | Oct 09 04:06:46 PM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949191604 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.1949191604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/20.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_cfg_cmd.1427122734 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 276845699 ps |
| CPU time | 6.64 seconds |
| Started | Oct 09 04:06:34 PM UTC 24 |
| Finished | Oct 09 04:06:42 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427122734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1427122734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/20.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_csb_read.551185234 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 122888580 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 04:06:23 PM UTC 24 |
| Finished | Oct 09 04:06:26 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551185234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.551185234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/20.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_all.3124906807 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 143793605540 ps |
| CPU time | 103.36 seconds |
| Started | Oct 09 04:06:40 PM UTC 24 |
| Finished | Oct 09 04:08:26 PM UTC 24 |
| Peak memory | 261776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124906807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3124906807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/20.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.3495007381 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 29715606574 ps |
| CPU time | 84.22 seconds |
| Started | Oct 09 04:06:42 PM UTC 24 |
| Finished | Oct 09 04:08:08 PM UTC 24 |
| Peak memory | 261840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495007381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3495007381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.950603105 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 10405594397 ps |
| CPU time | 157.41 seconds |
| Started | Oct 09 04:06:42 PM UTC 24 |
| Finished | Oct 09 04:09:22 PM UTC 24 |
| Peak memory | 284236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950603105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.950603105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode.3420760659 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1789671296 ps |
| CPU time | 10.82 seconds |
| Started | Oct 09 04:06:36 PM UTC 24 |
| Finished | Oct 09 04:06:49 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420760659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3420760659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/20.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.3149666861 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 4531443763 ps |
| CPU time | 98.05 seconds |
| Started | Oct 09 04:06:38 PM UTC 24 |
| Finished | Oct 09 04:08:18 PM UTC 24 |
| Peak memory | 274060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149666861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.3149666861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_intercept.2800319164 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 2707383178 ps |
| CPU time | 12.39 seconds |
| Started | Oct 09 04:06:33 PM UTC 24 |
| Finished | Oct 09 04:06:47 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800319164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2800319164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/20.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_mailbox.1089548681 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 450500017 ps |
| CPU time | 4.43 seconds |
| Started | Oct 09 04:06:33 PM UTC 24 |
| Finished | Oct 09 04:06:39 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089548681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1089548681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/20.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.3130920380 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1190622757 ps |
| CPU time | 7.88 seconds |
| Started | Oct 09 04:06:32 PM UTC 24 |
| Finished | Oct 09 04:06:41 PM UTC 24 |
| Peak memory | 245388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130920380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.3130920380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/20.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.942943084 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 524020486 ps |
| CPU time | 13.51 seconds |
| Started | Oct 09 04:06:30 PM UTC 24 |
| Finished | Oct 09 04:06:45 PM UTC 24 |
| Peak memory | 245144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942943084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.942943084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/20.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.2310399407 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 562759779 ps |
| CPU time | 6.62 seconds |
| Started | Oct 09 04:06:38 PM UTC 24 |
| Finished | Oct 09 04:06:46 PM UTC 24 |
| Peak memory | 233720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310399407 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.2310399407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/20.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_stress_all.2010983171 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 2449812410 ps |
| CPU time | 47.3 seconds |
| Started | Oct 09 04:06:43 PM UTC 24 |
| Finished | Oct 09 04:07:32 PM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010983171 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.2010983171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/20.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_all.433206884 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 15416002797 ps |
| CPU time | 43.79 seconds |
| Started | Oct 09 04:06:24 PM UTC 24 |
| Finished | Oct 09 04:07:10 PM UTC 24 |
| Peak memory | 227740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433206884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.433206884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/20.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.2977169544 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 2240769170 ps |
| CPU time | 6.99 seconds |
| Started | Oct 09 04:06:24 PM UTC 24 |
| Finished | Oct 09 04:06:32 PM UTC 24 |
| Peak memory | 227564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977169544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2977169544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/20.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_rw.3760520016 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 44349003 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 04:06:28 PM UTC 24 |
| Finished | Oct 09 04:06:31 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760520016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3760520016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/20.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.3472148091 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 140902787 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 04:06:26 PM UTC 24 |
| Finished | Oct 09 04:06:29 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472148091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3472148091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/20.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_upload.1582131241 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 7772252771 ps |
| CPU time | 6.73 seconds |
| Started | Oct 09 04:06:33 PM UTC 24 |
| Finished | Oct 09 04:06:41 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582131241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1582131241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/20.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_alert_test.628623924 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 25650768 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 04:07:14 PM UTC 24 |
| Finished | Oct 09 04:07:16 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628623924 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.628623924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/21.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_cfg_cmd.2285728385 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 469165340 ps |
| CPU time | 10.41 seconds |
| Started | Oct 09 04:06:55 PM UTC 24 |
| Finished | Oct 09 04:07:06 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285728385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2285728385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/21.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_csb_read.587671887 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 14892631 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 04:06:46 PM UTC 24 |
| Finished | Oct 09 04:06:48 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587671887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.587671887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/21.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_all.3317838326 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 7483214060 ps |
| CPU time | 41.53 seconds |
| Started | Oct 09 04:07:07 PM UTC 24 |
| Finished | Oct 09 04:07:50 PM UTC 24 |
| Peak memory | 247372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317838326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3317838326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/21.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.1884241258 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 54840800736 ps |
| CPU time | 237.13 seconds |
| Started | Oct 09 04:07:08 PM UTC 24 |
| Finished | Oct 09 04:11:09 PM UTC 24 |
| Peak memory | 261704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884241258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1884241258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.1990269386 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 8531689248 ps |
| CPU time | 107.53 seconds |
| Started | Oct 09 04:07:08 PM UTC 24 |
| Finished | Oct 09 04:08:58 PM UTC 24 |
| Peak memory | 278084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990269386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.1990269386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode.2658177348 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 12369009997 ps |
| CPU time | 47.32 seconds |
| Started | Oct 09 04:06:56 PM UTC 24 |
| Finished | Oct 09 04:07:45 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658177348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2658177348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/21.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.2093657391 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 2336730295 ps |
| CPU time | 65.85 seconds |
| Started | Oct 09 04:07:01 PM UTC 24 |
| Finished | Oct 09 04:08:09 PM UTC 24 |
| Peak memory | 261840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093657391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.2093657391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_intercept.469201433 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 13169376240 ps |
| CPU time | 39.87 seconds |
| Started | Oct 09 04:06:52 PM UTC 24 |
| Finished | Oct 09 04:07:34 PM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469201433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.469201433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/21.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_mailbox.1227410379 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 1178947000 ps |
| CPU time | 32.83 seconds |
| Started | Oct 09 04:06:53 PM UTC 24 |
| Finished | Oct 09 04:07:28 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227410379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1227410379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/21.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.3751760271 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 20025225191 ps |
| CPU time | 46.85 seconds |
| Started | Oct 09 04:06:51 PM UTC 24 |
| Finished | Oct 09 04:07:40 PM UTC 24 |
| Peak memory | 255756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751760271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.3751760271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/21.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.2135988946 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 259598296 ps |
| CPU time | 2.97 seconds |
| Started | Oct 09 04:06:49 PM UTC 24 |
| Finished | Oct 09 04:06:53 PM UTC 24 |
| Peak memory | 234692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135988946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2135988946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/21.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.2466877611 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 2200974669 ps |
| CPU time | 7.22 seconds |
| Started | Oct 09 04:07:07 PM UTC 24 |
| Finished | Oct 09 04:07:15 PM UTC 24 |
| Peak memory | 231576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466877611 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.2466877611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/21.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_stress_all.1093398055 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 55173982 ps |
| CPU time | 1.76 seconds |
| Started | Oct 09 04:07:11 PM UTC 24 |
| Finished | Oct 09 04:07:13 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093398055 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.1093398055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/21.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_all.181896136 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 6471369271 ps |
| CPU time | 53.45 seconds |
| Started | Oct 09 04:06:47 PM UTC 24 |
| Finished | Oct 09 04:07:42 PM UTC 24 |
| Peak memory | 231776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181896136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.181896136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/21.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.2719495785 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 1134119593 ps |
| CPU time | 7.02 seconds |
| Started | Oct 09 04:06:47 PM UTC 24 |
| Finished | Oct 09 04:06:55 PM UTC 24 |
| Peak memory | 227572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719495785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2719495785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/21.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_rw.623591858 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 1053192719 ps |
| CPU time | 2.69 seconds |
| Started | Oct 09 04:06:49 PM UTC 24 |
| Finished | Oct 09 04:06:53 PM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623591858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.623591858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/21.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.892645166 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 84764388 ps |
| CPU time | 1.38 seconds |
| Started | Oct 09 04:06:48 PM UTC 24 |
| Finished | Oct 09 04:06:50 PM UTC 24 |
| Peak memory | 214856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892645166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.892645166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/21.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_upload.3391394736 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 11176218897 ps |
| CPU time | 20.04 seconds |
| Started | Oct 09 04:06:54 PM UTC 24 |
| Finished | Oct 09 04:07:15 PM UTC 24 |
| Peak memory | 245392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391394736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3391394736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/21.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_alert_test.2441604797 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 26180722 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 04:07:37 PM UTC 24 |
| Finished | Oct 09 04:07:39 PM UTC 24 |
| Peak memory | 214784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441604797 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.2441604797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/22.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_cfg_cmd.2474333318 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 3349173656 ps |
| CPU time | 28.01 seconds |
| Started | Oct 09 04:07:29 PM UTC 24 |
| Finished | Oct 09 04:07:58 PM UTC 24 |
| Peak memory | 245388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474333318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2474333318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/22.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_csb_read.3833000466 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 31666119 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 04:07:14 PM UTC 24 |
| Finished | Oct 09 04:07:16 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833000466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3833000466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/22.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_all.2492847362 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 11584606796 ps |
| CPU time | 122.46 seconds |
| Started | Oct 09 04:07:31 PM UTC 24 |
| Finished | Oct 09 04:09:36 PM UTC 24 |
| Peak memory | 267788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492847362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2492847362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/22.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.1954456860 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 8017899920 ps |
| CPU time | 69.14 seconds |
| Started | Oct 09 04:07:33 PM UTC 24 |
| Finished | Oct 09 04:08:44 PM UTC 24 |
| Peak memory | 261840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954456860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1954456860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/22.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode.3771178227 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 1432715586 ps |
| CPU time | 22.04 seconds |
| Started | Oct 09 04:07:29 PM UTC 24 |
| Finished | Oct 09 04:07:52 PM UTC 24 |
| Peak memory | 234972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771178227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3771178227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/22.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.3178206473 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 23883755092 ps |
| CPU time | 123.99 seconds |
| Started | Oct 09 04:07:30 PM UTC 24 |
| Finished | Oct 09 04:09:37 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178206473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.3178206473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_intercept.3450829721 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 1654597218 ps |
| CPU time | 16.03 seconds |
| Started | Oct 09 04:07:21 PM UTC 24 |
| Finished | Oct 09 04:07:38 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450829721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3450829721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/22.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_mailbox.3593090577 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 345333779 ps |
| CPU time | 3.65 seconds |
| Started | Oct 09 04:07:26 PM UTC 24 |
| Finished | Oct 09 04:07:31 PM UTC 24 |
| Peak memory | 234884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593090577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3593090577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/22.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.3712935890 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 602113555 ps |
| CPU time | 8.9 seconds |
| Started | Oct 09 04:07:19 PM UTC 24 |
| Finished | Oct 09 04:07:30 PM UTC 24 |
| Peak memory | 251408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712935890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.3712935890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/22.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.3983377285 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 932009034 ps |
| CPU time | 9.55 seconds |
| Started | Oct 09 04:07:17 PM UTC 24 |
| Finished | Oct 09 04:07:28 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983377285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3983377285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/22.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.3167466948 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 114168752 ps |
| CPU time | 3.91 seconds |
| Started | Oct 09 04:07:31 PM UTC 24 |
| Finished | Oct 09 04:07:36 PM UTC 24 |
| Peak memory | 233808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167466948 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.3167466948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/22.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_all.2846714310 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 23155604871 ps |
| CPU time | 41.67 seconds |
| Started | Oct 09 04:07:16 PM UTC 24 |
| Finished | Oct 09 04:07:59 PM UTC 24 |
| Peak memory | 231916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846714310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2846714310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/22.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.1646971911 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 8538476694 ps |
| CPU time | 14.03 seconds |
| Started | Oct 09 04:07:15 PM UTC 24 |
| Finished | Oct 09 04:07:30 PM UTC 24 |
| Peak memory | 227624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646971911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1646971911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/22.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_rw.2451119948 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 79746568 ps |
| CPU time | 1.62 seconds |
| Started | Oct 09 04:07:17 PM UTC 24 |
| Finished | Oct 09 04:07:20 PM UTC 24 |
| Peak memory | 226924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451119948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2451119948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/22.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.3565452545 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 70515342 ps |
| CPU time | 1.39 seconds |
| Started | Oct 09 04:07:16 PM UTC 24 |
| Finished | Oct 09 04:07:18 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565452545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3565452545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/22.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_upload.559550864 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 21863272210 ps |
| CPU time | 23.63 seconds |
| Started | Oct 09 04:07:29 PM UTC 24 |
| Finished | Oct 09 04:07:54 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559550864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.559550864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/22.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_alert_test.2944467954 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 102210390 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 04:08:00 PM UTC 24 |
| Finished | Oct 09 04:08:02 PM UTC 24 |
| Peak memory | 214840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944467954 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.2944467954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/23.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_cfg_cmd.157503803 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 815846168 ps |
| CPU time | 9.18 seconds |
| Started | Oct 09 04:07:51 PM UTC 24 |
| Finished | Oct 09 04:08:02 PM UTC 24 |
| Peak memory | 234944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157503803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.157503803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/23.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_csb_read.3239482385 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 38696741 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 04:07:39 PM UTC 24 |
| Finished | Oct 09 04:07:41 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239482385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3239482385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/23.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_all.3866120837 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 96922509484 ps |
| CPU time | 169.11 seconds |
| Started | Oct 09 04:07:55 PM UTC 24 |
| Finished | Oct 09 04:10:47 PM UTC 24 |
| Peak memory | 265744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866120837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3866120837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/23.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.3399811202 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 9500761250 ps |
| CPU time | 18.03 seconds |
| Started | Oct 09 04:07:55 PM UTC 24 |
| Finished | Oct 09 04:08:14 PM UTC 24 |
| Peak memory | 251524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399811202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3399811202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.3174773952 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1565372476 ps |
| CPU time | 35.05 seconds |
| Started | Oct 09 04:07:57 PM UTC 24 |
| Finished | Oct 09 04:08:33 PM UTC 24 |
| Peak memory | 249544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174773952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.3174773952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode.62610200 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 1105337910 ps |
| CPU time | 6.35 seconds |
| Started | Oct 09 04:07:52 PM UTC 24 |
| Finished | Oct 09 04:08:00 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62610200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.62610200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/23.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.618928472 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 97269901726 ps |
| CPU time | 196.74 seconds |
| Started | Oct 09 04:07:52 PM UTC 24 |
| Finished | Oct 09 04:11:12 PM UTC 24 |
| Peak memory | 261776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618928472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.618928472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_intercept.1723064013 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 539231097 ps |
| CPU time | 6.92 seconds |
| Started | Oct 09 04:07:46 PM UTC 24 |
| Finished | Oct 09 04:07:54 PM UTC 24 |
| Peak memory | 235212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723064013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1723064013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/23.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_mailbox.2088967630 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 3290607940 ps |
| CPU time | 18.93 seconds |
| Started | Oct 09 04:07:46 PM UTC 24 |
| Finished | Oct 09 04:08:06 PM UTC 24 |
| Peak memory | 265876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088967630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2088967630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/23.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.280266603 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 8895133655 ps |
| CPU time | 40.66 seconds |
| Started | Oct 09 04:07:46 PM UTC 24 |
| Finished | Oct 09 04:08:28 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280266603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.280266603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/23.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.3763562432 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 1122933797 ps |
| CPU time | 11.77 seconds |
| Started | Oct 09 04:07:46 PM UTC 24 |
| Finished | Oct 09 04:07:59 PM UTC 24 |
| Peak memory | 245388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763562432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3763562432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/23.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.255579216 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 1843432470 ps |
| CPU time | 22.97 seconds |
| Started | Oct 09 04:07:54 PM UTC 24 |
| Finished | Oct 09 04:08:18 PM UTC 24 |
| Peak memory | 231524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255579216 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.255579216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/23.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.3469724273 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 206442909819 ps |
| CPU time | 274.85 seconds |
| Started | Oct 09 04:07:59 PM UTC 24 |
| Finished | Oct 09 04:12:38 PM UTC 24 |
| Peak memory | 268048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469724273 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.3469724273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/23.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_all.2063992806 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 13011511798 ps |
| CPU time | 31.86 seconds |
| Started | Oct 09 04:07:40 PM UTC 24 |
| Finished | Oct 09 04:08:14 PM UTC 24 |
| Peak memory | 227744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063992806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2063992806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/23.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.765659071 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 3273191529 ps |
| CPU time | 9.94 seconds |
| Started | Oct 09 04:07:40 PM UTC 24 |
| Finished | Oct 09 04:07:51 PM UTC 24 |
| Peak memory | 227616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765659071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.765659071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/23.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_rw.808807007 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 82144006 ps |
| CPU time | 1.56 seconds |
| Started | Oct 09 04:07:43 PM UTC 24 |
| Finished | Oct 09 04:07:45 PM UTC 24 |
| Peak memory | 216684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808807007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.808807007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/23.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.2322613345 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 32502148 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 04:07:42 PM UTC 24 |
| Finished | Oct 09 04:07:45 PM UTC 24 |
| Peak memory | 214856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322613345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2322613345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/23.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_upload.753604206 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 92605458 ps |
| CPU time | 3.08 seconds |
| Started | Oct 09 04:07:51 PM UTC 24 |
| Finished | Oct 09 04:07:56 PM UTC 24 |
| Peak memory | 234952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753604206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.753604206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/23.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_alert_test.3208432508 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 13572262 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 04:08:26 PM UTC 24 |
| Finished | Oct 09 04:08:28 PM UTC 24 |
| Peak memory | 214840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208432508 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.3208432508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/24.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_cfg_cmd.3458142814 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 756206268 ps |
| CPU time | 4.89 seconds |
| Started | Oct 09 04:08:12 PM UTC 24 |
| Finished | Oct 09 04:08:18 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458142814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3458142814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/24.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_csb_read.1607869766 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 17428964 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 04:08:00 PM UTC 24 |
| Finished | Oct 09 04:08:03 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607869766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1607869766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/24.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.3440062347 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 11232964934 ps |
| CPU time | 71.27 seconds |
| Started | Oct 09 04:08:19 PM UTC 24 |
| Finished | Oct 09 04:09:32 PM UTC 24 |
| Peak memory | 263700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440062347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3440062347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/24.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.766138005 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 2426816350 ps |
| CPU time | 37.88 seconds |
| Started | Oct 09 04:08:19 PM UTC 24 |
| Finished | Oct 09 04:08:58 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766138005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.766138005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.841721881 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 8368583397 ps |
| CPU time | 82.89 seconds |
| Started | Oct 09 04:08:24 PM UTC 24 |
| Finished | Oct 09 04:09:49 PM UTC 24 |
| Peak memory | 261772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841721881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.841721881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.361961873 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 1627576363 ps |
| CPU time | 19.44 seconds |
| Started | Oct 09 04:08:14 PM UTC 24 |
| Finished | Oct 09 04:08:35 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361961873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.361961873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/24.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.2348428234 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 392408079 ps |
| CPU time | 13.39 seconds |
| Started | Oct 09 04:08:16 PM UTC 24 |
| Finished | Oct 09 04:08:30 PM UTC 24 |
| Peak memory | 235084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348428234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.2348428234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_intercept.1265720469 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 1569394424 ps |
| CPU time | 14.01 seconds |
| Started | Oct 09 04:08:08 PM UTC 24 |
| Finished | Oct 09 04:08:23 PM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265720469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1265720469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/24.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_mailbox.553718485 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 38471195300 ps |
| CPU time | 86.15 seconds |
| Started | Oct 09 04:08:09 PM UTC 24 |
| Finished | Oct 09 04:09:37 PM UTC 24 |
| Peak memory | 249352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553718485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.553718485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/24.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.1881465249 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 23490679315 ps |
| CPU time | 50.52 seconds |
| Started | Oct 09 04:08:07 PM UTC 24 |
| Finished | Oct 09 04:08:59 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881465249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.1881465249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/24.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.2671857420 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 62181987 ps |
| CPU time | 3.1 seconds |
| Started | Oct 09 04:08:07 PM UTC 24 |
| Finished | Oct 09 04:08:11 PM UTC 24 |
| Peak memory | 245068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671857420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2671857420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/24.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.4095237581 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 168607290 ps |
| CPU time | 6.19 seconds |
| Started | Oct 09 04:08:19 PM UTC 24 |
| Finished | Oct 09 04:08:26 PM UTC 24 |
| Peak memory | 231452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095237581 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.4095237581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/24.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_stress_all.596093503 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 46483315827 ps |
| CPU time | 246.26 seconds |
| Started | Oct 09 04:08:24 PM UTC 24 |
| Finished | Oct 09 04:12:34 PM UTC 24 |
| Peak memory | 265852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596093503 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.596093503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/24.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_all.4025357554 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 4236694841 ps |
| CPU time | 43.03 seconds |
| Started | Oct 09 04:08:03 PM UTC 24 |
| Finished | Oct 09 04:08:47 PM UTC 24 |
| Peak memory | 227628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025357554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.4025357554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/24.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.4199093372 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 9553037121 ps |
| CPU time | 20.73 seconds |
| Started | Oct 09 04:08:01 PM UTC 24 |
| Finished | Oct 09 04:08:23 PM UTC 24 |
| Peak memory | 227692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199093372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4199093372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/24.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_rw.943677706 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 153745591 ps |
| CPU time | 2.29 seconds |
| Started | Oct 09 04:08:04 PM UTC 24 |
| Finished | Oct 09 04:08:07 PM UTC 24 |
| Peak memory | 227680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943677706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.943677706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/24.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.2805490783 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 39946535 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 04:08:04 PM UTC 24 |
| Finished | Oct 09 04:08:06 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805490783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2805490783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/24.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_upload.3622048525 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 10599596216 ps |
| CPU time | 28.85 seconds |
| Started | Oct 09 04:08:09 PM UTC 24 |
| Finished | Oct 09 04:08:40 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622048525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3622048525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/24.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_alert_test.424613180 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 34394923 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 04:08:46 PM UTC 24 |
| Finished | Oct 09 04:08:49 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424613180 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.424613180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/25.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_cfg_cmd.3024143070 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 199577053 ps |
| CPU time | 5.83 seconds |
| Started | Oct 09 04:08:36 PM UTC 24 |
| Finished | Oct 09 04:08:43 PM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024143070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3024143070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/25.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_csb_read.28018653 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 17236663 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 04:08:27 PM UTC 24 |
| Finished | Oct 09 04:08:30 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28018653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.28018653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/25.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_all.1541360268 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 20319093516 ps |
| CPU time | 175.1 seconds |
| Started | Oct 09 04:08:41 PM UTC 24 |
| Finished | Oct 09 04:11:39 PM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541360268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1541360268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/25.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.164329270 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 12918398204 ps |
| CPU time | 35.44 seconds |
| Started | Oct 09 04:08:41 PM UTC 24 |
| Finished | Oct 09 04:09:18 PM UTC 24 |
| Peak memory | 233832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164329270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.164329270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.397294480 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 7891037897 ps |
| CPU time | 92.58 seconds |
| Started | Oct 09 04:08:43 PM UTC 24 |
| Finished | Oct 09 04:10:18 PM UTC 24 |
| Peak memory | 284432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397294480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.397294480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.3207165831 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 163698291257 ps |
| CPU time | 140.51 seconds |
| Started | Oct 09 04:08:39 PM UTC 24 |
| Finished | Oct 09 04:11:02 PM UTC 24 |
| Peak memory | 263756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207165831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.3207165831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_intercept.2417773755 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 3991783632 ps |
| CPU time | 10.95 seconds |
| Started | Oct 09 04:08:33 PM UTC 24 |
| Finished | Oct 09 04:08:45 PM UTC 24 |
| Peak memory | 234952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417773755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2417773755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/25.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_mailbox.3913390047 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 300794425 ps |
| CPU time | 3.22 seconds |
| Started | Oct 09 04:08:34 PM UTC 24 |
| Finished | Oct 09 04:08:39 PM UTC 24 |
| Peak memory | 234376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913390047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3913390047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/25.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.3886731510 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 7508668788 ps |
| CPU time | 20.4 seconds |
| Started | Oct 09 04:08:32 PM UTC 24 |
| Finished | Oct 09 04:08:54 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886731510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.3886731510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/25.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.579961796 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 43963193613 ps |
| CPU time | 21.16 seconds |
| Started | Oct 09 04:08:31 PM UTC 24 |
| Finished | Oct 09 04:08:53 PM UTC 24 |
| Peak memory | 235088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579961796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.579961796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/25.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.1486336573 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 502160920 ps |
| CPU time | 5.29 seconds |
| Started | Oct 09 04:08:40 PM UTC 24 |
| Finished | Oct 09 04:08:46 PM UTC 24 |
| Peak memory | 231592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486336573 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.1486336573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/25.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.673588729 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 3752758267 ps |
| CPU time | 17.79 seconds |
| Started | Oct 09 04:08:44 PM UTC 24 |
| Finished | Oct 09 04:09:03 PM UTC 24 |
| Peak memory | 245312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673588729 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.673588729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/25.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_all.4162689460 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 1033175130 ps |
| CPU time | 9.17 seconds |
| Started | Oct 09 04:08:30 PM UTC 24 |
| Finished | Oct 09 04:08:40 PM UTC 24 |
| Peak memory | 227624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162689460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.4162689460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/25.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.1732425890 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 67082123 ps |
| CPU time | 1.89 seconds |
| Started | Oct 09 04:08:29 PM UTC 24 |
| Finished | Oct 09 04:08:31 PM UTC 24 |
| Peak memory | 216624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732425890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1732425890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/25.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_rw.1509123008 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 182670999 ps |
| CPU time | 2.17 seconds |
| Started | Oct 09 04:08:31 PM UTC 24 |
| Finished | Oct 09 04:08:34 PM UTC 24 |
| Peak memory | 227684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509123008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1509123008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/25.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.3419170438 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 76091883 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 04:08:30 PM UTC 24 |
| Finished | Oct 09 04:08:32 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419170438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3419170438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/25.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_upload.638805711 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 586032617 ps |
| CPU time | 2.71 seconds |
| Started | Oct 09 04:08:34 PM UTC 24 |
| Finished | Oct 09 04:08:38 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638805711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.638805711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/25.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_alert_test.3333248702 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 33867821 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 04:09:08 PM UTC 24 |
| Finished | Oct 09 04:09:10 PM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333248702 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.3333248702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/26.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_cfg_cmd.4058685042 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 825600918 ps |
| CPU time | 9.35 seconds |
| Started | Oct 09 04:09:00 PM UTC 24 |
| Finished | Oct 09 04:09:10 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058685042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.4058685042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/26.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_csb_read.1144536863 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 26239097 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 04:08:48 PM UTC 24 |
| Finished | Oct 09 04:08:50 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144536863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1144536863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/26.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.959638961 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 16371485875 ps |
| CPU time | 88.43 seconds |
| Started | Oct 09 04:09:03 PM UTC 24 |
| Finished | Oct 09 04:10:34 PM UTC 24 |
| Peak memory | 265748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959638961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.959638961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/26.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.3003815518 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 16125335532 ps |
| CPU time | 185.63 seconds |
| Started | Oct 09 04:09:05 PM UTC 24 |
| Finished | Oct 09 04:12:13 PM UTC 24 |
| Peak memory | 261772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003815518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3003815518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.2267888011 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 31064910427 ps |
| CPU time | 136.44 seconds |
| Started | Oct 09 04:09:00 PM UTC 24 |
| Finished | Oct 09 04:11:19 PM UTC 24 |
| Peak memory | 265800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267888011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.2267888011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_intercept.2462464162 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1423521253 ps |
| CPU time | 14.57 seconds |
| Started | Oct 09 04:08:57 PM UTC 24 |
| Finished | Oct 09 04:09:13 PM UTC 24 |
| Peak memory | 234888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462464162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2462464162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/26.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_mailbox.2968052228 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 3185422093 ps |
| CPU time | 33.92 seconds |
| Started | Oct 09 04:08:59 PM UTC 24 |
| Finished | Oct 09 04:09:34 PM UTC 24 |
| Peak memory | 261648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968052228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2968052228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/26.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.721061294 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1027468635 ps |
| CPU time | 11.9 seconds |
| Started | Oct 09 04:08:54 PM UTC 24 |
| Finished | Oct 09 04:09:08 PM UTC 24 |
| Peak memory | 249364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721061294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.721061294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/26.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.1047575888 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1145908212 ps |
| CPU time | 9.77 seconds |
| Started | Oct 09 04:08:54 PM UTC 24 |
| Finished | Oct 09 04:09:05 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047575888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1047575888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/26.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.770887796 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 1366316284 ps |
| CPU time | 13.74 seconds |
| Started | Oct 09 04:09:02 PM UTC 24 |
| Finished | Oct 09 04:09:17 PM UTC 24 |
| Peak memory | 233820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770887796 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.770887796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/26.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.4070824070 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 165834295 ps |
| CPU time | 1.58 seconds |
| Started | Oct 09 04:09:07 PM UTC 24 |
| Finished | Oct 09 04:09:09 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070824070 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.4070824070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/26.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_all.3074620759 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 1712938051 ps |
| CPU time | 30.79 seconds |
| Started | Oct 09 04:08:50 PM UTC 24 |
| Finished | Oct 09 04:09:22 PM UTC 24 |
| Peak memory | 227688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074620759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3074620759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/26.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.577535048 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 8985407628 ps |
| CPU time | 13.65 seconds |
| Started | Oct 09 04:08:48 PM UTC 24 |
| Finished | Oct 09 04:09:02 PM UTC 24 |
| Peak memory | 227572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577535048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.577535048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/26.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_rw.3124333908 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 391770184 ps |
| CPU time | 1.49 seconds |
| Started | Oct 09 04:08:54 PM UTC 24 |
| Finished | Oct 09 04:08:57 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124333908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3124333908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/26.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.3623124320 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 214191265 ps |
| CPU time | 1.44 seconds |
| Started | Oct 09 04:08:51 PM UTC 24 |
| Finished | Oct 09 04:08:53 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623124320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3623124320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/26.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_upload.340090500 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 3463180583 ps |
| CPU time | 19.74 seconds |
| Started | Oct 09 04:09:00 PM UTC 24 |
| Finished | Oct 09 04:09:21 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340090500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.340090500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/26.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_alert_test.3808363936 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 45458687 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 04:09:23 PM UTC 24 |
| Finished | Oct 09 04:09:25 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808363936 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.3808363936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/27.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_cfg_cmd.2382208889 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 328795911 ps |
| CPU time | 4.62 seconds |
| Started | Oct 09 04:09:18 PM UTC 24 |
| Finished | Oct 09 04:09:24 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382208889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2382208889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/27.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_csb_read.68332473 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 64909111 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 04:09:08 PM UTC 24 |
| Finished | Oct 09 04:09:10 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68332473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.68332473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/27.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.2449945701 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 4686587862 ps |
| CPU time | 45.84 seconds |
| Started | Oct 09 04:09:20 PM UTC 24 |
| Finished | Oct 09 04:10:07 PM UTC 24 |
| Peak memory | 263764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449945701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2449945701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/27.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.3973761349 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 31296838420 ps |
| CPU time | 151.48 seconds |
| Started | Oct 09 04:09:21 PM UTC 24 |
| Finished | Oct 09 04:11:56 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973761349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3973761349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.1638368728 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 76632091677 ps |
| CPU time | 701.99 seconds |
| Started | Oct 09 04:09:21 PM UTC 24 |
| Finished | Oct 09 04:21:12 PM UTC 24 |
| Peak memory | 284012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638368728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.1638368728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode.1942754604 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 143582902 ps |
| CPU time | 8.49 seconds |
| Started | Oct 09 04:09:18 PM UTC 24 |
| Finished | Oct 09 04:09:28 PM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942754604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1942754604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/27.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.2988257028 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 3990531757 ps |
| CPU time | 16.06 seconds |
| Started | Oct 09 04:09:20 PM UTC 24 |
| Finished | Oct 09 04:09:37 PM UTC 24 |
| Peak memory | 251400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988257028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.2988257028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_intercept.3288483672 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 153679538 ps |
| CPU time | 4.25 seconds |
| Started | Oct 09 04:09:14 PM UTC 24 |
| Finished | Oct 09 04:09:19 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288483672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3288483672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/27.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_mailbox.312517125 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 336780177 ps |
| CPU time | 3.11 seconds |
| Started | Oct 09 04:09:15 PM UTC 24 |
| Finished | Oct 09 04:09:19 PM UTC 24 |
| Peak memory | 229288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312517125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.312517125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/27.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.3296910590 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 1769100206 ps |
| CPU time | 7.54 seconds |
| Started | Oct 09 04:09:13 PM UTC 24 |
| Finished | Oct 09 04:09:22 PM UTC 24 |
| Peak memory | 235148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296910590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.3296910590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/27.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.272185865 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 6967089033 ps |
| CPU time | 6.12 seconds |
| Started | Oct 09 04:09:12 PM UTC 24 |
| Finished | Oct 09 04:09:19 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272185865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.272185865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/27.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.3517110791 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 1661222549 ps |
| CPU time | 11.27 seconds |
| Started | Oct 09 04:09:20 PM UTC 24 |
| Finished | Oct 09 04:09:32 PM UTC 24 |
| Peak memory | 231392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517110791 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.3517110791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/27.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.3431419094 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 40057040 ps |
| CPU time | 1.62 seconds |
| Started | Oct 09 04:09:21 PM UTC 24 |
| Finished | Oct 09 04:09:24 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431419094 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.3431419094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/27.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_all.202942691 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 268387789 ps |
| CPU time | 4.89 seconds |
| Started | Oct 09 04:09:11 PM UTC 24 |
| Finished | Oct 09 04:09:17 PM UTC 24 |
| Peak memory | 229724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202942691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.202942691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/27.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.2145845747 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 45606041 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 04:09:10 PM UTC 24 |
| Finished | Oct 09 04:09:12 PM UTC 24 |
| Peak memory | 214856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145845747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2145845747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/27.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_rw.1164678589 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 60076101 ps |
| CPU time | 1.45 seconds |
| Started | Oct 09 04:09:12 PM UTC 24 |
| Finished | Oct 09 04:09:14 PM UTC 24 |
| Peak memory | 226600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164678589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1164678589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/27.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.2647453910 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 45635853 ps |
| CPU time | 1.31 seconds |
| Started | Oct 09 04:09:12 PM UTC 24 |
| Finished | Oct 09 04:09:14 PM UTC 24 |
| Peak memory | 214856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647453910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2647453910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/27.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_upload.3455839189 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 3399742358 ps |
| CPU time | 10.59 seconds |
| Started | Oct 09 04:09:15 PM UTC 24 |
| Finished | Oct 09 04:09:27 PM UTC 24 |
| Peak memory | 247376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455839189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3455839189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/27.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_alert_test.2927324374 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 14501875 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 04:09:34 PM UTC 24 |
| Finished | Oct 09 04:09:36 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927324374 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.2927324374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/28.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_cfg_cmd.1207988815 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 675374576 ps |
| CPU time | 2.96 seconds |
| Started | Oct 09 04:09:29 PM UTC 24 |
| Finished | Oct 09 04:09:33 PM UTC 24 |
| Peak memory | 234892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207988815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1207988815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/28.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_csb_read.3893784214 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 46149884 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 04:09:23 PM UTC 24 |
| Finished | Oct 09 04:09:25 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893784214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3893784214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/28.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_all.333713187 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 150457406672 ps |
| CPU time | 203.71 seconds |
| Started | Oct 09 04:09:34 PM UTC 24 |
| Finished | Oct 09 04:13:01 PM UTC 24 |
| Peak memory | 278100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333713187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.333713187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/28.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.1768723218 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 21297703222 ps |
| CPU time | 107.21 seconds |
| Started | Oct 09 04:09:34 PM UTC 24 |
| Finished | Oct 09 04:11:23 PM UTC 24 |
| Peak memory | 261772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768723218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1768723218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/28.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.3578587203 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 1251199273 ps |
| CPU time | 15.21 seconds |
| Started | Oct 09 04:09:34 PM UTC 24 |
| Finished | Oct 09 04:09:50 PM UTC 24 |
| Peak memory | 247428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578587203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.3578587203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode.2633113351 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 1507832425 ps |
| CPU time | 14.94 seconds |
| Started | Oct 09 04:09:30 PM UTC 24 |
| Finished | Oct 09 04:09:46 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633113351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2633113351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/28.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.3277979863 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 70559063416 ps |
| CPU time | 306.88 seconds |
| Started | Oct 09 04:09:31 PM UTC 24 |
| Finished | Oct 09 04:14:43 PM UTC 24 |
| Peak memory | 282132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277979863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.3277979863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_intercept.3661868289 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 31669598380 ps |
| CPU time | 40.91 seconds |
| Started | Oct 09 04:09:28 PM UTC 24 |
| Finished | Oct 09 04:10:10 PM UTC 24 |
| Peak memory | 235212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661868289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3661868289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/28.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_mailbox.1710618689 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 165654473 ps |
| CPU time | 3.45 seconds |
| Started | Oct 09 04:09:28 PM UTC 24 |
| Finished | Oct 09 04:09:32 PM UTC 24 |
| Peak memory | 235008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710618689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1710618689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/28.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.2869665896 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 10922276362 ps |
| CPU time | 36.01 seconds |
| Started | Oct 09 04:09:26 PM UTC 24 |
| Finished | Oct 09 04:10:04 PM UTC 24 |
| Peak memory | 245388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869665896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.2869665896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/28.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.263856450 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 123352823 ps |
| CPU time | 3.18 seconds |
| Started | Oct 09 04:09:26 PM UTC 24 |
| Finished | Oct 09 04:09:31 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263856450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.263856450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/28.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.3754122715 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 636689514 ps |
| CPU time | 10.15 seconds |
| Started | Oct 09 04:09:33 PM UTC 24 |
| Finished | Oct 09 04:09:45 PM UTC 24 |
| Peak memory | 231520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754122715 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.3754122715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/28.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.2192207688 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 206350887 ps |
| CPU time | 1.55 seconds |
| Started | Oct 09 04:09:34 PM UTC 24 |
| Finished | Oct 09 04:09:37 PM UTC 24 |
| Peak memory | 216052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192207688 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.2192207688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/28.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_all.2000332080 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 3019096875 ps |
| CPU time | 33.51 seconds |
| Started | Oct 09 04:09:24 PM UTC 24 |
| Finished | Oct 09 04:09:59 PM UTC 24 |
| Peak memory | 231780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000332080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2000332080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/28.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.2131546892 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 16414459425 ps |
| CPU time | 13.36 seconds |
| Started | Oct 09 04:09:23 PM UTC 24 |
| Finished | Oct 09 04:09:37 PM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131546892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2131546892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/28.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_rw.2771150743 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 41862643 ps |
| CPU time | 2.53 seconds |
| Started | Oct 09 04:09:25 PM UTC 24 |
| Finished | Oct 09 04:09:29 PM UTC 24 |
| Peak memory | 227680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771150743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2771150743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/28.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.661719853 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 27657894 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 04:09:25 PM UTC 24 |
| Finished | Oct 09 04:09:28 PM UTC 24 |
| Peak memory | 214856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661719853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.661719853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/28.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/28.spi_device_upload.4011881938 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 209809426 ps |
| CPU time | 2.77 seconds |
| Started | Oct 09 04:09:29 PM UTC 24 |
| Finished | Oct 09 04:09:33 PM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011881938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.4011881938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/28.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_alert_test.3737124177 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 13711276 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 04:09:51 PM UTC 24 |
| Finished | Oct 09 04:09:53 PM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737124177 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.3737124177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/29.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_cfg_cmd.3303638445 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 5861472238 ps |
| CPU time | 21.69 seconds |
| Started | Oct 09 04:09:41 PM UTC 24 |
| Finished | Oct 09 04:10:05 PM UTC 24 |
| Peak memory | 235088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303638445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3303638445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/29.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_csb_read.4130720065 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 46893698 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 04:09:35 PM UTC 24 |
| Finished | Oct 09 04:09:37 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130720065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.4130720065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/29.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.1598036748 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 7505740909 ps |
| CPU time | 40.95 seconds |
| Started | Oct 09 04:09:47 PM UTC 24 |
| Finished | Oct 09 04:10:29 PM UTC 24 |
| Peak memory | 261840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598036748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1598036748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/29.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.1033643129 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 30353952366 ps |
| CPU time | 48.94 seconds |
| Started | Oct 09 04:09:49 PM UTC 24 |
| Finished | Oct 09 04:10:39 PM UTC 24 |
| Peak memory | 229732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033643129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1033643129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.2621156251 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 3335224575 ps |
| CPU time | 31.32 seconds |
| Started | Oct 09 04:09:50 PM UTC 24 |
| Finished | Oct 09 04:10:23 PM UTC 24 |
| Peak memory | 267844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621156251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.2621156251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.556986429 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 15127275712 ps |
| CPU time | 129.73 seconds |
| Started | Oct 09 04:09:46 PM UTC 24 |
| Finished | Oct 09 04:11:58 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556986429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.556986429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_intercept.1790701129 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 2746240768 ps |
| CPU time | 9.79 seconds |
| Started | Oct 09 04:09:39 PM UTC 24 |
| Finished | Oct 09 04:09:50 PM UTC 24 |
| Peak memory | 245452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790701129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1790701129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/29.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_mailbox.1081175265 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 6230755951 ps |
| CPU time | 34.87 seconds |
| Started | Oct 09 04:09:39 PM UTC 24 |
| Finished | Oct 09 04:10:16 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081175265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1081175265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/29.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.2506352539 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 134950049 ps |
| CPU time | 4.11 seconds |
| Started | Oct 09 04:09:39 PM UTC 24 |
| Finished | Oct 09 04:09:44 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506352539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.2506352539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/29.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.3747080094 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 4154217075 ps |
| CPU time | 16.74 seconds |
| Started | Oct 09 04:09:39 PM UTC 24 |
| Finished | Oct 09 04:09:57 PM UTC 24 |
| Peak memory | 245452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747080094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3747080094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/29.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.2641153354 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 88744551 ps |
| CPU time | 4.64 seconds |
| Started | Oct 09 04:09:46 PM UTC 24 |
| Finished | Oct 09 04:09:51 PM UTC 24 |
| Peak memory | 233504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641153354 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.2641153354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/29.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_stress_all.3104246464 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 10455586374 ps |
| CPU time | 167.11 seconds |
| Started | Oct 09 04:09:51 PM UTC 24 |
| Finished | Oct 09 04:12:41 PM UTC 24 |
| Peak memory | 263756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104246464 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.3104246464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/29.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_all.3794435797 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 4161279153 ps |
| CPU time | 35.98 seconds |
| Started | Oct 09 04:09:37 PM UTC 24 |
| Finished | Oct 09 04:10:15 PM UTC 24 |
| Peak memory | 227576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794435797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3794435797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/29.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.808582191 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 6051253233 ps |
| CPU time | 30.1 seconds |
| Started | Oct 09 04:09:37 PM UTC 24 |
| Finished | Oct 09 04:10:09 PM UTC 24 |
| Peak memory | 227532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808582191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.808582191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/29.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_rw.3195300467 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 127298579 ps |
| CPU time | 3.03 seconds |
| Started | Oct 09 04:09:39 PM UTC 24 |
| Finished | Oct 09 04:09:43 PM UTC 24 |
| Peak memory | 227552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195300467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3195300467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/29.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.869099031 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 42644153 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 04:09:37 PM UTC 24 |
| Finished | Oct 09 04:09:40 PM UTC 24 |
| Peak memory | 214864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869099031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.869099031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/29.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_upload.3255322778 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 8985131771 ps |
| CPU time | 20.5 seconds |
| Started | Oct 09 04:09:40 PM UTC 24 |
| Finished | Oct 09 04:10:02 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255322778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3255322778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/29.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.496008285 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 21835333 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 03:56:56 PM UTC 24 |
| Finished | Oct 09 03:56:58 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496008285 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.496008285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.3929673954 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 198069886 ps |
| CPU time | 4.25 seconds |
| Started | Oct 09 03:56:14 PM UTC 24 |
| Finished | Oct 09 03:56:19 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929673954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3929673954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.3501956469 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 42700432 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 03:55:53 PM UTC 24 |
| Finished | Oct 09 03:55:55 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501956469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3501956469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.1996740433 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 2398076129 ps |
| CPU time | 67.07 seconds |
| Started | Oct 09 03:56:33 PM UTC 24 |
| Finished | Oct 09 03:57:42 PM UTC 24 |
| Peak memory | 265744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996740433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1996740433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.1135107972 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 238975236221 ps |
| CPU time | 589.66 seconds |
| Started | Oct 09 03:56:40 PM UTC 24 |
| Finished | Oct 09 04:06:37 PM UTC 24 |
| Peak memory | 282192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135107972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1135107972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.2901131578 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 2770977629 ps |
| CPU time | 18.5 seconds |
| Started | Oct 09 03:56:20 PM UTC 24 |
| Finished | Oct 09 03:56:40 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901131578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2901131578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.1836759584 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 4031768669 ps |
| CPU time | 87.44 seconds |
| Started | Oct 09 03:56:22 PM UTC 24 |
| Finished | Oct 09 03:57:52 PM UTC 24 |
| Peak memory | 261720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836759584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.1836759584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.975698187 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 123808985 ps |
| CPU time | 6 seconds |
| Started | Oct 09 03:56:05 PM UTC 24 |
| Finished | Oct 09 03:56:12 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975698187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.975698187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.525068359 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 5161052963 ps |
| CPU time | 44.32 seconds |
| Started | Oct 09 03:56:07 PM UTC 24 |
| Finished | Oct 09 03:56:52 PM UTC 24 |
| Peak memory | 251524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525068359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.525068359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.1295465911 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 147792934 ps |
| CPU time | 3.27 seconds |
| Started | Oct 09 03:56:01 PM UTC 24 |
| Finished | Oct 09 03:56:06 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295465911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.1295465911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.3876421518 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 5785600897 ps |
| CPU time | 11.96 seconds |
| Started | Oct 09 03:56:00 PM UTC 24 |
| Finished | Oct 09 03:56:13 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876421518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3876421518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.2765882312 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 128865193 ps |
| CPU time | 5.5 seconds |
| Started | Oct 09 03:56:32 PM UTC 24 |
| Finished | Oct 09 03:56:39 PM UTC 24 |
| Peak memory | 229432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765882312 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.2765882312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.3109463055 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 281813247 ps |
| CPU time | 1.59 seconds |
| Started | Oct 09 03:56:53 PM UTC 24 |
| Finished | Oct 09 03:56:56 PM UTC 24 |
| Peak memory | 257636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109463055 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3109463055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.123996981 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1935360778 ps |
| CPU time | 73.71 seconds |
| Started | Oct 09 03:56:41 PM UTC 24 |
| Finished | Oct 09 03:57:56 PM UTC 24 |
| Peak memory | 261768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123996981 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.123996981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.1168302362 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2292648055 ps |
| CPU time | 33.42 seconds |
| Started | Oct 09 03:55:57 PM UTC 24 |
| Finished | Oct 09 03:56:32 PM UTC 24 |
| Peak memory | 227688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168302362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1168302362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.2130498334 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 415555185 ps |
| CPU time | 3.77 seconds |
| Started | Oct 09 03:55:56 PM UTC 24 |
| Finished | Oct 09 03:56:01 PM UTC 24 |
| Peak memory | 227712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130498334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2130498334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.1440191335 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 269023280 ps |
| CPU time | 3.19 seconds |
| Started | Oct 09 03:55:59 PM UTC 24 |
| Finished | Oct 09 03:56:03 PM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440191335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1440191335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.621425545 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 321148490 ps |
| CPU time | 1.57 seconds |
| Started | Oct 09 03:55:57 PM UTC 24 |
| Finished | Oct 09 03:56:00 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621425545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.621425545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.2247205697 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 3222220841 ps |
| CPU time | 17.74 seconds |
| Started | Oct 09 03:56:13 PM UTC 24 |
| Finished | Oct 09 03:56:32 PM UTC 24 |
| Peak memory | 251532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247205697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2247205697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/3.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_alert_test.704450381 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 52064424 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 04:10:10 PM UTC 24 |
| Finished | Oct 09 04:10:12 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704450381 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.704450381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/30.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_cfg_cmd.633237006 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 2552971124 ps |
| CPU time | 3.81 seconds |
| Started | Oct 09 04:10:05 PM UTC 24 |
| Finished | Oct 09 04:10:10 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633237006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.633237006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/30.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_csb_read.122925563 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 30848236 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 04:09:52 PM UTC 24 |
| Finished | Oct 09 04:09:54 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122925563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.122925563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/30.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_all.1741339890 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 17229181289 ps |
| CPU time | 95.28 seconds |
| Started | Oct 09 04:10:07 PM UTC 24 |
| Finished | Oct 09 04:11:44 PM UTC 24 |
| Peak memory | 265808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741339890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1741339890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/30.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.2492110409 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 63271373372 ps |
| CPU time | 617.68 seconds |
| Started | Oct 09 04:10:08 PM UTC 24 |
| Finished | Oct 09 04:20:34 PM UTC 24 |
| Peak memory | 278096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492110409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2492110409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/30.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.3020516905 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 8458644509 ps |
| CPU time | 76.48 seconds |
| Started | Oct 09 04:10:10 PM UTC 24 |
| Finished | Oct 09 04:11:29 PM UTC 24 |
| Peak memory | 267912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020516905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.3020516905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode.2867076900 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 1515674096 ps |
| CPU time | 9.51 seconds |
| Started | Oct 09 04:10:06 PM UTC 24 |
| Finished | Oct 09 04:10:16 PM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867076900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2867076900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/30.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.2442791402 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 83424701905 ps |
| CPU time | 105.33 seconds |
| Started | Oct 09 04:10:06 PM UTC 24 |
| Finished | Oct 09 04:11:53 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442791402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.2442791402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_intercept.513295213 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2962642417 ps |
| CPU time | 13.04 seconds |
| Started | Oct 09 04:10:00 PM UTC 24 |
| Finished | Oct 09 04:10:14 PM UTC 24 |
| Peak memory | 245452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513295213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.513295213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/30.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_mailbox.201223525 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 1171492050 ps |
| CPU time | 15.55 seconds |
| Started | Oct 09 04:10:03 PM UTC 24 |
| Finished | Oct 09 04:10:20 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201223525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.201223525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/30.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.1268329337 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 205122951 ps |
| CPU time | 4.88 seconds |
| Started | Oct 09 04:09:58 PM UTC 24 |
| Finished | Oct 09 04:10:04 PM UTC 24 |
| Peak memory | 251404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268329337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.1268329337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/30.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.3872095836 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 2366070289 ps |
| CPU time | 21.96 seconds |
| Started | Oct 09 04:09:58 PM UTC 24 |
| Finished | Oct 09 04:10:21 PM UTC 24 |
| Peak memory | 249484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872095836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3872095836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/30.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.2491525651 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 72720389 ps |
| CPU time | 5.13 seconds |
| Started | Oct 09 04:10:07 PM UTC 24 |
| Finished | Oct 09 04:10:13 PM UTC 24 |
| Peak memory | 233664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491525651 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.2491525651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/30.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.3728834911 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 41955778980 ps |
| CPU time | 155.85 seconds |
| Started | Oct 09 04:10:10 PM UTC 24 |
| Finished | Oct 09 04:12:49 PM UTC 24 |
| Peak memory | 265872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728834911 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.3728834911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/30.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_all.2286133332 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 8197755638 ps |
| CPU time | 45.55 seconds |
| Started | Oct 09 04:09:54 PM UTC 24 |
| Finished | Oct 09 04:10:41 PM UTC 24 |
| Peak memory | 227756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286133332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2286133332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/30.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.2829282576 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 19537319031 ps |
| CPU time | 13.04 seconds |
| Started | Oct 09 04:09:52 PM UTC 24 |
| Finished | Oct 09 04:10:07 PM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829282576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2829282576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/30.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_rw.392256857 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 232996910 ps |
| CPU time | 8.52 seconds |
| Started | Oct 09 04:09:56 PM UTC 24 |
| Finished | Oct 09 04:10:05 PM UTC 24 |
| Peak memory | 227560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392256857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.392256857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/30.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.1320727357 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 19058521 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 04:09:55 PM UTC 24 |
| Finished | Oct 09 04:09:57 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320727357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1320727357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/30.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_upload.723242087 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 1560484599 ps |
| CPU time | 3.37 seconds |
| Started | Oct 09 04:10:04 PM UTC 24 |
| Finished | Oct 09 04:10:09 PM UTC 24 |
| Peak memory | 234836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723242087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.723242087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/30.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_alert_test.661491006 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 11976811 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 04:10:24 PM UTC 24 |
| Finished | Oct 09 04:10:26 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661491006 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.661491006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/31.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_cfg_cmd.501355817 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 89101987 ps |
| CPU time | 3.88 seconds |
| Started | Oct 09 04:10:19 PM UTC 24 |
| Finished | Oct 09 04:10:24 PM UTC 24 |
| Peak memory | 245128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501355817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.501355817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/31.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_csb_read.627393893 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 18568085 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 04:10:12 PM UTC 24 |
| Finished | Oct 09 04:10:14 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627393893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.627393893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/31.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_all.13046241 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 38339825836 ps |
| CPU time | 158.35 seconds |
| Started | Oct 09 04:10:22 PM UTC 24 |
| Finished | Oct 09 04:13:03 PM UTC 24 |
| Peak memory | 261644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13046241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.13046241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/31.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.343576339 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 4272401416 ps |
| CPU time | 71.24 seconds |
| Started | Oct 09 04:10:22 PM UTC 24 |
| Finished | Oct 09 04:11:35 PM UTC 24 |
| Peak memory | 265804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343576339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.343576339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode.649547840 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 2357563529 ps |
| CPU time | 7.47 seconds |
| Started | Oct 09 04:10:19 PM UTC 24 |
| Finished | Oct 09 04:10:27 PM UTC 24 |
| Peak memory | 235152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649547840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.649547840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/31.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.1160128195 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 3416308012 ps |
| CPU time | 46.26 seconds |
| Started | Oct 09 04:10:20 PM UTC 24 |
| Finished | Oct 09 04:11:08 PM UTC 24 |
| Peak memory | 267916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160128195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.1160128195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_intercept.4141995410 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 1208936364 ps |
| CPU time | 5.86 seconds |
| Started | Oct 09 04:10:16 PM UTC 24 |
| Finished | Oct 09 04:10:23 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141995410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4141995410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/31.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_mailbox.681977814 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 4066481277 ps |
| CPU time | 64.47 seconds |
| Started | Oct 09 04:10:18 PM UTC 24 |
| Finished | Oct 09 04:11:24 PM UTC 24 |
| Peak memory | 235084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681977814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.681977814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/31.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.4017454343 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 173540875 ps |
| CPU time | 3.57 seconds |
| Started | Oct 09 04:10:16 PM UTC 24 |
| Finished | Oct 09 04:10:21 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017454343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.4017454343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/31.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.182964738 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 77114940 ps |
| CPU time | 3.25 seconds |
| Started | Oct 09 04:10:15 PM UTC 24 |
| Finished | Oct 09 04:10:19 PM UTC 24 |
| Peak memory | 234344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182964738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.182964738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/31.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.3371502508 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 4012255464 ps |
| CPU time | 14.3 seconds |
| Started | Oct 09 04:10:21 PM UTC 24 |
| Finished | Oct 09 04:10:37 PM UTC 24 |
| Peak memory | 233712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371502508 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.3371502508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/31.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.424212980 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 4117013561 ps |
| CPU time | 47.42 seconds |
| Started | Oct 09 04:10:24 PM UTC 24 |
| Finished | Oct 09 04:11:13 PM UTC 24 |
| Peak memory | 263816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424212980 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.424212980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/31.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_all.516020147 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 1324150825 ps |
| CPU time | 21.11 seconds |
| Started | Oct 09 04:10:14 PM UTC 24 |
| Finished | Oct 09 04:10:36 PM UTC 24 |
| Peak memory | 227556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516020147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.516020147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/31.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.3335576339 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 1142073376 ps |
| CPU time | 6.16 seconds |
| Started | Oct 09 04:10:14 PM UTC 24 |
| Finished | Oct 09 04:10:21 PM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335576339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3335576339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/31.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_rw.3373542313 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 10326166 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 04:10:15 PM UTC 24 |
| Finished | Oct 09 04:10:17 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373542313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3373542313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/31.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.514544216 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 89450340 ps |
| CPU time | 1.4 seconds |
| Started | Oct 09 04:10:15 PM UTC 24 |
| Finished | Oct 09 04:10:17 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514544216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.514544216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/31.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_upload.2954190021 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 932970442 ps |
| CPU time | 8.61 seconds |
| Started | Oct 09 04:10:19 PM UTC 24 |
| Finished | Oct 09 04:10:28 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954190021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2954190021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/31.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_alert_test.3145300843 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 12430254 ps |
| CPU time | 0.99 seconds |
| Started | Oct 09 04:10:45 PM UTC 24 |
| Finished | Oct 09 04:10:47 PM UTC 24 |
| Peak memory | 214840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145300843 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.3145300843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/32.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_cfg_cmd.113262380 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 3947878174 ps |
| CPU time | 20.62 seconds |
| Started | Oct 09 04:10:35 PM UTC 24 |
| Finished | Oct 09 04:10:57 PM UTC 24 |
| Peak memory | 245320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113262380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.113262380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/32.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_csb_read.308870553 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 57131910 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 04:10:25 PM UTC 24 |
| Finished | Oct 09 04:10:27 PM UTC 24 |
| Peak memory | 214744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308870553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.308870553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/32.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_all.2500338329 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 4783053027 ps |
| CPU time | 68.95 seconds |
| Started | Oct 09 04:10:39 PM UTC 24 |
| Finished | Oct 09 04:11:50 PM UTC 24 |
| Peak memory | 261644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500338329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2500338329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/32.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.248272591 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 78643853852 ps |
| CPU time | 198.12 seconds |
| Started | Oct 09 04:10:40 PM UTC 24 |
| Finished | Oct 09 04:14:02 PM UTC 24 |
| Peak memory | 261776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248272591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.248272591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.4144198789 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 12967932221 ps |
| CPU time | 160.35 seconds |
| Started | Oct 09 04:10:42 PM UTC 24 |
| Finished | Oct 09 04:13:25 PM UTC 24 |
| Peak memory | 267912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144198789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.4144198789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode.414373565 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 1575989337 ps |
| CPU time | 28.46 seconds |
| Started | Oct 09 04:10:37 PM UTC 24 |
| Finished | Oct 09 04:11:07 PM UTC 24 |
| Peak memory | 261576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414373565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.414373565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/32.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.3365455706 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 13701859308 ps |
| CPU time | 136.73 seconds |
| Started | Oct 09 04:10:37 PM UTC 24 |
| Finished | Oct 09 04:12:56 PM UTC 24 |
| Peak memory | 265872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365455706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.3365455706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_intercept.2452243795 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 4311929039 ps |
| CPU time | 13.08 seconds |
| Started | Oct 09 04:10:31 PM UTC 24 |
| Finished | Oct 09 04:10:45 PM UTC 24 |
| Peak memory | 245392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452243795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2452243795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/32.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_mailbox.2460492402 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 1685376575 ps |
| CPU time | 9.56 seconds |
| Started | Oct 09 04:10:32 PM UTC 24 |
| Finished | Oct 09 04:10:43 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460492402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2460492402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/32.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.3856956154 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 8886197453 ps |
| CPU time | 23.73 seconds |
| Started | Oct 09 04:10:29 PM UTC 24 |
| Finished | Oct 09 04:10:55 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856956154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.3856956154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/32.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.2910231935 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 398606064 ps |
| CPU time | 7.5 seconds |
| Started | Oct 09 04:10:29 PM UTC 24 |
| Finished | Oct 09 04:10:38 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910231935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2910231935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/32.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.2048814809 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 2340754274 ps |
| CPU time | 16.44 seconds |
| Started | Oct 09 04:10:37 PM UTC 24 |
| Finished | Oct 09 04:10:55 PM UTC 24 |
| Peak memory | 233632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048814809 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.2048814809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/32.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.2594410015 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 460872902 ps |
| CPU time | 1.5 seconds |
| Started | Oct 09 04:10:44 PM UTC 24 |
| Finished | Oct 09 04:10:46 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594410015 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.2594410015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/32.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_all.3924183565 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 3070544179 ps |
| CPU time | 19.57 seconds |
| Started | Oct 09 04:10:27 PM UTC 24 |
| Finished | Oct 09 04:10:48 PM UTC 24 |
| Peak memory | 227816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924183565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3924183565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/32.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.2443545716 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 141708033 ps |
| CPU time | 1.95 seconds |
| Started | Oct 09 04:10:25 PM UTC 24 |
| Finished | Oct 09 04:10:28 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443545716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2443545716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/32.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_rw.3193324445 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 21031527 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 04:10:28 PM UTC 24 |
| Finished | Oct 09 04:10:30 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193324445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3193324445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/32.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.1081207561 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 203150636 ps |
| CPU time | 1.39 seconds |
| Started | Oct 09 04:10:28 PM UTC 24 |
| Finished | Oct 09 04:10:31 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081207561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1081207561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/32.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_upload.262506741 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 4326047295 ps |
| CPU time | 11.77 seconds |
| Started | Oct 09 04:10:32 PM UTC 24 |
| Finished | Oct 09 04:10:45 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262506741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.262506741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/32.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_alert_test.1547258328 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 42478788 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 04:11:03 PM UTC 24 |
| Finished | Oct 09 04:11:05 PM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547258328 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.1547258328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/33.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_cfg_cmd.2493008146 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 106723687 ps |
| CPU time | 3.03 seconds |
| Started | Oct 09 04:10:56 PM UTC 24 |
| Finished | Oct 09 04:11:00 PM UTC 24 |
| Peak memory | 233744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493008146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2493008146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/33.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_csb_read.163792524 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 24118528 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 04:10:46 PM UTC 24 |
| Finished | Oct 09 04:10:48 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163792524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.163792524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/33.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_all.786721499 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 659517152 ps |
| CPU time | 13.27 seconds |
| Started | Oct 09 04:11:01 PM UTC 24 |
| Finished | Oct 09 04:11:16 PM UTC 24 |
| Peak memory | 247500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786721499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.786721499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/33.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.3250458244 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 35623141254 ps |
| CPU time | 154.6 seconds |
| Started | Oct 09 04:11:02 PM UTC 24 |
| Finished | Oct 09 04:13:39 PM UTC 24 |
| Peak memory | 267920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250458244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3250458244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.435475822 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 86102337121 ps |
| CPU time | 146.58 seconds |
| Started | Oct 09 04:11:03 PM UTC 24 |
| Finished | Oct 09 04:13:32 PM UTC 24 |
| Peak memory | 265808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435475822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.435475822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode.303963989 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 64024579 ps |
| CPU time | 6.36 seconds |
| Started | Oct 09 04:10:57 PM UTC 24 |
| Finished | Oct 09 04:11:05 PM UTC 24 |
| Peak memory | 244000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303963989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.303963989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/33.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.3570122276 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 53066334 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 04:10:59 PM UTC 24 |
| Finished | Oct 09 04:11:01 PM UTC 24 |
| Peak memory | 225964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570122276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.3570122276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_intercept.4164334634 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 212668300 ps |
| CPU time | 5.29 seconds |
| Started | Oct 09 04:10:52 PM UTC 24 |
| Finished | Oct 09 04:10:58 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164334634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.4164334634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/33.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_mailbox.3079160162 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 226688476 ps |
| CPU time | 7.47 seconds |
| Started | Oct 09 04:10:52 PM UTC 24 |
| Finished | Oct 09 04:11:00 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079160162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3079160162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/33.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.2713716105 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 10937768052 ps |
| CPU time | 21.06 seconds |
| Started | Oct 09 04:10:50 PM UTC 24 |
| Finished | Oct 09 04:11:12 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713716105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.2713716105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/33.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.3442251749 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 6984390756 ps |
| CPU time | 11.43 seconds |
| Started | Oct 09 04:10:48 PM UTC 24 |
| Finished | Oct 09 04:11:01 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442251749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3442251749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/33.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.1432181965 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 143584756 ps |
| CPU time | 5.13 seconds |
| Started | Oct 09 04:11:01 PM UTC 24 |
| Finished | Oct 09 04:11:08 PM UTC 24 |
| Peak memory | 234680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432181965 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.1432181965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/33.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.1484157098 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 527649653 ps |
| CPU time | 1.58 seconds |
| Started | Oct 09 04:11:03 PM UTC 24 |
| Finished | Oct 09 04:11:06 PM UTC 24 |
| Peak memory | 216492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484157098 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.1484157098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/33.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_all.1435988342 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 6418404633 ps |
| CPU time | 38.35 seconds |
| Started | Oct 09 04:10:47 PM UTC 24 |
| Finished | Oct 09 04:11:27 PM UTC 24 |
| Peak memory | 227684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435988342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1435988342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/33.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.736180658 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 50943039973 ps |
| CPU time | 32.47 seconds |
| Started | Oct 09 04:10:46 PM UTC 24 |
| Finished | Oct 09 04:11:20 PM UTC 24 |
| Peak memory | 227556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736180658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.736180658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/33.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_rw.1510872843 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 26682168 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 04:10:48 PM UTC 24 |
| Finished | Oct 09 04:10:51 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510872843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1510872843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/33.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.2581476335 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 207732129 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 04:10:48 PM UTC 24 |
| Finished | Oct 09 04:10:51 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581476335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2581476335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/33.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_upload.3257343009 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 803539232 ps |
| CPU time | 5.04 seconds |
| Started | Oct 09 04:10:55 PM UTC 24 |
| Finished | Oct 09 04:11:01 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257343009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3257343009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/33.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_alert_test.3805895967 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 35052491 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 04:11:15 PM UTC 24 |
| Finished | Oct 09 04:11:17 PM UTC 24 |
| Peak memory | 214840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805895967 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.3805895967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/34.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_cfg_cmd.3551428395 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 253317979 ps |
| CPU time | 3.61 seconds |
| Started | Oct 09 04:11:10 PM UTC 24 |
| Finished | Oct 09 04:11:15 PM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551428395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3551428395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/34.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_csb_read.4289512861 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 52297584 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 04:11:03 PM UTC 24 |
| Finished | Oct 09 04:11:05 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289512861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.4289512861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/34.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_all.2555153551 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 34913252637 ps |
| CPU time | 196.17 seconds |
| Started | Oct 09 04:11:14 PM UTC 24 |
| Finished | Oct 09 04:14:33 PM UTC 24 |
| Peak memory | 284244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555153551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2555153551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/34.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.1396954662 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 21871356280 ps |
| CPU time | 43.24 seconds |
| Started | Oct 09 04:11:14 PM UTC 24 |
| Finished | Oct 09 04:11:59 PM UTC 24 |
| Peak memory | 244256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396954662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1396954662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/34.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.724634199 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 21456930525 ps |
| CPU time | 101.62 seconds |
| Started | Oct 09 04:11:14 PM UTC 24 |
| Finished | Oct 09 04:12:58 PM UTC 24 |
| Peak memory | 276048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724634199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.724634199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode.3418270477 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 78281100 ps |
| CPU time | 2.99 seconds |
| Started | Oct 09 04:11:10 PM UTC 24 |
| Finished | Oct 09 04:11:14 PM UTC 24 |
| Peak memory | 245132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418270477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3418270477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/34.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.3351974217 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 1909609201 ps |
| CPU time | 33 seconds |
| Started | Oct 09 04:11:11 PM UTC 24 |
| Finished | Oct 09 04:11:46 PM UTC 24 |
| Peak memory | 247372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351974217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.3351974217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_intercept.964856320 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 207337455 ps |
| CPU time | 4.4 seconds |
| Started | Oct 09 04:11:09 PM UTC 24 |
| Finished | Oct 09 04:11:14 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964856320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.964856320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/34.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_mailbox.3254367265 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 189345099 ps |
| CPU time | 5.36 seconds |
| Started | Oct 09 04:11:09 PM UTC 24 |
| Finished | Oct 09 04:11:15 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254367265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3254367265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/34.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.2900356583 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 1976198971 ps |
| CPU time | 15.93 seconds |
| Started | Oct 09 04:11:08 PM UTC 24 |
| Finished | Oct 09 04:11:25 PM UTC 24 |
| Peak memory | 251404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900356583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.2900356583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/34.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.1356148067 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 51073419073 ps |
| CPU time | 20.53 seconds |
| Started | Oct 09 04:11:08 PM UTC 24 |
| Finished | Oct 09 04:11:29 PM UTC 24 |
| Peak memory | 235152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356148067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1356148067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/34.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.557697403 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 889607157 ps |
| CPU time | 8.54 seconds |
| Started | Oct 09 04:11:12 PM UTC 24 |
| Finished | Oct 09 04:11:22 PM UTC 24 |
| Peak memory | 231524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557697403 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.557697403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/34.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.517570405 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 19027152375 ps |
| CPU time | 124.14 seconds |
| Started | Oct 09 04:11:15 PM UTC 24 |
| Finished | Oct 09 04:13:22 PM UTC 24 |
| Peak memory | 261764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517570405 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.517570405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/34.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_all.3024332802 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 754430491 ps |
| CPU time | 3.01 seconds |
| Started | Oct 09 04:11:06 PM UTC 24 |
| Finished | Oct 09 04:11:10 PM UTC 24 |
| Peak memory | 227692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024332802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3024332802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/34.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.3675674592 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 14140919 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 04:11:05 PM UTC 24 |
| Finished | Oct 09 04:11:07 PM UTC 24 |
| Peak memory | 214856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675674592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3675674592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/34.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_rw.1766354784 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 104248600 ps |
| CPU time | 1.02 seconds |
| Started | Oct 09 04:11:06 PM UTC 24 |
| Finished | Oct 09 04:11:09 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766354784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1766354784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/34.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.1473346509 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 145768130 ps |
| CPU time | 1.34 seconds |
| Started | Oct 09 04:11:06 PM UTC 24 |
| Finished | Oct 09 04:11:09 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473346509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1473346509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/34.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_upload.1730454013 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 211506770 ps |
| CPU time | 3.17 seconds |
| Started | Oct 09 04:11:09 PM UTC 24 |
| Finished | Oct 09 04:11:13 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730454013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1730454013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/34.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_alert_test.2388366965 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 37449587 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 04:11:30 PM UTC 24 |
| Finished | Oct 09 04:11:32 PM UTC 24 |
| Peak memory | 212488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388366965 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.2388366965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/35.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_cfg_cmd.2103219809 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 2112195432 ps |
| CPU time | 19.88 seconds |
| Started | Oct 09 04:11:24 PM UTC 24 |
| Finished | Oct 09 04:11:46 PM UTC 24 |
| Peak memory | 234892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103219809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2103219809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/35.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_csb_read.3174382727 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 52452574 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 04:11:16 PM UTC 24 |
| Finished | Oct 09 04:11:18 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174382727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3174382727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/35.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.2670110115 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 54649201509 ps |
| CPU time | 436.83 seconds |
| Started | Oct 09 04:11:26 PM UTC 24 |
| Finished | Oct 09 04:18:49 PM UTC 24 |
| Peak memory | 267796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670110115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2670110115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/35.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.2151493829 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 4786315463 ps |
| CPU time | 20.57 seconds |
| Started | Oct 09 04:11:28 PM UTC 24 |
| Finished | Oct 09 04:11:50 PM UTC 24 |
| Peak memory | 229672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151493829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2151493829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.3789999908 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 43327170938 ps |
| CPU time | 156.18 seconds |
| Started | Oct 09 04:11:30 PM UTC 24 |
| Finished | Oct 09 04:14:09 PM UTC 24 |
| Peak memory | 263392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789999908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.3789999908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode.2478226191 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 31376838 ps |
| CPU time | 3.57 seconds |
| Started | Oct 09 04:11:24 PM UTC 24 |
| Finished | Oct 09 04:11:29 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478226191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2478226191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/35.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.2208572295 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1799008632 ps |
| CPU time | 32.59 seconds |
| Started | Oct 09 04:11:25 PM UTC 24 |
| Finished | Oct 09 04:11:59 PM UTC 24 |
| Peak memory | 261644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208572295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.2208572295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_intercept.1058482275 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 383244562 ps |
| CPU time | 13.09 seconds |
| Started | Oct 09 04:11:21 PM UTC 24 |
| Finished | Oct 09 04:11:35 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058482275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1058482275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/35.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_mailbox.716759424 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 1054693584 ps |
| CPU time | 13.44 seconds |
| Started | Oct 09 04:11:22 PM UTC 24 |
| Finished | Oct 09 04:11:37 PM UTC 24 |
| Peak memory | 251404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716759424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.716759424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/35.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.3130002495 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 856253704 ps |
| CPU time | 3.86 seconds |
| Started | Oct 09 04:11:20 PM UTC 24 |
| Finished | Oct 09 04:11:25 PM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130002495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.3130002495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/35.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.1641320809 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 2805569485 ps |
| CPU time | 17.75 seconds |
| Started | Oct 09 04:11:20 PM UTC 24 |
| Finished | Oct 09 04:11:39 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641320809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1641320809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/35.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.1810037058 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 145929372 ps |
| CPU time | 4.9 seconds |
| Started | Oct 09 04:11:26 PM UTC 24 |
| Finished | Oct 09 04:11:32 PM UTC 24 |
| Peak memory | 233632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810037058 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.1810037058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/35.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.62207628 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 806858120 ps |
| CPU time | 1.65 seconds |
| Started | Oct 09 04:11:30 PM UTC 24 |
| Finished | Oct 09 04:11:33 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62207628 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.62207628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/35.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_all.2212624061 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 1413332838 ps |
| CPU time | 16.01 seconds |
| Started | Oct 09 04:11:17 PM UTC 24 |
| Finished | Oct 09 04:11:35 PM UTC 24 |
| Peak memory | 227752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212624061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2212624061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/35.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.735405285 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 11986437 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 04:11:16 PM UTC 24 |
| Finished | Oct 09 04:11:18 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735405285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.735405285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/35.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_rw.3561060807 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 23514174 ps |
| CPU time | 1.91 seconds |
| Started | Oct 09 04:11:20 PM UTC 24 |
| Finished | Oct 09 04:11:23 PM UTC 24 |
| Peak memory | 226620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561060807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3561060807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/35.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.3530185731 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 20350968 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 04:11:19 PM UTC 24 |
| Finished | Oct 09 04:11:21 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530185731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3530185731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/35.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_upload.2800634340 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 4724381569 ps |
| CPU time | 13.47 seconds |
| Started | Oct 09 04:11:23 PM UTC 24 |
| Finished | Oct 09 04:11:38 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800634340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2800634340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/35.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_alert_test.2707784571 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 20491537 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 04:11:48 PM UTC 24 |
| Finished | Oct 09 04:11:50 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707784571 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.2707784571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/36.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_cfg_cmd.15881405 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 2012911710 ps |
| CPU time | 9.17 seconds |
| Started | Oct 09 04:11:39 PM UTC 24 |
| Finished | Oct 09 04:11:50 PM UTC 24 |
| Peak memory | 234952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15881405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.15881405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/36.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_csb_read.494748523 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 24505344 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 04:11:32 PM UTC 24 |
| Finished | Oct 09 04:11:35 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494748523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.494748523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/36.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_all.2893168010 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 8681589945 ps |
| CPU time | 63.49 seconds |
| Started | Oct 09 04:11:46 PM UTC 24 |
| Finished | Oct 09 04:12:51 PM UTC 24 |
| Peak memory | 261652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893168010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2893168010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/36.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.3188724008 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1227044273 ps |
| CPU time | 31.42 seconds |
| Started | Oct 09 04:11:47 PM UTC 24 |
| Finished | Oct 09 04:12:20 PM UTC 24 |
| Peak memory | 261640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188724008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3188724008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/36.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.3750741295 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 86361376398 ps |
| CPU time | 207.01 seconds |
| Started | Oct 09 04:11:47 PM UTC 24 |
| Finished | Oct 09 04:15:18 PM UTC 24 |
| Peak memory | 267912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750741295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.3750741295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode.1279246660 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 103908748 ps |
| CPU time | 4.04 seconds |
| Started | Oct 09 04:11:41 PM UTC 24 |
| Finished | Oct 09 04:11:46 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279246660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1279246660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/36.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.4288333652 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 593296414242 ps |
| CPU time | 263.48 seconds |
| Started | Oct 09 04:11:41 PM UTC 24 |
| Finished | Oct 09 04:16:08 PM UTC 24 |
| Peak memory | 261648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288333652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.4288333652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_intercept.3628595419 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 1383995986 ps |
| CPU time | 7.71 seconds |
| Started | Oct 09 04:11:38 PM UTC 24 |
| Finished | Oct 09 04:11:47 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628595419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3628595419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/36.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_mailbox.2195503482 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 1910578029 ps |
| CPU time | 24.81 seconds |
| Started | Oct 09 04:11:39 PM UTC 24 |
| Finished | Oct 09 04:12:06 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195503482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2195503482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/36.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.2313224189 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 6255846444 ps |
| CPU time | 10.89 seconds |
| Started | Oct 09 04:11:37 PM UTC 24 |
| Finished | Oct 09 04:11:49 PM UTC 24 |
| Peak memory | 229796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313224189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.2313224189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/36.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.990061356 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 2073774227 ps |
| CPU time | 6.39 seconds |
| Started | Oct 09 04:11:37 PM UTC 24 |
| Finished | Oct 09 04:11:45 PM UTC 24 |
| Peak memory | 235036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990061356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.990061356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/36.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.398062070 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 190256405 ps |
| CPU time | 4.47 seconds |
| Started | Oct 09 04:11:45 PM UTC 24 |
| Finished | Oct 09 04:11:50 PM UTC 24 |
| Peak memory | 231456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398062070 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.398062070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/36.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.651892964 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 54650030 ps |
| CPU time | 1.53 seconds |
| Started | Oct 09 04:11:47 PM UTC 24 |
| Finished | Oct 09 04:11:50 PM UTC 24 |
| Peak memory | 216316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651892964 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.651892964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/36.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_all.2250398893 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 5043493549 ps |
| CPU time | 25.91 seconds |
| Started | Oct 09 04:11:34 PM UTC 24 |
| Finished | Oct 09 04:12:01 PM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250398893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2250398893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/36.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.2653906337 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 7001440337 ps |
| CPU time | 22.08 seconds |
| Started | Oct 09 04:11:34 PM UTC 24 |
| Finished | Oct 09 04:11:57 PM UTC 24 |
| Peak memory | 227564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653906337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2653906337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/36.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_rw.3921375290 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 88966913 ps |
| CPU time | 1.83 seconds |
| Started | Oct 09 04:11:36 PM UTC 24 |
| Finished | Oct 09 04:11:39 PM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921375290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3921375290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/36.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.3735933334 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 227364289 ps |
| CPU time | 1.48 seconds |
| Started | Oct 09 04:11:36 PM UTC 24 |
| Finished | Oct 09 04:11:39 PM UTC 24 |
| Peak memory | 214856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735933334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3735933334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/36.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_upload.1349599243 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 2339550888 ps |
| CPU time | 12.84 seconds |
| Started | Oct 09 04:11:39 PM UTC 24 |
| Finished | Oct 09 04:11:54 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349599243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1349599243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/36.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_alert_test.1933435644 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 30072898 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 04:11:59 PM UTC 24 |
| Finished | Oct 09 04:12:02 PM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933435644 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.1933435644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/37.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_cfg_cmd.681062186 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 124604805 ps |
| CPU time | 3.9 seconds |
| Started | Oct 09 04:11:55 PM UTC 24 |
| Finished | Oct 09 04:12:00 PM UTC 24 |
| Peak memory | 235144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681062186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.681062186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/37.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_csb_read.1954676987 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 125940730 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 04:11:51 PM UTC 24 |
| Finished | Oct 09 04:11:53 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954676987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1954676987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/37.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.748202009 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 2278231234 ps |
| CPU time | 14.78 seconds |
| Started | Oct 09 04:11:58 PM UTC 24 |
| Finished | Oct 09 04:12:14 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748202009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.748202009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/37.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.3247736610 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 28404134098 ps |
| CPU time | 89.6 seconds |
| Started | Oct 09 04:11:59 PM UTC 24 |
| Finished | Oct 09 04:13:31 PM UTC 24 |
| Peak memory | 278156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247736610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3247736610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/37.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1437574960 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 10461600277 ps |
| CPU time | 114.82 seconds |
| Started | Oct 09 04:11:59 PM UTC 24 |
| Finished | Oct 09 04:13:56 PM UTC 24 |
| Peak memory | 268104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437574960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.1437574960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode.1614642592 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 392873709 ps |
| CPU time | 8.24 seconds |
| Started | Oct 09 04:11:55 PM UTC 24 |
| Finished | Oct 09 04:12:04 PM UTC 24 |
| Peak memory | 245332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614642592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1614642592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/37.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.1797948401 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 36018256922 ps |
| CPU time | 316.54 seconds |
| Started | Oct 09 04:11:57 PM UTC 24 |
| Finished | Oct 09 04:17:18 PM UTC 24 |
| Peak memory | 278156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797948401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.1797948401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_intercept.3271158764 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 538957682 ps |
| CPU time | 3.95 seconds |
| Started | Oct 09 04:11:53 PM UTC 24 |
| Finished | Oct 09 04:11:58 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271158764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3271158764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/37.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_mailbox.4122049281 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 899745580 ps |
| CPU time | 10.85 seconds |
| Started | Oct 09 04:11:54 PM UTC 24 |
| Finished | Oct 09 04:12:07 PM UTC 24 |
| Peak memory | 245124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122049281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.4122049281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/37.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.2920505050 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 40227705048 ps |
| CPU time | 10.63 seconds |
| Started | Oct 09 04:11:52 PM UTC 24 |
| Finished | Oct 09 04:12:04 PM UTC 24 |
| Peak memory | 235216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920505050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.2920505050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/37.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.108640996 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 2775805894 ps |
| CPU time | 5.2 seconds |
| Started | Oct 09 04:11:52 PM UTC 24 |
| Finished | Oct 09 04:11:58 PM UTC 24 |
| Peak memory | 245272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108640996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.108640996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/37.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.3190143979 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 99734427 ps |
| CPU time | 5.38 seconds |
| Started | Oct 09 04:11:57 PM UTC 24 |
| Finished | Oct 09 04:12:03 PM UTC 24 |
| Peak memory | 233568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190143979 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.3190143979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/37.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.806018419 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 56010577005 ps |
| CPU time | 558.9 seconds |
| Started | Oct 09 04:11:59 PM UTC 24 |
| Finished | Oct 09 04:21:26 PM UTC 24 |
| Peak memory | 278284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806018419 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.806018419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/37.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_all.1164400409 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 499538849 ps |
| CPU time | 3.98 seconds |
| Started | Oct 09 04:11:51 PM UTC 24 |
| Finished | Oct 09 04:11:56 PM UTC 24 |
| Peak memory | 227556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164400409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1164400409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/37.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.3183019998 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 4229061105 ps |
| CPU time | 9.5 seconds |
| Started | Oct 09 04:11:51 PM UTC 24 |
| Finished | Oct 09 04:12:01 PM UTC 24 |
| Peak memory | 227624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183019998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3183019998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/37.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_rw.1688894621 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 276922369 ps |
| CPU time | 1.91 seconds |
| Started | Oct 09 04:11:51 PM UTC 24 |
| Finished | Oct 09 04:11:54 PM UTC 24 |
| Peak memory | 226892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688894621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1688894621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/37.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.267830333 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 14827983 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 04:11:51 PM UTC 24 |
| Finished | Oct 09 04:11:53 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267830333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.267830333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/37.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_upload.3555458720 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 30516422988 ps |
| CPU time | 39.77 seconds |
| Started | Oct 09 04:11:55 PM UTC 24 |
| Finished | Oct 09 04:12:36 PM UTC 24 |
| Peak memory | 234984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555458720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3555458720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/37.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_alert_test.4009984489 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 36324418 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 04:12:15 PM UTC 24 |
| Finished | Oct 09 04:12:17 PM UTC 24 |
| Peak memory | 214840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009984489 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.4009984489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/38.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_cfg_cmd.2434707967 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 323273072 ps |
| CPU time | 3.34 seconds |
| Started | Oct 09 04:12:07 PM UTC 24 |
| Finished | Oct 09 04:12:11 PM UTC 24 |
| Peak memory | 235012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434707967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2434707967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/38.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_csb_read.2927167942 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 16284572 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 04:12:00 PM UTC 24 |
| Finished | Oct 09 04:12:02 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927167942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2927167942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/38.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_all.2867920684 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 2158793324 ps |
| CPU time | 68.03 seconds |
| Started | Oct 09 04:12:10 PM UTC 24 |
| Finished | Oct 09 04:13:20 PM UTC 24 |
| Peak memory | 267796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867920684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2867920684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/38.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.1706507112 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 27216755807 ps |
| CPU time | 276.27 seconds |
| Started | Oct 09 04:12:10 PM UTC 24 |
| Finished | Oct 09 04:16:51 PM UTC 24 |
| Peak memory | 265868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706507112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1706507112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/38.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.2499508908 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 65408278153 ps |
| CPU time | 75.78 seconds |
| Started | Oct 09 04:12:11 PM UTC 24 |
| Finished | Oct 09 04:13:29 PM UTC 24 |
| Peak memory | 244124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499508908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.2499508908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode.927735217 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 13642761083 ps |
| CPU time | 52.08 seconds |
| Started | Oct 09 04:12:07 PM UTC 24 |
| Finished | Oct 09 04:13:00 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927735217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.927735217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/38.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.1562517187 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 2192774373 ps |
| CPU time | 35.56 seconds |
| Started | Oct 09 04:12:08 PM UTC 24 |
| Finished | Oct 09 04:12:45 PM UTC 24 |
| Peak memory | 261644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562517187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.1562517187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_intercept.2017760951 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 584372752 ps |
| CPU time | 11.9 seconds |
| Started | Oct 09 04:12:05 PM UTC 24 |
| Finished | Oct 09 04:12:19 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017760951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2017760951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/38.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_mailbox.4287350792 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 286099720 ps |
| CPU time | 3.15 seconds |
| Started | Oct 09 04:12:06 PM UTC 24 |
| Finished | Oct 09 04:12:10 PM UTC 24 |
| Peak memory | 234036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287350792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.4287350792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/38.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.995776821 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 1005493380 ps |
| CPU time | 11.06 seconds |
| Started | Oct 09 04:12:04 PM UTC 24 |
| Finished | Oct 09 04:12:16 PM UTC 24 |
| Peak memory | 234908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995776821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.995776821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/38.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.2225080208 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 19775908793 ps |
| CPU time | 31.36 seconds |
| Started | Oct 09 04:12:03 PM UTC 24 |
| Finished | Oct 09 04:12:36 PM UTC 24 |
| Peak memory | 245516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225080208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2225080208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/38.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.3625214912 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 1272555169 ps |
| CPU time | 11.96 seconds |
| Started | Oct 09 04:12:09 PM UTC 24 |
| Finished | Oct 09 04:12:22 PM UTC 24 |
| Peak memory | 233568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625214912 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.3625214912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/38.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.2943018051 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 262210935946 ps |
| CPU time | 646.91 seconds |
| Started | Oct 09 04:12:13 PM UTC 24 |
| Finished | Oct 09 04:23:08 PM UTC 24 |
| Peak memory | 278100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943018051 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.2943018051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/38.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_all.2811842036 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 626701208 ps |
| CPU time | 7.07 seconds |
| Started | Oct 09 04:12:02 PM UTC 24 |
| Finished | Oct 09 04:12:10 PM UTC 24 |
| Peak memory | 227676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811842036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2811842036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/38.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.1736165230 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 553807882 ps |
| CPU time | 7.74 seconds |
| Started | Oct 09 04:12:01 PM UTC 24 |
| Finished | Oct 09 04:12:10 PM UTC 24 |
| Peak memory | 227592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736165230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1736165230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/38.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_rw.2086183180 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 44911348 ps |
| CPU time | 1.93 seconds |
| Started | Oct 09 04:12:03 PM UTC 24 |
| Finished | Oct 09 04:12:06 PM UTC 24 |
| Peak memory | 227064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086183180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2086183180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/38.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.1829854383 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 60443862 ps |
| CPU time | 1.36 seconds |
| Started | Oct 09 04:12:02 PM UTC 24 |
| Finished | Oct 09 04:12:04 PM UTC 24 |
| Peak memory | 214856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829854383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1829854383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/38.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_upload.279240332 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 399236455 ps |
| CPU time | 7.29 seconds |
| Started | Oct 09 04:12:06 PM UTC 24 |
| Finished | Oct 09 04:12:14 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279240332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.279240332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/38.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_alert_test.646877238 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 44031661 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 04:12:37 PM UTC 24 |
| Finished | Oct 09 04:12:39 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646877238 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.646877238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/39.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_cfg_cmd.378622185 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 1551951286 ps |
| CPU time | 6.78 seconds |
| Started | Oct 09 04:12:25 PM UTC 24 |
| Finished | Oct 09 04:12:33 PM UTC 24 |
| Peak memory | 245320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378622185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.378622185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/39.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_csb_read.167445012 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 77664034 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 04:12:15 PM UTC 24 |
| Finished | Oct 09 04:12:17 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167445012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.167445012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/39.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.2400025105 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 755039946 ps |
| CPU time | 15.29 seconds |
| Started | Oct 09 04:12:34 PM UTC 24 |
| Finished | Oct 09 04:12:50 PM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400025105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2400025105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/39.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.1458222786 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 43221123027 ps |
| CPU time | 430.38 seconds |
| Started | Oct 09 04:12:35 PM UTC 24 |
| Finished | Oct 09 04:19:51 PM UTC 24 |
| Peak memory | 261764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458222786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1458222786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/39.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.2565456518 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 30506622845 ps |
| CPU time | 156.41 seconds |
| Started | Oct 09 04:12:35 PM UTC 24 |
| Finished | Oct 09 04:15:14 PM UTC 24 |
| Peak memory | 265800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565456518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.2565456518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.4150236687 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 173547373 ps |
| CPU time | 3.89 seconds |
| Started | Oct 09 04:12:26 PM UTC 24 |
| Finished | Oct 09 04:12:31 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150236687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.4150236687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/39.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.4063659307 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 15779941438 ps |
| CPU time | 51.02 seconds |
| Started | Oct 09 04:12:32 PM UTC 24 |
| Finished | Oct 09 04:13:25 PM UTC 24 |
| Peak memory | 261704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063659307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.4063659307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_intercept.406471812 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 1142466627 ps |
| CPU time | 11.82 seconds |
| Started | Oct 09 04:12:22 PM UTC 24 |
| Finished | Oct 09 04:12:35 PM UTC 24 |
| Peak memory | 245452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406471812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.406471812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/39.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_mailbox.1134394485 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 8470257576 ps |
| CPU time | 90.35 seconds |
| Started | Oct 09 04:12:23 PM UTC 24 |
| Finished | Oct 09 04:13:55 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134394485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1134394485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/39.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.2484117936 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 373782010 ps |
| CPU time | 3.33 seconds |
| Started | Oct 09 04:12:21 PM UTC 24 |
| Finished | Oct 09 04:12:25 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484117936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.2484117936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/39.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.1923446805 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 423943677 ps |
| CPU time | 3.74 seconds |
| Started | Oct 09 04:12:19 PM UTC 24 |
| Finished | Oct 09 04:12:24 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923446805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1923446805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/39.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.2049536440 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 5177543610 ps |
| CPU time | 19.76 seconds |
| Started | Oct 09 04:12:33 PM UTC 24 |
| Finished | Oct 09 04:12:54 PM UTC 24 |
| Peak memory | 233568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049536440 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.2049536440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/39.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.4011547134 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 93017481805 ps |
| CPU time | 280.24 seconds |
| Started | Oct 09 04:12:36 PM UTC 24 |
| Finished | Oct 09 04:17:20 PM UTC 24 |
| Peak memory | 265868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011547134 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.4011547134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/39.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.4188978836 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 2326282277 ps |
| CPU time | 17.89 seconds |
| Started | Oct 09 04:12:17 PM UTC 24 |
| Finished | Oct 09 04:12:36 PM UTC 24 |
| Peak memory | 227736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188978836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.4188978836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/39.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.3918142999 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 3241125732 ps |
| CPU time | 16.78 seconds |
| Started | Oct 09 04:12:15 PM UTC 24 |
| Finished | Oct 09 04:12:33 PM UTC 24 |
| Peak memory | 227556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918142999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3918142999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/39.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_rw.119722376 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 248341006 ps |
| CPU time | 3.76 seconds |
| Started | Oct 09 04:12:18 PM UTC 24 |
| Finished | Oct 09 04:12:23 PM UTC 24 |
| Peak memory | 227564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119722376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.119722376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/39.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.2620679684 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 73462493 ps |
| CPU time | 1.59 seconds |
| Started | Oct 09 04:12:18 PM UTC 24 |
| Finished | Oct 09 04:12:21 PM UTC 24 |
| Peak memory | 214856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620679684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2620679684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/39.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_upload.786884846 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 3445733098 ps |
| CPU time | 26.49 seconds |
| Started | Oct 09 04:12:24 PM UTC 24 |
| Finished | Oct 09 04:12:52 PM UTC 24 |
| Peak memory | 261640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786884846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.786884846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/39.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.2113291052 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 24226892 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 03:58:01 PM UTC 24 |
| Finished | Oct 09 03:58:03 PM UTC 24 |
| Peak memory | 214840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113291052 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2113291052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.3372215107 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 134415291 ps |
| CPU time | 4.31 seconds |
| Started | Oct 09 03:57:44 PM UTC 24 |
| Finished | Oct 09 03:57:49 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372215107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3372215107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.2785087772 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 16526789 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 03:56:59 PM UTC 24 |
| Finished | Oct 09 03:57:01 PM UTC 24 |
| Peak memory | 214972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785087772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2785087772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.3953057636 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 7382315821 ps |
| CPU time | 48.45 seconds |
| Started | Oct 09 03:57:52 PM UTC 24 |
| Finished | Oct 09 03:58:42 PM UTC 24 |
| Peak memory | 245460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953057636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.3953057636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.691303294 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1082352392 ps |
| CPU time | 17.06 seconds |
| Started | Oct 09 03:57:44 PM UTC 24 |
| Finished | Oct 09 03:58:02 PM UTC 24 |
| Peak memory | 251340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691303294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.691303294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.62458938 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 5413121032 ps |
| CPU time | 55.61 seconds |
| Started | Oct 09 03:57:45 PM UTC 24 |
| Finished | Oct 09 03:58:42 PM UTC 24 |
| Peak memory | 249560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62458938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.62458938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.354756229 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 652595846 ps |
| CPU time | 4.98 seconds |
| Started | Oct 09 03:57:36 PM UTC 24 |
| Finished | Oct 09 03:57:42 PM UTC 24 |
| Peak memory | 234892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354756229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.354756229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.2670726231 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 4919357418 ps |
| CPU time | 51.38 seconds |
| Started | Oct 09 03:57:37 PM UTC 24 |
| Finished | Oct 09 03:58:30 PM UTC 24 |
| Peak memory | 235088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670726231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2670726231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.1671917279 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 42437339 ps |
| CPU time | 1.54 seconds |
| Started | Oct 09 03:57:02 PM UTC 24 |
| Finished | Oct 09 03:57:05 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671917279 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_parity.1671917279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.3370551859 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 118621252 ps |
| CPU time | 3.95 seconds |
| Started | Oct 09 03:57:30 PM UTC 24 |
| Finished | Oct 09 03:57:35 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370551859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.3370551859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.3608171280 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1790295966 ps |
| CPU time | 10.4 seconds |
| Started | Oct 09 03:57:27 PM UTC 24 |
| Finished | Oct 09 03:57:39 PM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608171280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3608171280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.3167095778 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 2956183123 ps |
| CPU time | 11.87 seconds |
| Started | Oct 09 03:57:47 PM UTC 24 |
| Finished | Oct 09 03:58:00 PM UTC 24 |
| Peak memory | 231480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167095778 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.3167095778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.3080029469 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 115725807 ps |
| CPU time | 1.81 seconds |
| Started | Oct 09 03:57:59 PM UTC 24 |
| Finished | Oct 09 03:58:01 PM UTC 24 |
| Peak memory | 257636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080029469 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3080029469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.3864293677 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 40939318547 ps |
| CPU time | 584.58 seconds |
| Started | Oct 09 03:57:57 PM UTC 24 |
| Finished | Oct 09 04:07:50 PM UTC 24 |
| Peak memory | 284300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864293677 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.3864293677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.484589503 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 755738943 ps |
| CPU time | 12.5 seconds |
| Started | Oct 09 03:57:23 PM UTC 24 |
| Finished | Oct 09 03:57:37 PM UTC 24 |
| Peak memory | 229720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484589503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.484589503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2908662794 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 946848827 ps |
| CPU time | 14.32 seconds |
| Started | Oct 09 03:57:05 PM UTC 24 |
| Finished | Oct 09 03:57:21 PM UTC 24 |
| Peak memory | 227588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908662794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2908662794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.334647930 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 626025772 ps |
| CPU time | 2.2 seconds |
| Started | Oct 09 03:57:26 PM UTC 24 |
| Finished | Oct 09 03:57:29 PM UTC 24 |
| Peak memory | 227616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334647930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.334647930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.695023460 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 28452346 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 03:57:23 PM UTC 24 |
| Finished | Oct 09 03:57:25 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695023460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.695023460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.3221052080 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1134774955 ps |
| CPU time | 5.25 seconds |
| Started | Oct 09 03:57:39 PM UTC 24 |
| Finished | Oct 09 03:57:46 PM UTC 24 |
| Peak memory | 234948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221052080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3221052080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/4.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.2835277786 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 23052172 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 04:12:58 PM UTC 24 |
| Finished | Oct 09 04:13:00 PM UTC 24 |
| Peak memory | 214840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835277786 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.2835277786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/40.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_cfg_cmd.2339582253 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 388280449 ps |
| CPU time | 2.25 seconds |
| Started | Oct 09 04:12:52 PM UTC 24 |
| Finished | Oct 09 04:12:55 PM UTC 24 |
| Peak memory | 234644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339582253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2339582253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/40.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_csb_read.2894430536 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 61152087 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 04:12:37 PM UTC 24 |
| Finished | Oct 09 04:12:39 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894430536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2894430536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/40.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.3094467503 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 50661109074 ps |
| CPU time | 121.55 seconds |
| Started | Oct 09 04:12:53 PM UTC 24 |
| Finished | Oct 09 04:14:57 PM UTC 24 |
| Peak memory | 261780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094467503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3094467503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/40.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.1332248986 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 163950967523 ps |
| CPU time | 232.9 seconds |
| Started | Oct 09 04:12:54 PM UTC 24 |
| Finished | Oct 09 04:16:51 PM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332248986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1332248986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.4164343936 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 16330385943 ps |
| CPU time | 142.57 seconds |
| Started | Oct 09 04:12:55 PM UTC 24 |
| Finished | Oct 09 04:15:21 PM UTC 24 |
| Peak memory | 284292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164343936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.4164343936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.2438151237 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 752137303 ps |
| CPU time | 16.59 seconds |
| Started | Oct 09 04:12:52 PM UTC 24 |
| Finished | Oct 09 04:13:10 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438151237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2438151237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/40.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.4237812020 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 41280015266 ps |
| CPU time | 179.39 seconds |
| Started | Oct 09 04:12:52 PM UTC 24 |
| Finished | Oct 09 04:15:54 PM UTC 24 |
| Peak memory | 261704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237812020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.4237812020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_intercept.2271140207 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 368437997 ps |
| CPU time | 4.58 seconds |
| Started | Oct 09 04:12:45 PM UTC 24 |
| Finished | Oct 09 04:12:51 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271140207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2271140207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/40.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.541167171 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 21356316481 ps |
| CPU time | 16.77 seconds |
| Started | Oct 09 04:12:46 PM UTC 24 |
| Finished | Oct 09 04:13:04 PM UTC 24 |
| Peak memory | 247304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541167171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.541167171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/40.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.1240349307 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 12365977400 ps |
| CPU time | 15.32 seconds |
| Started | Oct 09 04:12:44 PM UTC 24 |
| Finished | Oct 09 04:13:00 PM UTC 24 |
| Peak memory | 245320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240349307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.1240349307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/40.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.38359717 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 2530785534 ps |
| CPU time | 10.04 seconds |
| Started | Oct 09 04:12:43 PM UTC 24 |
| Finished | Oct 09 04:12:54 PM UTC 24 |
| Peak memory | 235268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38359717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.38359717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/40.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.2044415914 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 1829850985 ps |
| CPU time | 24.84 seconds |
| Started | Oct 09 04:12:53 PM UTC 24 |
| Finished | Oct 09 04:13:19 PM UTC 24 |
| Peak memory | 233568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044415914 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.2044415914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/40.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.2033222908 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 151916707335 ps |
| CPU time | 351.02 seconds |
| Started | Oct 09 04:12:57 PM UTC 24 |
| Finished | Oct 09 04:18:53 PM UTC 24 |
| Peak memory | 265808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033222908 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.2033222908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/40.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.504717205 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 4123303962 ps |
| CPU time | 21.92 seconds |
| Started | Oct 09 04:12:39 PM UTC 24 |
| Finished | Oct 09 04:13:03 PM UTC 24 |
| Peak memory | 227740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504717205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.504717205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/40.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.1885090744 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 5907651971 ps |
| CPU time | 29.33 seconds |
| Started | Oct 09 04:12:37 PM UTC 24 |
| Finished | Oct 09 04:13:08 PM UTC 24 |
| Peak memory | 227812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885090744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1885090744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/40.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_rw.2912940369 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 739781250 ps |
| CPU time | 2.6 seconds |
| Started | Oct 09 04:12:41 PM UTC 24 |
| Finished | Oct 09 04:12:44 PM UTC 24 |
| Peak memory | 227556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912940369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2912940369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/40.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.2872218621 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 186446971 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 04:12:40 PM UTC 24 |
| Finished | Oct 09 04:12:43 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872218621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2872218621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/40.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.246640755 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 886327126 ps |
| CPU time | 12.77 seconds |
| Started | Oct 09 04:12:50 PM UTC 24 |
| Finished | Oct 09 04:13:04 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246640755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.246640755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/40.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.3177935640 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 29221532 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 04:13:16 PM UTC 24 |
| Finished | Oct 09 04:13:18 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177935640 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.3177935640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/41.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.1352733464 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 99875538 ps |
| CPU time | 4.23 seconds |
| Started | Oct 09 04:13:05 PM UTC 24 |
| Finished | Oct 09 04:13:11 PM UTC 24 |
| Peak memory | 245256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352733464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1352733464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/41.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.911144731 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 20677949 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 04:12:59 PM UTC 24 |
| Finished | Oct 09 04:13:01 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911144731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.911144731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/41.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.3481290513 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 4526099841 ps |
| CPU time | 32.85 seconds |
| Started | Oct 09 04:13:10 PM UTC 24 |
| Finished | Oct 09 04:13:45 PM UTC 24 |
| Peak memory | 235016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481290513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3481290513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/41.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.479091992 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 34626396659 ps |
| CPU time | 210.49 seconds |
| Started | Oct 09 04:13:12 PM UTC 24 |
| Finished | Oct 09 04:16:46 PM UTC 24 |
| Peak memory | 261776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479091992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.479091992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.3145086030 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 4957852589 ps |
| CPU time | 79.66 seconds |
| Started | Oct 09 04:13:13 PM UTC 24 |
| Finished | Oct 09 04:14:34 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145086030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.3145086030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.2134422454 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 2253311703 ps |
| CPU time | 26.85 seconds |
| Started | Oct 09 04:13:09 PM UTC 24 |
| Finished | Oct 09 04:13:37 PM UTC 24 |
| Peak memory | 249416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134422454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2134422454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/41.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2848032019 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 1529622671 ps |
| CPU time | 27.76 seconds |
| Started | Oct 09 04:13:09 PM UTC 24 |
| Finished | Oct 09 04:13:38 PM UTC 24 |
| Peak memory | 263632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848032019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.2848032019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.3439140196 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 949066549 ps |
| CPU time | 11.92 seconds |
| Started | Oct 09 04:13:05 PM UTC 24 |
| Finished | Oct 09 04:13:18 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439140196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3439140196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/41.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.436930326 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 28696030 ps |
| CPU time | 3.03 seconds |
| Started | Oct 09 04:13:05 PM UTC 24 |
| Finished | Oct 09 04:13:09 PM UTC 24 |
| Peak memory | 233628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436930326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.436930326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/41.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.1102341494 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 1346239397 ps |
| CPU time | 13.87 seconds |
| Started | Oct 09 04:13:04 PM UTC 24 |
| Finished | Oct 09 04:13:19 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102341494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.1102341494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/41.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.3454997979 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 12665218141 ps |
| CPU time | 26.6 seconds |
| Started | Oct 09 04:13:02 PM UTC 24 |
| Finished | Oct 09 04:13:31 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454997979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3454997979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/41.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.1980640256 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 3827152712 ps |
| CPU time | 12.82 seconds |
| Started | Oct 09 04:13:10 PM UTC 24 |
| Finished | Oct 09 04:13:24 PM UTC 24 |
| Peak memory | 233696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980640256 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.1980640256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/41.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.657612162 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 198978260 ps |
| CPU time | 1.49 seconds |
| Started | Oct 09 04:13:13 PM UTC 24 |
| Finished | Oct 09 04:13:15 PM UTC 24 |
| Peak memory | 216432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657612162 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.657612162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/41.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.2090674521 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 2613172554 ps |
| CPU time | 8.99 seconds |
| Started | Oct 09 04:13:01 PM UTC 24 |
| Finished | Oct 09 04:13:12 PM UTC 24 |
| Peak memory | 227628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090674521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2090674521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/41.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.1672207922 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 4465208625 ps |
| CPU time | 14.35 seconds |
| Started | Oct 09 04:13:01 PM UTC 24 |
| Finished | Oct 09 04:13:17 PM UTC 24 |
| Peak memory | 227532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672207922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1672207922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/41.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.1131336261 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 197205120 ps |
| CPU time | 4.02 seconds |
| Started | Oct 09 04:13:02 PM UTC 24 |
| Finished | Oct 09 04:13:08 PM UTC 24 |
| Peak memory | 227560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131336261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1131336261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/41.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.2581272179 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 262869974 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 04:13:01 PM UTC 24 |
| Finished | Oct 09 04:13:04 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581272179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2581272179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/41.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.3705484890 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 1743405643 ps |
| CPU time | 12.32 seconds |
| Started | Oct 09 04:13:05 PM UTC 24 |
| Finished | Oct 09 04:13:19 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705484890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3705484890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/41.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.2934561730 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 13140784 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 04:13:32 PM UTC 24 |
| Finished | Oct 09 04:13:34 PM UTC 24 |
| Peak memory | 214840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934561730 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.2934561730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/42.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.812132243 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 123469021 ps |
| CPU time | 3.42 seconds |
| Started | Oct 09 04:13:25 PM UTC 24 |
| Finished | Oct 09 04:13:30 PM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812132243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.812132243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/42.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.3095872263 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 33288705 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 04:13:18 PM UTC 24 |
| Finished | Oct 09 04:13:21 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095872263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3095872263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/42.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.4264601115 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 38121218482 ps |
| CPU time | 182.23 seconds |
| Started | Oct 09 04:13:26 PM UTC 24 |
| Finished | Oct 09 04:16:32 PM UTC 24 |
| Peak memory | 265872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264601115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.4264601115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/42.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.3467673025 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 12731822751 ps |
| CPU time | 134.16 seconds |
| Started | Oct 09 04:13:27 PM UTC 24 |
| Finished | Oct 09 04:15:43 PM UTC 24 |
| Peak memory | 251456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467673025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3467673025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.3258453649 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 10814239952 ps |
| CPU time | 40.91 seconds |
| Started | Oct 09 04:13:30 PM UTC 24 |
| Finished | Oct 09 04:14:12 PM UTC 24 |
| Peak memory | 264004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258453649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.3258453649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.2588971619 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 1147331268 ps |
| CPU time | 21.43 seconds |
| Started | Oct 09 04:13:25 PM UTC 24 |
| Finished | Oct 09 04:13:48 PM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588971619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2588971619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/42.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.3006395386 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 1138639415 ps |
| CPU time | 22.44 seconds |
| Started | Oct 09 04:13:25 PM UTC 24 |
| Finished | Oct 09 04:13:49 PM UTC 24 |
| Peak memory | 261584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006395386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.3006395386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.3898990461 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 568012652 ps |
| CPU time | 11.18 seconds |
| Started | Oct 09 04:13:22 PM UTC 24 |
| Finished | Oct 09 04:13:34 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898990461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3898990461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/42.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.667223223 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 263177683 ps |
| CPU time | 12.24 seconds |
| Started | Oct 09 04:13:23 PM UTC 24 |
| Finished | Oct 09 04:13:36 PM UTC 24 |
| Peak memory | 251340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667223223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.667223223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/42.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.2689016238 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 2333966467 ps |
| CPU time | 15.17 seconds |
| Started | Oct 09 04:13:22 PM UTC 24 |
| Finished | Oct 09 04:13:38 PM UTC 24 |
| Peak memory | 249356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689016238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.2689016238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/42.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.3480582275 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 31592688 ps |
| CPU time | 3.41 seconds |
| Started | Oct 09 04:13:20 PM UTC 24 |
| Finished | Oct 09 04:13:25 PM UTC 24 |
| Peak memory | 244748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480582275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3480582275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/42.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.637823802 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 120658876 ps |
| CPU time | 4.85 seconds |
| Started | Oct 09 04:13:26 PM UTC 24 |
| Finished | Oct 09 04:13:32 PM UTC 24 |
| Peak memory | 229404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637823802 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.637823802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/42.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.2039644703 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 14165916675 ps |
| CPU time | 147.5 seconds |
| Started | Oct 09 04:13:31 PM UTC 24 |
| Finished | Oct 09 04:16:01 PM UTC 24 |
| Peak memory | 257624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039644703 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.2039644703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/42.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.2898593093 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 730732031 ps |
| CPU time | 10.22 seconds |
| Started | Oct 09 04:13:19 PM UTC 24 |
| Finished | Oct 09 04:13:31 PM UTC 24 |
| Peak memory | 227624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898593093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2898593093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/42.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.644816107 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 243820597 ps |
| CPU time | 3.05 seconds |
| Started | Oct 09 04:13:19 PM UTC 24 |
| Finished | Oct 09 04:13:24 PM UTC 24 |
| Peak memory | 217192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644816107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.644816107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/42.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.2770469460 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 88226335 ps |
| CPU time | 2.02 seconds |
| Started | Oct 09 04:13:20 PM UTC 24 |
| Finished | Oct 09 04:13:24 PM UTC 24 |
| Peak memory | 227816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770469460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2770469460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/42.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.273098772 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 245515575 ps |
| CPU time | 1.49 seconds |
| Started | Oct 09 04:13:20 PM UTC 24 |
| Finished | Oct 09 04:13:23 PM UTC 24 |
| Peak memory | 214584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273098772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.273098772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/42.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.3188653857 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 5848433594 ps |
| CPU time | 15.84 seconds |
| Started | Oct 09 04:13:24 PM UTC 24 |
| Finished | Oct 09 04:13:41 PM UTC 24 |
| Peak memory | 235084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188653857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3188653857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/42.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.172808983 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 21794686 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 04:13:42 PM UTC 24 |
| Finished | Oct 09 04:13:44 PM UTC 24 |
| Peak memory | 212856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172808983 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.172808983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/43.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.3849755949 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 1265430016 ps |
| CPU time | 11.12 seconds |
| Started | Oct 09 04:13:38 PM UTC 24 |
| Finished | Oct 09 04:13:50 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849755949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3849755949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/43.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.99724243 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 281194803 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 04:13:32 PM UTC 24 |
| Finished | Oct 09 04:13:34 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99724243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.99724243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/43.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.678140397 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 226219680 ps |
| CPU time | 1.45 seconds |
| Started | Oct 09 04:13:39 PM UTC 24 |
| Finished | Oct 09 04:13:42 PM UTC 24 |
| Peak memory | 225964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678140397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.678140397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/43.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.2677319443 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 10119559828 ps |
| CPU time | 73.98 seconds |
| Started | Oct 09 04:13:41 PM UTC 24 |
| Finished | Oct 09 04:14:57 PM UTC 24 |
| Peak memory | 261596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677319443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2677319443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.2155674923 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 9365796688 ps |
| CPU time | 78.36 seconds |
| Started | Oct 09 04:13:41 PM UTC 24 |
| Finished | Oct 09 04:15:01 PM UTC 24 |
| Peak memory | 279988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155674923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.2155674923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.3300655889 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 3177155398 ps |
| CPU time | 15.71 seconds |
| Started | Oct 09 04:13:39 PM UTC 24 |
| Finished | Oct 09 04:13:56 PM UTC 24 |
| Peak memory | 235160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300655889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3300655889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/43.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.1574980856 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 35140857008 ps |
| CPU time | 84.14 seconds |
| Started | Oct 09 04:13:39 PM UTC 24 |
| Finished | Oct 09 04:15:05 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574980856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.1574980856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.1696077522 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 67426353 ps |
| CPU time | 3.12 seconds |
| Started | Oct 09 04:13:37 PM UTC 24 |
| Finished | Oct 09 04:13:41 PM UTC 24 |
| Peak memory | 245396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696077522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1696077522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/43.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.2502761447 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 4538837495 ps |
| CPU time | 34.68 seconds |
| Started | Oct 09 04:13:37 PM UTC 24 |
| Finished | Oct 09 04:14:13 PM UTC 24 |
| Peak memory | 251408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502761447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2502761447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/43.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.2420237022 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 108911846 ps |
| CPU time | 2.9 seconds |
| Started | Oct 09 04:13:36 PM UTC 24 |
| Finished | Oct 09 04:13:40 PM UTC 24 |
| Peak memory | 234280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420237022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.2420237022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/43.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.490194427 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 108306326 ps |
| CPU time | 3.37 seconds |
| Started | Oct 09 04:13:35 PM UTC 24 |
| Finished | Oct 09 04:13:40 PM UTC 24 |
| Peak memory | 233564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490194427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.490194427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/43.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.4231507685 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 272025945 ps |
| CPU time | 3.6 seconds |
| Started | Oct 09 04:13:39 PM UTC 24 |
| Finished | Oct 09 04:13:44 PM UTC 24 |
| Peak memory | 231524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231507685 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.4231507685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/43.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.2021676204 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 54874501304 ps |
| CPU time | 542.29 seconds |
| Started | Oct 09 04:13:42 PM UTC 24 |
| Finished | Oct 09 04:22:51 PM UTC 24 |
| Peak memory | 282192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021676204 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.2021676204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/43.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.309511041 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 22565947034 ps |
| CPU time | 36.07 seconds |
| Started | Oct 09 04:13:33 PM UTC 24 |
| Finished | Oct 09 04:14:11 PM UTC 24 |
| Peak memory | 227752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309511041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.309511041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/43.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.1574085801 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 4330381714 ps |
| CPU time | 7.48 seconds |
| Started | Oct 09 04:13:32 PM UTC 24 |
| Finished | Oct 09 04:13:41 PM UTC 24 |
| Peak memory | 227564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574085801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1574085801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/43.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.3876610314 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 114841846 ps |
| CPU time | 2.25 seconds |
| Started | Oct 09 04:13:35 PM UTC 24 |
| Finished | Oct 09 04:13:39 PM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876610314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3876610314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/43.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.1444972410 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 32609218 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 04:13:33 PM UTC 24 |
| Finished | Oct 09 04:13:35 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444972410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1444972410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/43.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.2517242356 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 1221631236 ps |
| CPU time | 9.12 seconds |
| Started | Oct 09 04:13:37 PM UTC 24 |
| Finished | Oct 09 04:13:47 PM UTC 24 |
| Peak memory | 235016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517242356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2517242356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/43.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.231740699 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 18194600 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 04:14:01 PM UTC 24 |
| Finished | Oct 09 04:14:03 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231740699 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.231740699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/44.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.3741077157 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 964972692 ps |
| CPU time | 5.57 seconds |
| Started | Oct 09 04:13:50 PM UTC 24 |
| Finished | Oct 09 04:13:57 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741077157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3741077157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/44.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.2541891046 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 64439559 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 04:13:42 PM UTC 24 |
| Finished | Oct 09 04:13:44 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541891046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2541891046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/44.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.3094975867 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 6636206022 ps |
| CPU time | 40.24 seconds |
| Started | Oct 09 04:13:57 PM UTC 24 |
| Finished | Oct 09 04:14:38 PM UTC 24 |
| Peak memory | 251604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094975867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3094975867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/44.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.4281344008 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 22063599168 ps |
| CPU time | 144.22 seconds |
| Started | Oct 09 04:13:58 PM UTC 24 |
| Finished | Oct 09 04:16:25 PM UTC 24 |
| Peak memory | 265996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281344008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.4281344008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.1480770045 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 11741799907 ps |
| CPU time | 53.04 seconds |
| Started | Oct 09 04:13:58 PM UTC 24 |
| Finished | Oct 09 04:14:52 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480770045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.1480770045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.590697828 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 2369856698 ps |
| CPU time | 23.39 seconds |
| Started | Oct 09 04:13:51 PM UTC 24 |
| Finished | Oct 09 04:14:16 PM UTC 24 |
| Peak memory | 235080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590697828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.590697828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/44.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.3094519165 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 1755637174 ps |
| CPU time | 13.05 seconds |
| Started | Oct 09 04:13:52 PM UTC 24 |
| Finished | Oct 09 04:14:06 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094519165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.3094519165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.1037975704 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 166942889 ps |
| CPU time | 4 seconds |
| Started | Oct 09 04:13:49 PM UTC 24 |
| Finished | Oct 09 04:13:54 PM UTC 24 |
| Peak memory | 234892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037975704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1037975704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/44.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.1653088037 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 1701992602 ps |
| CPU time | 10.15 seconds |
| Started | Oct 09 04:13:49 PM UTC 24 |
| Finished | Oct 09 04:14:00 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653088037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1653088037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/44.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.356980311 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 601019494 ps |
| CPU time | 2.79 seconds |
| Started | Oct 09 04:13:48 PM UTC 24 |
| Finished | Oct 09 04:13:51 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356980311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.356980311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/44.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.512125728 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 122367563400 ps |
| CPU time | 32.99 seconds |
| Started | Oct 09 04:13:45 PM UTC 24 |
| Finished | Oct 09 04:14:20 PM UTC 24 |
| Peak memory | 261656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512125728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.512125728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/44.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.566195867 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 2520974501 ps |
| CPU time | 11.6 seconds |
| Started | Oct 09 04:13:54 PM UTC 24 |
| Finished | Oct 09 04:14:07 PM UTC 24 |
| Peak memory | 231464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566195867 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.566195867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/44.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.1170184139 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 21490163585 ps |
| CPU time | 135.23 seconds |
| Started | Oct 09 04:13:58 PM UTC 24 |
| Finished | Oct 09 04:16:15 PM UTC 24 |
| Peak memory | 278228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170184139 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.1170184139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/44.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.35227142 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 4448709013 ps |
| CPU time | 40.7 seconds |
| Started | Oct 09 04:13:45 PM UTC 24 |
| Finished | Oct 09 04:14:27 PM UTC 24 |
| Peak memory | 227680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35227142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.35227142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/44.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.1443320222 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 8327031589 ps |
| CPU time | 24.61 seconds |
| Started | Oct 09 04:13:43 PM UTC 24 |
| Finished | Oct 09 04:14:09 PM UTC 24 |
| Peak memory | 227692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443320222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1443320222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/44.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.1106379481 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 351142735 ps |
| CPU time | 1.36 seconds |
| Started | Oct 09 04:13:45 PM UTC 24 |
| Finished | Oct 09 04:13:48 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106379481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1106379481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/44.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.4009507527 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 536813013 ps |
| CPU time | 1.69 seconds |
| Started | Oct 09 04:13:45 PM UTC 24 |
| Finished | Oct 09 04:13:48 PM UTC 24 |
| Peak memory | 214856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009507527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4009507527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/44.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.1810284564 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 1381679914 ps |
| CPU time | 13.45 seconds |
| Started | Oct 09 04:13:49 PM UTC 24 |
| Finished | Oct 09 04:14:04 PM UTC 24 |
| Peak memory | 247312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810284564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1810284564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/44.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.2953185696 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 11831244 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 04:14:24 PM UTC 24 |
| Finished | Oct 09 04:14:26 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953185696 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.2953185696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/45.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.3963326488 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 610598825 ps |
| CPU time | 10.57 seconds |
| Started | Oct 09 04:14:11 PM UTC 24 |
| Finished | Oct 09 04:14:23 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963326488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3963326488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/45.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.3322906813 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 27279909 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 04:14:03 PM UTC 24 |
| Finished | Oct 09 04:14:05 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322906813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3322906813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/45.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.3926333038 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 18237478480 ps |
| CPU time | 239.57 seconds |
| Started | Oct 09 04:14:22 PM UTC 24 |
| Finished | Oct 09 04:18:26 PM UTC 24 |
| Peak memory | 276104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926333038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.3926333038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.1686661081 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 9991615979 ps |
| CPU time | 22.04 seconds |
| Started | Oct 09 04:14:12 PM UTC 24 |
| Finished | Oct 09 04:14:35 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686661081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1686661081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/45.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.3297184898 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 121936398181 ps |
| CPU time | 238.18 seconds |
| Started | Oct 09 04:14:13 PM UTC 24 |
| Finished | Oct 09 04:18:15 PM UTC 24 |
| Peak memory | 265996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297184898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.3297184898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.752447266 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 172662358 ps |
| CPU time | 5.27 seconds |
| Started | Oct 09 04:14:10 PM UTC 24 |
| Finished | Oct 09 04:14:16 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752447266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.752447266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/45.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.3980329434 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 1153539075 ps |
| CPU time | 23.81 seconds |
| Started | Oct 09 04:14:10 PM UTC 24 |
| Finished | Oct 09 04:14:35 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980329434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3980329434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/45.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.1818610464 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 1205451970 ps |
| CPU time | 12.41 seconds |
| Started | Oct 09 04:14:10 PM UTC 24 |
| Finished | Oct 09 04:14:23 PM UTC 24 |
| Peak memory | 251532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818610464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.1818610464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/45.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.2211497359 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 2077828674 ps |
| CPU time | 14.04 seconds |
| Started | Oct 09 04:14:09 PM UTC 24 |
| Finished | Oct 09 04:14:24 PM UTC 24 |
| Peak memory | 245388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211497359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2211497359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/45.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.629002438 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 303268544 ps |
| CPU time | 7.57 seconds |
| Started | Oct 09 04:14:14 PM UTC 24 |
| Finished | Oct 09 04:14:23 PM UTC 24 |
| Peak memory | 233504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629002438 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.629002438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/45.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.3510867762 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 295753617 ps |
| CPU time | 1.82 seconds |
| Started | Oct 09 04:14:24 PM UTC 24 |
| Finished | Oct 09 04:14:26 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510867762 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.3510867762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/45.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.2482821815 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 1219555652 ps |
| CPU time | 23.78 seconds |
| Started | Oct 09 04:14:04 PM UTC 24 |
| Finished | Oct 09 04:14:29 PM UTC 24 |
| Peak memory | 227756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482821815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2482821815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/45.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.2578950112 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 1288127244 ps |
| CPU time | 4.53 seconds |
| Started | Oct 09 04:14:04 PM UTC 24 |
| Finished | Oct 09 04:14:10 PM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578950112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2578950112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/45.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.572905412 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 45952080 ps |
| CPU time | 1.34 seconds |
| Started | Oct 09 04:14:07 PM UTC 24 |
| Finished | Oct 09 04:14:10 PM UTC 24 |
| Peak memory | 214916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572905412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.572905412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/45.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.2832152212 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 92168012 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 04:14:06 PM UTC 24 |
| Finished | Oct 09 04:14:09 PM UTC 24 |
| Peak memory | 214860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832152212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2832152212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/45.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.1084888417 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 5480703608 ps |
| CPU time | 31.92 seconds |
| Started | Oct 09 04:14:11 PM UTC 24 |
| Finished | Oct 09 04:14:44 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084888417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1084888417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/45.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.3524472042 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 15976895 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 04:14:45 PM UTC 24 |
| Finished | Oct 09 04:14:47 PM UTC 24 |
| Peak memory | 214784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524472042 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.3524472042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/46.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.4112178382 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 1005798163 ps |
| CPU time | 22.1 seconds |
| Started | Oct 09 04:14:35 PM UTC 24 |
| Finished | Oct 09 04:14:58 PM UTC 24 |
| Peak memory | 235148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112178382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4112178382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/46.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.269236185 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 93077112 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 04:14:26 PM UTC 24 |
| Finished | Oct 09 04:14:28 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269236185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.269236185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/46.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.306583258 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 67921298133 ps |
| CPU time | 250.14 seconds |
| Started | Oct 09 04:14:37 PM UTC 24 |
| Finished | Oct 09 04:18:51 PM UTC 24 |
| Peak memory | 267788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306583258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.306583258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/46.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.2534748642 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 20622352026 ps |
| CPU time | 84.21 seconds |
| Started | Oct 09 04:14:39 PM UTC 24 |
| Finished | Oct 09 04:16:05 PM UTC 24 |
| Peak memory | 261828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534748642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2534748642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/46.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.1810584839 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 1138569245 ps |
| CPU time | 42.48 seconds |
| Started | Oct 09 04:14:39 PM UTC 24 |
| Finished | Oct 09 04:15:23 PM UTC 24 |
| Peak memory | 245172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810584839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.1810584839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.1012507506 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 2310188944 ps |
| CPU time | 7.14 seconds |
| Started | Oct 09 04:14:35 PM UTC 24 |
| Finished | Oct 09 04:14:43 PM UTC 24 |
| Peak memory | 245272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012507506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1012507506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/46.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.3853132853 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 43799025704 ps |
| CPU time | 348.55 seconds |
| Started | Oct 09 04:14:35 PM UTC 24 |
| Finished | Oct 09 04:20:28 PM UTC 24 |
| Peak memory | 261644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853132853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.3853132853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.2132119759 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 270212747 ps |
| CPU time | 4.88 seconds |
| Started | Oct 09 04:14:33 PM UTC 24 |
| Finished | Oct 09 04:14:39 PM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132119759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2132119759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/46.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.344757735 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 603880313 ps |
| CPU time | 27.7 seconds |
| Started | Oct 09 04:14:33 PM UTC 24 |
| Finished | Oct 09 04:15:02 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344757735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.344757735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/46.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.1985122687 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 4710818270 ps |
| CPU time | 23.24 seconds |
| Started | Oct 09 04:14:30 PM UTC 24 |
| Finished | Oct 09 04:14:55 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985122687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.1985122687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/46.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.2797798703 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 364638048 ps |
| CPU time | 2.46 seconds |
| Started | Oct 09 04:14:30 PM UTC 24 |
| Finished | Oct 09 04:14:34 PM UTC 24 |
| Peak memory | 234304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797798703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2797798703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/46.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.3533946820 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 151097025 ps |
| CPU time | 5.06 seconds |
| Started | Oct 09 04:14:37 PM UTC 24 |
| Finished | Oct 09 04:14:43 PM UTC 24 |
| Peak memory | 231396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533946820 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.3533946820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/46.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.4218236537 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 30687721601 ps |
| CPU time | 422.38 seconds |
| Started | Oct 09 04:14:40 PM UTC 24 |
| Finished | Oct 09 04:21:48 PM UTC 24 |
| Peak memory | 276236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218236537 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.4218236537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/46.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.1443015111 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 1367715937 ps |
| CPU time | 8.94 seconds |
| Started | Oct 09 04:14:28 PM UTC 24 |
| Finished | Oct 09 04:14:38 PM UTC 24 |
| Peak memory | 227564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443015111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1443015111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/46.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.3517681131 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 781894499 ps |
| CPU time | 5.58 seconds |
| Started | Oct 09 04:14:26 PM UTC 24 |
| Finished | Oct 09 04:14:32 PM UTC 24 |
| Peak memory | 227520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517681131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3517681131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/46.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.4103584432 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 30188837 ps |
| CPU time | 1.35 seconds |
| Started | Oct 09 04:14:28 PM UTC 24 |
| Finished | Oct 09 04:14:30 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103584432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.4103584432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/46.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.1823790155 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 22959357 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 04:14:28 PM UTC 24 |
| Finished | Oct 09 04:14:30 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823790155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1823790155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/46.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.1058362543 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 29687919632 ps |
| CPU time | 42.64 seconds |
| Started | Oct 09 04:14:35 PM UTC 24 |
| Finished | Oct 09 04:15:19 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058362543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1058362543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/46.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.384303177 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 13478634 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 04:15:03 PM UTC 24 |
| Finished | Oct 09 04:15:05 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384303177 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.384303177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/47.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.3514803874 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 6713105815 ps |
| CPU time | 26.71 seconds |
| Started | Oct 09 04:14:56 PM UTC 24 |
| Finished | Oct 09 04:15:24 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514803874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3514803874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/47.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.2696918621 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 68105185 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 04:14:45 PM UTC 24 |
| Finished | Oct 09 04:14:47 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696918621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2696918621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/47.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.1827518851 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 4765457074 ps |
| CPU time | 65.83 seconds |
| Started | Oct 09 04:14:59 PM UTC 24 |
| Finished | Oct 09 04:16:07 PM UTC 24 |
| Peak memory | 263884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827518851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1827518851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/47.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.22173531 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 138002342309 ps |
| CPU time | 140.43 seconds |
| Started | Oct 09 04:15:01 PM UTC 24 |
| Finished | Oct 09 04:17:24 PM UTC 24 |
| Peak memory | 267908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22173531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.22173531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.3300511401 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 62308722382 ps |
| CPU time | 204.49 seconds |
| Started | Oct 09 04:15:01 PM UTC 24 |
| Finished | Oct 09 04:18:29 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300511401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.3300511401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.133452452 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 755465626 ps |
| CPU time | 18.42 seconds |
| Started | Oct 09 04:14:57 PM UTC 24 |
| Finished | Oct 09 04:15:17 PM UTC 24 |
| Peak memory | 251400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133452452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.133452452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/47.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.1929236145 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 2748553167 ps |
| CPU time | 39.95 seconds |
| Started | Oct 09 04:14:57 PM UTC 24 |
| Finished | Oct 09 04:15:39 PM UTC 24 |
| Peak memory | 261648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929236145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.1929236145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.469693971 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 319615467 ps |
| CPU time | 8.3 seconds |
| Started | Oct 09 04:14:50 PM UTC 24 |
| Finished | Oct 09 04:14:59 PM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469693971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.469693971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/47.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.160045703 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 19069157885 ps |
| CPU time | 99.25 seconds |
| Started | Oct 09 04:14:51 PM UTC 24 |
| Finished | Oct 09 04:16:32 PM UTC 24 |
| Peak memory | 245252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160045703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.160045703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/47.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.2929547264 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 22476756129 ps |
| CPU time | 14.71 seconds |
| Started | Oct 09 04:14:48 PM UTC 24 |
| Finished | Oct 09 04:15:05 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929547264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.2929547264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/47.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.2400209812 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 4847730470 ps |
| CPU time | 16.73 seconds |
| Started | Oct 09 04:14:47 PM UTC 24 |
| Finished | Oct 09 04:15:06 PM UTC 24 |
| Peak memory | 247564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400209812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2400209812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/47.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.845697572 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 1923622777 ps |
| CPU time | 8.88 seconds |
| Started | Oct 09 04:14:58 PM UTC 24 |
| Finished | Oct 09 04:15:08 PM UTC 24 |
| Peak memory | 233564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845697572 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.845697572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/47.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.2699200050 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 8219377087 ps |
| CPU time | 47.05 seconds |
| Started | Oct 09 04:15:02 PM UTC 24 |
| Finished | Oct 09 04:15:50 PM UTC 24 |
| Peak memory | 245332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699200050 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.2699200050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/47.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.1333546772 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 19354235631 ps |
| CPU time | 30.39 seconds |
| Started | Oct 09 04:14:46 PM UTC 24 |
| Finished | Oct 09 04:15:18 PM UTC 24 |
| Peak memory | 227688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333546772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1333546772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/47.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.1918524143 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 757888936 ps |
| CPU time | 9.42 seconds |
| Started | Oct 09 04:14:45 PM UTC 24 |
| Finished | Oct 09 04:14:56 PM UTC 24 |
| Peak memory | 227508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918524143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1918524143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/47.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.4154425473 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 60887572 ps |
| CPU time | 2.47 seconds |
| Started | Oct 09 04:14:46 PM UTC 24 |
| Finished | Oct 09 04:14:50 PM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154425473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.4154425473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/47.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.1536569113 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 90792993 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 04:14:46 PM UTC 24 |
| Finished | Oct 09 04:14:48 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536569113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1536569113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/47.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.1310471718 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 9572356815 ps |
| CPU time | 32.44 seconds |
| Started | Oct 09 04:14:53 PM UTC 24 |
| Finished | Oct 09 04:15:27 PM UTC 24 |
| Peak memory | 245456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310471718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1310471718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/47.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.3087042493 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 44157782 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 04:15:25 PM UTC 24 |
| Finished | Oct 09 04:15:27 PM UTC 24 |
| Peak memory | 214840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087042493 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.3087042493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/48.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.1859448366 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 2568589687 ps |
| CPU time | 9.66 seconds |
| Started | Oct 09 04:15:18 PM UTC 24 |
| Finished | Oct 09 04:15:29 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859448366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1859448366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/48.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.2186601696 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 19278116 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 04:15:06 PM UTC 24 |
| Finished | Oct 09 04:15:08 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186601696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2186601696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/48.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.3643864317 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 4038764909 ps |
| CPU time | 80.34 seconds |
| Started | Oct 09 04:15:21 PM UTC 24 |
| Finished | Oct 09 04:16:44 PM UTC 24 |
| Peak memory | 268052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643864317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3643864317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/48.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.1073854355 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 4781437140 ps |
| CPU time | 130.99 seconds |
| Started | Oct 09 04:15:23 PM UTC 24 |
| Finished | Oct 09 04:17:36 PM UTC 24 |
| Peak memory | 284292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073854355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1073854355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.138504488 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 4705125892 ps |
| CPU time | 61.73 seconds |
| Started | Oct 09 04:15:25 PM UTC 24 |
| Finished | Oct 09 04:16:28 PM UTC 24 |
| Peak memory | 261900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138504488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.138504488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.4284370956 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 95729804 ps |
| CPU time | 3.98 seconds |
| Started | Oct 09 04:15:19 PM UTC 24 |
| Finished | Oct 09 04:15:24 PM UTC 24 |
| Peak memory | 235160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284370956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.4284370956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/48.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.1577277647 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 32741093959 ps |
| CPU time | 54.49 seconds |
| Started | Oct 09 04:15:20 PM UTC 24 |
| Finished | Oct 09 04:16:17 PM UTC 24 |
| Peak memory | 250988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577277647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.1577277647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.591777407 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 500684083 ps |
| CPU time | 6.59 seconds |
| Started | Oct 09 04:15:13 PM UTC 24 |
| Finished | Oct 09 04:15:20 PM UTC 24 |
| Peak memory | 235148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591777407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.591777407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/48.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.2978287227 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 397340338 ps |
| CPU time | 13.74 seconds |
| Started | Oct 09 04:15:15 PM UTC 24 |
| Finished | Oct 09 04:15:30 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978287227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2978287227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/48.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.4203341640 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 48088413904 ps |
| CPU time | 22.44 seconds |
| Started | Oct 09 04:15:11 PM UTC 24 |
| Finished | Oct 09 04:15:34 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203341640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.4203341640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/48.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.1047470255 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 2229584026 ps |
| CPU time | 13.37 seconds |
| Started | Oct 09 04:15:09 PM UTC 24 |
| Finished | Oct 09 04:15:24 PM UTC 24 |
| Peak memory | 235280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047470255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1047470255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/48.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.786228695 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 357793730 ps |
| CPU time | 5.18 seconds |
| Started | Oct 09 04:15:20 PM UTC 24 |
| Finished | Oct 09 04:15:27 PM UTC 24 |
| Peak memory | 231168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786228695 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.786228695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/48.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.1935555810 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 10714125730 ps |
| CPU time | 58.26 seconds |
| Started | Oct 09 04:15:25 PM UTC 24 |
| Finished | Oct 09 04:16:25 PM UTC 24 |
| Peak memory | 278164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935555810 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.1935555810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/48.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.1092697068 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 7635957347 ps |
| CPU time | 36.72 seconds |
| Started | Oct 09 04:15:06 PM UTC 24 |
| Finished | Oct 09 04:15:44 PM UTC 24 |
| Peak memory | 227876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092697068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1092697068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/48.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.2471591736 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 5695943374 ps |
| CPU time | 12.61 seconds |
| Started | Oct 09 04:15:06 PM UTC 24 |
| Finished | Oct 09 04:15:20 PM UTC 24 |
| Peak memory | 227524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471591736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2471591736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/48.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.2033476446 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 27716334 ps |
| CPU time | 1.36 seconds |
| Started | Oct 09 04:15:09 PM UTC 24 |
| Finished | Oct 09 04:15:12 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033476446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2033476446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/48.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.700050904 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 26945215 ps |
| CPU time | 1 seconds |
| Started | Oct 09 04:15:07 PM UTC 24 |
| Finished | Oct 09 04:15:09 PM UTC 24 |
| Peak memory | 214856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700050904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.700050904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/48.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.861436546 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 593521621 ps |
| CPU time | 4.99 seconds |
| Started | Oct 09 04:15:18 PM UTC 24 |
| Finished | Oct 09 04:15:24 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861436546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.861436546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/48.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.1485322263 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 15175305 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 04:15:44 PM UTC 24 |
| Finished | Oct 09 04:15:47 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485322263 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.1485322263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/49.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.964010757 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 232279003 ps |
| CPU time | 4.56 seconds |
| Started | Oct 09 04:15:31 PM UTC 24 |
| Finished | Oct 09 04:15:37 PM UTC 24 |
| Peak memory | 235012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964010757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.964010757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/49.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.3209905276 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 11977155 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 04:15:25 PM UTC 24 |
| Finished | Oct 09 04:15:27 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209905276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3209905276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/49.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.1221396324 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 9271198034 ps |
| CPU time | 40.62 seconds |
| Started | Oct 09 04:15:35 PM UTC 24 |
| Finished | Oct 09 04:16:17 PM UTC 24 |
| Peak memory | 261660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221396324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1221396324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/49.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.524365878 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 3773251526 ps |
| CPU time | 86.52 seconds |
| Started | Oct 09 04:15:36 PM UTC 24 |
| Finished | Oct 09 04:17:05 PM UTC 24 |
| Peak memory | 265744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524365878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.524365878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.3427010325 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 3760668068 ps |
| CPU time | 138.05 seconds |
| Started | Oct 09 04:15:38 PM UTC 24 |
| Finished | Oct 09 04:17:59 PM UTC 24 |
| Peak memory | 278280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427010325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.3427010325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.1541322017 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 4641469976 ps |
| CPU time | 22.47 seconds |
| Started | Oct 09 04:15:32 PM UTC 24 |
| Finished | Oct 09 04:15:56 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541322017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1541322017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/49.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.3658848849 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 5784542025 ps |
| CPU time | 45.09 seconds |
| Started | Oct 09 04:15:33 PM UTC 24 |
| Finished | Oct 09 04:16:20 PM UTC 24 |
| Peak memory | 265868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658848849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.3658848849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.1896759117 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 8614364090 ps |
| CPU time | 26.77 seconds |
| Started | Oct 09 04:15:30 PM UTC 24 |
| Finished | Oct 09 04:15:58 PM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896759117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1896759117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/49.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.44455720 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 22510764054 ps |
| CPU time | 71.2 seconds |
| Started | Oct 09 04:15:31 PM UTC 24 |
| Finished | Oct 09 04:16:44 PM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44455720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.44455720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/49.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.142502794 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 99837724 ps |
| CPU time | 4.02 seconds |
| Started | Oct 09 04:15:29 PM UTC 24 |
| Finished | Oct 09 04:15:34 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142502794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.142502794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/49.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.4091850928 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 58452778 ps |
| CPU time | 3.98 seconds |
| Started | Oct 09 04:15:28 PM UTC 24 |
| Finished | Oct 09 04:15:33 PM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091850928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.4091850928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/49.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.744783781 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 3471511629 ps |
| CPU time | 8.14 seconds |
| Started | Oct 09 04:15:35 PM UTC 24 |
| Finished | Oct 09 04:15:44 PM UTC 24 |
| Peak memory | 229424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744783781 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.744783781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/49.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.3486734826 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 40752433195 ps |
| CPU time | 469.72 seconds |
| Started | Oct 09 04:15:39 PM UTC 24 |
| Finished | Oct 09 04:23:35 PM UTC 24 |
| Peak memory | 294480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486734826 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.3486734826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/49.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.889454675 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 5903537840 ps |
| CPU time | 41.03 seconds |
| Started | Oct 09 04:15:25 PM UTC 24 |
| Finished | Oct 09 04:16:08 PM UTC 24 |
| Peak memory | 227744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889454675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.889454675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/49.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.1772737716 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 6531524912 ps |
| CPU time | 5.64 seconds |
| Started | Oct 09 04:15:25 PM UTC 24 |
| Finished | Oct 09 04:15:32 PM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772737716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1772737716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/49.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.3895129745 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 35897460 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 04:15:27 PM UTC 24 |
| Finished | Oct 09 04:15:29 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895129745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3895129745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/49.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.849180338 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 30432268 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 04:15:27 PM UTC 24 |
| Finished | Oct 09 04:15:30 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849180338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.849180338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/49.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.3120899113 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 5307438731 ps |
| CPU time | 15.19 seconds |
| Started | Oct 09 04:15:31 PM UTC 24 |
| Finished | Oct 09 04:15:47 PM UTC 24 |
| Peak memory | 251600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120899113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3120899113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/49.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.318444576 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 13255075 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 03:58:31 PM UTC 24 |
| Finished | Oct 09 03:58:33 PM UTC 24 |
| Peak memory | 212856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318444576 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.318444576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.2224394859 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 474518813 ps |
| CPU time | 4.81 seconds |
| Started | Oct 09 03:58:18 PM UTC 24 |
| Finished | Oct 09 03:58:24 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224394859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2224394859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.1763217232 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 78283617 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 03:58:02 PM UTC 24 |
| Finished | Oct 09 03:58:04 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763217232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1763217232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.3949156091 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 26737721293 ps |
| CPU time | 84.93 seconds |
| Started | Oct 09 03:58:25 PM UTC 24 |
| Finished | Oct 09 03:59:52 PM UTC 24 |
| Peak memory | 235084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949156091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3949156091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.101825875 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 468814841 ps |
| CPU time | 5.35 seconds |
| Started | Oct 09 03:58:18 PM UTC 24 |
| Finished | Oct 09 03:58:24 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101825875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.101825875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.3634731313 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 98674846890 ps |
| CPU time | 187.7 seconds |
| Started | Oct 09 03:58:22 PM UTC 24 |
| Finished | Oct 09 04:01:33 PM UTC 24 |
| Peak memory | 261980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634731313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.3634731313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.981090614 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 264719238 ps |
| CPU time | 5.4 seconds |
| Started | Oct 09 03:58:11 PM UTC 24 |
| Finished | Oct 09 03:58:17 PM UTC 24 |
| Peak memory | 245256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981090614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.981090614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.3070648257 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 232362306 ps |
| CPU time | 4.71 seconds |
| Started | Oct 09 03:58:12 PM UTC 24 |
| Finished | Oct 09 03:58:17 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070648257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3070648257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.2517593394 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 50710994 ps |
| CPU time | 1.44 seconds |
| Started | Oct 09 03:58:02 PM UTC 24 |
| Finished | Oct 09 03:58:04 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517593394 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mem_parity.2517593394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.113721698 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 10880314903 ps |
| CPU time | 12.06 seconds |
| Started | Oct 09 03:58:08 PM UTC 24 |
| Finished | Oct 09 03:58:21 PM UTC 24 |
| Peak memory | 245464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113721698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.113721698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.3237821657 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 216938708 ps |
| CPU time | 3.6 seconds |
| Started | Oct 09 03:58:05 PM UTC 24 |
| Finished | Oct 09 03:58:10 PM UTC 24 |
| Peak memory | 244940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237821657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3237821657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.2886888488 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 509858474 ps |
| CPU time | 9.07 seconds |
| Started | Oct 09 03:58:23 PM UTC 24 |
| Finished | Oct 09 03:58:34 PM UTC 24 |
| Peak memory | 233588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886888488 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.2886888488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.304831497 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 2309660638 ps |
| CPU time | 33.38 seconds |
| Started | Oct 09 03:58:26 PM UTC 24 |
| Finished | Oct 09 03:59:01 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304831497 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.304831497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.2305649102 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2998973626 ps |
| CPU time | 17.83 seconds |
| Started | Oct 09 03:58:03 PM UTC 24 |
| Finished | Oct 09 03:58:22 PM UTC 24 |
| Peak memory | 231852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305649102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2305649102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2730063768 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 3818157299 ps |
| CPU time | 21.34 seconds |
| Started | Oct 09 03:58:02 PM UTC 24 |
| Finished | Oct 09 03:58:25 PM UTC 24 |
| Peak memory | 227628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730063768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2730063768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.2053083488 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 749013375 ps |
| CPU time | 4.32 seconds |
| Started | Oct 09 03:58:05 PM UTC 24 |
| Finished | Oct 09 03:58:11 PM UTC 24 |
| Peak memory | 227688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053083488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2053083488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.3731978792 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 42528081 ps |
| CPU time | 1.31 seconds |
| Started | Oct 09 03:58:04 PM UTC 24 |
| Finished | Oct 09 03:58:07 PM UTC 24 |
| Peak memory | 214856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731978792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3731978792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.2610481992 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 15265207557 ps |
| CPU time | 31.51 seconds |
| Started | Oct 09 03:58:13 PM UTC 24 |
| Finished | Oct 09 03:58:46 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610481992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2610481992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/5.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.293064899 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 13140327 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 03:59:11 PM UTC 24 |
| Finished | Oct 09 03:59:14 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293064899 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.293064899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.3108707607 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 33840741 ps |
| CPU time | 3.55 seconds |
| Started | Oct 09 03:58:46 PM UTC 24 |
| Finished | Oct 09 03:58:51 PM UTC 24 |
| Peak memory | 244812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108707607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3108707607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.2130212619 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 31014612 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 03:58:34 PM UTC 24 |
| Finished | Oct 09 03:58:36 PM UTC 24 |
| Peak memory | 214972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130212619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2130212619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.2505288372 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 1085590062 ps |
| CPU time | 26.6 seconds |
| Started | Oct 09 03:59:05 PM UTC 24 |
| Finished | Oct 09 03:59:33 PM UTC 24 |
| Peak memory | 249424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505288372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2505288372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.1549176408 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 23836823228 ps |
| CPU time | 43.89 seconds |
| Started | Oct 09 03:59:07 PM UTC 24 |
| Finished | Oct 09 03:59:53 PM UTC 24 |
| Peak memory | 251600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549176408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1549176408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.2821510317 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 1941956421 ps |
| CPU time | 11.05 seconds |
| Started | Oct 09 03:58:51 PM UTC 24 |
| Finished | Oct 09 03:59:04 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821510317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2821510317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.1154987931 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 57684333665 ps |
| CPU time | 106.32 seconds |
| Started | Oct 09 03:59:01 PM UTC 24 |
| Finished | Oct 09 04:00:50 PM UTC 24 |
| Peak memory | 249372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154987931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.1154987931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.1079209064 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 4493017682 ps |
| CPU time | 26.65 seconds |
| Started | Oct 09 03:58:42 PM UTC 24 |
| Finished | Oct 09 03:59:10 PM UTC 24 |
| Peak memory | 245520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079209064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1079209064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.3178617538 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 58270714252 ps |
| CPU time | 150.26 seconds |
| Started | Oct 09 03:58:43 PM UTC 24 |
| Finished | Oct 09 04:01:16 PM UTC 24 |
| Peak memory | 247376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178617538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3178617538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.1013702615 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 14601269 ps |
| CPU time | 1.66 seconds |
| Started | Oct 09 03:58:35 PM UTC 24 |
| Finished | Oct 09 03:58:38 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013702615 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mem_parity.1013702615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.4144130344 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 76485113574 ps |
| CPU time | 32.81 seconds |
| Started | Oct 09 03:58:42 PM UTC 24 |
| Finished | Oct 09 03:59:16 PM UTC 24 |
| Peak memory | 245524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144130344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.4144130344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.3237225243 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 1694947989 ps |
| CPU time | 18.92 seconds |
| Started | Oct 09 03:58:42 PM UTC 24 |
| Finished | Oct 09 03:59:02 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237225243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3237225243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2002069245 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 261024503 ps |
| CPU time | 6.9 seconds |
| Started | Oct 09 03:59:03 PM UTC 24 |
| Finished | Oct 09 03:59:11 PM UTC 24 |
| Peak memory | 233520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002069245 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.2002069245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.4273190678 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3071380257 ps |
| CPU time | 67.11 seconds |
| Started | Oct 09 03:59:11 PM UTC 24 |
| Finished | Oct 09 04:00:20 PM UTC 24 |
| Peak memory | 261972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273190678 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.4273190678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.2191355480 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 18611302298 ps |
| CPU time | 28.9 seconds |
| Started | Oct 09 03:58:37 PM UTC 24 |
| Finished | Oct 09 03:59:08 PM UTC 24 |
| Peak memory | 231844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191355480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2191355480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.3272566508 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 514378071 ps |
| CPU time | 4.18 seconds |
| Started | Oct 09 03:58:35 PM UTC 24 |
| Finished | Oct 09 03:58:40 PM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272566508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3272566508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.429090349 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 29514092 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 03:58:39 PM UTC 24 |
| Finished | Oct 09 03:58:41 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429090349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.429090349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.146816793 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 428537753 ps |
| CPU time | 1.66 seconds |
| Started | Oct 09 03:58:39 PM UTC 24 |
| Finished | Oct 09 03:58:41 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146816793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.146816793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.501021235 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 17092497889 ps |
| CPU time | 45.92 seconds |
| Started | Oct 09 03:58:43 PM UTC 24 |
| Finished | Oct 09 03:59:31 PM UTC 24 |
| Peak memory | 251400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501021235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.501021235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/6.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.1006733628 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 99512242 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 03:59:46 PM UTC 24 |
| Finished | Oct 09 03:59:48 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006733628 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1006733628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.1813410022 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 168175936 ps |
| CPU time | 6.89 seconds |
| Started | Oct 09 03:59:30 PM UTC 24 |
| Finished | Oct 09 03:59:38 PM UTC 24 |
| Peak memory | 235144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813410022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1813410022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.238356075 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 274653105 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 03:59:14 PM UTC 24 |
| Finished | Oct 09 03:59:17 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238356075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.238356075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.1460667608 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 31077035012 ps |
| CPU time | 207.75 seconds |
| Started | Oct 09 03:59:37 PM UTC 24 |
| Finished | Oct 09 04:03:08 PM UTC 24 |
| Peak memory | 261720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460667608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1460667608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1912643143 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 717126904 ps |
| CPU time | 17.35 seconds |
| Started | Oct 09 03:59:38 PM UTC 24 |
| Finished | Oct 09 03:59:57 PM UTC 24 |
| Peak memory | 235084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912643143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1912643143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1035787076 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 7457002408 ps |
| CPU time | 63.87 seconds |
| Started | Oct 09 03:59:39 PM UTC 24 |
| Finished | Oct 09 04:00:45 PM UTC 24 |
| Peak memory | 245456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035787076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.1035787076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.698648407 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 556090860 ps |
| CPU time | 11.99 seconds |
| Started | Oct 09 03:59:32 PM UTC 24 |
| Finished | Oct 09 03:59:45 PM UTC 24 |
| Peak memory | 245188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698648407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.698648407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.2117034002 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 12977999 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 03:59:34 PM UTC 24 |
| Finished | Oct 09 03:59:36 PM UTC 24 |
| Peak memory | 225968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117034002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.2117034002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.2304175531 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 3218371159 ps |
| CPU time | 20.34 seconds |
| Started | Oct 09 03:59:24 PM UTC 24 |
| Finished | Oct 09 03:59:46 PM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304175531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2304175531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.5735935 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 14894982929 ps |
| CPU time | 71.07 seconds |
| Started | Oct 09 03:59:26 PM UTC 24 |
| Finished | Oct 09 04:00:39 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5735935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM _TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_devi ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.5735935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.1977117361 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 15529396 ps |
| CPU time | 1.55 seconds |
| Started | Oct 09 03:59:17 PM UTC 24 |
| Finished | Oct 09 03:59:20 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977117361 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mem_parity.1977117361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3105777342 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 493712338 ps |
| CPU time | 3.67 seconds |
| Started | Oct 09 03:59:24 PM UTC 24 |
| Finished | Oct 09 03:59:29 PM UTC 24 |
| Peak memory | 234908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105777342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.3105777342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3976870842 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 989056670 ps |
| CPU time | 5.62 seconds |
| Started | Oct 09 03:59:22 PM UTC 24 |
| Finished | Oct 09 03:59:29 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976870842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3976870842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.277287902 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 1466534990 ps |
| CPU time | 5.6 seconds |
| Started | Oct 09 03:59:35 PM UTC 24 |
| Finished | Oct 09 03:59:42 PM UTC 24 |
| Peak memory | 231460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277287902 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.277287902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.846158665 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 156033962619 ps |
| CPU time | 364.45 seconds |
| Started | Oct 09 03:59:43 PM UTC 24 |
| Finished | Oct 09 04:05:52 PM UTC 24 |
| Peak memory | 267980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846158665 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.846158665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.2513268032 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 23403734 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 03:59:21 PM UTC 24 |
| Finished | Oct 09 03:59:23 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513268032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2513268032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.3287257460 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 19706416 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 03:59:17 PM UTC 24 |
| Finished | Oct 09 03:59:20 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287257460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3287257460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.15019582 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 756654031 ps |
| CPU time | 2.46 seconds |
| Started | Oct 09 03:59:22 PM UTC 24 |
| Finished | Oct 09 03:59:25 PM UTC 24 |
| Peak memory | 227688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15019582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_devi ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.15019582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1343753080 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 26823156 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 03:59:21 PM UTC 24 |
| Finished | Oct 09 03:59:23 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343753080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1343753080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.2304127487 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 151363476 ps |
| CPU time | 3.1 seconds |
| Started | Oct 09 03:59:30 PM UTC 24 |
| Finished | Oct 09 03:59:34 PM UTC 24 |
| Peak memory | 245252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304127487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2304127487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/7.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.644915437 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 73067946 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 04:00:25 PM UTC 24 |
| Finished | Oct 09 04:00:28 PM UTC 24 |
| Peak memory | 212856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644915437 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.644915437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.1633673782 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 197200971 ps |
| CPU time | 3.2 seconds |
| Started | Oct 09 04:00:08 PM UTC 24 |
| Finished | Oct 09 04:00:12 PM UTC 24 |
| Peak memory | 235152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633673782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1633673782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.124743128 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 54135117 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 03:59:47 PM UTC 24 |
| Finished | Oct 09 03:59:49 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124743128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.124743128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.462315329 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 31302890576 ps |
| CPU time | 120.62 seconds |
| Started | Oct 09 04:00:14 PM UTC 24 |
| Finished | Oct 09 04:02:17 PM UTC 24 |
| Peak memory | 267920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462315329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.462315329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.3433429135 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 55859367875 ps |
| CPU time | 560.13 seconds |
| Started | Oct 09 04:00:25 PM UTC 24 |
| Finished | Oct 09 04:09:53 PM UTC 24 |
| Peak memory | 284148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433429135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.3433429135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.2050359194 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 1503546767 ps |
| CPU time | 40.49 seconds |
| Started | Oct 09 04:00:09 PM UTC 24 |
| Finished | Oct 09 04:00:51 PM UTC 24 |
| Peak memory | 251404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050359194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2050359194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.2034667748 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 160762810 ps |
| CPU time | 6.38 seconds |
| Started | Oct 09 03:59:56 PM UTC 24 |
| Finished | Oct 09 04:00:03 PM UTC 24 |
| Peak memory | 235276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034667748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2034667748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.4192523383 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 9442871300 ps |
| CPU time | 27.04 seconds |
| Started | Oct 09 03:59:58 PM UTC 24 |
| Finished | Oct 09 04:00:26 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192523383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.4192523383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.592440658 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 23996070 ps |
| CPU time | 1.62 seconds |
| Started | Oct 09 03:59:47 PM UTC 24 |
| Finished | Oct 09 03:59:49 PM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592440658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mem_parity.592440658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.222924052 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 12891427548 ps |
| CPU time | 35.48 seconds |
| Started | Oct 09 03:59:54 PM UTC 24 |
| Finished | Oct 09 04:00:30 PM UTC 24 |
| Peak memory | 245272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222924052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.222924052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.3215309422 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 6975415699 ps |
| CPU time | 14.16 seconds |
| Started | Oct 09 03:59:53 PM UTC 24 |
| Finished | Oct 09 04:00:09 PM UTC 24 |
| Peak memory | 261784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215309422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3215309422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.1142446050 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 1435814629 ps |
| CPU time | 10.27 seconds |
| Started | Oct 09 04:00:12 PM UTC 24 |
| Finished | Oct 09 04:00:24 PM UTC 24 |
| Peak memory | 233588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142446050 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.1142446050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.2857562893 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 63940344408 ps |
| CPU time | 217.24 seconds |
| Started | Oct 09 04:00:25 PM UTC 24 |
| Finished | Oct 09 04:04:06 PM UTC 24 |
| Peak memory | 261600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857562893 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.2857562893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.3281427922 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 52698454981 ps |
| CPU time | 64.92 seconds |
| Started | Oct 09 03:59:50 PM UTC 24 |
| Finished | Oct 09 04:00:57 PM UTC 24 |
| Peak memory | 227752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281427922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3281427922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.725112337 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1002285105 ps |
| CPU time | 4.37 seconds |
| Started | Oct 09 03:59:49 PM UTC 24 |
| Finished | Oct 09 03:59:54 PM UTC 24 |
| Peak memory | 227480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725112337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.725112337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.51879791 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3098763329 ps |
| CPU time | 5.83 seconds |
| Started | Oct 09 03:59:52 PM UTC 24 |
| Finished | Oct 09 03:59:59 PM UTC 24 |
| Peak memory | 227624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51879791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_devi ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.51879791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3694924587 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 29001744 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 03:59:50 PM UTC 24 |
| Finished | Oct 09 03:59:52 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694924587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3694924587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.1860303313 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 15307690266 ps |
| CPU time | 26.48 seconds |
| Started | Oct 09 04:00:00 PM UTC 24 |
| Finished | Oct 09 04:00:28 PM UTC 24 |
| Peak memory | 247368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860303313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1860303313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/8.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.3120677781 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 10943321 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 04:00:57 PM UTC 24 |
| Finished | Oct 09 04:01:00 PM UTC 24 |
| Peak memory | 214784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120677781 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3120677781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1460783382 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 58460480 ps |
| CPU time | 3.1 seconds |
| Started | Oct 09 04:00:47 PM UTC 24 |
| Finished | Oct 09 04:00:51 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460783382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1460783382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.2118969038 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 17700374 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 04:00:27 PM UTC 24 |
| Finished | Oct 09 04:00:29 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118969038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2118969038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.3159463407 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 144230596003 ps |
| CPU time | 243.84 seconds |
| Started | Oct 09 04:00:52 PM UTC 24 |
| Finished | Oct 09 04:05:00 PM UTC 24 |
| Peak memory | 261644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159463407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3159463407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.342589645 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 9310996368 ps |
| CPU time | 90.13 seconds |
| Started | Oct 09 04:00:54 PM UTC 24 |
| Finished | Oct 09 04:02:26 PM UTC 24 |
| Peak memory | 251524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342589645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.342589645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.374100141 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 3072203295 ps |
| CPU time | 14.66 seconds |
| Started | Oct 09 04:00:51 PM UTC 24 |
| Finished | Oct 09 04:01:07 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374100141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.374100141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.247149701 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 22073420727 ps |
| CPU time | 48.78 seconds |
| Started | Oct 09 04:00:51 PM UTC 24 |
| Finished | Oct 09 04:01:41 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247149701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.247149701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.1095866254 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 300990996 ps |
| CPU time | 6.48 seconds |
| Started | Oct 09 04:00:36 PM UTC 24 |
| Finished | Oct 09 04:00:44 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095866254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1095866254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.2344338262 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 4474733534 ps |
| CPU time | 57.61 seconds |
| Started | Oct 09 04:00:40 PM UTC 24 |
| Finished | Oct 09 04:01:40 PM UTC 24 |
| Peak memory | 245272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344338262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2344338262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.1097914213 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 86056845 ps |
| CPU time | 1.35 seconds |
| Started | Oct 09 04:00:28 PM UTC 24 |
| Finished | Oct 09 04:00:31 PM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097914213 -asser t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mem_parity.1097914213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_mem_parity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.356838000 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 1580462367 ps |
| CPU time | 13.02 seconds |
| Started | Oct 09 04:00:35 PM UTC 24 |
| Finished | Oct 09 04:00:49 PM UTC 24 |
| Peak memory | 245276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356838000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.356838000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.1841350878 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 19432204327 ps |
| CPU time | 27.75 seconds |
| Started | Oct 09 04:00:32 PM UTC 24 |
| Finished | Oct 09 04:01:01 PM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841350878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1841350878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.858520638 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 810338679 ps |
| CPU time | 6.19 seconds |
| Started | Oct 09 04:00:52 PM UTC 24 |
| Finished | Oct 09 04:00:59 PM UTC 24 |
| Peak memory | 231528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858520638 -assert nopostproc +UVM_TESTNAME=spi_device_ba se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.858520638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.3153685188 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 23578577898 ps |
| CPU time | 313.4 seconds |
| Started | Oct 09 04:00:57 PM UTC 24 |
| Finished | Oct 09 04:06:15 PM UTC 24 |
| Peak memory | 282192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153685188 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.3153685188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.1534311636 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 19769949477 ps |
| CPU time | 21.16 seconds |
| Started | Oct 09 04:00:31 PM UTC 24 |
| Finished | Oct 09 04:00:53 PM UTC 24 |
| Peak memory | 231844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534311636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1534311636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.3920687842 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 8225774688 ps |
| CPU time | 25.52 seconds |
| Started | Oct 09 04:00:28 PM UTC 24 |
| Finished | Oct 09 04:00:56 PM UTC 24 |
| Peak memory | 227696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920687842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3920687842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.2804543471 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 49012715 ps |
| CPU time | 2.49 seconds |
| Started | Oct 09 04:00:32 PM UTC 24 |
| Finished | Oct 09 04:00:35 PM UTC 24 |
| Peak memory | 227556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804543471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2804543471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.54115675 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 94442164 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 04:00:32 PM UTC 24 |
| Finished | Oct 09 04:00:34 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54115675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.54115675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.360028977 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 867135939 ps |
| CPU time | 10.37 seconds |
| Started | Oct 09 04:00:45 PM UTC 24 |
| Finished | Oct 09 04:00:57 PM UTC 24 |
| Peak memory | 247240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360028977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_dev ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.360028977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/9.spi_device_upload/latest |
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