| T839 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_upload.998190488 |
|
|
Oct 12 02:33:29 PM UTC 24 |
Oct 12 02:33:57 PM UTC 24 |
2984348143 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.1504710190 |
|
|
Oct 12 02:33:17 PM UTC 24 |
Oct 12 02:33:58 PM UTC 24 |
1456084024 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.1826017475 |
|
|
Oct 12 02:33:58 PM UTC 24 |
Oct 12 02:34:00 PM UTC 24 |
24693396 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_rw.2055334297 |
|
|
Oct 12 02:33:59 PM UTC 24 |
Oct 12 02:34:04 PM UTC 24 |
141478609 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.946892093 |
|
|
Oct 12 02:34:01 PM UTC 24 |
Oct 12 02:34:09 PM UTC 24 |
180294956 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.633661852 |
|
|
Oct 12 02:32:20 PM UTC 24 |
Oct 12 02:34:11 PM UTC 24 |
56488097580 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.2228468455 |
|
|
Oct 12 02:33:57 PM UTC 24 |
Oct 12 02:34:12 PM UTC 24 |
409464152 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.2969519462 |
|
|
Oct 12 02:34:05 PM UTC 24 |
Oct 12 02:34:14 PM UTC 24 |
2806861844 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.135658307 |
|
|
Oct 12 02:31:37 PM UTC 24 |
Oct 12 02:34:16 PM UTC 24 |
45038891056 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.1159148055 |
|
|
Oct 12 02:34:12 PM UTC 24 |
Oct 12 02:34:16 PM UTC 24 |
350052918 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.3802646837 |
|
|
Oct 12 02:33:55 PM UTC 24 |
Oct 12 02:34:20 PM UTC 24 |
4716666254 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.3844114731 |
|
|
Oct 12 02:30:57 PM UTC 24 |
Oct 12 02:34:20 PM UTC 24 |
23556918024 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_cfg_cmd.2474494068 |
|
|
Oct 12 02:34:15 PM UTC 24 |
Oct 12 02:34:21 PM UTC 24 |
174446466 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_mailbox.2068413183 |
|
|
Oct 12 02:33:02 PM UTC 24 |
Oct 12 02:34:22 PM UTC 24 |
30273171065 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.1895110762 |
|
|
Oct 12 02:34:16 PM UTC 24 |
Oct 12 02:34:23 PM UTC 24 |
386320400 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.3866668285 |
|
|
Oct 12 02:33:41 PM UTC 24 |
Oct 12 02:34:26 PM UTC 24 |
25729575436 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.2823812714 |
|
|
Oct 12 02:34:25 PM UTC 24 |
Oct 12 02:34:27 PM UTC 24 |
90465177 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.1781633213 |
|
|
Oct 12 02:30:13 PM UTC 24 |
Oct 12 02:34:29 PM UTC 24 |
39305196376 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.2203674922 |
|
|
Oct 12 02:34:27 PM UTC 24 |
Oct 12 02:34:29 PM UTC 24 |
13865793 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.2206136573 |
|
|
Oct 12 02:34:28 PM UTC 24 |
Oct 12 02:34:30 PM UTC 24 |
24094659 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.2837131245 |
|
|
Oct 12 02:34:13 PM UTC 24 |
Oct 12 02:34:31 PM UTC 24 |
5118426111 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.2556993683 |
|
|
Oct 12 02:34:21 PM UTC 24 |
Oct 12 02:34:32 PM UTC 24 |
1201113721 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.682856150 |
|
|
Oct 12 02:34:32 PM UTC 24 |
Oct 12 02:34:34 PM UTC 24 |
70618321 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.1706693166 |
|
|
Oct 12 02:36:55 PM UTC 24 |
Oct 12 02:36:57 PM UTC 24 |
13867136 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.2466714868 |
|
|
Oct 12 02:31:09 PM UTC 24 |
Oct 12 02:34:35 PM UTC 24 |
78806915915 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.1812945984 |
|
|
Oct 12 02:34:33 PM UTC 24 |
Oct 12 02:34:36 PM UTC 24 |
83209368 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_intercept.2071894124 |
|
|
Oct 12 02:34:10 PM UTC 24 |
Oct 12 02:34:38 PM UTC 24 |
9672607861 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.2299576143 |
|
|
Oct 12 02:34:30 PM UTC 24 |
Oct 12 02:34:40 PM UTC 24 |
8776026674 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.2292819189 |
|
|
Oct 12 02:32:17 PM UTC 24 |
Oct 12 02:34:43 PM UTC 24 |
19489091358 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.2663469226 |
|
|
Oct 12 02:34:39 PM UTC 24 |
Oct 12 02:34:43 PM UTC 24 |
238538162 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.2891303106 |
|
|
Oct 12 02:34:37 PM UTC 24 |
Oct 12 02:34:47 PM UTC 24 |
1621299494 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.1966787890 |
|
|
Oct 12 02:32:36 PM UTC 24 |
Oct 12 02:34:47 PM UTC 24 |
17342953293 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.3272454967 |
|
|
Oct 12 02:34:31 PM UTC 24 |
Oct 12 02:34:50 PM UTC 24 |
11212497506 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.1186148395 |
|
|
Oct 12 02:33:10 PM UTC 24 |
Oct 12 02:34:53 PM UTC 24 |
10164989222 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.1038265254 |
|
|
Oct 12 02:34:41 PM UTC 24 |
Oct 12 02:34:55 PM UTC 24 |
4087917173 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.2720335030 |
|
|
Oct 12 02:34:48 PM UTC 24 |
Oct 12 02:34:58 PM UTC 24 |
894053988 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_mailbox.1604619325 |
|
|
Oct 12 02:33:27 PM UTC 24 |
Oct 12 02:35:00 PM UTC 24 |
46608043077 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.2902470256 |
|
|
Oct 12 02:34:59 PM UTC 24 |
Oct 12 02:35:01 PM UTC 24 |
12849466 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.3505101026 |
|
|
Oct 12 02:34:33 PM UTC 24 |
Oct 12 02:35:02 PM UTC 24 |
25288017324 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.262672907 |
|
|
Oct 12 02:34:35 PM UTC 24 |
Oct 12 02:35:02 PM UTC 24 |
4353748232 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.1634267089 |
|
|
Oct 12 02:32:46 PM UTC 24 |
Oct 12 02:35:03 PM UTC 24 |
8997102878 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.58595952 |
|
|
Oct 12 02:35:01 PM UTC 24 |
Oct 12 02:35:04 PM UTC 24 |
20934012 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.4157801902 |
|
|
Oct 12 02:35:04 PM UTC 24 |
Oct 12 02:35:06 PM UTC 24 |
31342675 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.353893772 |
|
|
Oct 12 02:35:04 PM UTC 24 |
Oct 12 02:35:07 PM UTC 24 |
75739587 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.27888986 |
|
|
Oct 12 02:35:05 PM UTC 24 |
Oct 12 02:35:09 PM UTC 24 |
138159599 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.1475391989 |
|
|
Oct 12 02:34:45 PM UTC 24 |
Oct 12 02:35:11 PM UTC 24 |
14183981290 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.1716238605 |
|
|
Oct 12 02:35:02 PM UTC 24 |
Oct 12 02:35:13 PM UTC 24 |
3746661998 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.3184367886 |
|
|
Oct 12 02:35:07 PM UTC 24 |
Oct 12 02:35:15 PM UTC 24 |
732112951 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/20.spi_device_stress_all.243320718 |
|
|
Oct 12 02:25:36 PM UTC 24 |
Oct 12 02:35:17 PM UTC 24 |
503544285765 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3963732765 |
|
|
Oct 12 02:35:14 PM UTC 24 |
Oct 12 02:35:18 PM UTC 24 |
84506361 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.1733673744 |
|
|
Oct 12 02:35:04 PM UTC 24 |
Oct 12 02:35:20 PM UTC 24 |
18315247727 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.1997795869 |
|
|
Oct 12 02:35:12 PM UTC 24 |
Oct 12 02:35:20 PM UTC 24 |
1439926288 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.4204607779 |
|
|
Oct 12 02:33:09 PM UTC 24 |
Oct 12 02:35:20 PM UTC 24 |
5923462444 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.2205847249 |
|
|
Oct 12 02:34:23 PM UTC 24 |
Oct 12 02:35:21 PM UTC 24 |
8328457011 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2965779193 |
|
|
Oct 12 02:35:20 PM UTC 24 |
Oct 12 02:35:27 PM UTC 24 |
465983129 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.1479263838 |
|
|
Oct 12 02:35:07 PM UTC 24 |
Oct 12 02:35:29 PM UTC 24 |
3259002103 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.3979190069 |
|
|
Oct 12 02:35:28 PM UTC 24 |
Oct 12 02:35:30 PM UTC 24 |
36502586 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.3216932398 |
|
|
Oct 12 02:35:30 PM UTC 24 |
Oct 12 02:35:32 PM UTC 24 |
41373875 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.3571355877 |
|
|
Oct 12 02:35:16 PM UTC 24 |
Oct 12 02:35:34 PM UTC 24 |
2302108006 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.2840527432 |
|
|
Oct 12 02:33:12 PM UTC 24 |
Oct 12 02:35:35 PM UTC 24 |
5035594024 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.2945322198 |
|
|
Oct 12 02:35:35 PM UTC 24 |
Oct 12 02:35:37 PM UTC 24 |
101571390 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.4115978928 |
|
|
Oct 12 02:35:36 PM UTC 24 |
Oct 12 02:35:38 PM UTC 24 |
199648817 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.296484415 |
|
|
Oct 12 02:35:31 PM UTC 24 |
Oct 12 02:35:40 PM UTC 24 |
2254435968 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.1062244093 |
|
|
Oct 12 02:35:38 PM UTC 24 |
Oct 12 02:35:45 PM UTC 24 |
1695714240 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.2894258109 |
|
|
Oct 12 02:34:37 PM UTC 24 |
Oct 12 02:35:48 PM UTC 24 |
22383093950 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.703755795 |
|
|
Oct 12 02:35:10 PM UTC 24 |
Oct 12 02:35:53 PM UTC 24 |
9433735175 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.150942599 |
|
|
Oct 12 02:35:41 PM UTC 24 |
Oct 12 02:35:54 PM UTC 24 |
1709218997 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.1536827178 |
|
|
Oct 12 02:35:33 PM UTC 24 |
Oct 12 02:35:55 PM UTC 24 |
2601464192 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.1717861517 |
|
|
Oct 12 02:34:54 PM UTC 24 |
Oct 12 02:35:56 PM UTC 24 |
2922864785 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.3100728972 |
|
|
Oct 12 02:35:39 PM UTC 24 |
Oct 12 02:36:01 PM UTC 24 |
11353811354 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.613383537 |
|
|
Oct 12 02:35:55 PM UTC 24 |
Oct 12 02:36:06 PM UTC 24 |
1183770512 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.1339802944 |
|
|
Oct 12 02:35:54 PM UTC 24 |
Oct 12 02:36:09 PM UTC 24 |
929370646 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.2131034444 |
|
|
Oct 12 02:36:06 PM UTC 24 |
Oct 12 02:36:16 PM UTC 24 |
1065272770 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.32319691 |
|
|
Oct 12 02:33:06 PM UTC 24 |
Oct 12 02:36:18 PM UTC 24 |
34244910161 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_all.3367556722 |
|
|
Oct 12 02:30:12 PM UTC 24 |
Oct 12 02:36:19 PM UTC 24 |
71170595685 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.205031087 |
|
|
Oct 12 02:36:19 PM UTC 24 |
Oct 12 02:36:21 PM UTC 24 |
22811193 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.2931787834 |
|
|
Oct 12 02:35:49 PM UTC 24 |
Oct 12 02:36:22 PM UTC 24 |
16157494140 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.2453572172 |
|
|
Oct 12 02:36:20 PM UTC 24 |
Oct 12 02:36:22 PM UTC 24 |
20069807 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.3541547593 |
|
|
Oct 12 02:36:24 PM UTC 24 |
Oct 12 02:36:25 PM UTC 24 |
46533162 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.390733382 |
|
|
Oct 12 02:36:27 PM UTC 24 |
Oct 12 02:36:29 PM UTC 24 |
73699408 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.2488609065 |
|
|
Oct 12 02:35:46 PM UTC 24 |
Oct 12 02:36:32 PM UTC 24 |
11165758255 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.2136795675 |
|
|
Oct 12 02:35:58 PM UTC 24 |
Oct 12 02:36:33 PM UTC 24 |
2580794947 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.1837097470 |
|
|
Oct 12 02:36:30 PM UTC 24 |
Oct 12 02:36:37 PM UTC 24 |
385540592 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.3136650678 |
|
|
Oct 12 02:36:34 PM UTC 24 |
Oct 12 02:36:39 PM UTC 24 |
90035918 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.46955243 |
|
|
Oct 12 02:35:21 PM UTC 24 |
Oct 12 02:36:40 PM UTC 24 |
2597665488 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.342355400 |
|
|
Oct 12 02:34:21 PM UTC 24 |
Oct 12 02:36:45 PM UTC 24 |
64693882055 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.170343338 |
|
|
Oct 12 02:36:22 PM UTC 24 |
Oct 12 02:36:45 PM UTC 24 |
13919050373 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.765121207 |
|
|
Oct 12 02:36:41 PM UTC 24 |
Oct 12 02:36:45 PM UTC 24 |
164200506 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.3966422255 |
|
|
Oct 12 02:34:18 PM UTC 24 |
Oct 12 02:36:45 PM UTC 24 |
9749342141 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.2267520588 |
|
|
Oct 12 02:36:47 PM UTC 24 |
Oct 12 02:36:49 PM UTC 24 |
54496371 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.94923918 |
|
|
Oct 12 02:36:23 PM UTC 24 |
Oct 12 02:36:51 PM UTC 24 |
1937938282 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.1132705885 |
|
|
Oct 12 02:26:04 PM UTC 24 |
Oct 12 02:36:53 PM UTC 24 |
317410569891 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.762368387 |
|
|
Oct 12 02:36:47 PM UTC 24 |
Oct 12 02:36:54 PM UTC 24 |
409331004 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2966284626 |
|
|
Oct 12 02:36:33 PM UTC 24 |
Oct 12 02:36:55 PM UTC 24 |
2837814304 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.141775356 |
|
|
Oct 12 02:36:56 PM UTC 24 |
Oct 12 02:36:58 PM UTC 24 |
279206600 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.3773373654 |
|
|
Oct 12 02:35:19 PM UTC 24 |
Oct 12 02:37:06 PM UTC 24 |
89824283310 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.905594024 |
|
|
Oct 12 02:36:40 PM UTC 24 |
Oct 12 02:37:07 PM UTC 24 |
4085793612 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.2241944012 |
|
|
Oct 12 02:37:08 PM UTC 24 |
Oct 12 02:37:10 PM UTC 24 |
463337718 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.3495306556 |
|
|
Oct 12 02:37:09 PM UTC 24 |
Oct 12 02:37:11 PM UTC 24 |
89054568 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.3906654507 |
|
|
Oct 12 02:36:39 PM UTC 24 |
Oct 12 02:37:21 PM UTC 24 |
13353942062 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.2463028321 |
|
|
Oct 12 02:33:43 PM UTC 24 |
Oct 12 02:37:21 PM UTC 24 |
25343416658 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.2755735047 |
|
|
Oct 12 02:31:15 PM UTC 24 |
Oct 12 02:37:24 PM UTC 24 |
38266060352 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.1853609316 |
|
|
Oct 12 02:28:00 PM UTC 24 |
Oct 12 02:37:24 PM UTC 24 |
82469758626 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.728424570 |
|
|
Oct 12 02:35:21 PM UTC 24 |
Oct 12 02:37:25 PM UTC 24 |
33576812164 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.3804662449 |
|
|
Oct 12 02:35:56 PM UTC 24 |
Oct 12 02:37:26 PM UTC 24 |
36861845008 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.1670278338 |
|
|
Oct 12 02:36:58 PM UTC 24 |
Oct 12 02:37:27 PM UTC 24 |
22611598810 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.593751683 |
|
|
Oct 12 02:37:25 PM UTC 24 |
Oct 12 02:37:29 PM UTC 24 |
235055815 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.3296881407 |
|
|
Oct 12 02:37:25 PM UTC 24 |
Oct 12 02:37:30 PM UTC 24 |
243535991 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.2783138781 |
|
|
Oct 12 02:36:09 PM UTC 24 |
Oct 12 02:37:30 PM UTC 24 |
12357709347 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.2754843893 |
|
|
Oct 12 02:37:12 PM UTC 24 |
Oct 12 02:37:32 PM UTC 24 |
1402362039 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.1192986176 |
|
|
Oct 12 02:37:28 PM UTC 24 |
Oct 12 02:37:34 PM UTC 24 |
746466983 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.3623170222 |
|
|
Oct 12 02:37:23 PM UTC 24 |
Oct 12 02:37:35 PM UTC 24 |
876314923 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.35389336 |
|
|
Oct 12 02:37:35 PM UTC 24 |
Oct 12 02:37:37 PM UTC 24 |
36658447 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.3352747531 |
|
|
Oct 12 02:36:59 PM UTC 24 |
Oct 12 02:37:37 PM UTC 24 |
23434886017 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.3324831482 |
|
|
Oct 12 02:37:36 PM UTC 24 |
Oct 12 02:37:38 PM UTC 24 |
14940041 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.2901210285 |
|
|
Oct 12 02:37:26 PM UTC 24 |
Oct 12 02:37:39 PM UTC 24 |
2230777288 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.2569833361 |
|
|
Oct 12 02:37:40 PM UTC 24 |
Oct 12 02:37:42 PM UTC 24 |
132519370 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.304422296 |
|
|
Oct 12 02:31:42 PM UTC 24 |
Oct 12 02:37:43 PM UTC 24 |
130580939882 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.1022644030 |
|
|
Oct 12 02:37:40 PM UTC 24 |
Oct 12 02:37:43 PM UTC 24 |
127686007 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.4051453077 |
|
|
Oct 12 02:37:44 PM UTC 24 |
Oct 12 02:37:50 PM UTC 24 |
175151526 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.2062508893 |
|
|
Oct 12 02:37:38 PM UTC 24 |
Oct 12 02:37:50 PM UTC 24 |
1849814874 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.939181995 |
|
|
Oct 12 02:36:45 PM UTC 24 |
Oct 12 02:37:51 PM UTC 24 |
16395390263 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.3701137634 |
|
|
Oct 12 02:37:30 PM UTC 24 |
Oct 12 02:37:53 PM UTC 24 |
1128473353 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.966814100 |
|
|
Oct 12 02:34:22 PM UTC 24 |
Oct 12 02:37:54 PM UTC 24 |
101900524288 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.1450652980 |
|
|
Oct 12 02:37:11 PM UTC 24 |
Oct 12 02:37:57 PM UTC 24 |
7777567404 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.3997750823 |
|
|
Oct 12 02:37:53 PM UTC 24 |
Oct 12 02:37:59 PM UTC 24 |
172496828 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.1602165215 |
|
|
Oct 12 02:37:21 PM UTC 24 |
Oct 12 02:38:01 PM UTC 24 |
3335570878 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.2827510778 |
|
|
Oct 12 02:37:52 PM UTC 24 |
Oct 12 02:38:03 PM UTC 24 |
3898529389 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.1143412006 |
|
|
Oct 12 02:37:38 PM UTC 24 |
Oct 12 02:38:03 PM UTC 24 |
6180569994 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.2272233137 |
|
|
Oct 12 02:37:58 PM UTC 24 |
Oct 12 02:38:04 PM UTC 24 |
219202343 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.549337157 |
|
|
Oct 12 02:37:54 PM UTC 24 |
Oct 12 02:38:04 PM UTC 24 |
1085248939 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.1280436317 |
|
|
Oct 12 02:37:52 PM UTC 24 |
Oct 12 02:38:06 PM UTC 24 |
3161122097 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.2850388026 |
|
|
Oct 12 02:38:06 PM UTC 24 |
Oct 12 02:38:08 PM UTC 24 |
59011093 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.34801269 |
|
|
Oct 12 02:38:06 PM UTC 24 |
Oct 12 02:38:08 PM UTC 24 |
65153388 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.613349468 |
|
|
Oct 12 02:38:09 PM UTC 24 |
Oct 12 02:38:11 PM UTC 24 |
25397160 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.2464424147 |
|
|
Oct 12 02:38:07 PM UTC 24 |
Oct 12 02:38:13 PM UTC 24 |
1533333522 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.888766735 |
|
|
Oct 12 02:38:12 PM UTC 24 |
Oct 12 02:38:15 PM UTC 24 |
102551088 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.325119606 |
|
|
Oct 12 02:29:53 PM UTC 24 |
Oct 12 02:38:17 PM UTC 24 |
189710468942 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.712698619 |
|
|
Oct 12 02:38:09 PM UTC 24 |
Oct 12 02:38:20 PM UTC 24 |
2296696250 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.98754237 |
|
|
Oct 12 02:38:18 PM UTC 24 |
Oct 12 02:38:25 PM UTC 24 |
261732040 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.1426447986 |
|
|
Oct 12 02:36:45 PM UTC 24 |
Oct 12 02:38:25 PM UTC 24 |
19902606890 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.2272648679 |
|
|
Oct 12 02:38:15 PM UTC 24 |
Oct 12 02:38:26 PM UTC 24 |
996644427 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.3451571933 |
|
|
Oct 12 02:37:43 PM UTC 24 |
Oct 12 02:38:26 PM UTC 24 |
6499660497 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.1100117104 |
|
|
Oct 12 02:37:44 PM UTC 24 |
Oct 12 02:38:27 PM UTC 24 |
4757018571 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.3295509244 |
|
|
Oct 12 02:38:16 PM UTC 24 |
Oct 12 02:38:29 PM UTC 24 |
11930156241 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.247231256 |
|
|
Oct 12 02:38:28 PM UTC 24 |
Oct 12 02:38:36 PM UTC 24 |
222384833 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.2839670327 |
|
|
Oct 12 02:38:27 PM UTC 24 |
Oct 12 02:38:37 PM UTC 24 |
5902563666 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.3529452765 |
|
|
Oct 12 02:36:02 PM UTC 24 |
Oct 12 02:38:38 PM UTC 24 |
40394898150 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.2455318397 |
|
|
Oct 12 02:38:21 PM UTC 24 |
Oct 12 02:38:43 PM UTC 24 |
1138319980 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.2541888463 |
|
|
Oct 12 02:38:27 PM UTC 24 |
Oct 12 02:38:45 PM UTC 24 |
3268687533 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.1642137980 |
|
|
Oct 12 02:38:43 PM UTC 24 |
Oct 12 02:38:45 PM UTC 24 |
76176681 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.3496147006 |
|
|
Oct 12 02:30:18 PM UTC 24 |
Oct 12 02:38:46 PM UTC 24 |
43533298994 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.707496999 |
|
|
Oct 12 02:37:55 PM UTC 24 |
Oct 12 02:38:47 PM UTC 24 |
2849247323 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.2058676291 |
|
|
Oct 12 02:29:07 PM UTC 24 |
Oct 12 02:38:47 PM UTC 24 |
345696686592 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.3701716540 |
|
|
Oct 12 02:38:27 PM UTC 24 |
Oct 12 02:38:48 PM UTC 24 |
613635658 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.2095297695 |
|
|
Oct 12 02:38:47 PM UTC 24 |
Oct 12 02:38:49 PM UTC 24 |
20387189 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.3618506100 |
|
|
Oct 12 02:38:48 PM UTC 24 |
Oct 12 02:38:50 PM UTC 24 |
72131708 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.4213650205 |
|
|
Oct 12 02:38:48 PM UTC 24 |
Oct 12 02:38:51 PM UTC 24 |
72332780 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.2429750687 |
|
|
Oct 12 02:38:01 PM UTC 24 |
Oct 12 02:38:54 PM UTC 24 |
3175108064 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.2384915102 |
|
|
Oct 12 02:29:26 PM UTC 24 |
Oct 12 02:38:54 PM UTC 24 |
105878869339 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.1412882058 |
|
|
Oct 12 02:38:47 PM UTC 24 |
Oct 12 02:38:55 PM UTC 24 |
1080916374 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.2564032525 |
|
|
Oct 12 02:38:50 PM UTC 24 |
Oct 12 02:38:57 PM UTC 24 |
2109736957 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.785665253 |
|
|
Oct 12 02:38:27 PM UTC 24 |
Oct 12 02:38:58 PM UTC 24 |
23937148293 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.1626438902 |
|
|
Oct 12 02:38:52 PM UTC 24 |
Oct 12 02:38:58 PM UTC 24 |
1855040801 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.2450592071 |
|
|
Oct 12 02:38:30 PM UTC 24 |
Oct 12 02:38:59 PM UTC 24 |
1497857681 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.1633779126 |
|
|
Oct 12 02:38:52 PM UTC 24 |
Oct 12 02:39:00 PM UTC 24 |
233239196 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.783617432 |
|
|
Oct 12 02:38:56 PM UTC 24 |
Oct 12 02:39:00 PM UTC 24 |
1295663966 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.2425219397 |
|
|
Oct 12 02:37:33 PM UTC 24 |
Oct 12 02:39:00 PM UTC 24 |
40706059950 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.813463299 |
|
|
Oct 12 02:34:49 PM UTC 24 |
Oct 12 02:39:03 PM UTC 24 |
141448722533 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.2850919184 |
|
|
Oct 12 02:39:02 PM UTC 24 |
Oct 12 02:39:04 PM UTC 24 |
35844829 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.84872299 |
|
|
Oct 12 02:38:56 PM UTC 24 |
Oct 12 02:39:04 PM UTC 24 |
348720530 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.605766053 |
|
|
Oct 12 02:39:01 PM UTC 24 |
Oct 12 02:39:05 PM UTC 24 |
1218242893 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.3536144919 |
|
|
Oct 12 02:37:31 PM UTC 24 |
Oct 12 02:39:05 PM UTC 24 |
16613097563 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.2862762807 |
|
|
Oct 12 02:39:03 PM UTC 24 |
Oct 12 02:39:05 PM UTC 24 |
15217292 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.3831065059 |
|
|
Oct 12 02:38:50 PM UTC 24 |
Oct 12 02:39:08 PM UTC 24 |
16395668906 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.2131311465 |
|
|
Oct 12 02:39:06 PM UTC 24 |
Oct 12 02:39:09 PM UTC 24 |
183598846 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.3817434672 |
|
|
Oct 12 02:39:07 PM UTC 24 |
Oct 12 02:39:09 PM UTC 24 |
44134315 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2902157118 |
|
|
Oct 12 02:39:07 PM UTC 24 |
Oct 12 02:39:10 PM UTC 24 |
1292744336 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.1449099527 |
|
|
Oct 12 02:39:07 PM UTC 24 |
Oct 12 02:39:11 PM UTC 24 |
529950809 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.90203719 |
|
|
Oct 12 02:34:51 PM UTC 24 |
Oct 12 02:39:11 PM UTC 24 |
94628789586 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.4227695542 |
|
|
Oct 12 02:39:09 PM UTC 24 |
Oct 12 02:39:13 PM UTC 24 |
986760107 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.2535408108 |
|
|
Oct 12 02:39:11 PM UTC 24 |
Oct 12 02:39:15 PM UTC 24 |
1106047820 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.2653757225 |
|
|
Oct 12 02:39:11 PM UTC 24 |
Oct 12 02:39:16 PM UTC 24 |
172185356 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.1720434195 |
|
|
Oct 12 02:33:47 PM UTC 24 |
Oct 12 02:39:16 PM UTC 24 |
45916822997 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.3257699507 |
|
|
Oct 12 02:38:59 PM UTC 24 |
Oct 12 02:39:17 PM UTC 24 |
1655868345 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.2533757627 |
|
|
Oct 12 02:39:12 PM UTC 24 |
Oct 12 02:39:20 PM UTC 24 |
1043509908 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.3952089699 |
|
|
Oct 12 02:39:10 PM UTC 24 |
Oct 12 02:39:22 PM UTC 24 |
487978722 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_all.2200193927 |
|
|
Oct 12 02:32:16 PM UTC 24 |
Oct 12 02:39:23 PM UTC 24 |
49177799572 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.4157675773 |
|
|
Oct 12 02:39:23 PM UTC 24 |
Oct 12 02:39:25 PM UTC 24 |
11280654 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.870314104 |
|
|
Oct 12 02:39:16 PM UTC 24 |
Oct 12 02:39:32 PM UTC 24 |
722379363 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.1910484466 |
|
|
Oct 12 02:38:02 PM UTC 24 |
Oct 12 02:39:34 PM UTC 24 |
12615371688 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.3060043482 |
|
|
Oct 12 02:39:12 PM UTC 24 |
Oct 12 02:39:35 PM UTC 24 |
3137777828 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.2829746370 |
|
|
Oct 12 02:38:48 PM UTC 24 |
Oct 12 02:39:37 PM UTC 24 |
2931985860 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.1846646540 |
|
|
Oct 12 02:39:06 PM UTC 24 |
Oct 12 02:39:38 PM UTC 24 |
4168326566 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.744262495 |
|
|
Oct 12 02:39:01 PM UTC 24 |
Oct 12 02:39:41 PM UTC 24 |
3759394679 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.4229441635 |
|
|
Oct 12 02:36:52 PM UTC 24 |
Oct 12 02:39:44 PM UTC 24 |
50322466197 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.3882873289 |
|
|
Oct 12 02:26:52 PM UTC 24 |
Oct 12 02:39:47 PM UTC 24 |
87875541417 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.4128161557 |
|
|
Oct 12 02:38:56 PM UTC 24 |
Oct 12 02:39:52 PM UTC 24 |
3120100995 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_all.2536674909 |
|
|
Oct 12 02:29:50 PM UTC 24 |
Oct 12 02:39:58 PM UTC 24 |
253896171890 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.1606421647 |
|
|
Oct 12 02:38:04 PM UTC 24 |
Oct 12 02:40:04 PM UTC 24 |
26155804434 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.1966262566 |
|
|
Oct 12 02:29:51 PM UTC 24 |
Oct 12 02:40:17 PM UTC 24 |
67386881458 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.1205754720 |
|
|
Oct 12 02:37:28 PM UTC 24 |
Oct 12 02:40:17 PM UTC 24 |
50123239102 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.3315616567 |
|
|
Oct 12 02:39:15 PM UTC 24 |
Oct 12 02:40:23 PM UTC 24 |
50092338962 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3370613133 |
|
|
Oct 12 02:38:37 PM UTC 24 |
Oct 12 02:40:35 PM UTC 24 |
29707792342 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.2031072482 |
|
|
Oct 12 02:39:01 PM UTC 24 |
Oct 12 02:40:39 PM UTC 24 |
3180684670 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.3450436071 |
|
|
Oct 12 02:39:21 PM UTC 24 |
Oct 12 02:41:00 PM UTC 24 |
29111932117 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.3944469751 |
|
|
Oct 12 02:20:55 PM UTC 24 |
Oct 12 02:41:08 PM UTC 24 |
415708151939 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.104497123 |
|
|
Oct 12 02:35:22 PM UTC 24 |
Oct 12 02:41:10 PM UTC 24 |
124812687399 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.2115919507 |
|
|
Oct 12 02:38:04 PM UTC 24 |
Oct 12 02:41:20 PM UTC 24 |
53475327615 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.3451738264 |
|
|
Oct 12 02:38:38 PM UTC 24 |
Oct 12 02:41:20 PM UTC 24 |
9831313711 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.3910074110 |
|
|
Oct 12 02:38:59 PM UTC 24 |
Oct 12 02:41:35 PM UTC 24 |
68411933336 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.2411426629 |
|
|
Oct 12 02:39:18 PM UTC 24 |
Oct 12 02:41:51 PM UTC 24 |
27365064001 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.1145248715 |
|
|
Oct 12 02:31:39 PM UTC 24 |
Oct 12 02:42:03 PM UTC 24 |
438725664733 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.651714367 |
|
|
Oct 12 02:37:31 PM UTC 24 |
Oct 12 02:42:07 PM UTC 24 |
262064702154 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.4172433997 |
|
|
Oct 12 02:38:39 PM UTC 24 |
Oct 12 02:42:09 PM UTC 24 |
37532528988 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.3471302152 |
|
|
Oct 12 02:34:45 PM UTC 24 |
Oct 12 02:42:47 PM UTC 24 |
246217770626 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.3738836308 |
|
|
Oct 12 02:39:18 PM UTC 24 |
Oct 12 02:42:52 PM UTC 24 |
15819186570 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.22941910 |
|
|
Oct 12 02:38:59 PM UTC 24 |
Oct 12 02:43:40 PM UTC 24 |
36637631829 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.1612973669 |
|
|
Oct 12 02:33:39 PM UTC 24 |
Oct 12 02:43:50 PM UTC 24 |
319476616261 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.1914169555 |
|
|
Oct 12 02:35:22 PM UTC 24 |
Oct 12 02:43:51 PM UTC 24 |
160243555589 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.3415370249 |
|
|
Oct 12 02:39:17 PM UTC 24 |
Oct 12 02:44:26 PM UTC 24 |
78039875329 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1781321008 |
|
|
Oct 12 02:36:50 PM UTC 24 |
Oct 12 02:44:39 PM UTC 24 |
49554699422 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.3371457284 |
|
|
Oct 12 02:36:55 PM UTC 24 |
Oct 12 02:46:31 PM UTC 24 |
110578586449 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.1778863316 |
|
|
Oct 12 02:29:30 PM UTC 24 |
Oct 12 02:47:39 PM UTC 24 |
125536434506 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.4075067839 |
|
|
Oct 12 02:34:56 PM UTC 24 |
Oct 12 02:49:07 PM UTC 24 |
383546826117 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.283058361 |
|
|
Oct 12 02:36:17 PM UTC 24 |
Oct 12 02:50:43 PM UTC 24 |
67701753704 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.3477976138 |
|
|
Oct 12 02:08:21 PM UTC 24 |
Oct 12 02:08:23 PM UTC 24 |
13508331 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.1009043882 |
|
|
Oct 12 02:08:21 PM UTC 24 |
Oct 12 02:08:23 PM UTC 24 |
45575750 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.4062165874 |
|
|
Oct 12 02:08:37 PM UTC 24 |
Oct 12 02:08:40 PM UTC 24 |
80235151 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1926297945 |
|
|
Oct 12 02:08:21 PM UTC 24 |
Oct 12 02:08:23 PM UTC 24 |
40275319 ps |
| T1038 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.1395182718 |
|
|
Oct 12 02:08:21 PM UTC 24 |
Oct 12 02:08:23 PM UTC 24 |
32506304 ps |
| T1039 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2510338846 |
|
|
Oct 12 02:08:21 PM UTC 24 |
Oct 12 02:08:23 PM UTC 24 |
11444021 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.936845917 |
|
|
Oct 12 02:08:21 PM UTC 24 |
Oct 12 02:08:23 PM UTC 24 |
62907814 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1249486038 |
|
|
Oct 12 02:08:21 PM UTC 24 |
Oct 12 02:08:23 PM UTC 24 |
88353905 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.129042772 |
|
|
Oct 12 02:08:21 PM UTC 24 |
Oct 12 02:08:24 PM UTC 24 |
59673160 ps |
| T1040 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.184718093 |
|
|
Oct 12 02:08:21 PM UTC 24 |
Oct 12 02:08:24 PM UTC 24 |
108074205 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1851981445 |
|
|
Oct 12 02:08:21 PM UTC 24 |
Oct 12 02:08:24 PM UTC 24 |
34019599 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.2870518487 |
|
|
Oct 12 02:08:21 PM UTC 24 |
Oct 12 02:08:24 PM UTC 24 |
135457801 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1458644714 |
|
|
Oct 12 02:08:21 PM UTC 24 |
Oct 12 02:08:24 PM UTC 24 |
62819715 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2238281269 |
|
|
Oct 12 02:08:21 PM UTC 24 |
Oct 12 02:08:24 PM UTC 24 |
91369135 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.177116584 |
|
|
Oct 12 02:08:21 PM UTC 24 |
Oct 12 02:08:26 PM UTC 24 |
125757923 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2118668739 |
|
|
Oct 12 02:08:21 PM UTC 24 |
Oct 12 02:08:26 PM UTC 24 |
136248174 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2184200013 |
|
|
Oct 12 02:08:21 PM UTC 24 |
Oct 12 02:08:26 PM UTC 24 |
56234468 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.2037979395 |
|
|
Oct 12 02:08:32 PM UTC 24 |
Oct 12 02:08:40 PM UTC 24 |
305409788 ps |
| T1041 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.3633404434 |
|
|
Oct 12 02:08:24 PM UTC 24 |
Oct 12 02:08:26 PM UTC 24 |
26515958 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.3435254381 |
|
|
Oct 12 02:08:36 PM UTC 24 |
Oct 12 02:08:40 PM UTC 24 |
107036155 ps |
| T1042 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.91397812 |
|
|
Oct 12 02:08:24 PM UTC 24 |
Oct 12 02:08:26 PM UTC 24 |
24991493 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.3854539111 |
|
|
Oct 12 02:08:24 PM UTC 24 |
Oct 12 02:08:27 PM UTC 24 |
31183912 ps |
| T1043 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.2877387785 |
|
|
Oct 12 02:08:25 PM UTC 24 |
Oct 12 02:08:27 PM UTC 24 |
17718529 ps |
| T1044 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.1271362691 |
|
|
Oct 12 02:08:25 PM UTC 24 |
Oct 12 02:08:27 PM UTC 24 |
135564136 ps |