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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.77 98.70 96.89 99.01 89.36 98.59 95.56 99.26


Total test records in report: 1151
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T114 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1159139829 Oct 12 02:08:24 PM UTC 24 Oct 12 02:08:27 PM UTC 24 39325279 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1648388443 Oct 12 02:08:25 PM UTC 24 Oct 12 02:08:27 PM UTC 24 22377205 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.1510818151 Oct 12 02:08:25 PM UTC 24 Oct 12 02:08:27 PM UTC 24 19662266 ps
T135 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.3792773811 Oct 12 02:08:21 PM UTC 24 Oct 12 02:08:27 PM UTC 24 221849944 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.2710935021 Oct 12 02:08:24 PM UTC 24 Oct 12 02:08:27 PM UTC 24 28707022 ps
T136 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.664664014 Oct 12 02:08:21 PM UTC 24 Oct 12 02:08:28 PM UTC 24 396220057 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.99552415 Oct 12 02:08:24 PM UTC 24 Oct 12 02:08:28 PM UTC 24 51197239 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.402348025 Oct 12 02:08:25 PM UTC 24 Oct 12 02:08:28 PM UTC 24 140211329 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.3719345343 Oct 12 02:08:21 PM UTC 24 Oct 12 02:08:29 PM UTC 24 1197995435 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.777319866 Oct 12 02:08:26 PM UTC 24 Oct 12 02:08:29 PM UTC 24 74888372 ps
T1045 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1850961301 Oct 12 02:08:34 PM UTC 24 Oct 12 02:08:37 PM UTC 24 25822312 ps
T1046 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3908811053 Oct 12 02:08:24 PM UTC 24 Oct 12 02:08:29 PM UTC 24 116509177 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2181503642 Oct 12 02:08:21 PM UTC 24 Oct 12 02:08:30 PM UTC 24 516640441 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.654384903 Oct 12 02:08:28 PM UTC 24 Oct 12 02:08:30 PM UTC 24 24437802 ps
T1047 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.2243705593 Oct 12 02:08:27 PM UTC 24 Oct 12 02:08:30 PM UTC 24 17395599 ps
T1048 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.3916161112 Oct 12 02:08:27 PM UTC 24 Oct 12 02:08:30 PM UTC 24 33202259 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.1148541144 Oct 12 02:08:24 PM UTC 24 Oct 12 02:08:30 PM UTC 24 192248745 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1260390197 Oct 12 02:08:26 PM UTC 24 Oct 12 02:08:30 PM UTC 24 210405766 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.602752768 Oct 12 02:08:28 PM UTC 24 Oct 12 02:08:31 PM UTC 24 135771092 ps
T1049 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.1769609430 Oct 12 02:08:29 PM UTC 24 Oct 12 02:08:31 PM UTC 24 73434736 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.2647964636 Oct 12 02:08:28 PM UTC 24 Oct 12 02:08:32 PM UTC 24 25059070 ps
T1050 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.1335260632 Oct 12 02:08:29 PM UTC 24 Oct 12 02:08:32 PM UTC 24 33347002 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.1540928342 Oct 12 02:08:29 PM UTC 24 Oct 12 02:08:32 PM UTC 24 402189634 ps
T1051 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2878126564 Oct 12 02:08:29 PM UTC 24 Oct 12 02:08:33 PM UTC 24 70324972 ps
T1052 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.610234183 Oct 12 02:08:30 PM UTC 24 Oct 12 02:08:33 PM UTC 24 22262165 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.1085546230 Oct 12 02:08:26 PM UTC 24 Oct 12 02:08:33 PM UTC 24 583694540 ps
T1053 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.883930320 Oct 12 02:08:29 PM UTC 24 Oct 12 02:08:33 PM UTC 24 73063727 ps
T137 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.2389014850 Oct 12 02:08:25 PM UTC 24 Oct 12 02:08:33 PM UTC 24 296948785 ps
T1054 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2940388896 Oct 12 02:08:30 PM UTC 24 Oct 12 02:08:34 PM UTC 24 280521887 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.2112520703 Oct 12 02:08:30 PM UTC 24 Oct 12 02:08:34 PM UTC 24 37685589 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.2610256610 Oct 12 02:08:26 PM UTC 24 Oct 12 02:08:34 PM UTC 24 113430205 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1379034734 Oct 12 02:08:29 PM UTC 24 Oct 12 02:08:35 PM UTC 24 233501245 ps
T1055 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.4051770284 Oct 12 02:08:26 PM UTC 24 Oct 12 02:08:35 PM UTC 24 115781860 ps
T1056 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.2912643951 Oct 12 02:08:33 PM UTC 24 Oct 12 02:08:35 PM UTC 24 88466949 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.4267351169 Oct 12 02:08:32 PM UTC 24 Oct 12 02:08:35 PM UTC 24 37138331 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.1655601410 Oct 12 02:08:32 PM UTC 24 Oct 12 02:08:35 PM UTC 24 60433285 ps
T1057 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3512972228 Oct 12 02:08:32 PM UTC 24 Oct 12 02:08:36 PM UTC 24 227876557 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.3406965272 Oct 12 02:08:33 PM UTC 24 Oct 12 02:08:36 PM UTC 24 44874546 ps
T1058 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.2633562568 Oct 12 02:08:34 PM UTC 24 Oct 12 02:08:36 PM UTC 24 15915449 ps
T1059 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.548683635 Oct 12 02:08:32 PM UTC 24 Oct 12 02:08:36 PM UTC 24 59440441 ps
T1060 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1157461523 Oct 12 02:08:21 PM UTC 24 Oct 12 02:08:36 PM UTC 24 2640772789 ps
T1061 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3053185591 Oct 12 02:08:33 PM UTC 24 Oct 12 02:08:36 PM UTC 24 70066737 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1900291458 Oct 12 02:08:33 PM UTC 24 Oct 12 02:08:37 PM UTC 24 146826992 ps
T1062 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3714330211 Oct 12 02:08:34 PM UTC 24 Oct 12 02:08:38 PM UTC 24 45812877 ps
T1063 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.1521693165 Oct 12 02:08:36 PM UTC 24 Oct 12 02:08:38 PM UTC 24 20720027 ps
T1064 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.1901220694 Oct 12 02:08:36 PM UTC 24 Oct 12 02:08:38 PM UTC 24 14184117 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.2190265669 Oct 12 02:08:34 PM UTC 24 Oct 12 02:08:38 PM UTC 24 123805143 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.435361441 Oct 12 02:08:33 PM UTC 24 Oct 12 02:08:38 PM UTC 24 58998582 ps
T1065 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4229261963 Oct 12 02:08:26 PM UTC 24 Oct 12 02:08:38 PM UTC 24 787011895 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2853944509 Oct 12 02:08:24 PM UTC 24 Oct 12 02:08:38 PM UTC 24 907502086 ps
T1066 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.789523737 Oct 12 02:08:36 PM UTC 24 Oct 12 02:08:39 PM UTC 24 43193499 ps
T1067 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.1906735019 Oct 12 02:08:38 PM UTC 24 Oct 12 02:08:40 PM UTC 24 16413801 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.1778797338 Oct 12 02:08:24 PM UTC 24 Oct 12 02:08:40 PM UTC 24 1389415148 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.110752618 Oct 12 02:08:24 PM UTC 24 Oct 12 02:08:40 PM UTC 24 1793713739 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.2734259627 Oct 12 02:08:34 PM UTC 24 Oct 12 02:08:40 PM UTC 24 74136687 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.2105227401 Oct 12 02:08:38 PM UTC 24 Oct 12 02:08:40 PM UTC 24 43701223 ps
T1068 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2202569317 Oct 12 02:08:37 PM UTC 24 Oct 12 02:08:41 PM UTC 24 47812098 ps
T1069 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2353624789 Oct 12 02:08:36 PM UTC 24 Oct 12 02:08:41 PM UTC 24 119991002 ps
T1070 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.97289828 Oct 12 02:08:39 PM UTC 24 Oct 12 02:08:41 PM UTC 24 27513532 ps
T1071 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3539625371 Oct 12 02:08:36 PM UTC 24 Oct 12 02:08:41 PM UTC 24 322857235 ps
T1072 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.1414424792 Oct 12 02:08:40 PM UTC 24 Oct 12 02:08:41 PM UTC 24 23699505 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.1606513024 Oct 12 02:08:21 PM UTC 24 Oct 12 02:08:42 PM UTC 24 3706725134 ps
T1073 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1108107005 Oct 12 02:08:37 PM UTC 24 Oct 12 02:08:42 PM UTC 24 217414805 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.421823253 Oct 12 02:08:39 PM UTC 24 Oct 12 02:08:42 PM UTC 24 51182636 ps
T1074 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.337635294 Oct 12 02:08:39 PM UTC 24 Oct 12 02:08:42 PM UTC 24 113841247 ps
T1075 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.366395741 Oct 12 02:08:28 PM UTC 24 Oct 12 02:08:43 PM UTC 24 411818125 ps
T1076 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.3617875423 Oct 12 02:08:50 PM UTC 24 Oct 12 02:08:52 PM UTC 24 51058575 ps
T1077 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4251942574 Oct 12 02:08:39 PM UTC 24 Oct 12 02:08:43 PM UTC 24 350060567 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.1460536382 Oct 12 02:08:39 PM UTC 24 Oct 12 02:08:43 PM UTC 24 129894677 ps
T1078 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.3407128545 Oct 12 02:08:41 PM UTC 24 Oct 12 02:08:43 PM UTC 24 24542234 ps
T1079 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3472559478 Oct 12 02:08:38 PM UTC 24 Oct 12 02:08:43 PM UTC 24 980886107 ps
T1080 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.414875739 Oct 12 02:08:37 PM UTC 24 Oct 12 02:08:44 PM UTC 24 210601104 ps
T1081 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3718461639 Oct 12 02:08:41 PM UTC 24 Oct 12 02:08:44 PM UTC 24 108321297 ps
T1082 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1943073695 Oct 12 02:08:41 PM UTC 24 Oct 12 02:08:44 PM UTC 24 46230789 ps
T1083 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.2630306218 Oct 12 02:08:41 PM UTC 24 Oct 12 02:08:44 PM UTC 24 276900633 ps
T1084 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2982495181 Oct 12 02:08:39 PM UTC 24 Oct 12 02:08:44 PM UTC 24 203053580 ps
T1085 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2418678654 Oct 12 02:08:43 PM UTC 24 Oct 12 02:08:45 PM UTC 24 45473191 ps
T1086 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.722447861 Oct 12 02:08:34 PM UTC 24 Oct 12 02:08:45 PM UTC 24 1458058598 ps
T1087 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.144508476 Oct 12 02:08:41 PM UTC 24 Oct 12 02:08:45 PM UTC 24 155878030 ps
T1088 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2086017627 Oct 12 02:08:41 PM UTC 24 Oct 12 02:08:45 PM UTC 24 162167418 ps
T1089 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.3062958868 Oct 12 02:08:40 PM UTC 24 Oct 12 02:08:45 PM UTC 24 190783859 ps
T1090 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.2890162264 Oct 12 02:08:41 PM UTC 24 Oct 12 02:08:45 PM UTC 24 92838700 ps
T1091 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.1087568982 Oct 12 02:08:43 PM UTC 24 Oct 12 02:08:45 PM UTC 24 199486256 ps
T1092 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.2372031612 Oct 12 02:08:41 PM UTC 24 Oct 12 02:08:45 PM UTC 24 50783777 ps
T1093 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.2460481656 Oct 12 02:08:41 PM UTC 24 Oct 12 02:08:45 PM UTC 24 95884955 ps
T1094 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.3933117217 Oct 12 02:08:50 PM UTC 24 Oct 12 02:08:52 PM UTC 24 13507064 ps
T1095 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.1225690463 Oct 12 02:08:44 PM UTC 24 Oct 12 02:08:46 PM UTC 24 14718979 ps
T1096 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.2043492116 Oct 12 02:08:39 PM UTC 24 Oct 12 02:08:46 PM UTC 24 157350255 ps
T1097 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.1943913848 Oct 12 02:08:45 PM UTC 24 Oct 12 02:08:46 PM UTC 24 12193533 ps
T1098 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3865088737 Oct 12 02:08:43 PM UTC 24 Oct 12 02:08:46 PM UTC 24 45007972 ps
T1099 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1946782808 Oct 12 02:08:44 PM UTC 24 Oct 12 02:08:47 PM UTC 24 68634296 ps
T1100 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.3185222115 Oct 12 02:08:44 PM UTC 24 Oct 12 02:08:47 PM UTC 24 69654369 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.184562595 Oct 12 02:08:29 PM UTC 24 Oct 12 02:08:48 PM UTC 24 307724520 ps
T1101 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3109388968 Oct 12 02:08:43 PM UTC 24 Oct 12 02:08:48 PM UTC 24 106354357 ps
T1102 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.1824257835 Oct 12 02:08:44 PM UTC 24 Oct 12 02:08:48 PM UTC 24 70451404 ps
T1103 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4206377027 Oct 12 02:08:44 PM UTC 24 Oct 12 02:08:48 PM UTC 24 436968584 ps
T1104 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.301815708 Oct 12 02:08:50 PM UTC 24 Oct 12 02:08:52 PM UTC 24 30652753 ps
T1105 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.1158441294 Oct 12 02:08:47 PM UTC 24 Oct 12 02:08:49 PM UTC 24 48268643 ps
T1106 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.4078820011 Oct 12 02:08:47 PM UTC 24 Oct 12 02:08:49 PM UTC 24 33450688 ps
T1107 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.3329497858 Oct 12 02:08:50 PM UTC 24 Oct 12 02:08:52 PM UTC 24 57761077 ps
T1108 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.3558355081 Oct 12 02:08:47 PM UTC 24 Oct 12 02:08:49 PM UTC 24 31355360 ps
T1109 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.4198435409 Oct 12 02:08:43 PM UTC 24 Oct 12 02:08:49 PM UTC 24 223549130 ps
T1110 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.972941781 Oct 12 02:08:47 PM UTC 24 Oct 12 02:08:49 PM UTC 24 15103931 ps
T1111 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.1738833138 Oct 12 02:08:47 PM UTC 24 Oct 12 02:08:49 PM UTC 24 92416839 ps
T1112 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.2921532708 Oct 12 02:08:47 PM UTC 24 Oct 12 02:08:49 PM UTC 24 58497743 ps
T1113 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.2634470963 Oct 12 02:08:47 PM UTC 24 Oct 12 02:08:50 PM UTC 24 77662552 ps
T1114 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.4258205958 Oct 12 02:08:47 PM UTC 24 Oct 12 02:08:50 PM UTC 24 421691833 ps
T1115 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.4287486322 Oct 12 02:08:50 PM UTC 24 Oct 12 02:08:52 PM UTC 24 74780470 ps
T1116 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.2271245472 Oct 12 02:08:47 PM UTC 24 Oct 12 02:08:50 PM UTC 24 115202799 ps
T1117 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.3957403305 Oct 12 02:08:49 PM UTC 24 Oct 12 02:08:50 PM UTC 24 15694682 ps
T1118 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.647298120 Oct 12 02:08:49 PM UTC 24 Oct 12 02:08:51 PM UTC 24 13668463 ps
T1119 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.2604259258 Oct 12 02:08:49 PM UTC 24 Oct 12 02:08:51 PM UTC 24 18899101 ps
T1120 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.3857566208 Oct 12 02:08:51 PM UTC 24 Oct 12 02:08:52 PM UTC 24 18855371 ps
T1121 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.2625064944 Oct 12 02:08:49 PM UTC 24 Oct 12 02:08:51 PM UTC 24 42867537 ps
T1122 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2109702630 Oct 12 02:08:47 PM UTC 24 Oct 12 02:08:51 PM UTC 24 397323456 ps
T1123 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.3812759809 Oct 12 02:08:47 PM UTC 24 Oct 12 02:08:51 PM UTC 24 150047486 ps
T1124 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.1107764746 Oct 12 02:08:49 PM UTC 24 Oct 12 02:08:51 PM UTC 24 43775340 ps
T1125 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3748604742 Oct 12 02:08:47 PM UTC 24 Oct 12 02:08:51 PM UTC 24 42795779 ps
T1126 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2526240933 Oct 12 02:08:47 PM UTC 24 Oct 12 02:08:51 PM UTC 24 207511595 ps
T1127 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.4090863091 Oct 12 02:08:49 PM UTC 24 Oct 12 02:08:51 PM UTC 24 38574625 ps
T1128 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1513314744 Oct 12 02:08:47 PM UTC 24 Oct 12 02:08:51 PM UTC 24 95196656 ps
T1129 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2429219256 Oct 12 02:08:47 PM UTC 24 Oct 12 02:08:51 PM UTC 24 130128123 ps
T1130 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.220909285 Oct 12 02:08:49 PM UTC 24 Oct 12 02:08:51 PM UTC 24 48312563 ps
T1131 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.808045344 Oct 12 02:08:49 PM UTC 24 Oct 12 02:08:51 PM UTC 24 42176045 ps
T1132 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.2170956109 Oct 12 02:08:49 PM UTC 24 Oct 12 02:08:51 PM UTC 24 42169227 ps
T1133 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1713711497 Oct 12 02:08:47 PM UTC 24 Oct 12 02:08:51 PM UTC 24 157466542 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.3707916225 Oct 12 02:08:36 PM UTC 24 Oct 12 02:08:52 PM UTC 24 684994201 ps
T1134 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.3490879343 Oct 12 02:08:50 PM UTC 24 Oct 12 02:08:52 PM UTC 24 12194644 ps
T1135 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.2688648325 Oct 12 02:08:50 PM UTC 24 Oct 12 02:08:52 PM UTC 24 143681013 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.1136999898 Oct 12 02:08:44 PM UTC 24 Oct 12 02:08:52 PM UTC 24 288370052 ps
T1136 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.3648190897 Oct 12 02:08:50 PM UTC 24 Oct 12 02:08:52 PM UTC 24 32330599 ps
T1137 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.2872307337 Oct 12 02:08:50 PM UTC 24 Oct 12 02:08:52 PM UTC 24 36728957 ps
T1138 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.1378030771 Oct 12 02:08:52 PM UTC 24 Oct 12 02:08:53 PM UTC 24 83951326 ps
T1139 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3279803160 Oct 12 02:08:52 PM UTC 24 Oct 12 02:08:53 PM UTC 24 25537929 ps
T1140 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.772986665 Oct 12 02:08:30 PM UTC 24 Oct 12 02:08:53 PM UTC 24 1227747642 ps
T1141 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.783870820 Oct 12 02:08:52 PM UTC 24 Oct 12 02:08:54 PM UTC 24 21816822 ps
T1142 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.2620615475 Oct 12 02:08:52 PM UTC 24 Oct 12 02:08:54 PM UTC 24 47146142 ps
T1143 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.1104507507 Oct 12 02:08:52 PM UTC 24 Oct 12 02:08:54 PM UTC 24 44488647 ps
T1144 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.3639657234 Oct 12 02:08:52 PM UTC 24 Oct 12 02:08:54 PM UTC 24 16942220 ps
T1145 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.3789609295 Oct 12 02:08:52 PM UTC 24 Oct 12 02:08:54 PM UTC 24 29080081 ps
T1146 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.2208166160 Oct 12 02:08:52 PM UTC 24 Oct 12 02:08:54 PM UTC 24 14816228 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.1407495001 Oct 12 02:08:38 PM UTC 24 Oct 12 02:08:54 PM UTC 24 1387026340 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.3600565897 Oct 12 02:08:40 PM UTC 24 Oct 12 02:08:56 PM UTC 24 747077793 ps
T1147 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4217066683 Oct 12 02:08:21 PM UTC 24 Oct 12 02:08:56 PM UTC 24 2444185175 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3510359634 Oct 12 02:08:36 PM UTC 24 Oct 12 02:08:58 PM UTC 24 846586565 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.4145539418 Oct 12 02:08:47 PM UTC 24 Oct 12 02:09:00 PM UTC 24 200019341 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.3853723513 Oct 12 02:08:41 PM UTC 24 Oct 12 02:09:00 PM UTC 24 1693120585 ps
T1148 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.880667204 Oct 12 02:08:41 PM UTC 24 Oct 12 02:09:02 PM UTC 24 3915627840 ps
T1149 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.800894001 Oct 12 02:08:47 PM UTC 24 Oct 12 02:09:05 PM UTC 24 1810930234 ps
T1150 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.2863503870 Oct 12 02:08:44 PM UTC 24 Oct 12 02:09:06 PM UTC 24 8246438846 ps
T1151 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2860657775 Oct 12 02:08:28 PM UTC 24 Oct 12 02:09:07 PM UTC 24 22549461701 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.1975229245
Short name T10
Test name
Test status
Simulation time 96712414 ps
CPU time 3.13 seconds
Started Oct 12 02:18:37 PM UTC 24
Finished Oct 12 02:18:44 PM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975229245 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.1975229245
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.1769787078
Short name T52
Test name
Test status
Simulation time 14831278898 ps
CPU time 33.49 seconds
Started Oct 12 02:18:37 PM UTC 24
Finished Oct 12 02:19:15 PM UTC 24
Peak memory 251232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769787078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.1769787078
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.1683745996
Short name T21
Test name
Test status
Simulation time 404712208 ps
CPU time 5.79 seconds
Started Oct 12 02:18:44 PM UTC 24
Finished Oct 12 02:18:52 PM UTC 24
Peak memory 245168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683745996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1683745996
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.2986288400
Short name T50
Test name
Test status
Simulation time 22358284934 ps
CPU time 143.75 seconds
Started Oct 12 02:19:24 PM UTC 24
Finished Oct 12 02:21:51 PM UTC 24
Peak memory 283984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986288400 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.2986288400
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.1819498496
Short name T30
Test name
Test status
Simulation time 2272981246 ps
CPU time 19.26 seconds
Started Oct 12 02:18:32 PM UTC 24
Finished Oct 12 02:19:02 PM UTC 24
Peak memory 227360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819498496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1819498496
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.1243454828
Short name T72
Test name
Test status
Simulation time 18048703654 ps
CPU time 132.16 seconds
Started Oct 12 02:19:21 PM UTC 24
Finished Oct 12 02:21:36 PM UTC 24
Peak memory 261800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243454828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.1243454828
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.306157997
Short name T112
Test name
Test status
Simulation time 25002344073 ps
CPU time 163.33 seconds
Started Oct 12 02:19:11 PM UTC 24
Finished Oct 12 02:21:58 PM UTC 24
Peak memory 267928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306157997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.306157997
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1249486038
Short name T113
Test name
Test status
Simulation time 88353905 ps
CPU time 1.23 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:23 PM UTC 24
Peak memory 214312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249486038 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.1249486038
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.3308012420
Short name T3
Test name
Test status
Simulation time 17207899 ps
CPU time 0.66 seconds
Started Oct 12 02:18:27 PM UTC 24
Finished Oct 12 02:18:32 PM UTC 24
Peak memory 225464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308012420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3308012420
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1375418551
Short name T67
Test name
Test status
Simulation time 32087715423 ps
CPU time 33.19 seconds
Started Oct 12 02:20:02 PM UTC 24
Finished Oct 12 02:20:36 PM UTC 24
Peak memory 251296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375418551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.1375418551
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.3792773811
Short name T135
Test name
Test status
Simulation time 221849944 ps
CPU time 5.29 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:27 PM UTC 24
Peak memory 227976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792773811 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3792773811
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.1020790299
Short name T6
Test name
Test status
Simulation time 56563753 ps
CPU time 0.95 seconds
Started Oct 12 02:18:39 PM UTC 24
Finished Oct 12 02:18:41 PM UTC 24
Peak memory 256900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020790299 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1020790299
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.2366111418
Short name T126
Test name
Test status
Simulation time 7607000776 ps
CPU time 15.35 seconds
Started Oct 12 02:18:53 PM UTC 24
Finished Oct 12 02:19:10 PM UTC 24
Peak memory 234848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366111418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2366111418
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.1076016873
Short name T73
Test name
Test status
Simulation time 7671533195 ps
CPU time 204.79 seconds
Started Oct 12 02:18:38 PM UTC 24
Finished Oct 12 02:22:07 PM UTC 24
Peak memory 284004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076016873 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.1076016873
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.3988739764
Short name T233
Test name
Test status
Simulation time 6040799795 ps
CPU time 164.47 seconds
Started Oct 12 02:21:52 PM UTC 24
Finished Oct 12 02:24:40 PM UTC 24
Peak memory 275812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988739764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3988739764
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3321584900
Short name T4
Test name
Test status
Simulation time 686057924 ps
CPU time 3.67 seconds
Started Oct 12 02:18:27 PM UTC 24
Finished Oct 12 02:18:35 PM UTC 24
Peak memory 227240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321584900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3321584900
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1281253648
Short name T74
Test name
Test status
Simulation time 5371175925 ps
CPU time 128.49 seconds
Started Oct 12 02:20:01 PM UTC 24
Finished Oct 12 02:22:13 PM UTC 24
Peak memory 265628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281253648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1281253648
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.1077733165
Short name T207
Test name
Test status
Simulation time 12630534139 ps
CPU time 68.02 seconds
Started Oct 12 02:23:20 PM UTC 24
Finished Oct 12 02:24:29 PM UTC 24
Peak memory 263720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077733165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.1077733165
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.1778797338
Short name T194
Test name
Test status
Simulation time 1389415148 ps
CPU time 14.73 seconds
Started Oct 12 02:08:24 PM UTC 24
Finished Oct 12 02:08:40 PM UTC 24
Peak memory 227976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778797338 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.1778797338
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.1675588493
Short name T91
Test name
Test status
Simulation time 15522058258 ps
CPU time 62.56 seconds
Started Oct 12 02:18:37 PM UTC 24
Finished Oct 12 02:19:44 PM UTC 24
Peak memory 261416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675588493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1675588493
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.527133097
Short name T267
Test name
Test status
Simulation time 42763711979 ps
CPU time 146.86 seconds
Started Oct 12 02:23:24 PM UTC 24
Finished Oct 12 02:25:54 PM UTC 24
Peak memory 267612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527133097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.527133097
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_all.3991451167
Short name T242
Test name
Test status
Simulation time 8524788846 ps
CPU time 115.76 seconds
Started Oct 12 02:23:03 PM UTC 24
Finished Oct 12 02:25:01 PM UTC 24
Peak memory 276024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991451167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3991451167
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.2679965155
Short name T232
Test name
Test status
Simulation time 2790940686 ps
CPU time 73.98 seconds
Started Oct 12 02:22:15 PM UTC 24
Finished Oct 12 02:23:30 PM UTC 24
Peak memory 265572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679965155 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.2679965155
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.3765361153
Short name T206
Test name
Test status
Simulation time 9214681649 ps
CPU time 60.32 seconds
Started Oct 12 02:21:27 PM UTC 24
Finished Oct 12 02:22:29 PM UTC 24
Peak memory 263844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765361153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3765361153
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.3462650105
Short name T44
Test name
Test status
Simulation time 34742915 ps
CPU time 1.22 seconds
Started Oct 12 02:18:48 PM UTC 24
Finished Oct 12 02:18:52 PM UTC 24
Peak memory 228880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462650105 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_parity.3462650105
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.2292819189
Short name T352
Test name
Test status
Simulation time 19489091358 ps
CPU time 143.07 seconds
Started Oct 12 02:32:17 PM UTC 24
Finished Oct 12 02:34:43 PM UTC 24
Peak memory 265568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292819189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2292819189
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/36.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.594265736
Short name T166
Test name
Test status
Simulation time 102928070581 ps
CPU time 135.75 seconds
Started Oct 12 02:23:04 PM UTC 24
Finished Oct 12 02:25:23 PM UTC 24
Peak memory 265824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594265736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.594265736
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.3029103073
Short name T236
Test name
Test status
Simulation time 234298816538 ps
CPU time 320.08 seconds
Started Oct 12 02:19:42 PM UTC 24
Finished Oct 12 02:25:06 PM UTC 24
Peak memory 267856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029103073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.3029103073
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.4172433997
Short name T359
Test name
Test status
Simulation time 37532528988 ps
CPU time 206.43 seconds
Started Oct 12 02:38:39 PM UTC 24
Finished Oct 12 02:42:09 PM UTC 24
Peak memory 296352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172433997 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.4172433997
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/47.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.1695292832
Short name T200
Test name
Test status
Simulation time 119744688234 ps
CPU time 349.34 seconds
Started Oct 12 02:21:28 PM UTC 24
Finished Oct 12 02:27:23 PM UTC 24
Peak memory 294304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695292832 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.1695292832
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1495025597
Short name T208
Test name
Test status
Simulation time 323306426 ps
CPU time 10.39 seconds
Started Oct 12 02:19:30 PM UTC 24
Finished Oct 12 02:19:41 PM UTC 24
Peak memory 244956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495025597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1495025597
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.518287973
Short name T111
Test name
Test status
Simulation time 6454738793 ps
CPU time 123.19 seconds
Started Oct 12 02:19:40 PM UTC 24
Finished Oct 12 02:21:45 PM UTC 24
Peak memory 278116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518287973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.518287973
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.1753975799
Short name T103
Test name
Test status
Simulation time 18250972 ps
CPU time 1.13 seconds
Started Oct 12 02:18:42 PM UTC 24
Finished Oct 12 02:18:51 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753975799 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1753975799
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_stress_all.3846245239
Short name T199
Test name
Test status
Simulation time 76569335443 ps
CPU time 89.15 seconds
Started Oct 12 02:25:19 PM UTC 24
Finished Oct 12 02:26:51 PM UTC 24
Peak memory 265896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846245239 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.3846245239
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.325119606
Short name T360
Test name
Test status
Simulation time 189710468942 ps
CPU time 497.74 seconds
Started Oct 12 02:29:53 PM UTC 24
Finished Oct 12 02:38:17 PM UTC 24
Peak memory 294248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325119606 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.325119606
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/31.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.3789780629
Short name T25
Test name
Test status
Simulation time 1275294142 ps
CPU time 9.35 seconds
Started Oct 12 02:18:44 PM UTC 24
Finished Oct 12 02:18:55 PM UTC 24
Peak memory 251112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789780629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.3789780629
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.13468224
Short name T55
Test name
Test status
Simulation time 456796102 ps
CPU time 8.3 seconds
Started Oct 12 02:19:09 PM UTC 24
Finished Oct 12 02:19:18 PM UTC 24
Peak memory 245168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13468224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.13468224
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.3677879476
Short name T313
Test name
Test status
Simulation time 14853891048 ps
CPU time 113.11 seconds
Started Oct 12 02:27:05 PM UTC 24
Finished Oct 12 02:29:00 PM UTC 24
Peak memory 267560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677879476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3677879476
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/24.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.414875739
Short name T1080
Test name
Test status
Simulation time 210601104 ps
CPU time 5.28 seconds
Started Oct 12 02:08:37 PM UTC 24
Finished Oct 12 02:08:44 PM UTC 24
Peak memory 227980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414875739 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.414875739
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.1136999898
Short name T219
Test name
Test status
Simulation time 288370052 ps
CPU time 6.87 seconds
Started Oct 12 02:08:44 PM UTC 24
Finished Oct 12 02:08:52 PM UTC 24
Peak memory 227508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136999898 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.1136999898
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.1839215352
Short name T310
Test name
Test status
Simulation time 34527647556 ps
CPU time 342.28 seconds
Started Oct 12 02:21:24 PM UTC 24
Finished Oct 12 02:27:12 PM UTC 24
Peak memory 274036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839215352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1839215352
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode.4189677273
Short name T376
Test name
Test status
Simulation time 2066242125 ps
CPU time 14.64 seconds
Started Oct 12 02:32:32 PM UTC 24
Finished Oct 12 02:32:48 PM UTC 24
Peak memory 244904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189677273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.4189677273
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/37.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.92696821
Short name T249
Test name
Test status
Simulation time 3716887855 ps
CPU time 21.12 seconds
Started Oct 12 02:20:12 PM UTC 24
Finished Oct 12 02:20:35 PM UTC 24
Peak memory 245084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92696821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.92696821
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2238281269
Short name T155
Test name
Test status
Simulation time 91369135 ps
CPU time 2.66 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:24 PM UTC 24
Peak memory 215760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238281269 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2238281269
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.1914169555
Short name T84
Test name
Test status
Simulation time 160243555589 ps
CPU time 501.75 seconds
Started Oct 12 02:35:22 PM UTC 24
Finished Oct 12 02:43:51 PM UTC 24
Peak memory 278180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914169555 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.1914169555
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/42.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.86921232
Short name T5
Test name
Test status
Simulation time 274962353 ps
CPU time 0.73 seconds
Started Oct 12 02:18:33 PM UTC 24
Finished Oct 12 02:18:36 PM UTC 24
Peak memory 216400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86921232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.86921232
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_stress_all.1081268080
Short name T274
Test name
Test status
Simulation time 31825745919 ps
CPU time 147.06 seconds
Started Oct 12 02:23:28 PM UTC 24
Finished Oct 12 02:25:58 PM UTC 24
Peak memory 277920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081268080 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.1081268080
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.1132705885
Short name T921
Test name
Test status
Simulation time 317410569891 ps
CPU time 641.32 seconds
Started Oct 12 02:26:04 PM UTC 24
Finished Oct 12 02:36:53 PM UTC 24
Peak memory 277900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132705885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1132705885
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.3105670822
Short name T372
Test name
Test status
Simulation time 4862752091 ps
CPU time 17.95 seconds
Started Oct 12 02:27:00 PM UTC 24
Finished Oct 12 02:27:19 PM UTC 24
Peak memory 247072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105670822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3105670822
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/24.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.224367631
Short name T280
Test name
Test status
Simulation time 987350791 ps
CPU time 14.79 seconds
Started Oct 12 02:28:10 PM UTC 24
Finished Oct 12 02:28:27 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224367631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.224367631
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/27.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.2058676291
Short name T263
Test name
Test status
Simulation time 345696686592 ps
CPU time 572.65 seconds
Started Oct 12 02:29:07 PM UTC 24
Finished Oct 12 02:38:47 PM UTC 24
Peak memory 277904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058676291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.2058676291
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.759233312
Short name T45
Test name
Test status
Simulation time 1652176967 ps
CPU time 27.39 seconds
Started Oct 12 02:18:37 PM UTC 24
Finished Oct 12 02:19:09 PM UTC 24
Peak memory 229352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759233312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.759233312
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3510359634
Short name T217
Test name
Test status
Simulation time 846586565 ps
CPU time 20.48 seconds
Started Oct 12 02:08:36 PM UTC 24
Finished Oct 12 02:08:58 PM UTC 24
Peak memory 228068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510359634 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.3510359634
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.1407495001
Short name T218
Test name
Test status
Simulation time 1387026340 ps
CPU time 15.33 seconds
Started Oct 12 02:08:38 PM UTC 24
Finished Oct 12 02:08:54 PM UTC 24
Peak memory 227996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407495001 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.1407495001
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.3853723513
Short name T223
Test name
Test status
Simulation time 1693120585 ps
CPU time 17.8 seconds
Started Oct 12 02:08:41 PM UTC 24
Finished Oct 12 02:09:00 PM UTC 24
Peak memory 230000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853723513 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.3853723513
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.845524862
Short name T102
Test name
Test status
Simulation time 209269786 ps
CPU time 5.95 seconds
Started Oct 12 02:18:36 PM UTC 24
Finished Oct 12 02:19:03 PM UTC 24
Peak memory 234908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845524862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.845524862
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.1482601962
Short name T49
Test name
Test status
Simulation time 191108122206 ps
CPU time 125.97 seconds
Started Oct 12 02:18:45 PM UTC 24
Finished Oct 12 02:20:53 PM UTC 24
Peak memory 263724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482601962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.1482601962
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.1878706538
Short name T42
Test name
Test status
Simulation time 36069815661 ps
CPU time 67.47 seconds
Started Oct 12 02:21:53 PM UTC 24
Finished Oct 12 02:23:02 PM UTC 24
Peak memory 261768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878706538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1878706538
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.159714174
Short name T256
Test name
Test status
Simulation time 63584183616 ps
CPU time 327.86 seconds
Started Oct 12 02:21:56 PM UTC 24
Finished Oct 12 02:27:28 PM UTC 24
Peak memory 267876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159714174 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.159714174
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.4005616332
Short name T171
Test name
Test status
Simulation time 8540281048 ps
CPU time 94.22 seconds
Started Oct 12 02:23:50 PM UTC 24
Finished Oct 12 02:25:27 PM UTC 24
Peak memory 265704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005616332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4005616332
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.215136506
Short name T237
Test name
Test status
Simulation time 130092617814 ps
CPU time 268.12 seconds
Started Oct 12 02:23:53 PM UTC 24
Finished Oct 12 02:28:25 PM UTC 24
Peak memory 278176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215136506 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.215136506
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.3219326304
Short name T357
Test name
Test status
Simulation time 108974855497 ps
CPU time 241.53 seconds
Started Oct 12 02:27:35 PM UTC 24
Finished Oct 12 02:31:40 PM UTC 24
Peak memory 277860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219326304 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.3219326304
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/25.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_cfg_cmd.3087750262
Short name T230
Test name
Test status
Simulation time 772398695 ps
CPU time 8.05 seconds
Started Oct 12 02:27:50 PM UTC 24
Finished Oct 12 02:27:59 PM UTC 24
Peak memory 244920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087750262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3087750262
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/26.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.4281385937
Short name T58
Test name
Test status
Simulation time 1825040803 ps
CPU time 10.66 seconds
Started Oct 12 02:18:58 PM UTC 24
Finished Oct 12 02:19:11 PM UTC 24
Peak memory 251172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281385937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.4281385937
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.2619060928
Short name T1
Test name
Test status
Simulation time 38161682 ps
CPU time 0.73 seconds
Started Oct 12 02:18:22 PM UTC 24
Finished Oct 12 02:18:31 PM UTC 24
Peak memory 215360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619060928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2619060928
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.3435254381
Short name T134
Test name
Test status
Simulation time 107036155 ps
CPU time 3.28 seconds
Started Oct 12 02:08:36 PM UTC 24
Finished Oct 12 02:08:40 PM UTC 24
Peak memory 225956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435254381 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.3435254381
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.3719345343
Short name T160
Test name
Test status
Simulation time 1197995435 ps
CPU time 6.93 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:29 PM UTC 24
Peak memory 217688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719345343 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.3719345343
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1157461523
Short name T1060
Test name
Test status
Simulation time 2640772789 ps
CPU time 14.4 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:36 PM UTC 24
Peak memory 225784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157461523 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.1157461523
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1926297945
Short name T1037
Test name
Test status
Simulation time 40275319 ps
CPU time 0.89 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:23 PM UTC 24
Peak memory 214460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926297945 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.1926297945
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2118668739
Short name T132
Test name
Test status
Simulation time 136248174 ps
CPU time 3.64 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:26 PM UTC 24
Peak memory 230048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2118668739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.spi_device_csr_mem_rw_with_rand_reset.2118668739
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.1009043882
Short name T1036
Test name
Test status
Simulation time 45575750 ps
CPU time 0.81 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:23 PM UTC 24
Peak memory 213512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009043882 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1009043882
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1851981445
Short name T153
Test name
Test status
Simulation time 34019599 ps
CPU time 1.78 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:24 PM UTC 24
Peak memory 224680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851981445 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.1851981445
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.3477976138
Short name T1035
Test name
Test status
Simulation time 13508331 ps
CPU time 0.76 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:23 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477976138 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.3477976138
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.184718093
Short name T1040
Test name
Test status
Simulation time 108074205 ps
CPU time 1.65 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:24 PM UTC 24
Peak memory 215000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184718093 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstanding.184718093
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.936845917
Short name T130
Test name
Test status
Simulation time 62907814 ps
CPU time 1.61 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:23 PM UTC 24
Peak memory 224988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936845917 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.936845917
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.1606513024
Short name T215
Test name
Test status
Simulation time 3706725134 ps
CPU time 19.98 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:42 PM UTC 24
Peak memory 228060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606513024 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.1606513024
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2181503642
Short name T188
Test name
Test status
Simulation time 516640441 ps
CPU time 7.08 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:30 PM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181503642 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.2181503642
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4217066683
Short name T1147
Test name
Test status
Simulation time 2444185175 ps
CPU time 33.61 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:56 PM UTC 24
Peak memory 225600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217066683 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.4217066683
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2184200013
Short name T148
Test name
Test status
Simulation time 56234468 ps
CPU time 3.27 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:26 PM UTC 24
Peak memory 229972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2184200013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.spi_device_csr_mem_rw_with_rand_reset.2184200013
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.129042772
Short name T183
Test name
Test status
Simulation time 59673160 ps
CPU time 1.3 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:24 PM UTC 24
Peak memory 224684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129042772 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.129042772
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.1395182718
Short name T1038
Test name
Test status
Simulation time 32506304 ps
CPU time 0.8 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:23 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395182718 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1395182718
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.2870518487
Short name T154
Test name
Test status
Simulation time 135457801 ps
CPU time 1.57 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:24 PM UTC 24
Peak memory 224680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870518487 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.2870518487
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2510338846
Short name T1039
Test name
Test status
Simulation time 11444021 ps
CPU time 0.66 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:23 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510338846 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.2510338846
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1458644714
Short name T197
Test name
Test status
Simulation time 62819715 ps
CPU time 1.67 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:24 PM UTC 24
Peak memory 225148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458644714 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstanding.1458644714
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.664664014
Short name T136
Test name
Test status
Simulation time 396220057 ps
CPU time 5.45 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:28 PM UTC 24
Peak memory 227880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664664014 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.664664014
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2202569317
Short name T1068
Test name
Test status
Simulation time 47812098 ps
CPU time 2.08 seconds
Started Oct 12 02:08:37 PM UTC 24
Finished Oct 12 02:08:41 PM UTC 24
Peak memory 228128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2202569317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
10.spi_device_csr_mem_rw_with_rand_reset.2202569317
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.4062165874
Short name T182
Test name
Test status
Simulation time 80235151 ps
CPU time 1.81 seconds
Started Oct 12 02:08:37 PM UTC 24
Finished Oct 12 02:08:40 PM UTC 24
Peak memory 214400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062165874 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.4062165874
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.1901220694
Short name T1064
Test name
Test status
Simulation time 14184117 ps
CPU time 0.9 seconds
Started Oct 12 02:08:36 PM UTC 24
Finished Oct 12 02:08:38 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901220694 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.1901220694
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1108107005
Short name T1073
Test name
Test status
Simulation time 217414805 ps
CPU time 3.81 seconds
Started Oct 12 02:08:37 PM UTC 24
Finished Oct 12 02:08:42 PM UTC 24
Peak memory 225932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108107005 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstanding.1108107005
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4251942574
Short name T1077
Test name
Test status
Simulation time 350060567 ps
CPU time 2.81 seconds
Started Oct 12 02:08:39 PM UTC 24
Finished Oct 12 02:08:43 PM UTC 24
Peak memory 228176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4251942574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
11.spi_device_csr_mem_rw_with_rand_reset.4251942574
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.2105227401
Short name T163
Test name
Test status
Simulation time 43701223 ps
CPU time 1.81 seconds
Started Oct 12 02:08:38 PM UTC 24
Finished Oct 12 02:08:40 PM UTC 24
Peak memory 214400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105227401 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.2105227401
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.1906735019
Short name T1067
Test name
Test status
Simulation time 16413801 ps
CPU time 1.11 seconds
Started Oct 12 02:08:38 PM UTC 24
Finished Oct 12 02:08:40 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906735019 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.1906735019
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3472559478
Short name T1079
Test name
Test status
Simulation time 980886107 ps
CPU time 4.57 seconds
Started Oct 12 02:08:38 PM UTC 24
Finished Oct 12 02:08:43 PM UTC 24
Peak memory 226024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472559478 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstanding.3472559478
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2982495181
Short name T1084
Test name
Test status
Simulation time 203053580 ps
CPU time 3.75 seconds
Started Oct 12 02:08:39 PM UTC 24
Finished Oct 12 02:08:44 PM UTC 24
Peak memory 229984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2982495181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
12.spi_device_csr_mem_rw_with_rand_reset.2982495181
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.421823253
Short name T164
Test name
Test status
Simulation time 51182636 ps
CPU time 1.91 seconds
Started Oct 12 02:08:39 PM UTC 24
Finished Oct 12 02:08:42 PM UTC 24
Peak memory 224700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421823253 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.421823253
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.97289828
Short name T1070
Test name
Test status
Simulation time 27513532 ps
CPU time 0.86 seconds
Started Oct 12 02:08:39 PM UTC 24
Finished Oct 12 02:08:41 PM UTC 24
Peak memory 212440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97289828 -assert nopostproc +UVM_TESTNAME=spi
_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.97289828
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.337635294
Short name T1074
Test name
Test status
Simulation time 113841247 ps
CPU time 1.94 seconds
Started Oct 12 02:08:39 PM UTC 24
Finished Oct 12 02:08:42 PM UTC 24
Peak memory 225268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337635294 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstanding.337635294
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.1460536382
Short name T149
Test name
Test status
Simulation time 129894677 ps
CPU time 2.8 seconds
Started Oct 12 02:08:39 PM UTC 24
Finished Oct 12 02:08:43 PM UTC 24
Peak memory 226120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460536382 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.1460536382
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.2043492116
Short name T1096
Test name
Test status
Simulation time 157350255 ps
CPU time 6.06 seconds
Started Oct 12 02:08:39 PM UTC 24
Finished Oct 12 02:08:46 PM UTC 24
Peak memory 226068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043492116 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.2043492116
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1943073695
Short name T1082
Test name
Test status
Simulation time 46230789 ps
CPU time 1.94 seconds
Started Oct 12 02:08:41 PM UTC 24
Finished Oct 12 02:08:44 PM UTC 24
Peak memory 224736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1943073695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
13.spi_device_csr_mem_rw_with_rand_reset.1943073695
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.2630306218
Short name T1083
Test name
Test status
Simulation time 276900633 ps
CPU time 1.95 seconds
Started Oct 12 02:08:41 PM UTC 24
Finished Oct 12 02:08:44 PM UTC 24
Peak memory 224640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630306218 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.2630306218
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.1414424792
Short name T1072
Test name
Test status
Simulation time 23699505 ps
CPU time 0.83 seconds
Started Oct 12 02:08:40 PM UTC 24
Finished Oct 12 02:08:41 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414424792 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.1414424792
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3718461639
Short name T1081
Test name
Test status
Simulation time 108321297 ps
CPU time 1.93 seconds
Started Oct 12 02:08:41 PM UTC 24
Finished Oct 12 02:08:44 PM UTC 24
Peak memory 225084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718461639 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstanding.3718461639
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.3062958868
Short name T1089
Test name
Test status
Simulation time 190783859 ps
CPU time 4.48 seconds
Started Oct 12 02:08:40 PM UTC 24
Finished Oct 12 02:08:45 PM UTC 24
Peak memory 226056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062958868 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.3062958868
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.3600565897
Short name T224
Test name
Test status
Simulation time 747077793 ps
CPU time 15.26 seconds
Started Oct 12 02:08:40 PM UTC 24
Finished Oct 12 02:08:56 PM UTC 24
Peak memory 228024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600565897 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.3600565897
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2086017627
Short name T1088
Test name
Test status
Simulation time 162167418 ps
CPU time 2.36 seconds
Started Oct 12 02:08:41 PM UTC 24
Finished Oct 12 02:08:45 PM UTC 24
Peak memory 228112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2086017627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
14.spi_device_csr_mem_rw_with_rand_reset.2086017627
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.2890162264
Short name T1090
Test name
Test status
Simulation time 92838700 ps
CPU time 2.71 seconds
Started Oct 12 02:08:41 PM UTC 24
Finished Oct 12 02:08:45 PM UTC 24
Peak memory 225648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890162264 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.2890162264
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.3407128545
Short name T1078
Test name
Test status
Simulation time 24542234 ps
CPU time 0.99 seconds
Started Oct 12 02:08:41 PM UTC 24
Finished Oct 12 02:08:43 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407128545 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.3407128545
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.144508476
Short name T1087
Test name
Test status
Simulation time 155878030 ps
CPU time 2.32 seconds
Started Oct 12 02:08:41 PM UTC 24
Finished Oct 12 02:08:45 PM UTC 24
Peak memory 215348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144508476 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstanding.144508476
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.2460481656
Short name T1093
Test name
Test status
Simulation time 95884955 ps
CPU time 3.27 seconds
Started Oct 12 02:08:41 PM UTC 24
Finished Oct 12 02:08:45 PM UTC 24
Peak memory 225988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460481656 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.2460481656
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3109388968
Short name T1101
Test name
Test status
Simulation time 106354357 ps
CPU time 3.99 seconds
Started Oct 12 02:08:43 PM UTC 24
Finished Oct 12 02:08:48 PM UTC 24
Peak memory 228224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3109388968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
15.spi_device_csr_mem_rw_with_rand_reset.3109388968
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.1087568982
Short name T1091
Test name
Test status
Simulation time 199486256 ps
CPU time 1.65 seconds
Started Oct 12 02:08:43 PM UTC 24
Finished Oct 12 02:08:45 PM UTC 24
Peak memory 216504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087568982 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.1087568982
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2418678654
Short name T1085
Test name
Test status
Simulation time 45473191 ps
CPU time 0.92 seconds
Started Oct 12 02:08:43 PM UTC 24
Finished Oct 12 02:08:45 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418678654 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.2418678654
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3865088737
Short name T1098
Test name
Test status
Simulation time 45007972 ps
CPU time 2.75 seconds
Started Oct 12 02:08:43 PM UTC 24
Finished Oct 12 02:08:46 PM UTC 24
Peak memory 226088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865088737 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstanding.3865088737
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.2372031612
Short name T1092
Test name
Test status
Simulation time 50783777 ps
CPU time 2.82 seconds
Started Oct 12 02:08:41 PM UTC 24
Finished Oct 12 02:08:45 PM UTC 24
Peak memory 225928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372031612 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.2372031612
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.880667204
Short name T1148
Test name
Test status
Simulation time 3915627840 ps
CPU time 19.42 seconds
Started Oct 12 02:08:41 PM UTC 24
Finished Oct 12 02:09:02 PM UTC 24
Peak memory 228056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880667204 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.880667204
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1946782808
Short name T1099
Test name
Test status
Simulation time 68634296 ps
CPU time 1.88 seconds
Started Oct 12 02:08:44 PM UTC 24
Finished Oct 12 02:08:47 PM UTC 24
Peak memory 224736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1946782808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.spi_device_csr_mem_rw_with_rand_reset.1946782808
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.1824257835
Short name T1102
Test name
Test status
Simulation time 70451404 ps
CPU time 2.45 seconds
Started Oct 12 02:08:44 PM UTC 24
Finished Oct 12 02:08:48 PM UTC 24
Peak memory 225824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824257835 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.1824257835
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.1225690463
Short name T1095
Test name
Test status
Simulation time 14718979 ps
CPU time 0.82 seconds
Started Oct 12 02:08:44 PM UTC 24
Finished Oct 12 02:08:46 PM UTC 24
Peak memory 211932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225690463 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.1225690463
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4206377027
Short name T1103
Test name
Test status
Simulation time 436968584 ps
CPU time 3.17 seconds
Started Oct 12 02:08:44 PM UTC 24
Finished Oct 12 02:08:48 PM UTC 24
Peak memory 225828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206377027 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstanding.4206377027
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.4198435409
Short name T1109
Test name
Test status
Simulation time 223549130 ps
CPU time 5.34 seconds
Started Oct 12 02:08:43 PM UTC 24
Finished Oct 12 02:08:49 PM UTC 24
Peak memory 228196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198435409 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.4198435409
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2429219256
Short name T1129
Test name
Test status
Simulation time 130128123 ps
CPU time 3.25 seconds
Started Oct 12 02:08:47 PM UTC 24
Finished Oct 12 02:08:51 PM UTC 24
Peak memory 227692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2429219256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
17.spi_device_csr_mem_rw_with_rand_reset.2429219256
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.2271245472
Short name T1116
Test name
Test status
Simulation time 115202799 ps
CPU time 2.55 seconds
Started Oct 12 02:08:47 PM UTC 24
Finished Oct 12 02:08:50 PM UTC 24
Peak memory 226076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271245472 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.2271245472
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.1943913848
Short name T1097
Test name
Test status
Simulation time 12193533 ps
CPU time 0.83 seconds
Started Oct 12 02:08:45 PM UTC 24
Finished Oct 12 02:08:46 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943913848 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.1943913848
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1713711497
Short name T1133
Test name
Test status
Simulation time 157466542 ps
CPU time 3.77 seconds
Started Oct 12 02:08:47 PM UTC 24
Finished Oct 12 02:08:51 PM UTC 24
Peak memory 226060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713711497 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstanding.1713711497
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.3185222115
Short name T1100
Test name
Test status
Simulation time 69654369 ps
CPU time 2.03 seconds
Started Oct 12 02:08:44 PM UTC 24
Finished Oct 12 02:08:47 PM UTC 24
Peak memory 226180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185222115 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.3185222115
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.2863503870
Short name T1150
Test name
Test status
Simulation time 8246438846 ps
CPU time 20.25 seconds
Started Oct 12 02:08:44 PM UTC 24
Finished Oct 12 02:09:06 PM UTC 24
Peak memory 227984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863503870 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.2863503870
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1513314744
Short name T1128
Test name
Test status
Simulation time 95196656 ps
CPU time 3 seconds
Started Oct 12 02:08:47 PM UTC 24
Finished Oct 12 02:08:51 PM UTC 24
Peak memory 227872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1513314744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
18.spi_device_csr_mem_rw_with_rand_reset.1513314744
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.1738833138
Short name T1111
Test name
Test status
Simulation time 92416839 ps
CPU time 1.47 seconds
Started Oct 12 02:08:47 PM UTC 24
Finished Oct 12 02:08:49 PM UTC 24
Peak memory 224680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738833138 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.1738833138
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.1158441294
Short name T1105
Test name
Test status
Simulation time 48268643 ps
CPU time 0.74 seconds
Started Oct 12 02:08:47 PM UTC 24
Finished Oct 12 02:08:49 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158441294 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.1158441294
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3748604742
Short name T1125
Test name
Test status
Simulation time 42795779 ps
CPU time 2.96 seconds
Started Oct 12 02:08:47 PM UTC 24
Finished Oct 12 02:08:51 PM UTC 24
Peak memory 225856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748604742 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstanding.3748604742
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.3812759809
Short name T1123
Test name
Test status
Simulation time 150047486 ps
CPU time 3.06 seconds
Started Oct 12 02:08:47 PM UTC 24
Finished Oct 12 02:08:51 PM UTC 24
Peak memory 226004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812759809 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.3812759809
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.4145539418
Short name T222
Test name
Test status
Simulation time 200019341 ps
CPU time 11.77 seconds
Started Oct 12 02:08:47 PM UTC 24
Finished Oct 12 02:09:00 PM UTC 24
Peak memory 226080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145539418 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.4145539418
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2526240933
Short name T1126
Test name
Test status
Simulation time 207511595 ps
CPU time 2.61 seconds
Started Oct 12 02:08:47 PM UTC 24
Finished Oct 12 02:08:51 PM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2526240933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
19.spi_device_csr_mem_rw_with_rand_reset.2526240933
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.2634470963
Short name T1113
Test name
Test status
Simulation time 77662552 ps
CPU time 1.54 seconds
Started Oct 12 02:08:47 PM UTC 24
Finished Oct 12 02:08:50 PM UTC 24
Peak memory 224640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634470963 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.2634470963
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.4078820011
Short name T1106
Test name
Test status
Simulation time 33450688 ps
CPU time 0.97 seconds
Started Oct 12 02:08:47 PM UTC 24
Finished Oct 12 02:08:49 PM UTC 24
Peak memory 212340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078820011 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.4078820011
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2109702630
Short name T1122
Test name
Test status
Simulation time 397323456 ps
CPU time 2.66 seconds
Started Oct 12 02:08:47 PM UTC 24
Finished Oct 12 02:08:51 PM UTC 24
Peak memory 228176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109702630 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstanding.2109702630
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.4258205958
Short name T1114
Test name
Test status
Simulation time 421691833 ps
CPU time 1.78 seconds
Started Oct 12 02:08:47 PM UTC 24
Finished Oct 12 02:08:50 PM UTC 24
Peak memory 226796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258205958 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.4258205958
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.800894001
Short name T1149
Test name
Test status
Simulation time 1810930234 ps
CPU time 16.35 seconds
Started Oct 12 02:08:47 PM UTC 24
Finished Oct 12 02:09:05 PM UTC 24
Peak memory 227908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800894001 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.800894001
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.110752618
Short name T195
Test name
Test status
Simulation time 1793713739 ps
CPU time 14.69 seconds
Started Oct 12 02:08:24 PM UTC 24
Finished Oct 12 02:08:40 PM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110752618 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.110752618
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2853944509
Short name T193
Test name
Test status
Simulation time 907502086 ps
CPU time 12.83 seconds
Started Oct 12 02:08:24 PM UTC 24
Finished Oct 12 02:08:38 PM UTC 24
Peak memory 215744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853944509 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.2853944509
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1159139829
Short name T114
Test name
Test status
Simulation time 39325279 ps
CPU time 1.55 seconds
Started Oct 12 02:08:24 PM UTC 24
Finished Oct 12 02:08:27 PM UTC 24
Peak memory 215000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159139829 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.1159139829
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.99552415
Short name T151
Test name
Test status
Simulation time 51197239 ps
CPU time 1.87 seconds
Started Oct 12 02:08:24 PM UTC 24
Finished Oct 12 02:08:28 PM UTC 24
Peak memory 224736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=99552415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.spi_device_csr_mem_rw_with_rand_reset.99552415
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.2710935021
Short name T158
Test name
Test status
Simulation time 28707022 ps
CPU time 2.01 seconds
Started Oct 12 02:08:24 PM UTC 24
Finished Oct 12 02:08:27 PM UTC 24
Peak memory 225964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710935021 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2710935021
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.3633404434
Short name T1041
Test name
Test status
Simulation time 26515958 ps
CPU time 0.77 seconds
Started Oct 12 02:08:24 PM UTC 24
Finished Oct 12 02:08:26 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633404434 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3633404434
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.3854539111
Short name T156
Test name
Test status
Simulation time 31183912 ps
CPU time 1.39 seconds
Started Oct 12 02:08:24 PM UTC 24
Finished Oct 12 02:08:27 PM UTC 24
Peak memory 224680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854539111 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.3854539111
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.91397812
Short name T1042
Test name
Test status
Simulation time 24991493 ps
CPU time 0.9 seconds
Started Oct 12 02:08:24 PM UTC 24
Finished Oct 12 02:08:26 PM UTC 24
Peak memory 212436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91397812 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.91397812
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3908811053
Short name T1046
Test name
Test status
Simulation time 116509177 ps
CPU time 3.68 seconds
Started Oct 12 02:08:24 PM UTC 24
Finished Oct 12 02:08:29 PM UTC 24
Peak memory 225960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908811053 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstanding.3908811053
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.177116584
Short name T131
Test name
Test status
Simulation time 125757923 ps
CPU time 3.1 seconds
Started Oct 12 02:08:21 PM UTC 24
Finished Oct 12 02:08:26 PM UTC 24
Peak memory 226196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177116584 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.177116584
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.2921532708
Short name T1112
Test name
Test status
Simulation time 58497743 ps
CPU time 1.01 seconds
Started Oct 12 02:08:47 PM UTC 24
Finished Oct 12 02:08:49 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921532708 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.2921532708
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/20.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.3558355081
Short name T1108
Test name
Test status
Simulation time 31355360 ps
CPU time 0.79 seconds
Started Oct 12 02:08:47 PM UTC 24
Finished Oct 12 02:08:49 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558355081 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.3558355081
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/21.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.972941781
Short name T1110
Test name
Test status
Simulation time 15103931 ps
CPU time 0.85 seconds
Started Oct 12 02:08:47 PM UTC 24
Finished Oct 12 02:08:49 PM UTC 24
Peak memory 212500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972941781 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.972941781
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/22.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.3957403305
Short name T1117
Test name
Test status
Simulation time 15694682 ps
CPU time 0.8 seconds
Started Oct 12 02:08:49 PM UTC 24
Finished Oct 12 02:08:50 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957403305 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.3957403305
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/23.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.2625064944
Short name T1121
Test name
Test status
Simulation time 42867537 ps
CPU time 1.13 seconds
Started Oct 12 02:08:49 PM UTC 24
Finished Oct 12 02:08:51 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625064944 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.2625064944
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/24.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.647298120
Short name T1118
Test name
Test status
Simulation time 13668463 ps
CPU time 0.96 seconds
Started Oct 12 02:08:49 PM UTC 24
Finished Oct 12 02:08:51 PM UTC 24
Peak memory 212484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647298120 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.647298120
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/25.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.4090863091
Short name T1127
Test name
Test status
Simulation time 38574625 ps
CPU time 1.07 seconds
Started Oct 12 02:08:49 PM UTC 24
Finished Oct 12 02:08:51 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090863091 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.4090863091
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/26.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.2604259258
Short name T1119
Test name
Test status
Simulation time 18899101 ps
CPU time 0.96 seconds
Started Oct 12 02:08:49 PM UTC 24
Finished Oct 12 02:08:51 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604259258 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.2604259258
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/27.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.808045344
Short name T1131
Test name
Test status
Simulation time 42176045 ps
CPU time 1.02 seconds
Started Oct 12 02:08:49 PM UTC 24
Finished Oct 12 02:08:51 PM UTC 24
Peak memory 212484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808045344 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.808045344
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/28.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.220909285
Short name T1130
Test name
Test status
Simulation time 48312563 ps
CPU time 1.02 seconds
Started Oct 12 02:08:49 PM UTC 24
Finished Oct 12 02:08:51 PM UTC 24
Peak memory 212484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220909285 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.220909285
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/29.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.4051770284
Short name T1055
Test name
Test status
Simulation time 115781860 ps
CPU time 7.28 seconds
Started Oct 12 02:08:26 PM UTC 24
Finished Oct 12 02:08:35 PM UTC 24
Peak memory 225840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051770284 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.4051770284
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4229261963
Short name T1065
Test name
Test status
Simulation time 787011895 ps
CPU time 10.78 seconds
Started Oct 12 02:08:26 PM UTC 24
Finished Oct 12 02:08:38 PM UTC 24
Peak memory 215792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229261963 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.4229261963
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1648388443
Short name T115
Test name
Test status
Simulation time 22377205 ps
CPU time 1.22 seconds
Started Oct 12 02:08:25 PM UTC 24
Finished Oct 12 02:08:27 PM UTC 24
Peak memory 224872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648388443 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.1648388443
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1260390197
Short name T152
Test name
Test status
Simulation time 210405766 ps
CPU time 2.66 seconds
Started Oct 12 02:08:26 PM UTC 24
Finished Oct 12 02:08:30 PM UTC 24
Peak memory 227928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1260390197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.spi_device_csr_mem_rw_with_rand_reset.1260390197
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.402348025
Short name T159
Test name
Test status
Simulation time 140211329 ps
CPU time 1.79 seconds
Started Oct 12 02:08:25 PM UTC 24
Finished Oct 12 02:08:28 PM UTC 24
Peak memory 224684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402348025 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.402348025
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.2877387785
Short name T1043
Test name
Test status
Simulation time 17718529 ps
CPU time 0.81 seconds
Started Oct 12 02:08:25 PM UTC 24
Finished Oct 12 02:08:27 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877387785 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2877387785
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.1510818151
Short name T157
Test name
Test status
Simulation time 19662266 ps
CPU time 1.26 seconds
Started Oct 12 02:08:25 PM UTC 24
Finished Oct 12 02:08:27 PM UTC 24
Peak memory 224680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510818151 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.1510818151
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.1271362691
Short name T1044
Test name
Test status
Simulation time 135564136 ps
CPU time 0.81 seconds
Started Oct 12 02:08:25 PM UTC 24
Finished Oct 12 02:08:27 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271362691 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.1271362691
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.777319866
Short name T187
Test name
Test status
Simulation time 74888372 ps
CPU time 1.88 seconds
Started Oct 12 02:08:26 PM UTC 24
Finished Oct 12 02:08:29 PM UTC 24
Peak memory 225280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777319866 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstanding.777319866
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.1148541144
Short name T142
Test name
Test status
Simulation time 192248745 ps
CPU time 4.11 seconds
Started Oct 12 02:08:24 PM UTC 24
Finished Oct 12 02:08:30 PM UTC 24
Peak memory 225896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148541144 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1148541144
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.2389014850
Short name T137
Test name
Test status
Simulation time 296948785 ps
CPU time 7.36 seconds
Started Oct 12 02:08:25 PM UTC 24
Finished Oct 12 02:08:33 PM UTC 24
Peak memory 227880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389014850 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.2389014850
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.1107764746
Short name T1124
Test name
Test status
Simulation time 43775340 ps
CPU time 0.87 seconds
Started Oct 12 02:08:49 PM UTC 24
Finished Oct 12 02:08:51 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107764746 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.1107764746
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/30.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.2170956109
Short name T1132
Test name
Test status
Simulation time 42169227 ps
CPU time 1.01 seconds
Started Oct 12 02:08:49 PM UTC 24
Finished Oct 12 02:08:51 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170956109 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.2170956109
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/31.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.3617875423
Short name T1076
Test name
Test status
Simulation time 51058575 ps
CPU time 1.02 seconds
Started Oct 12 02:08:50 PM UTC 24
Finished Oct 12 02:08:52 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617875423 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.3617875423
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/32.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.3490879343
Short name T1134
Test name
Test status
Simulation time 12194644 ps
CPU time 0.83 seconds
Started Oct 12 02:08:50 PM UTC 24
Finished Oct 12 02:08:52 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490879343 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.3490879343
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/33.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.3933117217
Short name T1094
Test name
Test status
Simulation time 13507064 ps
CPU time 0.92 seconds
Started Oct 12 02:08:50 PM UTC 24
Finished Oct 12 02:08:52 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933117217 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.3933117217
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/34.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.3648190897
Short name T1136
Test name
Test status
Simulation time 32330599 ps
CPU time 0.87 seconds
Started Oct 12 02:08:50 PM UTC 24
Finished Oct 12 02:08:52 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648190897 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.3648190897
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/35.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.4287486322
Short name T1115
Test name
Test status
Simulation time 74780470 ps
CPU time 1.03 seconds
Started Oct 12 02:08:50 PM UTC 24
Finished Oct 12 02:08:52 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287486322 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.4287486322
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/36.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.3329497858
Short name T1107
Test name
Test status
Simulation time 57761077 ps
CPU time 0.94 seconds
Started Oct 12 02:08:50 PM UTC 24
Finished Oct 12 02:08:52 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329497858 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.3329497858
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/37.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.301815708
Short name T1104
Test name
Test status
Simulation time 30652753 ps
CPU time 0.81 seconds
Started Oct 12 02:08:50 PM UTC 24
Finished Oct 12 02:08:52 PM UTC 24
Peak memory 212500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301815708 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.301815708
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/38.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.2688648325
Short name T1135
Test name
Test status
Simulation time 143681013 ps
CPU time 0.95 seconds
Started Oct 12 02:08:50 PM UTC 24
Finished Oct 12 02:08:52 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688648325 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.2688648325
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/39.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.366395741
Short name T1075
Test name
Test status
Simulation time 411818125 ps
CPU time 13.24 seconds
Started Oct 12 02:08:28 PM UTC 24
Finished Oct 12 02:08:43 PM UTC 24
Peak memory 226028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366395741 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.366395741
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2860657775
Short name T1151
Test name
Test status
Simulation time 22549461701 ps
CPU time 37.71 seconds
Started Oct 12 02:08:28 PM UTC 24
Finished Oct 12 02:09:07 PM UTC 24
Peak memory 215644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860657775 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.2860657775
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.654384903
Short name T196
Test name
Test status
Simulation time 24437802 ps
CPU time 1.05 seconds
Started Oct 12 02:08:28 PM UTC 24
Finished Oct 12 02:08:30 PM UTC 24
Peak memory 214460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654384903 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.654384903
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.883930320
Short name T1053
Test name
Test status
Simulation time 73063727 ps
CPU time 2.65 seconds
Started Oct 12 02:08:29 PM UTC 24
Finished Oct 12 02:08:33 PM UTC 24
Peak memory 227940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=883930320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.spi_device_csr_mem_rw_with_rand_reset.883930320
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.602752768
Short name T161
Test name
Test status
Simulation time 135771092 ps
CPU time 2.37 seconds
Started Oct 12 02:08:28 PM UTC 24
Finished Oct 12 02:08:31 PM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602752768 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.602752768
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.2243705593
Short name T1047
Test name
Test status
Simulation time 17395599 ps
CPU time 1.12 seconds
Started Oct 12 02:08:27 PM UTC 24
Finished Oct 12 02:08:30 PM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243705593 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2243705593
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.2647964636
Short name T165
Test name
Test status
Simulation time 25059070 ps
CPU time 2.79 seconds
Started Oct 12 02:08:28 PM UTC 24
Finished Oct 12 02:08:32 PM UTC 24
Peak memory 225860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647964636 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.2647964636
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.3916161112
Short name T1048
Test name
Test status
Simulation time 33202259 ps
CPU time 0.97 seconds
Started Oct 12 02:08:27 PM UTC 24
Finished Oct 12 02:08:30 PM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916161112 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.3916161112
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1379034734
Short name T189
Test name
Test status
Simulation time 233501245 ps
CPU time 4.45 seconds
Started Oct 12 02:08:29 PM UTC 24
Finished Oct 12 02:08:35 PM UTC 24
Peak memory 225888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379034734 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstanding.1379034734
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.1085546230
Short name T143
Test name
Test status
Simulation time 583694540 ps
CPU time 5 seconds
Started Oct 12 02:08:26 PM UTC 24
Finished Oct 12 02:08:33 PM UTC 24
Peak memory 227936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085546230 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1085546230
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.2610256610
Short name T220
Test name
Test status
Simulation time 113430205 ps
CPU time 6.69 seconds
Started Oct 12 02:08:26 PM UTC 24
Finished Oct 12 02:08:34 PM UTC 24
Peak memory 225948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610256610 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.2610256610
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.2872307337
Short name T1137
Test name
Test status
Simulation time 36728957 ps
CPU time 0.91 seconds
Started Oct 12 02:08:50 PM UTC 24
Finished Oct 12 02:08:52 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872307337 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.2872307337
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/40.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.3857566208
Short name T1120
Test name
Test status
Simulation time 18855371 ps
CPU time 0.79 seconds
Started Oct 12 02:08:51 PM UTC 24
Finished Oct 12 02:08:52 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857566208 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.3857566208
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/41.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3279803160
Short name T1139
Test name
Test status
Simulation time 25537929 ps
CPU time 0.78 seconds
Started Oct 12 02:08:52 PM UTC 24
Finished Oct 12 02:08:53 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279803160 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.3279803160
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/42.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.1378030771
Short name T1138
Test name
Test status
Simulation time 83951326 ps
CPU time 0.72 seconds
Started Oct 12 02:08:52 PM UTC 24
Finished Oct 12 02:08:53 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378030771 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.1378030771
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/43.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.2620615475
Short name T1142
Test name
Test status
Simulation time 47146142 ps
CPU time 0.9 seconds
Started Oct 12 02:08:52 PM UTC 24
Finished Oct 12 02:08:54 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620615475 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.2620615475
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/44.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.783870820
Short name T1141
Test name
Test status
Simulation time 21816822 ps
CPU time 0.87 seconds
Started Oct 12 02:08:52 PM UTC 24
Finished Oct 12 02:08:54 PM UTC 24
Peak memory 212500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783870820 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.783870820
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/45.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.1104507507
Short name T1143
Test name
Test status
Simulation time 44488647 ps
CPU time 0.84 seconds
Started Oct 12 02:08:52 PM UTC 24
Finished Oct 12 02:08:54 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104507507 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.1104507507
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/46.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.3789609295
Short name T1145
Test name
Test status
Simulation time 29080081 ps
CPU time 0.85 seconds
Started Oct 12 02:08:52 PM UTC 24
Finished Oct 12 02:08:54 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789609295 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.3789609295
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/47.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.3639657234
Short name T1144
Test name
Test status
Simulation time 16942220 ps
CPU time 0.76 seconds
Started Oct 12 02:08:52 PM UTC 24
Finished Oct 12 02:08:54 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639657234 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.3639657234
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/48.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.2208166160
Short name T1146
Test name
Test status
Simulation time 14816228 ps
CPU time 0.97 seconds
Started Oct 12 02:08:52 PM UTC 24
Finished Oct 12 02:08:54 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208166160 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.2208166160
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/49.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2940388896
Short name T1054
Test name
Test status
Simulation time 280521887 ps
CPU time 2.17 seconds
Started Oct 12 02:08:30 PM UTC 24
Finished Oct 12 02:08:34 PM UTC 24
Peak memory 228132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2940388896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
5.spi_device_csr_mem_rw_with_rand_reset.2940388896
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.1335260632
Short name T1050
Test name
Test status
Simulation time 33347002 ps
CPU time 1.65 seconds
Started Oct 12 02:08:29 PM UTC 24
Finished Oct 12 02:08:32 PM UTC 24
Peak memory 214400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335260632 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1335260632
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.1769609430
Short name T1049
Test name
Test status
Simulation time 73434736 ps
CPU time 1.13 seconds
Started Oct 12 02:08:29 PM UTC 24
Finished Oct 12 02:08:31 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769609430 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1769609430
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2878126564
Short name T1051
Test name
Test status
Simulation time 70324972 ps
CPU time 2.16 seconds
Started Oct 12 02:08:29 PM UTC 24
Finished Oct 12 02:08:33 PM UTC 24
Peak memory 215588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878126564 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstanding.2878126564
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.1540928342
Short name T145
Test name
Test status
Simulation time 402189634 ps
CPU time 2.04 seconds
Started Oct 12 02:08:29 PM UTC 24
Finished Oct 12 02:08:32 PM UTC 24
Peak memory 228004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540928342 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1540928342
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.184562595
Short name T216
Test name
Test status
Simulation time 307724520 ps
CPU time 17.15 seconds
Started Oct 12 02:08:29 PM UTC 24
Finished Oct 12 02:08:48 PM UTC 24
Peak memory 225604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184562595 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.184562595
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3512972228
Short name T1057
Test name
Test status
Simulation time 227876557 ps
CPU time 2.84 seconds
Started Oct 12 02:08:32 PM UTC 24
Finished Oct 12 02:08:36 PM UTC 24
Peak memory 227936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3512972228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
6.spi_device_csr_mem_rw_with_rand_reset.3512972228
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.4267351169
Short name T162
Test name
Test status
Simulation time 37138331 ps
CPU time 2.37 seconds
Started Oct 12 02:08:32 PM UTC 24
Finished Oct 12 02:08:35 PM UTC 24
Peak memory 225960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267351169 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.4267351169
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.610234183
Short name T1052
Test name
Test status
Simulation time 22262165 ps
CPU time 1.08 seconds
Started Oct 12 02:08:30 PM UTC 24
Finished Oct 12 02:08:33 PM UTC 24
Peak memory 212440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610234183 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.610234183
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.548683635
Short name T1059
Test name
Test status
Simulation time 59440441 ps
CPU time 3.56 seconds
Started Oct 12 02:08:32 PM UTC 24
Finished Oct 12 02:08:36 PM UTC 24
Peak memory 226116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548683635 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstanding.548683635
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.2112520703
Short name T144
Test name
Test status
Simulation time 37685589 ps
CPU time 2.96 seconds
Started Oct 12 02:08:30 PM UTC 24
Finished Oct 12 02:08:34 PM UTC 24
Peak memory 228192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112520703 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2112520703
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.772986665
Short name T1140
Test name
Test status
Simulation time 1227747642 ps
CPU time 21.66 seconds
Started Oct 12 02:08:30 PM UTC 24
Finished Oct 12 02:08:53 PM UTC 24
Peak memory 225892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772986665 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.772986665
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3053185591
Short name T1061
Test name
Test status
Simulation time 70066737 ps
CPU time 2.5 seconds
Started Oct 12 02:08:33 PM UTC 24
Finished Oct 12 02:08:36 PM UTC 24
Peak memory 227880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3053185591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
7.spi_device_csr_mem_rw_with_rand_reset.3053185591
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.3406965272
Short name T190
Test name
Test status
Simulation time 44874546 ps
CPU time 1.93 seconds
Started Oct 12 02:08:33 PM UTC 24
Finished Oct 12 02:08:36 PM UTC 24
Peak memory 224680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406965272 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3406965272
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.2912643951
Short name T1056
Test name
Test status
Simulation time 88466949 ps
CPU time 1.11 seconds
Started Oct 12 02:08:33 PM UTC 24
Finished Oct 12 02:08:35 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912643951 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2912643951
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1900291458
Short name T191
Test name
Test status
Simulation time 146826992 ps
CPU time 3.01 seconds
Started Oct 12 02:08:33 PM UTC 24
Finished Oct 12 02:08:37 PM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900291458 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstanding.1900291458
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.1655601410
Short name T147
Test name
Test status
Simulation time 60433285 ps
CPU time 2.53 seconds
Started Oct 12 02:08:32 PM UTC 24
Finished Oct 12 02:08:35 PM UTC 24
Peak memory 225896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655601410 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1655601410
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.2037979395
Short name T133
Test name
Test status
Simulation time 305409788 ps
CPU time 7.49 seconds
Started Oct 12 02:08:32 PM UTC 24
Finished Oct 12 02:08:40 PM UTC 24
Peak memory 227944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037979395 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.2037979395
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3714330211
Short name T1062
Test name
Test status
Simulation time 45812877 ps
CPU time 2.22 seconds
Started Oct 12 02:08:34 PM UTC 24
Finished Oct 12 02:08:38 PM UTC 24
Peak memory 225952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3714330211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
8.spi_device_csr_mem_rw_with_rand_reset.3714330211
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.2190265669
Short name T192
Test name
Test status
Simulation time 123805143 ps
CPU time 2.93 seconds
Started Oct 12 02:08:34 PM UTC 24
Finished Oct 12 02:08:38 PM UTC 24
Peak memory 225824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190265669 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2190265669
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.2633562568
Short name T1058
Test name
Test status
Simulation time 15915449 ps
CPU time 1.05 seconds
Started Oct 12 02:08:34 PM UTC 24
Finished Oct 12 02:08:36 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633562568 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2633562568
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1850961301
Short name T1045
Test name
Test status
Simulation time 25822312 ps
CPU time 1.89 seconds
Started Oct 12 02:08:34 PM UTC 24
Finished Oct 12 02:08:37 PM UTC 24
Peak memory 215060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850961301 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstanding.1850961301
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.435361441
Short name T146
Test name
Test status
Simulation time 58998582 ps
CPU time 4.19 seconds
Started Oct 12 02:08:33 PM UTC 24
Finished Oct 12 02:08:38 PM UTC 24
Peak memory 226196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435361441 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.435361441
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.722447861
Short name T1086
Test name
Test status
Simulation time 1458058598 ps
CPU time 9.36 seconds
Started Oct 12 02:08:34 PM UTC 24
Finished Oct 12 02:08:45 PM UTC 24
Peak memory 227924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722447861 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.722447861
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2353624789
Short name T1069
Test name
Test status
Simulation time 119991002 ps
CPU time 3.69 seconds
Started Oct 12 02:08:36 PM UTC 24
Finished Oct 12 02:08:41 PM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2353624789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
9.spi_device_csr_mem_rw_with_rand_reset.2353624789
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.789523737
Short name T1066
Test name
Test status
Simulation time 43193499 ps
CPU time 1.68 seconds
Started Oct 12 02:08:36 PM UTC 24
Finished Oct 12 02:08:39 PM UTC 24
Peak memory 214464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789523737 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.789523737
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.1521693165
Short name T1063
Test name
Test status
Simulation time 20720027 ps
CPU time 1.07 seconds
Started Oct 12 02:08:36 PM UTC 24
Finished Oct 12 02:08:38 PM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521693165 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1521693165
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3539625371
Short name T1071
Test name
Test status
Simulation time 322857235 ps
CPU time 4.54 seconds
Started Oct 12 02:08:36 PM UTC 24
Finished Oct 12 02:08:41 PM UTC 24
Peak memory 226088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539625371 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstanding.3539625371
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.2734259627
Short name T150
Test name
Test status
Simulation time 74136687 ps
CPU time 5.03 seconds
Started Oct 12 02:08:34 PM UTC 24
Finished Oct 12 02:08:40 PM UTC 24
Peak memory 227944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734259627 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2734259627
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.3707916225
Short name T221
Test name
Test status
Simulation time 684994201 ps
CPU time 14.67 seconds
Started Oct 12 02:08:36 PM UTC 24
Finished Oct 12 02:08:52 PM UTC 24
Peak memory 228076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707916225 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.3707916225
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.3464043115
Short name T12
Test name
Test status
Simulation time 145121672 ps
CPU time 5.08 seconds
Started Oct 12 02:18:37 PM UTC 24
Finished Oct 12 02:18:46 PM UTC 24
Peak memory 245044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464043115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3464043115
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.3470296006
Short name T7
Test name
Test status
Simulation time 39270696 ps
CPU time 0.76 seconds
Started Oct 12 02:18:37 PM UTC 24
Finished Oct 12 02:18:42 PM UTC 24
Peak memory 225168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470296006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.3470296006
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.4213021084
Short name T11
Test name
Test status
Simulation time 1690409481 ps
CPU time 3.99 seconds
Started Oct 12 02:18:33 PM UTC 24
Finished Oct 12 02:18:45 PM UTC 24
Peak memory 234692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213021084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4213021084
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.105646444
Short name T99
Test name
Test status
Simulation time 7757604377 ps
CPU time 20.64 seconds
Started Oct 12 02:18:34 PM UTC 24
Finished Oct 12 02:19:04 PM UTC 24
Peak memory 234996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105646444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.105646444
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.1558082084
Short name T2
Test name
Test status
Simulation time 24945120 ps
CPU time 0.92 seconds
Started Oct 12 02:18:22 PM UTC 24
Finished Oct 12 02:18:31 PM UTC 24
Peak memory 228880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558082084 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_parity.1558082084
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2746496849
Short name T22
Test name
Test status
Simulation time 14758332430 ps
CPU time 11.97 seconds
Started Oct 12 02:18:33 PM UTC 24
Finished Oct 12 02:18:53 PM UTC 24
Peak memory 245036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746496849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.2746496849
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.3385691180
Short name T9
Test name
Test status
Simulation time 99351396 ps
CPU time 2.75 seconds
Started Oct 12 02:18:33 PM UTC 24
Finished Oct 12 02:18:44 PM UTC 24
Peak memory 244904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385691180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3385691180
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.2809590582
Short name T8
Test name
Test status
Simulation time 102117399 ps
CPU time 1.31 seconds
Started Oct 12 02:18:33 PM UTC 24
Finished Oct 12 02:18:42 PM UTC 24
Peak memory 226236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809590582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2809590582
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.681784872
Short name T23
Test name
Test status
Simulation time 1406722262 ps
CPU time 11.16 seconds
Started Oct 12 02:18:34 PM UTC 24
Finished Oct 12 02:18:54 PM UTC 24
Peak memory 244972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681784872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.681784872
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/0.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.3577385095
Short name T104
Test name
Test status
Simulation time 13172385 ps
CPU time 1.11 seconds
Started Oct 12 02:18:47 PM UTC 24
Finished Oct 12 02:18:52 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577385095 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3577385095
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.18549987
Short name T16
Test name
Test status
Simulation time 108552304 ps
CPU time 2.41 seconds
Started Oct 12 02:18:45 PM UTC 24
Finished Oct 12 02:18:48 PM UTC 24
Peak memory 244960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18549987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.18549987
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.539449938
Short name T20
Test name
Test status
Simulation time 17525629 ps
CPU time 1.03 seconds
Started Oct 12 02:18:42 PM UTC 24
Finished Oct 12 02:18:51 PM UTC 24
Peak memory 213656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539449938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.539449938
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.2241130512
Short name T110
Test name
Test status
Simulation time 35652720186 ps
CPU time 138.55 seconds
Started Oct 12 02:18:45 PM UTC 24
Finished Oct 12 02:21:06 PM UTC 24
Peak memory 261428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241130512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2241130512
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.1589921398
Short name T54
Test name
Test status
Simulation time 2279930850 ps
CPU time 45.08 seconds
Started Oct 12 02:18:45 PM UTC 24
Finished Oct 12 02:19:42 PM UTC 24
Peak memory 267932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589921398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1589921398
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.1207562072
Short name T273
Test name
Test status
Simulation time 55489749014 ps
CPU time 269.5 seconds
Started Oct 12 02:18:45 PM UTC 24
Finished Oct 12 02:23:29 PM UTC 24
Peak memory 261788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207562072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.1207562072
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.2543614596
Short name T17
Test name
Test status
Simulation time 1546922726 ps
CPU time 3.47 seconds
Started Oct 12 02:18:45 PM UTC 24
Finished Oct 12 02:18:49 PM UTC 24
Peak memory 234716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543614596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2543614596
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.543457461
Short name T250
Test name
Test status
Simulation time 33650469090 ps
CPU time 79.22 seconds
Started Oct 12 02:18:44 PM UTC 24
Finished Oct 12 02:20:06 PM UTC 24
Peak memory 251184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543457461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.543457461
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.2707454482
Short name T26
Test name
Test status
Simulation time 57330828 ps
CPU time 1.14 seconds
Started Oct 12 02:18:43 PM UTC 24
Finished Oct 12 02:18:47 PM UTC 24
Peak memory 228940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707454482 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_parity.2707454482
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.3860226223
Short name T14
Test name
Test status
Simulation time 45289762 ps
CPU time 2.03 seconds
Started Oct 12 02:18:44 PM UTC 24
Finished Oct 12 02:18:48 PM UTC 24
Peak memory 234636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860226223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3860226223
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.1593678152
Short name T47
Test name
Test status
Simulation time 644777560 ps
CPU time 9.46 seconds
Started Oct 12 02:18:45 PM UTC 24
Finished Oct 12 02:18:56 PM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593678152 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.1593678152
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.1554645625
Short name T33
Test name
Test status
Simulation time 80496863 ps
CPU time 1.51 seconds
Started Oct 12 02:18:47 PM UTC 24
Finished Oct 12 02:18:53 PM UTC 24
Peak memory 256900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554645625 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1554645625
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.3183011906
Short name T18
Test name
Test status
Simulation time 68297320 ps
CPU time 1.11 seconds
Started Oct 12 02:18:46 PM UTC 24
Finished Oct 12 02:18:51 PM UTC 24
Peak memory 213480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183011906 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.3183011906
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.1249577963
Short name T28
Test name
Test status
Simulation time 1225702641 ps
CPU time 6.31 seconds
Started Oct 12 02:18:43 PM UTC 24
Finished Oct 12 02:18:52 PM UTC 24
Peak memory 227280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249577963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1249577963
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.3619959555
Short name T117
Test name
Test status
Simulation time 34233716513 ps
CPU time 21.86 seconds
Started Oct 12 02:18:43 PM UTC 24
Finished Oct 12 02:19:08 PM UTC 24
Peak memory 227376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619959555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3619959555
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.3197060122
Short name T15
Test name
Test status
Simulation time 209245838 ps
CPU time 2.64 seconds
Started Oct 12 02:18:43 PM UTC 24
Finished Oct 12 02:18:48 PM UTC 24
Peak memory 227240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197060122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3197060122
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.2441855301
Short name T13
Test name
Test status
Simulation time 390889450 ps
CPU time 1.33 seconds
Started Oct 12 02:18:43 PM UTC 24
Finished Oct 12 02:18:47 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441855301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2441855301
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.866781724
Short name T64
Test name
Test status
Simulation time 3085093308 ps
CPU time 11.9 seconds
Started Oct 12 02:18:45 PM UTC 24
Finished Oct 12 02:18:58 PM UTC 24
Peak memory 234748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866781724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.866781724
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/1.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.3680784314
Short name T443
Test name
Test status
Simulation time 12520682 ps
CPU time 1.16 seconds
Started Oct 12 02:21:32 PM UTC 24
Finished Oct 12 02:21:35 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680784314 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.3680784314
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.3852754697
Short name T441
Test name
Test status
Simulation time 381507255 ps
CPU time 7.92 seconds
Started Oct 12 02:21:18 PM UTC 24
Finished Oct 12 02:21:27 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852754697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3852754697
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.298059820
Short name T432
Test name
Test status
Simulation time 24693070 ps
CPU time 1.18 seconds
Started Oct 12 02:20:59 PM UTC 24
Finished Oct 12 02:21:02 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298059820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.298059820
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.1875061441
Short name T257
Test name
Test status
Simulation time 11992770238 ps
CPU time 92.11 seconds
Started Oct 12 02:21:27 PM UTC 24
Finished Oct 12 02:23:02 PM UTC 24
Peak memory 267660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875061441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.1875061441
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.615160010
Short name T440
Test name
Test status
Simulation time 533055186 ps
CPU time 5.61 seconds
Started Oct 12 02:21:19 PM UTC 24
Finished Oct 12 02:21:26 PM UTC 24
Peak memory 234664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615160010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.615160010
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.1635624894
Short name T169
Test name
Test status
Simulation time 51804036266 ps
CPU time 241.45 seconds
Started Oct 12 02:21:20 PM UTC 24
Finished Oct 12 02:25:25 PM UTC 24
Peak memory 263464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635624894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.1635624894
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.2586709379
Short name T311
Test name
Test status
Simulation time 352470936 ps
CPU time 7.93 seconds
Started Oct 12 02:21:08 PM UTC 24
Finished Oct 12 02:21:17 PM UTC 24
Peak memory 234876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586709379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2586709379
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.1507880257
Short name T438
Test name
Test status
Simulation time 508663740 ps
CPU time 10.19 seconds
Started Oct 12 02:21:10 PM UTC 24
Finished Oct 12 02:21:21 PM UTC 24
Peak memory 244892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507880257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1507880257
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.2773745939
Short name T433
Test name
Test status
Simulation time 25372355 ps
CPU time 1.48 seconds
Started Oct 12 02:21:01 PM UTC 24
Finished Oct 12 02:21:03 PM UTC 24
Peak memory 229004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773745939 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mem_parity.2773745939
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.568696044
Short name T272
Test name
Test status
Simulation time 4712150330 ps
CPU time 10.24 seconds
Started Oct 12 02:21:07 PM UTC 24
Finished Oct 12 02:21:18 PM UTC 24
Peak memory 245348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568696044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.568696044
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.2627408291
Short name T301
Test name
Test status
Simulation time 9751463260 ps
CPU time 49.22 seconds
Started Oct 12 02:21:07 PM UTC 24
Finished Oct 12 02:21:58 PM UTC 24
Peak memory 261728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627408291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2627408291
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.1745571290
Short name T442
Test name
Test status
Simulation time 1067737759 ps
CPU time 4 seconds
Started Oct 12 02:21:22 PM UTC 24
Finished Oct 12 02:21:27 PM UTC 24
Peak memory 233420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745571290 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.1745571290
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.1981284818
Short name T391
Test name
Test status
Simulation time 4560174945 ps
CPU time 36.86 seconds
Started Oct 12 02:21:04 PM UTC 24
Finished Oct 12 02:21:42 PM UTC 24
Peak memory 227476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981284818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1981284818
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.250985917
Short name T444
Test name
Test status
Simulation time 24457150675 ps
CPU time 31.74 seconds
Started Oct 12 02:21:03 PM UTC 24
Finished Oct 12 02:21:36 PM UTC 24
Peak memory 227372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250985917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.250985917
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.331150267
Short name T437
Test name
Test status
Simulation time 122544661 ps
CPU time 3.11 seconds
Started Oct 12 02:21:05 PM UTC 24
Finished Oct 12 02:21:09 PM UTC 24
Peak memory 227228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331150267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.331150267
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.1575159538
Short name T435
Test name
Test status
Simulation time 320391927 ps
CPU time 1.27 seconds
Started Oct 12 02:21:04 PM UTC 24
Finished Oct 12 02:21:06 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575159538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1575159538
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.1272501148
Short name T291
Test name
Test status
Simulation time 2253106044 ps
CPU time 19.01 seconds
Started Oct 12 02:21:12 PM UTC 24
Finished Oct 12 02:21:32 PM UTC 24
Peak memory 245088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272501148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1272501148
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/10.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.2543522100
Short name T453
Test name
Test status
Simulation time 19075358 ps
CPU time 1.11 seconds
Started Oct 12 02:21:56 PM UTC 24
Finished Oct 12 02:21:58 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543522100 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.2543522100
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.3347928594
Short name T321
Test name
Test status
Simulation time 990436033 ps
CPU time 12.42 seconds
Started Oct 12 02:21:46 PM UTC 24
Finished Oct 12 02:22:00 PM UTC 24
Peak memory 234612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347928594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3347928594
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.1387816167
Short name T445
Test name
Test status
Simulation time 45124938 ps
CPU time 1.19 seconds
Started Oct 12 02:21:36 PM UTC 24
Finished Oct 12 02:21:38 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387816167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1387816167
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.437399713
Short name T234
Test name
Test status
Simulation time 79582171455 ps
CPU time 186.48 seconds
Started Oct 12 02:21:54 PM UTC 24
Finished Oct 12 02:25:03 PM UTC 24
Peak memory 261728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437399713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.437399713
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.749615142
Short name T378
Test name
Test status
Simulation time 265982363 ps
CPU time 5.4 seconds
Started Oct 12 02:21:48 PM UTC 24
Finished Oct 12 02:21:54 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749615142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.749615142
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.3672809356
Short name T228
Test name
Test status
Simulation time 12575183104 ps
CPU time 87.51 seconds
Started Oct 12 02:21:48 PM UTC 24
Finished Oct 12 02:23:17 PM UTC 24
Peak memory 261472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672809356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.3672809356
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.408056306
Short name T235
Test name
Test status
Simulation time 725089509 ps
CPU time 13.34 seconds
Started Oct 12 02:21:44 PM UTC 24
Finished Oct 12 02:21:59 PM UTC 24
Peak memory 245156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408056306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.408056306
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.4226060949
Short name T312
Test name
Test status
Simulation time 1466984903 ps
CPU time 21.33 seconds
Started Oct 12 02:21:45 PM UTC 24
Finished Oct 12 02:22:08 PM UTC 24
Peak memory 245048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226060949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.4226060949
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.2656959804
Short name T446
Test name
Test status
Simulation time 39003267 ps
CPU time 1.6 seconds
Started Oct 12 02:21:37 PM UTC 24
Finished Oct 12 02:21:40 PM UTC 24
Peak memory 229004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656959804 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mem_parity.2656959804
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.1988964094
Short name T450
Test name
Test status
Simulation time 70955170 ps
CPU time 3.05 seconds
Started Oct 12 02:21:44 PM UTC 24
Finished Oct 12 02:21:48 PM UTC 24
Peak memory 233240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988964094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.1988964094
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.3010537287
Short name T449
Test name
Test status
Simulation time 31133850 ps
CPU time 2.88 seconds
Started Oct 12 02:21:43 PM UTC 24
Finished Oct 12 02:21:47 PM UTC 24
Peak memory 244892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010537287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3010537287
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.629455850
Short name T452
Test name
Test status
Simulation time 115185292 ps
CPU time 4.78 seconds
Started Oct 12 02:21:49 PM UTC 24
Finished Oct 12 02:21:55 PM UTC 24
Peak memory 233304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629455850 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.629455850
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.1137528097
Short name T395
Test name
Test status
Simulation time 435834761 ps
CPU time 6.55 seconds
Started Oct 12 02:21:39 PM UTC 24
Finished Oct 12 02:21:47 PM UTC 24
Peak memory 227304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137528097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1137528097
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.1485225377
Short name T447
Test name
Test status
Simulation time 725538680 ps
CPU time 4.34 seconds
Started Oct 12 02:21:37 PM UTC 24
Finished Oct 12 02:21:42 PM UTC 24
Peak memory 227344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485225377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1485225377
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.2185410598
Short name T451
Test name
Test status
Simulation time 101240667 ps
CPU time 5.71 seconds
Started Oct 12 02:21:43 PM UTC 24
Finished Oct 12 02:21:50 PM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185410598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2185410598
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.3908577416
Short name T448
Test name
Test status
Simulation time 958271628 ps
CPU time 1.6 seconds
Started Oct 12 02:21:40 PM UTC 24
Finished Oct 12 02:21:43 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908577416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3908577416
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.2574529603
Short name T328
Test name
Test status
Simulation time 2821240196 ps
CPU time 7.76 seconds
Started Oct 12 02:21:46 PM UTC 24
Finished Oct 12 02:21:55 PM UTC 24
Peak memory 245048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574529603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2574529603
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/11.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.4221803129
Short name T460
Test name
Test status
Simulation time 14288470 ps
CPU time 1.09 seconds
Started Oct 12 02:22:16 PM UTC 24
Finished Oct 12 02:22:18 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221803129 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.4221803129
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.574006715
Short name T459
Test name
Test status
Simulation time 103001304 ps
CPU time 2.72 seconds
Started Oct 12 02:22:10 PM UTC 24
Finished Oct 12 02:22:14 PM UTC 24
Peak memory 234084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574006715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.574006715
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.3956215133
Short name T454
Test name
Test status
Simulation time 17008361 ps
CPU time 1.17 seconds
Started Oct 12 02:21:56 PM UTC 24
Finished Oct 12 02:21:58 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956215133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3956215133
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_all.2867850006
Short name T288
Test name
Test status
Simulation time 362404317 ps
CPU time 7.51 seconds
Started Oct 12 02:22:13 PM UTC 24
Finished Oct 12 02:22:22 PM UTC 24
Peak memory 246952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867850006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2867850006
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.906751742
Short name T627
Test name
Test status
Simulation time 85494210127 ps
CPU time 342.97 seconds
Started Oct 12 02:22:13 PM UTC 24
Finished Oct 12 02:28:01 PM UTC 24
Peak memory 284236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906751742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.906751742
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.2925712493
Short name T489
Test name
Test status
Simulation time 11238525021 ps
CPU time 62.35 seconds
Started Oct 12 02:22:14 PM UTC 24
Finished Oct 12 02:23:18 PM UTC 24
Peak memory 261456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925712493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.2925712493
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.3970929791
Short name T374
Test name
Test status
Simulation time 438038631 ps
CPU time 11.98 seconds
Started Oct 12 02:22:10 PM UTC 24
Finished Oct 12 02:22:23 PM UTC 24
Peak memory 244892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970929791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3970929791
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.2810692007
Short name T225
Test name
Test status
Simulation time 3679983790 ps
CPU time 41.84 seconds
Started Oct 12 02:22:13 PM UTC 24
Finished Oct 12 02:22:56 PM UTC 24
Peak memory 261476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810692007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.2810692007
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.2522938636
Short name T253
Test name
Test status
Simulation time 1745911184 ps
CPU time 9.47 seconds
Started Oct 12 02:22:05 PM UTC 24
Finished Oct 12 02:22:15 PM UTC 24
Peak memory 234720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522938636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2522938636
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.2445577795
Short name T464
Test name
Test status
Simulation time 2451360079 ps
CPU time 16.1 seconds
Started Oct 12 02:22:05 PM UTC 24
Finished Oct 12 02:22:22 PM UTC 24
Peak memory 244984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445577795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2445577795
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.1115002600
Short name T455
Test name
Test status
Simulation time 26147898 ps
CPU time 1.58 seconds
Started Oct 12 02:21:58 PM UTC 24
Finished Oct 12 02:22:01 PM UTC 24
Peak memory 229004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115002600 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mem_parity.1115002600
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.2601689664
Short name T75
Test name
Test status
Simulation time 3784974435 ps
CPU time 14.03 seconds
Started Oct 12 02:22:02 PM UTC 24
Finished Oct 12 02:22:18 PM UTC 24
Peak memory 245092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601689664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.2601689664
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.671260960
Short name T325
Test name
Test status
Simulation time 5483216343 ps
CPU time 8.69 seconds
Started Oct 12 02:22:02 PM UTC 24
Finished Oct 12 02:22:12 PM UTC 24
Peak memory 235124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671260960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.671260960
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.68225416
Short name T461
Test name
Test status
Simulation time 139958824 ps
CPU time 6.31 seconds
Started Oct 12 02:22:13 PM UTC 24
Finished Oct 12 02:22:21 PM UTC 24
Peak memory 233168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68225416 -assert nopostproc +UVM_TESTNAME=spi_device_bas
e_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.68225416
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.3942335247
Short name T387
Test name
Test status
Simulation time 7369317361 ps
CPU time 30.8 seconds
Started Oct 12 02:22:00 PM UTC 24
Finished Oct 12 02:22:32 PM UTC 24
Peak memory 227736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942335247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3942335247
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.552302969
Short name T458
Test name
Test status
Simulation time 2833364516 ps
CPU time 10.93 seconds
Started Oct 12 02:22:00 PM UTC 24
Finished Oct 12 02:22:12 PM UTC 24
Peak memory 227432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552302969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.552302969
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.1390647978
Short name T457
Test name
Test status
Simulation time 60991134 ps
CPU time 1.74 seconds
Started Oct 12 02:22:00 PM UTC 24
Finished Oct 12 02:22:03 PM UTC 24
Peak memory 226516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390647978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1390647978
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.3206111929
Short name T456
Test name
Test status
Simulation time 30034884 ps
CPU time 1.23 seconds
Started Oct 12 02:22:00 PM UTC 24
Finished Oct 12 02:22:02 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206111929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3206111929
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.773804230
Short name T283
Test name
Test status
Simulation time 1206019373 ps
CPU time 4.06 seconds
Started Oct 12 02:22:09 PM UTC 24
Finished Oct 12 02:22:14 PM UTC 24
Peak memory 234724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773804230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.773804230
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/12.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_alert_test.3008909922
Short name T470
Test name
Test status
Simulation time 32515993 ps
CPU time 1.12 seconds
Started Oct 12 02:22:43 PM UTC 24
Finished Oct 12 02:22:45 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008909922 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.3008909922
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_cfg_cmd.3724439814
Short name T307
Test name
Test status
Simulation time 2182734847 ps
CPU time 6.34 seconds
Started Oct 12 02:22:32 PM UTC 24
Finished Oct 12 02:22:39 PM UTC 24
Peak memory 234736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724439814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3724439814
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.1553457140
Short name T462
Test name
Test status
Simulation time 56131351 ps
CPU time 1.15 seconds
Started Oct 12 02:22:19 PM UTC 24
Finished Oct 12 02:22:21 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553457140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1553457140
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.4109401541
Short name T546
Test name
Test status
Simulation time 115179292315 ps
CPU time 199.2 seconds
Started Oct 12 02:22:37 PM UTC 24
Finished Oct 12 02:25:59 PM UTC 24
Peak memory 267808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109401541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.4109401541
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.4018047534
Short name T389
Test name
Test status
Simulation time 26874578937 ps
CPU time 109.27 seconds
Started Oct 12 02:22:40 PM UTC 24
Finished Oct 12 02:24:32 PM UTC 24
Peak memory 251492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018047534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.4018047534
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.1446058125
Short name T508
Test name
Test status
Simulation time 7961596087 ps
CPU time 83.11 seconds
Started Oct 12 02:22:40 PM UTC 24
Finished Oct 12 02:24:05 PM UTC 24
Peak memory 261508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446058125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.1446058125
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode.3478713470
Short name T472
Test name
Test status
Simulation time 2971779113 ps
CPU time 14.12 seconds
Started Oct 12 02:22:32 PM UTC 24
Finished Oct 12 02:22:47 PM UTC 24
Peak memory 235004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478713470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3478713470
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.3662786720
Short name T602
Test name
Test status
Simulation time 45370985768 ps
CPU time 278.45 seconds
Started Oct 12 02:22:33 PM UTC 24
Finished Oct 12 02:27:15 PM UTC 24
Peak memory 261412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662786720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.3662786720
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_intercept.2161861538
Short name T324
Test name
Test status
Simulation time 537427204 ps
CPU time 5.95 seconds
Started Oct 12 02:22:25 PM UTC 24
Finished Oct 12 02:22:33 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161861538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2161861538
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mailbox.2101199275
Short name T346
Test name
Test status
Simulation time 519258080 ps
CPU time 3.67 seconds
Started Oct 12 02:22:27 PM UTC 24
Finished Oct 12 02:22:31 PM UTC 24
Peak memory 234660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101199275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2101199275
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.986846355
Short name T463
Test name
Test status
Simulation time 161080688 ps
CPU time 1.56 seconds
Started Oct 12 02:22:19 PM UTC 24
Finished Oct 12 02:22:21 PM UTC 24
Peak memory 228996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986846355 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mem_parity.986846355
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.2237472301
Short name T265
Test name
Test status
Simulation time 4269190806 ps
CPU time 14.98 seconds
Started Oct 12 02:22:24 PM UTC 24
Finished Oct 12 02:22:41 PM UTC 24
Peak memory 249440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237472301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.2237472301
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.35012791
Short name T322
Test name
Test status
Simulation time 4535703330 ps
CPU time 12.19 seconds
Started Oct 12 02:22:23 PM UTC 24
Finished Oct 12 02:22:37 PM UTC 24
Peak memory 245148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35012791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.35012791
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.900491362
Short name T468
Test name
Test status
Simulation time 806909116 ps
CPU time 6.32 seconds
Started Oct 12 02:22:34 PM UTC 24
Finished Oct 12 02:22:41 PM UTC 24
Peak memory 231176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900491362 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.900491362
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.4069435189
Short name T469
Test name
Test status
Simulation time 39620258 ps
CPU time 1.45 seconds
Started Oct 12 02:22:41 PM UTC 24
Finished Oct 12 02:22:44 PM UTC 24
Peak memory 216328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069435189 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.4069435189
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_all.1374275927
Short name T386
Test name
Test status
Simulation time 4454020622 ps
CPU time 32.37 seconds
Started Oct 12 02:22:22 PM UTC 24
Finished Oct 12 02:22:56 PM UTC 24
Peak memory 231832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374275927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1374275927
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.3073065075
Short name T467
Test name
Test status
Simulation time 616590190 ps
CPU time 7.49 seconds
Started Oct 12 02:22:22 PM UTC 24
Finished Oct 12 02:22:31 PM UTC 24
Peak memory 227280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073065075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3073065075
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.1706085298
Short name T466
Test name
Test status
Simulation time 41124069 ps
CPU time 1.07 seconds
Started Oct 12 02:22:23 PM UTC 24
Finished Oct 12 02:22:25 PM UTC 24
Peak memory 213472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706085298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1706085298
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.205850929
Short name T465
Test name
Test status
Simulation time 41322537 ps
CPU time 1.08 seconds
Started Oct 12 02:22:22 PM UTC 24
Finished Oct 12 02:22:24 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205850929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.205850929
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_upload.3588929960
Short name T279
Test name
Test status
Simulation time 4136762247 ps
CPU time 8.59 seconds
Started Oct 12 02:22:30 PM UTC 24
Finished Oct 12 02:22:40 PM UTC 24
Peak memory 234792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588929960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3588929960
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/13.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_alert_test.1432400781
Short name T482
Test name
Test status
Simulation time 16058911 ps
CPU time 1.1 seconds
Started Oct 12 02:23:09 PM UTC 24
Finished Oct 12 02:23:11 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432400781 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.1432400781
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_cfg_cmd.3109528661
Short name T479
Test name
Test status
Simulation time 62700720 ps
CPU time 3.12 seconds
Started Oct 12 02:22:58 PM UTC 24
Finished Oct 12 02:23:02 PM UTC 24
Peak memory 244580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109528661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3109528661
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_csb_read.1172873543
Short name T471
Test name
Test status
Simulation time 21120456 ps
CPU time 1.22 seconds
Started Oct 12 02:22:45 PM UTC 24
Finished Oct 12 02:22:47 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172873543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1172873543
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.2796747478
Short name T558
Test name
Test status
Simulation time 15496081334 ps
CPU time 191.41 seconds
Started Oct 12 02:23:03 PM UTC 24
Finished Oct 12 02:26:18 PM UTC 24
Peak memory 261472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796747478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2796747478
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode.161119289
Short name T488
Test name
Test status
Simulation time 1900475497 ps
CPU time 18.76 seconds
Started Oct 12 02:22:58 PM UTC 24
Finished Oct 12 02:23:18 PM UTC 24
Peak memory 234848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161119289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.161119289
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.920426988
Short name T300
Test name
Test status
Simulation time 32550361878 ps
CPU time 290.73 seconds
Started Oct 12 02:23:01 PM UTC 24
Finished Oct 12 02:27:56 PM UTC 24
Peak memory 261416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920426988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.920426988
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_intercept.1558833073
Short name T343
Test name
Test status
Simulation time 14721730799 ps
CPU time 18.67 seconds
Started Oct 12 02:22:55 PM UTC 24
Finished Oct 12 02:23:15 PM UTC 24
Peak memory 234848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558833073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1558833073
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mailbox.2529396498
Short name T298
Test name
Test status
Simulation time 48848083170 ps
CPU time 112.57 seconds
Started Oct 12 02:22:57 PM UTC 24
Finished Oct 12 02:24:52 PM UTC 24
Peak memory 244756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529396498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2529396498
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mem_parity.2847256851
Short name T473
Test name
Test status
Simulation time 131867235 ps
CPU time 1.54 seconds
Started Oct 12 02:22:46 PM UTC 24
Finished Oct 12 02:22:48 PM UTC 24
Peak memory 228944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847256851 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mem_parity.2847256851
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.718260943
Short name T477
Test name
Test status
Simulation time 33489187 ps
CPU time 2.91 seconds
Started Oct 12 02:22:52 PM UTC 24
Finished Oct 12 02:22:56 PM UTC 24
Peak memory 244644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718260943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.718260943
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.3021109335
Short name T323
Test name
Test status
Simulation time 4200790357 ps
CPU time 10.55 seconds
Started Oct 12 02:22:52 PM UTC 24
Finished Oct 12 02:23:04 PM UTC 24
Peak memory 234740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021109335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3021109335
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.454736814
Short name T483
Test name
Test status
Simulation time 192700691 ps
CPU time 6.46 seconds
Started Oct 12 02:23:03 PM UTC 24
Finished Oct 12 02:23:11 PM UTC 24
Peak memory 233420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454736814 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.454736814
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.4218448642
Short name T480
Test name
Test status
Simulation time 45103384 ps
CPU time 1.49 seconds
Started Oct 12 02:23:05 PM UTC 24
Finished Oct 12 02:23:08 PM UTC 24
Peak memory 216060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218448642 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.4218448642
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_all.3500360504
Short name T478
Test name
Test status
Simulation time 2293638112 ps
CPU time 10.85 seconds
Started Oct 12 02:22:48 PM UTC 24
Finished Oct 12 02:23:00 PM UTC 24
Peak memory 227732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500360504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3500360504
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.1912174981
Short name T476
Test name
Test status
Simulation time 688176256 ps
CPU time 6.36 seconds
Started Oct 12 02:22:48 PM UTC 24
Finished Oct 12 02:22:55 PM UTC 24
Peak memory 227268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912174981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1912174981
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_rw.1180195604
Short name T475
Test name
Test status
Simulation time 393905658 ps
CPU time 4.16 seconds
Started Oct 12 02:22:49 PM UTC 24
Finished Oct 12 02:22:54 PM UTC 24
Peak memory 227288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180195604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1180195604
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.2695950938
Short name T474
Test name
Test status
Simulation time 15356387 ps
CPU time 1.14 seconds
Started Oct 12 02:22:49 PM UTC 24
Finished Oct 12 02:22:51 PM UTC 24
Peak memory 216516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695950938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2695950938
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_upload.3824698295
Short name T290
Test name
Test status
Simulation time 1343805909 ps
CPU time 5.11 seconds
Started Oct 12 02:22:57 PM UTC 24
Finished Oct 12 02:23:03 PM UTC 24
Peak memory 234980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824698295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3824698295
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/14.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_alert_test.3329155636
Short name T492
Test name
Test status
Simulation time 14831545 ps
CPU time 1.1 seconds
Started Oct 12 02:23:30 PM UTC 24
Finished Oct 12 02:23:32 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329155636 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.3329155636
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_cfg_cmd.3262476584
Short name T308
Test name
Test status
Simulation time 1156830924 ps
CPU time 11.73 seconds
Started Oct 12 02:23:19 PM UTC 24
Finished Oct 12 02:23:31 PM UTC 24
Peak memory 245112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262476584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3262476584
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_csb_read.3254086540
Short name T484
Test name
Test status
Simulation time 115005943 ps
CPU time 1.19 seconds
Started Oct 12 02:23:11 PM UTC 24
Finished Oct 12 02:23:13 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254086540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3254086540
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_all.2738685793
Short name T491
Test name
Test status
Simulation time 90722967 ps
CPU time 1.25 seconds
Started Oct 12 02:23:21 PM UTC 24
Finished Oct 12 02:23:23 PM UTC 24
Peak memory 225168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738685793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2738685793
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.2418384293
Short name T342
Test name
Test status
Simulation time 50175942468 ps
CPU time 523.85 seconds
Started Oct 12 02:23:22 PM UTC 24
Finished Oct 12 02:32:12 PM UTC 24
Peak memory 282012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418384293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2418384293
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode.3973316311
Short name T380
Test name
Test status
Simulation time 344375172 ps
CPU time 8.23 seconds
Started Oct 12 02:23:19 PM UTC 24
Finished Oct 12 02:23:28 PM UTC 24
Peak memory 234648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973316311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3973316311
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_intercept.574138780
Short name T351
Test name
Test status
Simulation time 309791402 ps
CPU time 2.92 seconds
Started Oct 12 02:23:16 PM UTC 24
Finished Oct 12 02:23:20 PM UTC 24
Peak memory 234964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574138780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.574138780
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mailbox.3813412973
Short name T245
Test name
Test status
Simulation time 22278891531 ps
CPU time 73.07 seconds
Started Oct 12 02:23:17 PM UTC 24
Finished Oct 12 02:24:33 PM UTC 24
Peak memory 249192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813412973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3813412973
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mem_parity.2442053231
Short name T486
Test name
Test status
Simulation time 17439177 ps
CPU time 1.48 seconds
Started Oct 12 02:23:12 PM UTC 24
Finished Oct 12 02:23:14 PM UTC 24
Peak memory 229004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442053231 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mem_parity.2442053231
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.3173388790
Short name T337
Test name
Test status
Simulation time 150124319244 ps
CPU time 56.88 seconds
Started Oct 12 02:23:15 PM UTC 24
Finished Oct 12 02:24:14 PM UTC 24
Peak memory 261476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173388790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.3173388790
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.3893118314
Short name T317
Test name
Test status
Simulation time 1423925955 ps
CPU time 11.31 seconds
Started Oct 12 02:23:15 PM UTC 24
Finished Oct 12 02:23:28 PM UTC 24
Peak memory 234656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893118314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3893118314
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.1399469757
Short name T498
Test name
Test status
Simulation time 8649420817 ps
CPU time 18.5 seconds
Started Oct 12 02:23:21 PM UTC 24
Finished Oct 12 02:23:41 PM UTC 24
Peak memory 233612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399469757 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.1399469757
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_all.506974952
Short name T499
Test name
Test status
Simulation time 3334425913 ps
CPU time 32.52 seconds
Started Oct 12 02:23:12 PM UTC 24
Finished Oct 12 02:23:46 PM UTC 24
Peak memory 227796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506974952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.506974952
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.1609822831
Short name T490
Test name
Test status
Simulation time 941068172 ps
CPU time 7.54 seconds
Started Oct 12 02:23:12 PM UTC 24
Finished Oct 12 02:23:21 PM UTC 24
Peak memory 227284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609822831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1609822831
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_rw.3375845485
Short name T487
Test name
Test status
Simulation time 17600274 ps
CPU time 1.07 seconds
Started Oct 12 02:23:14 PM UTC 24
Finished Oct 12 02:23:16 PM UTC 24
Peak memory 213472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375845485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3375845485
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.3331041480
Short name T485
Test name
Test status
Simulation time 47306857 ps
CPU time 0.91 seconds
Started Oct 12 02:23:12 PM UTC 24
Finished Oct 12 02:23:14 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331041480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3331041480
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_upload.2141805173
Short name T270
Test name
Test status
Simulation time 22661164186 ps
CPU time 13.38 seconds
Started Oct 12 02:23:19 PM UTC 24
Finished Oct 12 02:23:33 PM UTC 24
Peak memory 234876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141805173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2141805173
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/15.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_alert_test.515593977
Short name T502
Test name
Test status
Simulation time 23509323 ps
CPU time 1.09 seconds
Started Oct 12 02:23:53 PM UTC 24
Finished Oct 12 02:23:55 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515593977 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.515593977
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_cfg_cmd.4074290724
Short name T318
Test name
Test status
Simulation time 3928526383 ps
CPU time 8.6 seconds
Started Oct 12 02:23:42 PM UTC 24
Finished Oct 12 02:23:52 PM UTC 24
Peak memory 234744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074290724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4074290724
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_csb_read.3574085955
Short name T493
Test name
Test status
Simulation time 14781789 ps
CPU time 1.18 seconds
Started Oct 12 02:23:30 PM UTC 24
Finished Oct 12 02:23:32 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574085955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3574085955
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_all.2779812796
Short name T255
Test name
Test status
Simulation time 3253192560 ps
CPU time 90.33 seconds
Started Oct 12 02:23:49 PM UTC 24
Finished Oct 12 02:25:22 PM UTC 24
Peak memory 265512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779812796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2779812796
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2486971394
Short name T229
Test name
Test status
Simulation time 17084411939 ps
CPU time 49.81 seconds
Started Oct 12 02:23:52 PM UTC 24
Finished Oct 12 02:24:43 PM UTC 24
Peak memory 245152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486971394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.2486971394
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode.3024440263
Short name T503
Test name
Test status
Simulation time 552838053 ps
CPU time 11.36 seconds
Started Oct 12 02:23:43 PM UTC 24
Finished Oct 12 02:23:55 PM UTC 24
Peak memory 244896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024440263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3024440263
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.3566075163
Short name T501
Test name
Test status
Simulation time 30560247 ps
CPU time 1.13 seconds
Started Oct 12 02:23:47 PM UTC 24
Finished Oct 12 02:23:49 PM UTC 24
Peak memory 225164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566075163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.3566075163
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_intercept.717781806
Short name T287
Test name
Test status
Simulation time 2381691569 ps
CPU time 7.34 seconds
Started Oct 12 02:23:38 PM UTC 24
Finished Oct 12 02:23:46 PM UTC 24
Peak memory 235044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717781806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.717781806
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mailbox.3056682237
Short name T282
Test name
Test status
Simulation time 1838340808 ps
CPU time 13.15 seconds
Started Oct 12 02:23:38 PM UTC 24
Finished Oct 12 02:23:52 PM UTC 24
Peak memory 239704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056682237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3056682237
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mem_parity.1702835572
Short name T494
Test name
Test status
Simulation time 16283369 ps
CPU time 1.48 seconds
Started Oct 12 02:23:32 PM UTC 24
Finished Oct 12 02:23:34 PM UTC 24
Peak memory 229004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702835572 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mem_parity.1702835572
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.2237486615
Short name T335
Test name
Test status
Simulation time 4136257700 ps
CPU time 13.34 seconds
Started Oct 12 02:23:36 PM UTC 24
Finished Oct 12 02:23:51 PM UTC 24
Peak memory 234840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237486615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.2237486615
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.864441178
Short name T266
Test name
Test status
Simulation time 638604721 ps
CPU time 5.69 seconds
Started Oct 12 02:23:35 PM UTC 24
Finished Oct 12 02:23:42 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864441178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.864441178
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.1995866033
Short name T506
Test name
Test status
Simulation time 2100115444 ps
CPU time 15.62 seconds
Started Oct 12 02:23:47 PM UTC 24
Finished Oct 12 02:24:04 PM UTC 24
Peak memory 233164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995866033 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.1995866033
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_all.2178006240
Short name T500
Test name
Test status
Simulation time 2987813036 ps
CPU time 14.75 seconds
Started Oct 12 02:23:33 PM UTC 24
Finished Oct 12 02:23:49 PM UTC 24
Peak memory 227416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178006240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2178006240
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.3935558851
Short name T497
Test name
Test status
Simulation time 827115788 ps
CPU time 5.18 seconds
Started Oct 12 02:23:33 PM UTC 24
Finished Oct 12 02:23:39 PM UTC 24
Peak memory 216784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935558851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3935558851
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_rw.4015587158
Short name T496
Test name
Test status
Simulation time 59205025 ps
CPU time 1.47 seconds
Started Oct 12 02:23:34 PM UTC 24
Finished Oct 12 02:23:37 PM UTC 24
Peak memory 216392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015587158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.4015587158
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.2879423466
Short name T495
Test name
Test status
Simulation time 52086716 ps
CPU time 1.34 seconds
Started Oct 12 02:23:33 PM UTC 24
Finished Oct 12 02:23:35 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879423466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2879423466
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_upload.427669790
Short name T327
Test name
Test status
Simulation time 22542556773 ps
CPU time 40.08 seconds
Started Oct 12 02:23:40 PM UTC 24
Finished Oct 12 02:24:21 PM UTC 24
Peak memory 245280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427669790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.427669790
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/16.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/17.spi_device_alert_test.761340694
Short name T514
Test name
Test status
Simulation time 86506741 ps
CPU time 1.09 seconds
Started Oct 12 02:24:26 PM UTC 24
Finished Oct 12 02:24:28 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761340694 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.761340694
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/17.spi_device_cfg_cmd.2884178166
Short name T513
Test name
Test status
Simulation time 192965076 ps
CPU time 6.02 seconds
Started Oct 12 02:24:13 PM UTC 24
Finished Oct 12 02:24:20 PM UTC 24
Peak memory 234844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884178166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2884178166
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/17.spi_device_csb_read.1472263954
Short name T504
Test name
Test status
Simulation time 17419776 ps
CPU time 1.19 seconds
Started Oct 12 02:23:56 PM UTC 24
Finished Oct 12 02:23:58 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472263954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1472263954
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_all.2475732617
Short name T659
Test name
Test status
Simulation time 32688227000 ps
CPU time 273.77 seconds
Started Oct 12 02:24:20 PM UTC 24
Finished Oct 12 02:28:57 PM UTC 24
Peak memory 273960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475732617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2475732617
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.4035968736
Short name T299
Test name
Test status
Simulation time 2466176671 ps
CPU time 42.1 seconds
Started Oct 12 02:24:21 PM UTC 24
Finished Oct 12 02:25:04 PM UTC 24
Peak memory 251216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035968736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.4035968736
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.2558809644
Short name T362
Test name
Test status
Simulation time 60085128589 ps
CPU time 523.96 seconds
Started Oct 12 02:24:22 PM UTC 24
Finished Oct 12 02:33:12 PM UTC 24
Peak memory 276128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558809644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.2558809644
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode.943729727
Short name T379
Test name
Test status
Simulation time 247041452 ps
CPU time 3.92 seconds
Started Oct 12 02:24:14 PM UTC 24
Finished Oct 12 02:24:19 PM UTC 24
Peak memory 244852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943729727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.943729727
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.4007943040
Short name T533
Test name
Test status
Simulation time 22535738422 ps
CPU time 76.36 seconds
Started Oct 12 02:24:15 PM UTC 24
Finished Oct 12 02:25:34 PM UTC 24
Peak memory 261416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007943040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.4007943040
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/17.spi_device_intercept.2581473458
Short name T268
Test name
Test status
Simulation time 1163031943 ps
CPU time 15.39 seconds
Started Oct 12 02:24:09 PM UTC 24
Finished Oct 12 02:24:25 PM UTC 24
Peak memory 244956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581473458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2581473458
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mailbox.3143392520
Short name T512
Test name
Test status
Simulation time 348171212 ps
CPU time 6.4 seconds
Started Oct 12 02:24:10 PM UTC 24
Finished Oct 12 02:24:17 PM UTC 24
Peak memory 251056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143392520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3143392520
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mem_parity.3339083487
Short name T505
Test name
Test status
Simulation time 29807999 ps
CPU time 1.52 seconds
Started Oct 12 02:23:56 PM UTC 24
Finished Oct 12 02:23:58 PM UTC 24
Peak memory 229004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339083487 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mem_parity.3339083487
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.296174346
Short name T336
Test name
Test status
Simulation time 687193756 ps
CPU time 3.74 seconds
Started Oct 12 02:24:08 PM UTC 24
Finished Oct 12 02:24:12 PM UTC 24
Peak memory 244960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296174346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.296174346
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.1419779701
Short name T344
Test name
Test status
Simulation time 2587233948 ps
CPU time 6.05 seconds
Started Oct 12 02:24:07 PM UTC 24
Finished Oct 12 02:24:14 PM UTC 24
Peak memory 234744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419779701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1419779701
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.1782371696
Short name T516
Test name
Test status
Simulation time 6733009585 ps
CPU time 12.43 seconds
Started Oct 12 02:24:18 PM UTC 24
Finished Oct 12 02:24:32 PM UTC 24
Peak memory 229408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782371696 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.1782371696
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/17.spi_device_stress_all.2668181665
Short name T261
Test name
Test status
Simulation time 51618403082 ps
CPU time 515.04 seconds
Started Oct 12 02:24:23 PM UTC 24
Finished Oct 12 02:33:05 PM UTC 24
Peak memory 277860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668181665 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.2668181665
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_all.2490742958
Short name T510
Test name
Test status
Simulation time 1539948367 ps
CPU time 7.29 seconds
Started Oct 12 02:23:59 PM UTC 24
Finished Oct 12 02:24:08 PM UTC 24
Peak memory 227288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490742958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2490742958
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.3818325077
Short name T507
Test name
Test status
Simulation time 1396409075 ps
CPU time 4.33 seconds
Started Oct 12 02:23:59 PM UTC 24
Finished Oct 12 02:24:05 PM UTC 24
Peak memory 227560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818325077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3818325077
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_rw.2437053298
Short name T511
Test name
Test status
Simulation time 35112820 ps
CPU time 2.72 seconds
Started Oct 12 02:24:05 PM UTC 24
Finished Oct 12 02:24:09 PM UTC 24
Peak memory 227560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437053298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2437053298
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.3799894278
Short name T509
Test name
Test status
Simulation time 94478301 ps
CPU time 1.28 seconds
Started Oct 12 02:24:04 PM UTC 24
Finished Oct 12 02:24:07 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799894278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3799894278
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/17.spi_device_upload.1878542020
Short name T315
Test name
Test status
Simulation time 1525164365 ps
CPU time 8.71 seconds
Started Oct 12 02:24:12 PM UTC 24
Finished Oct 12 02:24:22 PM UTC 24
Peak memory 244960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878542020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1878542020
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/17.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/18.spi_device_alert_test.2979207940
Short name T524
Test name
Test status
Simulation time 43616844 ps
CPU time 1.1 seconds
Started Oct 12 02:24:53 PM UTC 24
Finished Oct 12 02:24:56 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979207940 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.2979207940
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/18.spi_device_cfg_cmd.1767397656
Short name T345
Test name
Test status
Simulation time 4026706901 ps
CPU time 8.87 seconds
Started Oct 12 02:24:40 PM UTC 24
Finished Oct 12 02:24:51 PM UTC 24
Peak memory 245024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767397656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1767397656
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/18.spi_device_csb_read.2905693709
Short name T515
Test name
Test status
Simulation time 32853679 ps
CPU time 1.19 seconds
Started Oct 12 02:24:29 PM UTC 24
Finished Oct 12 02:24:32 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905693709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2905693709
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_all.541215066
Short name T561
Test name
Test status
Simulation time 18461089280 ps
CPU time 94.18 seconds
Started Oct 12 02:24:44 PM UTC 24
Finished Oct 12 02:26:20 PM UTC 24
Peak memory 267560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541215066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.541215066
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.48958551
Short name T302
Test name
Test status
Simulation time 3806731486 ps
CPU time 24.87 seconds
Started Oct 12 02:24:52 PM UTC 24
Finished Oct 12 02:25:18 PM UTC 24
Peak memory 245084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48958551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.48958551
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.1559046343
Short name T525
Test name
Test status
Simulation time 110631640 ps
CPU time 3.71 seconds
Started Oct 12 02:24:52 PM UTC 24
Finished Oct 12 02:24:57 PM UTC 24
Peak memory 229412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559046343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.1559046343
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode.3377597819
Short name T167
Test name
Test status
Simulation time 1854075440 ps
CPU time 41.87 seconds
Started Oct 12 02:24:40 PM UTC 24
Finished Oct 12 02:25:24 PM UTC 24
Peak memory 251040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377597819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3377597819
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.2107834794
Short name T340
Test name
Test status
Simulation time 7199433840 ps
CPU time 18.18 seconds
Started Oct 12 02:24:43 PM UTC 24
Finished Oct 12 02:25:02 PM UTC 24
Peak memory 234788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107834794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.2107834794
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/18.spi_device_intercept.3258972516
Short name T522
Test name
Test status
Simulation time 351959239 ps
CPU time 3.56 seconds
Started Oct 12 02:24:36 PM UTC 24
Finished Oct 12 02:24:41 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258972516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3258972516
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mailbox.4244256449
Short name T239
Test name
Test status
Simulation time 702192254 ps
CPU time 20.17 seconds
Started Oct 12 02:24:37 PM UTC 24
Finished Oct 12 02:24:59 PM UTC 24
Peak memory 245116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244256449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.4244256449
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mem_parity.4005411646
Short name T517
Test name
Test status
Simulation time 18347786 ps
CPU time 1.46 seconds
Started Oct 12 02:24:30 PM UTC 24
Finished Oct 12 02:24:33 PM UTC 24
Peak memory 229004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005411646 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mem_parity.4005411646
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.2415710923
Short name T520
Test name
Test status
Simulation time 136870106 ps
CPU time 2.89 seconds
Started Oct 12 02:24:34 PM UTC 24
Finished Oct 12 02:24:38 PM UTC 24
Peak memory 233984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415710923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.2415710923
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.1252779545
Short name T320
Test name
Test status
Simulation time 4760511350 ps
CPU time 7.45 seconds
Started Oct 12 02:24:34 PM UTC 24
Finished Oct 12 02:24:42 PM UTC 24
Peak memory 234744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252779545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1252779545
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.2977694335
Short name T523
Test name
Test status
Simulation time 144331295 ps
CPU time 6.49 seconds
Started Oct 12 02:24:44 PM UTC 24
Finished Oct 12 02:24:51 PM UTC 24
Peak memory 233252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977694335 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.2977694335
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.984084797
Short name T43
Test name
Test status
Simulation time 24994407474 ps
CPU time 86.39 seconds
Started Oct 12 02:24:52 PM UTC 24
Finished Oct 12 02:26:21 PM UTC 24
Peak memory 267680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984084797 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.984084797
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_all.3565076062
Short name T388
Test name
Test status
Simulation time 4126414146 ps
CPU time 24.46 seconds
Started Oct 12 02:24:33 PM UTC 24
Finished Oct 12 02:24:58 PM UTC 24
Peak memory 226740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565076062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3565076062
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.2931674227
Short name T521
Test name
Test status
Simulation time 3169232096 ps
CPU time 6.12 seconds
Started Oct 12 02:24:33 PM UTC 24
Finished Oct 12 02:24:40 PM UTC 24
Peak memory 227368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931674227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2931674227
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_rw.3892944116
Short name T519
Test name
Test status
Simulation time 221382296 ps
CPU time 2.35 seconds
Started Oct 12 02:24:33 PM UTC 24
Finished Oct 12 02:24:36 PM UTC 24
Peak memory 227224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892944116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3892944116
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.1289194471
Short name T518
Test name
Test status
Simulation time 57855255 ps
CPU time 1.19 seconds
Started Oct 12 02:24:33 PM UTC 24
Finished Oct 12 02:24:35 PM UTC 24
Peak memory 214960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289194471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1289194471
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/18.spi_device_upload.3474845284
Short name T246
Test name
Test status
Simulation time 3413063827 ps
CPU time 12.2 seconds
Started Oct 12 02:24:39 PM UTC 24
Finished Oct 12 02:24:53 PM UTC 24
Peak memory 244968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474845284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3474845284
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/18.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_alert_test.3141484729
Short name T532
Test name
Test status
Simulation time 12957484 ps
CPU time 1.09 seconds
Started Oct 12 02:25:20 PM UTC 24
Finished Oct 12 02:25:22 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141484729 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.3141484729
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_cfg_cmd.1688716593
Short name T303
Test name
Test status
Simulation time 2917045359 ps
CPU time 15.51 seconds
Started Oct 12 02:25:06 PM UTC 24
Finished Oct 12 02:25:22 PM UTC 24
Peak memory 234996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688716593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1688716593
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_csb_read.1541551208
Short name T526
Test name
Test status
Simulation time 48716184 ps
CPU time 1.07 seconds
Started Oct 12 02:24:56 PM UTC 24
Finished Oct 12 02:24:58 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541551208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1541551208
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_all.3025896708
Short name T673
Test name
Test status
Simulation time 60645697411 ps
CPU time 239.5 seconds
Started Oct 12 02:25:12 PM UTC 24
Finished Oct 12 02:29:15 PM UTC 24
Peak memory 261728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025896708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3025896708
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.753406619
Short name T281
Test name
Test status
Simulation time 7457141384 ps
CPU time 190.24 seconds
Started Oct 12 02:25:17 PM UTC 24
Finished Oct 12 02:28:31 PM UTC 24
Peak memory 283980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753406619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.753406619
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.3453381117
Short name T553
Test name
Test status
Simulation time 76793130829 ps
CPU time 51.7 seconds
Started Oct 12 02:25:18 PM UTC 24
Finished Oct 12 02:26:12 PM UTC 24
Peak memory 261468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453381117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.3453381117
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode.1496901369
Short name T381
Test name
Test status
Simulation time 967195124 ps
CPU time 25.99 seconds
Started Oct 12 02:25:07 PM UTC 24
Finished Oct 12 02:25:34 PM UTC 24
Peak memory 251100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496901369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1496901369
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.1129106806
Short name T593
Test name
Test status
Simulation time 27101651791 ps
CPU time 110.39 seconds
Started Oct 12 02:25:07 PM UTC 24
Finished Oct 12 02:26:59 PM UTC 24
Peak memory 263464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129106806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.1129106806
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_intercept.2340581222
Short name T294
Test name
Test status
Simulation time 3583143460 ps
CPU time 12.9 seconds
Started Oct 12 02:25:03 PM UTC 24
Finished Oct 12 02:25:17 PM UTC 24
Peak memory 234848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340581222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2340581222
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mailbox.582486498
Short name T542
Test name
Test status
Simulation time 5137049528 ps
CPU time 49.35 seconds
Started Oct 12 02:25:04 PM UTC 24
Finished Oct 12 02:25:55 PM UTC 24
Peak memory 251176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582486498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.582486498
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mem_parity.4082423246
Short name T527
Test name
Test status
Simulation time 43094432 ps
CPU time 1.49 seconds
Started Oct 12 02:24:58 PM UTC 24
Finished Oct 12 02:25:00 PM UTC 24
Peak memory 229004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082423246 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mem_parity.4082423246
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.1404606078
Short name T333
Test name
Test status
Simulation time 1472131440 ps
CPU time 11.87 seconds
Started Oct 12 02:25:03 PM UTC 24
Finished Oct 12 02:25:16 PM UTC 24
Peak memory 244956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404606078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.1404606078
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.3869369514
Short name T277
Test name
Test status
Simulation time 38721785 ps
CPU time 3.11 seconds
Started Oct 12 02:25:02 PM UTC 24
Finished Oct 12 02:25:06 PM UTC 24
Peak memory 244956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869369514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3869369514
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.2307412482
Short name T531
Test name
Test status
Simulation time 657364794 ps
CPU time 7 seconds
Started Oct 12 02:25:11 PM UTC 24
Finished Oct 12 02:25:19 PM UTC 24
Peak memory 233416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307412482 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.2307412482
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_all.2755887081
Short name T545
Test name
Test status
Simulation time 34507440295 ps
CPU time 57.71 seconds
Started Oct 12 02:25:00 PM UTC 24
Finished Oct 12 02:25:59 PM UTC 24
Peak memory 227628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755887081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2755887081
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.1092555341
Short name T530
Test name
Test status
Simulation time 8898358562 ps
CPU time 11.78 seconds
Started Oct 12 02:24:59 PM UTC 24
Finished Oct 12 02:25:12 PM UTC 24
Peak memory 227680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092555341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1092555341
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_rw.3625944186
Short name T529
Test name
Test status
Simulation time 159266366 ps
CPU time 2.97 seconds
Started Oct 12 02:25:01 PM UTC 24
Finished Oct 12 02:25:05 PM UTC 24
Peak memory 227564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625944186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3625944186
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.4068590340
Short name T528
Test name
Test status
Simulation time 35584035 ps
CPU time 1.14 seconds
Started Oct 12 02:25:00 PM UTC 24
Finished Oct 12 02:25:02 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068590340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.4068590340
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_upload.4111269229
Short name T305
Test name
Test status
Simulation time 218248211 ps
CPU time 3.1 seconds
Started Oct 12 02:25:06 PM UTC 24
Finished Oct 12 02:25:10 PM UTC 24
Peak memory 234620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111269229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.4111269229
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/19.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.1825012154
Short name T106
Test name
Test status
Simulation time 11413827 ps
CPU time 1.09 seconds
Started Oct 12 02:18:56 PM UTC 24
Finished Oct 12 02:18:58 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825012154 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1825012154
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.97623242
Short name T60
Test name
Test status
Simulation time 136270085 ps
CPU time 4.31 seconds
Started Oct 12 02:18:53 PM UTC 24
Finished Oct 12 02:18:59 PM UTC 24
Peak memory 234660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97623242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.97623242
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.2497709287
Short name T19
Test name
Test status
Simulation time 19312115 ps
CPU time 1.06 seconds
Started Oct 12 02:18:48 PM UTC 24
Finished Oct 12 02:18:51 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497709287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2497709287
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.3370080617
Short name T252
Test name
Test status
Simulation time 36121741700 ps
CPU time 172.93 seconds
Started Oct 12 02:18:53 PM UTC 24
Finished Oct 12 02:21:50 PM UTC 24
Peak memory 261744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370080617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3370080617
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.1043256189
Short name T262
Test name
Test status
Simulation time 179330300844 ps
CPU time 434.05 seconds
Started Oct 12 02:18:54 PM UTC 24
Finished Oct 12 02:26:14 PM UTC 24
Peak memory 277836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043256189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1043256189
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.485596142
Short name T53
Test name
Test status
Simulation time 2724162132 ps
CPU time 42.77 seconds
Started Oct 12 02:18:54 PM UTC 24
Finished Oct 12 02:19:39 PM UTC 24
Peak memory 263508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485596142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.485596142
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.2067677296
Short name T204
Test name
Test status
Simulation time 676166913 ps
CPU time 7.87 seconds
Started Oct 12 02:18:53 PM UTC 24
Finished Oct 12 02:19:03 PM UTC 24
Peak memory 234716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067677296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2067677296
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.895196706
Short name T400
Test name
Test status
Simulation time 81383607 ps
CPU time 1.14 seconds
Started Oct 12 02:18:53 PM UTC 24
Finished Oct 12 02:18:56 PM UTC 24
Peak memory 225168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895196706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.895196706
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.710684820
Short name T98
Test name
Test status
Simulation time 2630938695 ps
CPU time 10.05 seconds
Started Oct 12 02:18:52 PM UTC 24
Finished Oct 12 02:19:03 PM UTC 24
Peak memory 245028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710684820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.710684820
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.3740051950
Short name T24
Test name
Test status
Simulation time 50301811 ps
CPU time 2.27 seconds
Started Oct 12 02:18:52 PM UTC 24
Finished Oct 12 02:18:55 PM UTC 24
Peak memory 245152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740051950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3740051950
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.2617175865
Short name T63
Test name
Test status
Simulation time 592471071 ps
CPU time 5.08 seconds
Started Oct 12 02:18:52 PM UTC 24
Finished Oct 12 02:18:58 PM UTC 24
Peak memory 244972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617175865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.2617175865
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.960828658
Short name T56
Test name
Test status
Simulation time 2379074295 ps
CPU time 6.86 seconds
Started Oct 12 02:18:51 PM UTC 24
Finished Oct 12 02:18:58 PM UTC 24
Peak memory 234804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960828658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.960828658
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.3110675452
Short name T48
Test name
Test status
Simulation time 138999996 ps
CPU time 4.3 seconds
Started Oct 12 02:18:53 PM UTC 24
Finished Oct 12 02:19:00 PM UTC 24
Peak memory 233336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110675452 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.3110675452
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.1055467081
Short name T35
Test name
Test status
Simulation time 90141329 ps
CPU time 1.78 seconds
Started Oct 12 02:18:54 PM UTC 24
Finished Oct 12 02:18:57 PM UTC 24
Peak memory 258964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055467081 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1055467081
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.812275475
Short name T34
Test name
Test status
Simulation time 61908004 ps
CPU time 1.58 seconds
Started Oct 12 02:18:54 PM UTC 24
Finished Oct 12 02:18:57 PM UTC 24
Peak memory 216288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812275475 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.812275475
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.3020916944
Short name T95
Test name
Test status
Simulation time 3851939274 ps
CPU time 29.22 seconds
Started Oct 12 02:18:49 PM UTC 24
Finished Oct 12 02:19:20 PM UTC 24
Peak memory 231504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020916944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3020916944
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.3161382109
Short name T116
Test name
Test status
Simulation time 11560402 ps
CPU time 0.93 seconds
Started Oct 12 02:18:49 PM UTC 24
Finished Oct 12 02:18:51 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161382109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3161382109
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.3445285632
Short name T29
Test name
Test status
Simulation time 231682701 ps
CPU time 2 seconds
Started Oct 12 02:18:51 PM UTC 24
Finished Oct 12 02:18:54 PM UTC 24
Peak memory 226472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445285632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3445285632
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.565712832
Short name T32
Test name
Test status
Simulation time 41450721 ps
CPU time 1.11 seconds
Started Oct 12 02:18:51 PM UTC 24
Finished Oct 12 02:18:53 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565712832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.565712832
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/2.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/20.spi_device_alert_test.810020674
Short name T537
Test name
Test status
Simulation time 13940836 ps
CPU time 1.09 seconds
Started Oct 12 02:25:42 PM UTC 24
Finished Oct 12 02:25:44 PM UTC 24
Peak memory 213464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810020674 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.810020674
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/20.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/20.spi_device_cfg_cmd.3739480963
Short name T535
Test name
Test status
Simulation time 29023346 ps
CPU time 2.92 seconds
Started Oct 12 02:25:32 PM UTC 24
Finished Oct 12 02:25:36 PM UTC 24
Peak memory 234660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739480963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3739480963
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/20.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/20.spi_device_csb_read.3133776465
Short name T168
Test name
Test status
Simulation time 22823880 ps
CPU time 1.07 seconds
Started Oct 12 02:25:23 PM UTC 24
Finished Oct 12 02:25:25 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133776465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3133776465
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/20.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_all.322848671
Short name T559
Test name
Test status
Simulation time 3990458405 ps
CPU time 43.02 seconds
Started Oct 12 02:25:34 PM UTC 24
Finished Oct 12 02:26:19 PM UTC 24
Peak memory 263512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322848671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.322848671
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/20.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.1412735160
Short name T540
Test name
Test status
Simulation time 1787959158 ps
CPU time 13.63 seconds
Started Oct 12 02:25:35 PM UTC 24
Finished Oct 12 02:25:50 PM UTC 24
Peak memory 229444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412735160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1412735160
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.1031295210
Short name T306
Test name
Test status
Simulation time 1783223355 ps
CPU time 47.95 seconds
Started Oct 12 02:25:35 PM UTC 24
Finished Oct 12 02:26:25 PM UTC 24
Peak memory 265444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031295210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.1031295210
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode.3195110318
Short name T371
Test name
Test status
Simulation time 5762174082 ps
CPU time 30.14 seconds
Started Oct 12 02:25:33 PM UTC 24
Finished Oct 12 02:26:04 PM UTC 24
Peak memory 245020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195110318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3195110318
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/20.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.1920203773
Short name T331
Test name
Test status
Simulation time 2153475078 ps
CPU time 39.88 seconds
Started Oct 12 02:25:34 PM UTC 24
Finished Oct 12 02:26:15 PM UTC 24
Peak memory 251176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920203773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.1920203773
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/20.spi_device_intercept.2534637450
Short name T174
Test name
Test status
Simulation time 426802007 ps
CPU time 3.89 seconds
Started Oct 12 02:25:27 PM UTC 24
Finished Oct 12 02:25:32 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534637450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2534637450
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/20.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/20.spi_device_mailbox.2411619139
Short name T563
Test name
Test status
Simulation time 16934745562 ps
CPU time 52.06 seconds
Started Oct 12 02:25:27 PM UTC 24
Finished Oct 12 02:26:21 PM UTC 24
Peak memory 245028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411619139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2411619139
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/20.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.2270213395
Short name T173
Test name
Test status
Simulation time 108482214 ps
CPU time 3.11 seconds
Started Oct 12 02:25:26 PM UTC 24
Finished Oct 12 02:25:30 PM UTC 24
Peak memory 244644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270213395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.2270213395
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/20.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.1861277237
Short name T534
Test name
Test status
Simulation time 867048888 ps
CPU time 6.25 seconds
Started Oct 12 02:25:26 PM UTC 24
Finished Oct 12 02:25:34 PM UTC 24
Peak memory 244960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861277237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1861277237
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/20.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.949253127
Short name T536
Test name
Test status
Simulation time 382325417 ps
CPU time 6.04 seconds
Started Oct 12 02:25:34 PM UTC 24
Finished Oct 12 02:25:41 PM UTC 24
Peak memory 233440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949253127 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.949253127
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/20.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/20.spi_device_stress_all.243320718
Short name T880
Test name
Test status
Simulation time 503544285765 ps
CPU time 573.91 seconds
Started Oct 12 02:25:36 PM UTC 24
Finished Oct 12 02:35:17 PM UTC 24
Peak memory 284008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243320718 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.243320718
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/20.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_all.1970672711
Short name T175
Test name
Test status
Simulation time 8057194995 ps
CPU time 8.8 seconds
Started Oct 12 02:25:23 PM UTC 24
Finished Oct 12 02:25:33 PM UTC 24
Peak memory 227476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970672711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1970672711
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/20.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.3774077112
Short name T538
Test name
Test status
Simulation time 2232386885 ps
CPU time 20.84 seconds
Started Oct 12 02:25:23 PM UTC 24
Finished Oct 12 02:25:45 PM UTC 24
Peak memory 227368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774077112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3774077112
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/20.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_rw.1293118576
Short name T172
Test name
Test status
Simulation time 23974205 ps
CPU time 1.42 seconds
Started Oct 12 02:25:25 PM UTC 24
Finished Oct 12 02:25:28 PM UTC 24
Peak memory 216392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293118576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1293118576
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/20.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.2478888676
Short name T170
Test name
Test status
Simulation time 24936280 ps
CPU time 1.23 seconds
Started Oct 12 02:25:24 PM UTC 24
Finished Oct 12 02:25:26 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478888676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2478888676
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/20.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/20.spi_device_upload.2435437242
Short name T543
Test name
Test status
Simulation time 10676863404 ps
CPU time 26.18 seconds
Started Oct 12 02:25:29 PM UTC 24
Finished Oct 12 02:25:56 PM UTC 24
Peak memory 251232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435437242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2435437242
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/20.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_alert_test.2329012800
Short name T554
Test name
Test status
Simulation time 15503854 ps
CPU time 1.14 seconds
Started Oct 12 02:26:10 PM UTC 24
Finished Oct 12 02:26:12 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329012800 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.2329012800
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/21.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_cfg_cmd.3956628558
Short name T551
Test name
Test status
Simulation time 15823169706 ps
CPU time 7.77 seconds
Started Oct 12 02:26:00 PM UTC 24
Finished Oct 12 02:26:09 PM UTC 24
Peak memory 245028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956628558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3956628558
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/21.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_csb_read.307088406
Short name T539
Test name
Test status
Simulation time 30918575 ps
CPU time 1.16 seconds
Started Oct 12 02:25:45 PM UTC 24
Finished Oct 12 02:25:47 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307088406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.307088406
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/21.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_all.4056711024
Short name T652
Test name
Test status
Simulation time 16226935322 ps
CPU time 161.35 seconds
Started Oct 12 02:26:04 PM UTC 24
Finished Oct 12 02:28:48 PM UTC 24
Peak memory 265512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056711024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.4056711024
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/21.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.3896425064
Short name T580
Test name
Test status
Simulation time 5753937185 ps
CPU time 42.98 seconds
Started Oct 12 02:26:06 PM UTC 24
Finished Oct 12 02:26:50 PM UTC 24
Peak memory 229524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896425064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.3896425064
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode.3448927091
Short name T550
Test name
Test status
Simulation time 856442406 ps
CPU time 4.5 seconds
Started Oct 12 02:26:00 PM UTC 24
Finished Oct 12 02:26:06 PM UTC 24
Peak memory 245156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448927091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3448927091
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/21.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.3960410238
Short name T548
Test name
Test status
Simulation time 14088635 ps
CPU time 1.18 seconds
Started Oct 12 02:26:01 PM UTC 24
Finished Oct 12 02:26:03 PM UTC 24
Peak memory 225164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960410238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.3960410238
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_intercept.1898687265
Short name T547
Test name
Test status
Simulation time 29030054 ps
CPU time 2.86 seconds
Started Oct 12 02:25:57 PM UTC 24
Finished Oct 12 02:26:00 PM UTC 24
Peak memory 233240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898687265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1898687265
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/21.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_mailbox.1513135725
Short name T571
Test name
Test status
Simulation time 3170247329 ps
CPU time 32.93 seconds
Started Oct 12 02:25:59 PM UTC 24
Finished Oct 12 02:26:33 PM UTC 24
Peak memory 251176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513135725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1513135725
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/21.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.1050976577
Short name T275
Test name
Test status
Simulation time 752829128 ps
CPU time 6.01 seconds
Started Oct 12 02:25:57 PM UTC 24
Finished Oct 12 02:26:04 PM UTC 24
Peak memory 234804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050976577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.1050976577
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/21.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.38578772
Short name T575
Test name
Test status
Simulation time 40677052757 ps
CPU time 40.66 seconds
Started Oct 12 02:25:54 PM UTC 24
Finished Oct 12 02:26:36 PM UTC 24
Peak memory 244980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38578772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.38578772
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/21.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.1235888426
Short name T552
Test name
Test status
Simulation time 381115036 ps
CPU time 5.38 seconds
Started Oct 12 02:26:04 PM UTC 24
Finished Oct 12 02:26:11 PM UTC 24
Peak memory 229280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235888426 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.1235888426
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/21.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_stress_all.930839431
Short name T350
Test name
Test status
Simulation time 48666299806 ps
CPU time 367.28 seconds
Started Oct 12 02:26:07 PM UTC 24
Finished Oct 12 02:32:19 PM UTC 24
Peak memory 294500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930839431 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.930839431
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/21.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_all.743957794
Short name T585
Test name
Test status
Simulation time 10703228303 ps
CPU time 64.71 seconds
Started Oct 12 02:25:48 PM UTC 24
Finished Oct 12 02:26:54 PM UTC 24
Peak memory 227372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743957794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.743957794
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/21.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.2150803923
Short name T549
Test name
Test status
Simulation time 2681895532 ps
CPU time 16.46 seconds
Started Oct 12 02:25:46 PM UTC 24
Finished Oct 12 02:26:04 PM UTC 24
Peak memory 227324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150803923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2150803923
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/21.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_rw.2673187702
Short name T544
Test name
Test status
Simulation time 470443875 ps
CPU time 3.08 seconds
Started Oct 12 02:25:54 PM UTC 24
Finished Oct 12 02:25:58 PM UTC 24
Peak memory 227240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673187702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2673187702
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/21.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.3163245916
Short name T541
Test name
Test status
Simulation time 127504837 ps
CPU time 1.16 seconds
Started Oct 12 02:25:51 PM UTC 24
Finished Oct 12 02:25:53 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163245916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3163245916
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/21.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_upload.4271480611
Short name T556
Test name
Test status
Simulation time 7818469755 ps
CPU time 15 seconds
Started Oct 12 02:26:00 PM UTC 24
Finished Oct 12 02:26:16 PM UTC 24
Peak memory 251160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271480611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4271480611
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/21.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/22.spi_device_alert_test.2472643235
Short name T569
Test name
Test status
Simulation time 15289592 ps
CPU time 1.01 seconds
Started Oct 12 02:26:28 PM UTC 24
Finished Oct 12 02:26:31 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472643235 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.2472643235
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/22.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/22.spi_device_cfg_cmd.1095387812
Short name T568
Test name
Test status
Simulation time 2159934343 ps
CPU time 9.69 seconds
Started Oct 12 02:26:20 PM UTC 24
Finished Oct 12 02:26:31 PM UTC 24
Peak memory 234780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095387812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1095387812
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/22.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/22.spi_device_csb_read.1596278963
Short name T555
Test name
Test status
Simulation time 40478472 ps
CPU time 0.93 seconds
Started Oct 12 02:26:12 PM UTC 24
Finished Oct 12 02:26:14 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596278963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1596278963
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/22.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_all.3182446162
Short name T613
Test name
Test status
Simulation time 6628680937 ps
CPU time 70.99 seconds
Started Oct 12 02:26:22 PM UTC 24
Finished Oct 12 02:27:34 PM UTC 24
Peak memory 261476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182446162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3182446162
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/22.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.277105094
Short name T177
Test name
Test status
Simulation time 42166087458 ps
CPU time 433.78 seconds
Started Oct 12 02:26:26 PM UTC 24
Finished Oct 12 02:33:46 PM UTC 24
Peak memory 278112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277105094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.277105094
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/22.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.1560768944
Short name T792
Test name
Test status
Simulation time 31049598760 ps
CPU time 354.14 seconds
Started Oct 12 02:26:27 PM UTC 24
Finished Oct 12 02:32:26 PM UTC 24
Peak memory 261784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560768944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.1560768944
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode.2587616487
Short name T567
Test name
Test status
Simulation time 134228116 ps
CPU time 6.05 seconds
Started Oct 12 02:26:22 PM UTC 24
Finished Oct 12 02:26:29 PM UTC 24
Peak memory 234612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587616487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2587616487
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/22.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.2826897941
Short name T259
Test name
Test status
Simulation time 65899584723 ps
CPU time 140.81 seconds
Started Oct 12 02:26:22 PM UTC 24
Finished Oct 12 02:28:45 PM UTC 24
Peak memory 265512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826897941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.2826897941
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/22.spi_device_intercept.3468447726
Short name T564
Test name
Test status
Simulation time 141374562 ps
CPU time 7.09 seconds
Started Oct 12 02:26:18 PM UTC 24
Finished Oct 12 02:26:26 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468447726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3468447726
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/22.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/22.spi_device_mailbox.2291703033
Short name T583
Test name
Test status
Simulation time 2131575364 ps
CPU time 30.73 seconds
Started Oct 12 02:26:19 PM UTC 24
Finished Oct 12 02:26:51 PM UTC 24
Peak memory 251104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291703033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2291703033
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/22.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.1499352852
Short name T243
Test name
Test status
Simulation time 545104535 ps
CPU time 11.5 seconds
Started Oct 12 02:26:17 PM UTC 24
Finished Oct 12 02:26:29 PM UTC 24
Peak memory 244964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499352852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.1499352852
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/22.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.339399687
Short name T562
Test name
Test status
Simulation time 113943625 ps
CPU time 2.85 seconds
Started Oct 12 02:26:17 PM UTC 24
Finished Oct 12 02:26:21 PM UTC 24
Peak memory 233204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339399687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.339399687
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/22.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.1696465126
Short name T565
Test name
Test status
Simulation time 507321959 ps
CPU time 5.14 seconds
Started Oct 12 02:26:22 PM UTC 24
Finished Oct 12 02:26:28 PM UTC 24
Peak memory 231072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696465126 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.1696465126
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/22.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.4149337850
Short name T658
Test name
Test status
Simulation time 24801599680 ps
CPU time 146.57 seconds
Started Oct 12 02:26:27 PM UTC 24
Finished Oct 12 02:28:57 PM UTC 24
Peak memory 267680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149337850 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.4149337850
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/22.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_all.1483380224
Short name T572
Test name
Test status
Simulation time 7864669791 ps
CPU time 19.19 seconds
Started Oct 12 02:26:13 PM UTC 24
Finished Oct 12 02:26:33 PM UTC 24
Peak memory 227416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483380224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1483380224
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/22.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.898383351
Short name T581
Test name
Test status
Simulation time 32562061131 ps
CPU time 35.74 seconds
Started Oct 12 02:26:13 PM UTC 24
Finished Oct 12 02:26:50 PM UTC 24
Peak memory 227672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898383351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.898383351
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/22.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_rw.822599507
Short name T560
Test name
Test status
Simulation time 144205083 ps
CPU time 3.2 seconds
Started Oct 12 02:26:15 PM UTC 24
Finished Oct 12 02:26:20 PM UTC 24
Peak memory 227564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822599507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.822599507
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/22.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.2297065028
Short name T557
Test name
Test status
Simulation time 25713076 ps
CPU time 1.29 seconds
Started Oct 12 02:26:14 PM UTC 24
Finished Oct 12 02:26:17 PM UTC 24
Peak memory 216516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297065028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2297065028
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/22.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/22.spi_device_upload.3557938586
Short name T566
Test name
Test status
Simulation time 2372444036 ps
CPU time 8.19 seconds
Started Oct 12 02:26:19 PM UTC 24
Finished Oct 12 02:26:28 PM UTC 24
Peak memory 245028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557938586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3557938586
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/22.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/23.spi_device_alert_test.2875463338
Short name T586
Test name
Test status
Simulation time 12420592 ps
CPU time 1.11 seconds
Started Oct 12 02:26:53 PM UTC 24
Finished Oct 12 02:26:55 PM UTC 24
Peak memory 213464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875463338 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.2875463338
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/23.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/23.spi_device_cfg_cmd.2742468812
Short name T579
Test name
Test status
Simulation time 121960162 ps
CPU time 3.48 seconds
Started Oct 12 02:26:37 PM UTC 24
Finished Oct 12 02:26:42 PM UTC 24
Peak memory 234716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742468812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2742468812
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/23.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/23.spi_device_csb_read.1139593693
Short name T570
Test name
Test status
Simulation time 66846623 ps
CPU time 1.08 seconds
Started Oct 12 02:26:30 PM UTC 24
Finished Oct 12 02:26:32 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139593693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1139593693
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/23.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_all.4187281703
Short name T654
Test name
Test status
Simulation time 29488537501 ps
CPU time 126.92 seconds
Started Oct 12 02:26:43 PM UTC 24
Finished Oct 12 02:28:52 PM UTC 24
Peak memory 261316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187281703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.4187281703
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/23.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.3686584785
Short name T782
Test name
Test status
Simulation time 134066423826 ps
CPU time 320.02 seconds
Started Oct 12 02:26:51 PM UTC 24
Finished Oct 12 02:32:15 PM UTC 24
Peak memory 261712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686584785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3686584785
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.3463988505
Short name T592
Test name
Test status
Simulation time 4688233196 ps
CPU time 6.62 seconds
Started Oct 12 02:26:51 PM UTC 24
Finished Oct 12 02:26:59 PM UTC 24
Peak memory 233748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463988505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.3463988505
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode.3389057210
Short name T375
Test name
Test status
Simulation time 3883223865 ps
CPU time 53.69 seconds
Started Oct 12 02:26:41 PM UTC 24
Finished Oct 12 02:27:37 PM UTC 24
Peak memory 261672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389057210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3389057210
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/23.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.163124183
Short name T605
Test name
Test status
Simulation time 2456997935 ps
CPU time 35.34 seconds
Started Oct 12 02:26:41 PM UTC 24
Finished Oct 12 02:27:18 PM UTC 24
Peak memory 251168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163124183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.163124183
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/23.spi_device_intercept.2949599237
Short name T588
Test name
Test status
Simulation time 3143341064 ps
CPU time 19.36 seconds
Started Oct 12 02:26:35 PM UTC 24
Finished Oct 12 02:26:55 PM UTC 24
Peak memory 229592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949599237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2949599237
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/23.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/23.spi_device_mailbox.916785607
Short name T584
Test name
Test status
Simulation time 2910790386 ps
CPU time 16.38 seconds
Started Oct 12 02:26:36 PM UTC 24
Finished Oct 12 02:26:53 PM UTC 24
Peak memory 247076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916785607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.916785607
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/23.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.3275496014
Short name T576
Test name
Test status
Simulation time 99492405 ps
CPU time 4.74 seconds
Started Oct 12 02:26:35 PM UTC 24
Finished Oct 12 02:26:40 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275496014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.3275496014
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/23.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.4046487223
Short name T348
Test name
Test status
Simulation time 20639945424 ps
CPU time 18.06 seconds
Started Oct 12 02:26:33 PM UTC 24
Finished Oct 12 02:26:53 PM UTC 24
Peak memory 251488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046487223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4046487223
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/23.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.1987663756
Short name T582
Test name
Test status
Simulation time 231776190 ps
CPU time 6.67 seconds
Started Oct 12 02:26:43 PM UTC 24
Finished Oct 12 02:26:51 PM UTC 24
Peak memory 231256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987663756 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.1987663756
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/23.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.3882873289
Short name T1017
Test name
Test status
Simulation time 87875541417 ps
CPU time 765.01 seconds
Started Oct 12 02:26:52 PM UTC 24
Finished Oct 12 02:39:47 PM UTC 24
Peak memory 283772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882873289 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.3882873289
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/23.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_all.1507112119
Short name T590
Test name
Test status
Simulation time 2117638864 ps
CPU time 24.59 seconds
Started Oct 12 02:26:31 PM UTC 24
Finished Oct 12 02:26:57 PM UTC 24
Peak memory 227288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507112119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1507112119
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/23.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.2300746292
Short name T578
Test name
Test status
Simulation time 1911828383 ps
CPU time 9.62 seconds
Started Oct 12 02:26:30 PM UTC 24
Finished Oct 12 02:26:41 PM UTC 24
Peak memory 227288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300746292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2300746292
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/23.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_rw.2703238327
Short name T574
Test name
Test status
Simulation time 88476139 ps
CPU time 2.13 seconds
Started Oct 12 02:26:32 PM UTC 24
Finished Oct 12 02:26:35 PM UTC 24
Peak memory 216992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703238327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2703238327
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/23.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.2362628285
Short name T573
Test name
Test status
Simulation time 79343784 ps
CPU time 1.26 seconds
Started Oct 12 02:26:32 PM UTC 24
Finished Oct 12 02:26:35 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362628285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2362628285
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/23.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/23.spi_device_upload.1473099195
Short name T577
Test name
Test status
Simulation time 393532038 ps
CPU time 3.63 seconds
Started Oct 12 02:26:36 PM UTC 24
Finished Oct 12 02:26:41 PM UTC 24
Peak memory 234652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473099195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1473099195
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/23.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_alert_test.666887368
Short name T600
Test name
Test status
Simulation time 68930309 ps
CPU time 1.09 seconds
Started Oct 12 02:27:10 PM UTC 24
Finished Oct 12 02:27:12 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666887368 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.666887368
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/24.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_cfg_cmd.3178624290
Short name T595
Test name
Test status
Simulation time 73502432 ps
CPU time 2.96 seconds
Started Oct 12 02:27:00 PM UTC 24
Finished Oct 12 02:27:04 PM UTC 24
Peak memory 245108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178624290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3178624290
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/24.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_csb_read.660709376
Short name T587
Test name
Test status
Simulation time 14458392 ps
CPU time 1.13 seconds
Started Oct 12 02:26:53 PM UTC 24
Finished Oct 12 02:26:55 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660709376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.660709376
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/24.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.4053064676
Short name T670
Test name
Test status
Simulation time 50960651923 ps
CPU time 124.51 seconds
Started Oct 12 02:27:06 PM UTC 24
Finished Oct 12 02:29:13 PM UTC 24
Peak memory 267584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053064676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.4053064676
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.80740077
Short name T615
Test name
Test status
Simulation time 6634441749 ps
CPU time 32.19 seconds
Started Oct 12 02:27:06 PM UTC 24
Finished Oct 12 02:27:39 PM UTC 24
Peak memory 261780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80740077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.80740077
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.1287802485
Short name T330
Test name
Test status
Simulation time 107016695901 ps
CPU time 229.31 seconds
Started Oct 12 02:27:03 PM UTC 24
Finished Oct 12 02:30:56 PM UTC 24
Peak memory 277792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287802485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.1287802485
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_intercept.613497857
Short name T596
Test name
Test status
Simulation time 148973824 ps
CPU time 4.98 seconds
Started Oct 12 02:26:59 PM UTC 24
Finished Oct 12 02:27:05 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613497857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.613497857
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/24.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_mailbox.2783761114
Short name T594
Test name
Test status
Simulation time 116523787 ps
CPU time 3.24 seconds
Started Oct 12 02:26:59 PM UTC 24
Finished Oct 12 02:27:03 PM UTC 24
Peak memory 244580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783761114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2783761114
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/24.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.3976540523
Short name T329
Test name
Test status
Simulation time 741203849 ps
CPU time 5.2 seconds
Started Oct 12 02:26:56 PM UTC 24
Finished Oct 12 02:27:03 PM UTC 24
Peak memory 234856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976540523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.3976540523
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/24.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.2680279745
Short name T609
Test name
Test status
Simulation time 5185004812 ps
CPU time 31.68 seconds
Started Oct 12 02:26:55 PM UTC 24
Finished Oct 12 02:27:28 PM UTC 24
Peak memory 234736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680279745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2680279745
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/24.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.3247287435
Short name T599
Test name
Test status
Simulation time 521483413 ps
CPU time 5.78 seconds
Started Oct 12 02:27:04 PM UTC 24
Finished Oct 12 02:27:10 PM UTC 24
Peak memory 233224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247287435 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.3247287435
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/24.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_stress_all.2608357743
Short name T597
Test name
Test status
Simulation time 73673204 ps
CPU time 1.51 seconds
Started Oct 12 02:27:07 PM UTC 24
Finished Oct 12 02:27:10 PM UTC 24
Peak memory 216344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608357743 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.2608357743
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/24.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_all.3707789330
Short name T612
Test name
Test status
Simulation time 4852706849 ps
CPU time 38.82 seconds
Started Oct 12 02:26:54 PM UTC 24
Finished Oct 12 02:27:34 PM UTC 24
Peak memory 227416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707789330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3707789330
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/24.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.1046548472
Short name T598
Test name
Test status
Simulation time 762594619 ps
CPU time 11.62 seconds
Started Oct 12 02:26:54 PM UTC 24
Finished Oct 12 02:27:07 PM UTC 24
Peak memory 227280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046548472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1046548472
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/24.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_rw.564709771
Short name T589
Test name
Test status
Simulation time 10428193 ps
CPU time 1.07 seconds
Started Oct 12 02:26:55 PM UTC 24
Finished Oct 12 02:26:57 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564709771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.564709771
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/24.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.1398043240
Short name T591
Test name
Test status
Simulation time 180430564 ps
CPU time 1.43 seconds
Started Oct 12 02:26:55 PM UTC 24
Finished Oct 12 02:26:58 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398043240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1398043240
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/24.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_upload.2018646822
Short name T347
Test name
Test status
Simulation time 1449489618 ps
CPU time 5.32 seconds
Started Oct 12 02:26:59 PM UTC 24
Finished Oct 12 02:27:05 PM UTC 24
Peak memory 234668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018646822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2018646822
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/24.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/25.spi_device_alert_test.1673018263
Short name T614
Test name
Test status
Simulation time 13378653 ps
CPU time 1.12 seconds
Started Oct 12 02:27:35 PM UTC 24
Finished Oct 12 02:27:37 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673018263 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.1673018263
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/25.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/25.spi_device_cfg_cmd.4131166961
Short name T610
Test name
Test status
Simulation time 58213591 ps
CPU time 4.06 seconds
Started Oct 12 02:27:24 PM UTC 24
Finished Oct 12 02:27:29 PM UTC 24
Peak memory 234932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131166961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.4131166961
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/25.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/25.spi_device_csb_read.1427919854
Short name T601
Test name
Test status
Simulation time 59063519 ps
CPU time 1.15 seconds
Started Oct 12 02:27:11 PM UTC 24
Finished Oct 12 02:27:14 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427919854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1427919854
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/25.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_all.2532185653
Short name T338
Test name
Test status
Simulation time 31480235585 ps
CPU time 108.97 seconds
Started Oct 12 02:27:30 PM UTC 24
Finished Oct 12 02:29:21 PM UTC 24
Peak memory 261412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532185653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2532185653
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/25.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.3195095011
Short name T238
Test name
Test status
Simulation time 15464401519 ps
CPU time 82.34 seconds
Started Oct 12 02:27:30 PM UTC 24
Finished Oct 12 02:28:54 PM UTC 24
Peak memory 263564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195095011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3195095011
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.4136328919
Short name T639
Test name
Test status
Simulation time 5741206897 ps
CPU time 45.7 seconds
Started Oct 12 02:27:32 PM UTC 24
Finished Oct 12 02:28:19 PM UTC 24
Peak memory 229648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136328919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.4136328919
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode.1676394703
Short name T611
Test name
Test status
Simulation time 38965395 ps
CPU time 3.59 seconds
Started Oct 12 02:27:26 PM UTC 24
Finished Oct 12 02:27:31 PM UTC 24
Peak memory 244852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676394703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1676394703
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/25.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.1933269137
Short name T628
Test name
Test status
Simulation time 884627492 ps
CPU time 32.11 seconds
Started Oct 12 02:27:28 PM UTC 24
Finished Oct 12 02:28:02 PM UTC 24
Peak memory 249000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933269137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.1933269137
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/25.spi_device_intercept.4207694694
Short name T608
Test name
Test status
Simulation time 865315186 ps
CPU time 6.42 seconds
Started Oct 12 02:27:20 PM UTC 24
Finished Oct 12 02:27:27 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207694694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.4207694694
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/25.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/25.spi_device_mailbox.3425136429
Short name T624
Test name
Test status
Simulation time 12497702828 ps
CPU time 27.86 seconds
Started Oct 12 02:27:21 PM UTC 24
Finished Oct 12 02:27:50 PM UTC 24
Peak memory 244984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425136429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3425136429
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/25.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.39878701
Short name T620
Test name
Test status
Simulation time 24593225148 ps
CPU time 24.77 seconds
Started Oct 12 02:27:19 PM UTC 24
Finished Oct 12 02:27:46 PM UTC 24
Peak memory 249440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39878701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.39878701
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/25.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.409284674
Short name T629
Test name
Test status
Simulation time 4675409369 ps
CPU time 43.18 seconds
Started Oct 12 02:27:18 PM UTC 24
Finished Oct 12 02:28:03 PM UTC 24
Peak memory 251136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409284674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.409284674
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/25.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.1323571837
Short name T623
Test name
Test status
Simulation time 1704991198 ps
CPU time 18.16 seconds
Started Oct 12 02:27:30 PM UTC 24
Finished Oct 12 02:27:49 PM UTC 24
Peak memory 231328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323571837 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.1323571837
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/25.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_all.390951310
Short name T607
Test name
Test status
Simulation time 565343749 ps
CPU time 10.45 seconds
Started Oct 12 02:27:14 PM UTC 24
Finished Oct 12 02:27:25 PM UTC 24
Peak memory 231596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390951310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.390951310
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/25.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.1540789338
Short name T606
Test name
Test status
Simulation time 1498265049 ps
CPU time 6.59 seconds
Started Oct 12 02:27:13 PM UTC 24
Finished Oct 12 02:27:20 PM UTC 24
Peak memory 227292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540789338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1540789338
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/25.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_rw.1333630143
Short name T604
Test name
Test status
Simulation time 34014228 ps
CPU time 1.06 seconds
Started Oct 12 02:27:16 PM UTC 24
Finished Oct 12 02:27:18 PM UTC 24
Peak memory 213472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333630143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1333630143
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/25.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.2486559338
Short name T603
Test name
Test status
Simulation time 143942158 ps
CPU time 1.44 seconds
Started Oct 12 02:27:15 PM UTC 24
Finished Oct 12 02:27:17 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486559338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2486559338
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/25.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/25.spi_device_upload.2824274752
Short name T619
Test name
Test status
Simulation time 17019733865 ps
CPU time 21.11 seconds
Started Oct 12 02:27:22 PM UTC 24
Finished Oct 12 02:27:44 PM UTC 24
Peak memory 235124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824274752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2824274752
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/25.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_alert_test.3547710131
Short name T630
Test name
Test status
Simulation time 11764906 ps
CPU time 1.1 seconds
Started Oct 12 02:28:03 PM UTC 24
Finished Oct 12 02:28:06 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547710131 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.3547710131
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/26.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_csb_read.1866862450
Short name T616
Test name
Test status
Simulation time 14670702 ps
CPU time 1.15 seconds
Started Oct 12 02:27:38 PM UTC 24
Finished Oct 12 02:27:40 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866862450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1866862450
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/26.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.1120824058
Short name T723
Test name
Test status
Simulation time 36334231641 ps
CPU time 144.15 seconds
Started Oct 12 02:27:57 PM UTC 24
Finished Oct 12 02:30:23 PM UTC 24
Peak memory 261408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120824058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1120824058
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/26.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.3545527708
Short name T663
Test name
Test status
Simulation time 2489255386 ps
CPU time 61.86 seconds
Started Oct 12 02:27:57 PM UTC 24
Finished Oct 12 02:29:00 PM UTC 24
Peak memory 265884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545527708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3545527708
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.1853609316
Short name T180
Test name
Test status
Simulation time 82469758626 ps
CPU time 556.84 seconds
Started Oct 12 02:28:00 PM UTC 24
Finished Oct 12 02:37:24 PM UTC 24
Peak memory 263500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853609316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.1853609316
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode.1071982167
Short name T373
Test name
Test status
Simulation time 2788325088 ps
CPU time 12.79 seconds
Started Oct 12 02:27:51 PM UTC 24
Finished Oct 12 02:28:05 PM UTC 24
Peak memory 245040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071982167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1071982167
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/26.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.1657840960
Short name T626
Test name
Test status
Simulation time 37521397 ps
CPU time 1.11 seconds
Started Oct 12 02:27:51 PM UTC 24
Finished Oct 12 02:27:53 PM UTC 24
Peak memory 225164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657840960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.1657840960
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_intercept.1295138905
Short name T625
Test name
Test status
Simulation time 200405055 ps
CPU time 3.1 seconds
Started Oct 12 02:27:47 PM UTC 24
Finished Oct 12 02:27:51 PM UTC 24
Peak memory 234960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295138905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1295138905
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/26.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_mailbox.1069016102
Short name T633
Test name
Test status
Simulation time 1859682155 ps
CPU time 16.47 seconds
Started Oct 12 02:27:49 PM UTC 24
Finished Oct 12 02:28:06 PM UTC 24
Peak memory 245216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069016102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1069016102
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/26.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.365365952
Short name T339
Test name
Test status
Simulation time 835110046 ps
CPU time 8.91 seconds
Started Oct 12 02:27:45 PM UTC 24
Finished Oct 12 02:27:55 PM UTC 24
Peak memory 234872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365365952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.365365952
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/26.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.4087721029
Short name T349
Test name
Test status
Simulation time 3946164563 ps
CPU time 31.38 seconds
Started Oct 12 02:27:44 PM UTC 24
Finished Oct 12 02:28:17 PM UTC 24
Peak memory 263460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087721029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.4087721029
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/26.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.3091705715
Short name T634
Test name
Test status
Simulation time 951317016 ps
CPU time 13.6 seconds
Started Oct 12 02:27:55 PM UTC 24
Finished Oct 12 02:28:09 PM UTC 24
Peak memory 233164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091705715 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.3091705715
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/26.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.419491726
Short name T202
Test name
Test status
Simulation time 36605067357 ps
CPU time 78.26 seconds
Started Oct 12 02:28:02 PM UTC 24
Finished Oct 12 02:29:22 PM UTC 24
Peak memory 265832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419491726 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.419491726
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/26.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_all.1941720620
Short name T617
Test name
Test status
Simulation time 15638550 ps
CPU time 1.09 seconds
Started Oct 12 02:27:41 PM UTC 24
Finished Oct 12 02:27:43 PM UTC 24
Peak memory 213404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941720620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1941720620
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/26.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.4093661423
Short name T622
Test name
Test status
Simulation time 18191737884 ps
CPU time 8.93 seconds
Started Oct 12 02:27:39 PM UTC 24
Finished Oct 12 02:27:49 PM UTC 24
Peak memory 227424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093661423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.4093661423
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/26.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_rw.2437941761
Short name T621
Test name
Test status
Simulation time 244465891 ps
CPU time 2.67 seconds
Started Oct 12 02:27:44 PM UTC 24
Finished Oct 12 02:27:48 PM UTC 24
Peak memory 227236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437941761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2437941761
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/26.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.431971375
Short name T618
Test name
Test status
Simulation time 72740218 ps
CPU time 1.34 seconds
Started Oct 12 02:27:41 PM UTC 24
Finished Oct 12 02:27:43 PM UTC 24
Peak memory 216340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431971375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.431971375
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/26.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_upload.687530804
Short name T632
Test name
Test status
Simulation time 4515008050 ps
CPU time 14.47 seconds
Started Oct 12 02:27:50 PM UTC 24
Finished Oct 12 02:28:06 PM UTC 24
Peak memory 245096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687530804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.687530804
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/26.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/27.spi_device_alert_test.2512116395
Short name T642
Test name
Test status
Simulation time 25855178 ps
CPU time 1.1 seconds
Started Oct 12 02:28:28 PM UTC 24
Finished Oct 12 02:28:31 PM UTC 24
Peak memory 213660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512116395 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.2512116395
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/27.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/27.spi_device_cfg_cmd.147952385
Short name T641
Test name
Test status
Simulation time 711676313 ps
CPU time 5.57 seconds
Started Oct 12 02:28:18 PM UTC 24
Finished Oct 12 02:28:25 PM UTC 24
Peak memory 244896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147952385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.147952385
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/27.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/27.spi_device_csb_read.2097929105
Short name T631
Test name
Test status
Simulation time 24363984 ps
CPU time 1.14 seconds
Started Oct 12 02:28:03 PM UTC 24
Finished Oct 12 02:28:06 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097929105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2097929105
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/27.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.1540822017
Short name T668
Test name
Test status
Simulation time 3043805992 ps
CPU time 41.7 seconds
Started Oct 12 02:28:25 PM UTC 24
Finished Oct 12 02:29:08 PM UTC 24
Peak memory 261472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540822017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1540822017
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/27.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.1946609490
Short name T717
Test name
Test status
Simulation time 13880935753 ps
CPU time 103.45 seconds
Started Oct 12 02:28:26 PM UTC 24
Finished Oct 12 02:30:12 PM UTC 24
Peak memory 245284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946609490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1946609490
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.4292630889
Short name T248
Test name
Test status
Simulation time 27932358256 ps
CPU time 120.07 seconds
Started Oct 12 02:28:26 PM UTC 24
Finished Oct 12 02:30:29 PM UTC 24
Peak memory 263580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292630889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.4292630889
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode.3896431046
Short name T382
Test name
Test status
Simulation time 1415073004 ps
CPU time 30.81 seconds
Started Oct 12 02:28:18 PM UTC 24
Finished Oct 12 02:28:51 PM UTC 24
Peak memory 249000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896431046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3896431046
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/27.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.259724884
Short name T358
Test name
Test status
Simulation time 9642025256 ps
CPU time 86.27 seconds
Started Oct 12 02:28:20 PM UTC 24
Finished Oct 12 02:29:49 PM UTC 24
Peak memory 251176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259724884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.259724884
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/27.spi_device_intercept.1142666007
Short name T244
Test name
Test status
Simulation time 2300973641 ps
CPU time 15.23 seconds
Started Oct 12 02:28:11 PM UTC 24
Finished Oct 12 02:28:27 PM UTC 24
Peak memory 245028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142666007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1142666007
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/27.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/27.spi_device_mailbox.2728193228
Short name T260
Test name
Test status
Simulation time 573903296 ps
CPU time 15.32 seconds
Started Oct 12 02:28:13 PM UTC 24
Finished Oct 12 02:28:30 PM UTC 24
Peak memory 249000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728193228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2728193228
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/27.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.278262815
Short name T304
Test name
Test status
Simulation time 5944682630 ps
CPU time 13.49 seconds
Started Oct 12 02:28:08 PM UTC 24
Finished Oct 12 02:28:23 PM UTC 24
Peak memory 247400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278262815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.278262815
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/27.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.2946785007
Short name T647
Test name
Test status
Simulation time 803665451 ps
CPU time 10.78 seconds
Started Oct 12 02:28:23 PM UTC 24
Finished Oct 12 02:28:36 PM UTC 24
Peak memory 233316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946785007 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.2946785007
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/27.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.1213085237
Short name T643
Test name
Test status
Simulation time 34498598 ps
CPU time 1.43 seconds
Started Oct 12 02:28:28 PM UTC 24
Finished Oct 12 02:28:31 PM UTC 24
Peak memory 215888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213085237 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.1213085237
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/27.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_all.1380299051
Short name T640
Test name
Test status
Simulation time 7446858138 ps
CPU time 14.97 seconds
Started Oct 12 02:28:07 PM UTC 24
Finished Oct 12 02:28:23 PM UTC 24
Peak memory 227688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380299051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1380299051
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/27.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.288552463
Short name T636
Test name
Test status
Simulation time 358684357 ps
CPU time 3.67 seconds
Started Oct 12 02:28:07 PM UTC 24
Finished Oct 12 02:28:12 PM UTC 24
Peak memory 227028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288552463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.288552463
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/27.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_rw.893567905
Short name T637
Test name
Test status
Simulation time 98844450 ps
CPU time 4.17 seconds
Started Oct 12 02:28:07 PM UTC 24
Finished Oct 12 02:28:12 PM UTC 24
Peak memory 227280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893567905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.893567905
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/27.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.903485188
Short name T635
Test name
Test status
Simulation time 47792714 ps
CPU time 1.32 seconds
Started Oct 12 02:28:07 PM UTC 24
Finished Oct 12 02:28:09 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903485188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.903485188
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/27.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/27.spi_device_upload.3710206930
Short name T638
Test name
Test status
Simulation time 417128118 ps
CPU time 2.78 seconds
Started Oct 12 02:28:13 PM UTC 24
Finished Oct 12 02:28:17 PM UTC 24
Peak memory 234608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710206930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3710206930
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/27.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/28.spi_device_alert_test.3309849053
Short name T657
Test name
Test status
Simulation time 13670288 ps
CPU time 1.11 seconds
Started Oct 12 02:28:55 PM UTC 24
Finished Oct 12 02:28:57 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309849053 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.3309849053
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/28.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/28.spi_device_cfg_cmd.4237666899
Short name T656
Test name
Test status
Simulation time 571002535 ps
CPU time 9.3 seconds
Started Oct 12 02:28:45 PM UTC 24
Finished Oct 12 02:28:55 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237666899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.4237666899
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/28.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/28.spi_device_csb_read.3845010359
Short name T644
Test name
Test status
Simulation time 130488972 ps
CPU time 1.23 seconds
Started Oct 12 02:28:30 PM UTC 24
Finished Oct 12 02:28:33 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845010359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3845010359
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/28.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_all.1331187620
Short name T264
Test name
Test status
Simulation time 5146118328 ps
CPU time 47.88 seconds
Started Oct 12 02:28:51 PM UTC 24
Finished Oct 12 02:29:40 PM UTC 24
Peak memory 263724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331187620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1331187620
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/28.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.3651298251
Short name T709
Test name
Test status
Simulation time 17451003036 ps
CPU time 71.33 seconds
Started Oct 12 02:28:52 PM UTC 24
Finished Oct 12 02:30:05 PM UTC 24
Peak memory 261544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651298251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3651298251
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/28.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.3646093442
Short name T701
Test name
Test status
Simulation time 3722975363 ps
CPU time 59.29 seconds
Started Oct 12 02:28:53 PM UTC 24
Finished Oct 12 02:29:54 PM UTC 24
Peak memory 261468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646093442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.3646093442
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode.1362452702
Short name T655
Test name
Test status
Simulation time 158350737 ps
CPU time 4.87 seconds
Started Oct 12 02:28:46 PM UTC 24
Finished Oct 12 02:28:52 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362452702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1362452702
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/28.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.2539239438
Short name T667
Test name
Test status
Simulation time 3211400609 ps
CPU time 18.74 seconds
Started Oct 12 02:28:46 PM UTC 24
Finished Oct 12 02:29:06 PM UTC 24
Peak memory 251176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539239438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.2539239438
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/28.spi_device_intercept.3612925732
Short name T651
Test name
Test status
Simulation time 799217820 ps
CPU time 7.23 seconds
Started Oct 12 02:28:38 PM UTC 24
Finished Oct 12 02:28:46 PM UTC 24
Peak memory 234612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612925732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3612925732
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/28.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/28.spi_device_mailbox.634097406
Short name T675
Test name
Test status
Simulation time 57052691740 ps
CPU time 36.3 seconds
Started Oct 12 02:28:41 PM UTC 24
Finished Oct 12 02:29:18 PM UTC 24
Peak memory 235004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634097406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.634097406
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/28.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.3852410708
Short name T649
Test name
Test status
Simulation time 58872943 ps
CPU time 2.82 seconds
Started Oct 12 02:28:36 PM UTC 24
Finished Oct 12 02:28:40 PM UTC 24
Peak memory 234036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852410708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.3852410708
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/28.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.1190796095
Short name T665
Test name
Test status
Simulation time 3910610852 ps
CPU time 24.98 seconds
Started Oct 12 02:28:35 PM UTC 24
Finished Oct 12 02:29:01 PM UTC 24
Peak memory 247092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190796095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1190796095
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/28.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.2540891229
Short name T669
Test name
Test status
Simulation time 18053103702 ps
CPU time 21 seconds
Started Oct 12 02:28:50 PM UTC 24
Finished Oct 12 02:29:12 PM UTC 24
Peak memory 233352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540891229 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.2540891229
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/28.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.3814904663
Short name T201
Test name
Test status
Simulation time 118905487 ps
CPU time 1.5 seconds
Started Oct 12 02:28:53 PM UTC 24
Finished Oct 12 02:28:56 PM UTC 24
Peak memory 216344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814904663 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.3814904663
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/28.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_all.2640142430
Short name T653
Test name
Test status
Simulation time 1013164780 ps
CPU time 16.42 seconds
Started Oct 12 02:28:32 PM UTC 24
Finished Oct 12 02:28:49 PM UTC 24
Peak memory 227244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640142430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2640142430
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/28.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.1697487
Short name T650
Test name
Test status
Simulation time 2573713044 ps
CPU time 8.6 seconds
Started Oct 12 02:28:32 PM UTC 24
Finished Oct 12 02:28:41 PM UTC 24
Peak memory 227416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM
_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1697487
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/28.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_rw.3724858179
Short name T648
Test name
Test status
Simulation time 41379403 ps
CPU time 1.65 seconds
Started Oct 12 02:28:34 PM UTC 24
Finished Oct 12 02:28:37 PM UTC 24
Peak memory 226532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724858179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3724858179
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/28.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.1654259964
Short name T645
Test name
Test status
Simulation time 17714202 ps
CPU time 1.17 seconds
Started Oct 12 02:28:32 PM UTC 24
Finished Oct 12 02:28:34 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654259964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1654259964
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/28.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/28.spi_device_upload.2085827270
Short name T646
Test name
Test status
Simulation time 28465255781 ps
CPU time 10.37 seconds
Started Oct 12 02:28:42 PM UTC 24
Finished Oct 12 02:28:53 PM UTC 24
Peak memory 235004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085827270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2085827270
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/28.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_alert_test.915065585
Short name T672
Test name
Test status
Simulation time 13201325 ps
CPU time 1.11 seconds
Started Oct 12 02:29:13 PM UTC 24
Finished Oct 12 02:29:15 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915065585 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.915065585
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/29.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_cfg_cmd.656037789
Short name T679
Test name
Test status
Simulation time 7207384933 ps
CPU time 17.22 seconds
Started Oct 12 02:29:02 PM UTC 24
Finished Oct 12 02:29:21 PM UTC 24
Peak memory 245024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656037789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.656037789
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/29.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_csb_read.3654850091
Short name T660
Test name
Test status
Simulation time 50770808 ps
CPU time 1.17 seconds
Started Oct 12 02:28:56 PM UTC 24
Finished Oct 12 02:28:58 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654850091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3654850091
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/29.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.721008003
Short name T680
Test name
Test status
Simulation time 1607298292 ps
CPU time 17.11 seconds
Started Oct 12 02:29:05 PM UTC 24
Finished Oct 12 02:29:23 PM UTC 24
Peak memory 245224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721008003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.721008003
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/29.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.537663689
Short name T341
Test name
Test status
Simulation time 42713218383 ps
CPU time 119.29 seconds
Started Oct 12 02:29:06 PM UTC 24
Finished Oct 12 02:31:08 PM UTC 24
Peak memory 251360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537663689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.537663689
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode.2815710881
Short name T682
Test name
Test status
Simulation time 2812605329 ps
CPU time 22.66 seconds
Started Oct 12 02:29:02 PM UTC 24
Finished Oct 12 02:29:26 PM UTC 24
Peak memory 234788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815710881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2815710881
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/29.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.773615382
Short name T729
Test name
Test status
Simulation time 63780403526 ps
CPU time 88.07 seconds
Started Oct 12 02:29:02 PM UTC 24
Finished Oct 12 02:30:33 PM UTC 24
Peak memory 261468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773615382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.773615382
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_intercept.1905938640
Short name T677
Test name
Test status
Simulation time 2178191520 ps
CPU time 17.44 seconds
Started Oct 12 02:29:00 PM UTC 24
Finished Oct 12 02:29:19 PM UTC 24
Peak memory 234744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905938640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1905938640
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/29.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_mailbox.3467047389
Short name T314
Test name
Test status
Simulation time 84246647 ps
CPU time 3.49 seconds
Started Oct 12 02:29:00 PM UTC 24
Finished Oct 12 02:29:05 PM UTC 24
Peak memory 234660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467047389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3467047389
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/29.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.2578229240
Short name T361
Test name
Test status
Simulation time 1046882552 ps
CPU time 3.42 seconds
Started Oct 12 02:28:59 PM UTC 24
Finished Oct 12 02:29:03 PM UTC 24
Peak memory 245176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578229240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.2578229240
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/29.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.3114149174
Short name T289
Test name
Test status
Simulation time 1659169917 ps
CPU time 18.82 seconds
Started Oct 12 02:28:59 PM UTC 24
Finished Oct 12 02:29:19 PM UTC 24
Peak memory 245164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114149174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3114149174
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/29.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.2778691480
Short name T671
Test name
Test status
Simulation time 895178603 ps
CPU time 10.31 seconds
Started Oct 12 02:29:03 PM UTC 24
Finished Oct 12 02:29:14 PM UTC 24
Peak memory 233600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778691480 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.2778691480
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/29.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_stress_all.2502139868
Short name T764
Test name
Test status
Simulation time 178292462932 ps
CPU time 140.27 seconds
Started Oct 12 02:29:09 PM UTC 24
Finished Oct 12 02:31:32 PM UTC 24
Peak memory 261532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502139868 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.2502139868
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/29.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_all.656335887
Short name T662
Test name
Test status
Simulation time 57089727 ps
CPU time 1.11 seconds
Started Oct 12 02:28:57 PM UTC 24
Finished Oct 12 02:29:00 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656335887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.656335887
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/29.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.2721224562
Short name T661
Test name
Test status
Simulation time 93994108 ps
CPU time 1.45 seconds
Started Oct 12 02:28:56 PM UTC 24
Finished Oct 12 02:28:59 PM UTC 24
Peak memory 216392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721224562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2721224562
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/29.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_rw.3398283347
Short name T666
Test name
Test status
Simulation time 27649309 ps
CPU time 1.47 seconds
Started Oct 12 02:28:59 PM UTC 24
Finished Oct 12 02:29:01 PM UTC 24
Peak memory 226432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398283347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3398283347
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/29.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.2523340876
Short name T664
Test name
Test status
Simulation time 203169325 ps
CPU time 1.66 seconds
Started Oct 12 02:28:57 PM UTC 24
Finished Oct 12 02:29:00 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523340876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2523340876
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/29.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_upload.1269207048
Short name T293
Test name
Test status
Simulation time 3556980641 ps
CPU time 15.13 seconds
Started Oct 12 02:29:02 PM UTC 24
Finished Oct 12 02:29:19 PM UTC 24
Peak memory 245088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269207048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1269207048
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/29.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.727797472
Short name T105
Test name
Test status
Simulation time 13122531 ps
CPU time 1.06 seconds
Started Oct 12 02:19:04 PM UTC 24
Finished Oct 12 02:19:06 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727797472 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.727797472
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.1438575389
Short name T101
Test name
Test status
Simulation time 112874463 ps
CPU time 3.78 seconds
Started Oct 12 02:18:59 PM UTC 24
Finished Oct 12 02:19:04 PM UTC 24
Peak memory 234612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438575389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1438575389
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.1967999859
Short name T401
Test name
Test status
Simulation time 46960760 ps
CPU time 1.13 seconds
Started Oct 12 02:18:56 PM UTC 24
Finished Oct 12 02:18:58 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967999859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1967999859
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.2752920604
Short name T402
Test name
Test status
Simulation time 37660285 ps
CPU time 0.94 seconds
Started Oct 12 02:19:03 PM UTC 24
Finished Oct 12 02:19:05 PM UTC 24
Peak memory 225176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752920604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2752920604
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.559477492
Short name T41
Test name
Test status
Simulation time 27146751074 ps
CPU time 87.21 seconds
Started Oct 12 02:19:03 PM UTC 24
Finished Oct 12 02:20:32 PM UTC 24
Peak memory 267596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559477492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.559477492
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.499564303
Short name T251
Test name
Test status
Simulation time 87816085440 ps
CPU time 249.45 seconds
Started Oct 12 02:19:04 PM UTC 24
Finished Oct 12 02:23:17 PM UTC 24
Peak memory 267652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499564303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.499564303
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.3518766253
Short name T139
Test name
Test status
Simulation time 945409845 ps
CPU time 15.06 seconds
Started Oct 12 02:18:59 PM UTC 24
Finished Oct 12 02:19:16 PM UTC 24
Peak memory 244904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518766253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3518766253
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.3660189256
Short name T94
Test name
Test status
Simulation time 57235103711 ps
CPU time 103.22 seconds
Started Oct 12 02:19:01 PM UTC 24
Finished Oct 12 02:20:46 PM UTC 24
Peak memory 261472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660189256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.3660189256
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.552004477
Short name T61
Test name
Test status
Simulation time 194167497 ps
CPU time 5.8 seconds
Started Oct 12 02:18:58 PM UTC 24
Finished Oct 12 02:19:06 PM UTC 24
Peak memory 234976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552004477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.552004477
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.3924423825
Short name T124
Test name
Test status
Simulation time 33218480404 ps
CPU time 33.14 seconds
Started Oct 12 02:18:58 PM UTC 24
Finished Oct 12 02:19:34 PM UTC 24
Peak memory 245104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924423825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3924423825
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.97093491
Short name T46
Test name
Test status
Simulation time 27751061 ps
CPU time 1.53 seconds
Started Oct 12 02:18:57 PM UTC 24
Finished Oct 12 02:19:02 PM UTC 24
Peak memory 228996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97093491 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_parity.97093491
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.1365984666
Short name T57
Test name
Test status
Simulation time 2987619043 ps
CPU time 4.34 seconds
Started Oct 12 02:18:58 PM UTC 24
Finished Oct 12 02:19:05 PM UTC 24
Peak memory 234864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365984666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1365984666
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.1760286878
Short name T138
Test name
Test status
Simulation time 6217355874 ps
CPU time 4.61 seconds
Started Oct 12 02:19:01 PM UTC 24
Finished Oct 12 02:19:06 PM UTC 24
Peak memory 229260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760286878 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.1760286878
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.426837314
Short name T36
Test name
Test status
Simulation time 151381111 ps
CPU time 1.54 seconds
Started Oct 12 02:19:04 PM UTC 24
Finished Oct 12 02:19:07 PM UTC 24
Peak memory 256904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426837314 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.426837314
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.3128324943
Short name T37
Test name
Test status
Simulation time 63335096 ps
CPU time 1.54 seconds
Started Oct 12 02:19:04 PM UTC 24
Finished Oct 12 02:19:07 PM UTC 24
Peak memory 216332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128324943 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.3128324943
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.3544521428
Short name T119
Test name
Test status
Simulation time 6647281923 ps
CPU time 62.93 seconds
Started Oct 12 02:18:57 PM UTC 24
Finished Oct 12 02:20:05 PM UTC 24
Peak memory 227368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544521428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3544521428
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.1270304927
Short name T96
Test name
Test status
Simulation time 20912080240 ps
CPU time 19.55 seconds
Started Oct 12 02:18:57 PM UTC 24
Finished Oct 12 02:19:21 PM UTC 24
Peak memory 227408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270304927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1270304927
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.1236615122
Short name T83
Test name
Test status
Simulation time 53521394 ps
CPU time 1.96 seconds
Started Oct 12 02:18:57 PM UTC 24
Finished Oct 12 02:19:03 PM UTC 24
Peak memory 226472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236615122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1236615122
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.959945418
Short name T31
Test name
Test status
Simulation time 256781180 ps
CPU time 1.36 seconds
Started Oct 12 02:18:57 PM UTC 24
Finished Oct 12 02:19:02 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959945418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.959945418
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.4210982352
Short name T62
Test name
Test status
Simulation time 2803962300 ps
CPU time 19.88 seconds
Started Oct 12 02:18:59 PM UTC 24
Finished Oct 12 02:19:21 PM UTC 24
Peak memory 249120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210982352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.4210982352
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/3.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_alert_test.3410426879
Short name T685
Test name
Test status
Simulation time 21142878 ps
CPU time 1.13 seconds
Started Oct 12 02:29:31 PM UTC 24
Finished Oct 12 02:29:33 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410426879 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.3410426879
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/30.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_cfg_cmd.651623931
Short name T686
Test name
Test status
Simulation time 1468689655 ps
CPU time 11.69 seconds
Started Oct 12 02:29:21 PM UTC 24
Finished Oct 12 02:29:34 PM UTC 24
Peak memory 244848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651623931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.651623931
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/30.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_csb_read.417767808
Short name T674
Test name
Test status
Simulation time 69140877 ps
CPU time 1.19 seconds
Started Oct 12 02:29:14 PM UTC 24
Finished Oct 12 02:29:16 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417767808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.417767808
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/30.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_all.2319046930
Short name T735
Test name
Test status
Simulation time 5455860323 ps
CPU time 76.02 seconds
Started Oct 12 02:29:24 PM UTC 24
Finished Oct 12 02:30:42 PM UTC 24
Peak memory 261416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319046930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2319046930
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/30.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.2384915102
Short name T980
Test name
Test status
Simulation time 105878869339 ps
CPU time 561.23 seconds
Started Oct 12 02:29:26 PM UTC 24
Finished Oct 12 02:38:54 PM UTC 24
Peak memory 278048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384915102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2384915102
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/30.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.3445342078
Short name T715
Test name
Test status
Simulation time 2251887450 ps
CPU time 42.59 seconds
Started Oct 12 02:29:27 PM UTC 24
Finished Oct 12 02:30:11 PM UTC 24
Peak memory 265608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445342078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.3445342078
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode.893858258
Short name T683
Test name
Test status
Simulation time 291886540 ps
CPU time 6.08 seconds
Started Oct 12 02:29:22 PM UTC 24
Finished Oct 12 02:29:29 PM UTC 24
Peak memory 234664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893858258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.893858258
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/30.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.1330450255
Short name T754
Test name
Test status
Simulation time 140142592341 ps
CPU time 113.33 seconds
Started Oct 12 02:29:22 PM UTC 24
Finished Oct 12 02:31:18 PM UTC 24
Peak memory 261476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330450255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.1330450255
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_intercept.870152650
Short name T691
Test name
Test status
Simulation time 762663448 ps
CPU time 16.04 seconds
Started Oct 12 02:29:21 PM UTC 24
Finished Oct 12 02:29:38 PM UTC 24
Peak memory 234652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870152650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.870152650
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/30.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_mailbox.4202179593
Short name T688
Test name
Test status
Simulation time 1233911132 ps
CPU time 13.24 seconds
Started Oct 12 02:29:21 PM UTC 24
Finished Oct 12 02:29:35 PM UTC 24
Peak memory 234720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202179593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.4202179593
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/30.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.1774284035
Short name T687
Test name
Test status
Simulation time 1093190928 ps
CPU time 11.99 seconds
Started Oct 12 02:29:21 PM UTC 24
Finished Oct 12 02:29:34 PM UTC 24
Peak memory 245152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774284035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.1774284035
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/30.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.877653392
Short name T681
Test name
Test status
Simulation time 31661355 ps
CPU time 3.2 seconds
Started Oct 12 02:29:21 PM UTC 24
Finished Oct 12 02:29:25 PM UTC 24
Peak memory 244640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877653392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.877653392
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/30.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.3936742552
Short name T690
Test name
Test status
Simulation time 1292386586 ps
CPU time 12.62 seconds
Started Oct 12 02:29:24 PM UTC 24
Finished Oct 12 02:29:37 PM UTC 24
Peak memory 233220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936742552 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.3936742552
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/30.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.1778863316
Short name T88
Test name
Test status
Simulation time 125536434506 ps
CPU time 1075.75 seconds
Started Oct 12 02:29:30 PM UTC 24
Finished Oct 12 02:47:39 PM UTC 24
Peak memory 286120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778863316 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.1778863316
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/30.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_all.3743596794
Short name T695
Test name
Test status
Simulation time 2573864454 ps
CPU time 26.18 seconds
Started Oct 12 02:29:15 PM UTC 24
Finished Oct 12 02:29:43 PM UTC 24
Peak memory 227408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743596794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3743596794
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/30.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.5794373
Short name T684
Test name
Test status
Simulation time 7923370438 ps
CPU time 13.19 seconds
Started Oct 12 02:29:15 PM UTC 24
Finished Oct 12 02:29:29 PM UTC 24
Peak memory 227416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5794373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM
_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.5794373
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/30.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_rw.1402613141
Short name T678
Test name
Test status
Simulation time 42037870 ps
CPU time 2.06 seconds
Started Oct 12 02:29:17 PM UTC 24
Finished Oct 12 02:29:20 PM UTC 24
Peak memory 217296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402613141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1402613141
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/30.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.3288830277
Short name T676
Test name
Test status
Simulation time 317892844 ps
CPU time 1.22 seconds
Started Oct 12 02:29:17 PM UTC 24
Finished Oct 12 02:29:19 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288830277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3288830277
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/30.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/30.spi_device_upload.2454059964
Short name T692
Test name
Test status
Simulation time 24021251279 ps
CPU time 16.43 seconds
Started Oct 12 02:29:21 PM UTC 24
Finished Oct 12 02:29:38 PM UTC 24
Peak memory 234916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454059964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2454059964
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/30.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_alert_test.4240871902
Short name T704
Test name
Test status
Simulation time 36842450 ps
CPU time 1.09 seconds
Started Oct 12 02:29:54 PM UTC 24
Finished Oct 12 02:29:56 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240871902 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.4240871902
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/31.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_cfg_cmd.3907583072
Short name T699
Test name
Test status
Simulation time 1732142801 ps
CPU time 6.11 seconds
Started Oct 12 02:29:43 PM UTC 24
Finished Oct 12 02:29:50 PM UTC 24
Peak memory 234656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907583072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3907583072
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/31.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_csb_read.790098419
Short name T689
Test name
Test status
Simulation time 59502494 ps
CPU time 1.18 seconds
Started Oct 12 02:29:34 PM UTC 24
Finished Oct 12 02:29:36 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790098419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.790098419
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/31.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_all.2536674909
Short name T1019
Test name
Test status
Simulation time 253896171890 ps
CPU time 600.51 seconds
Started Oct 12 02:29:50 PM UTC 24
Finished Oct 12 02:39:58 PM UTC 24
Peak memory 277860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536674909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2536674909
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/31.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.4022443562
Short name T738
Test name
Test status
Simulation time 4026894704 ps
CPU time 51.85 seconds
Started Oct 12 02:29:51 PM UTC 24
Finished Oct 12 02:30:44 PM UTC 24
Peak memory 261512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022443562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.4022443562
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.1966262566
Short name T1021
Test name
Test status
Simulation time 67386881458 ps
CPU time 618.67 seconds
Started Oct 12 02:29:51 PM UTC 24
Finished Oct 12 02:40:17 PM UTC 24
Peak memory 284064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966262566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.1966262566
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode.321886412
Short name T702
Test name
Test status
Simulation time 354646822 ps
CPU time 10.63 seconds
Started Oct 12 02:29:44 PM UTC 24
Finished Oct 12 02:29:56 PM UTC 24
Peak memory 234804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321886412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.321886412
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/31.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.2907441082
Short name T778
Test name
Test status
Simulation time 17613710500 ps
CPU time 139.09 seconds
Started Oct 12 02:29:44 PM UTC 24
Finished Oct 12 02:32:06 PM UTC 24
Peak memory 251428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907441082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.2907441082
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_intercept.570524453
Short name T700
Test name
Test status
Simulation time 776350185 ps
CPU time 12.25 seconds
Started Oct 12 02:29:39 PM UTC 24
Finished Oct 12 02:29:52 PM UTC 24
Peak memory 234720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570524453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.570524453
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/31.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_mailbox.3830893608
Short name T705
Test name
Test status
Simulation time 1474498132 ps
CPU time 15.96 seconds
Started Oct 12 02:29:40 PM UTC 24
Finished Oct 12 02:29:57 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830893608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3830893608
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/31.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.3373985150
Short name T696
Test name
Test status
Simulation time 36443697 ps
CPU time 2.92 seconds
Started Oct 12 02:29:39 PM UTC 24
Finished Oct 12 02:29:43 PM UTC 24
Peak memory 244896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373985150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.3373985150
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/31.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.2962011829
Short name T698
Test name
Test status
Simulation time 1480027646 ps
CPU time 9.73 seconds
Started Oct 12 02:29:39 PM UTC 24
Finished Oct 12 02:29:50 PM UTC 24
Peak memory 234744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962011829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2962011829
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/31.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.195002927
Short name T703
Test name
Test status
Simulation time 1297129426 ps
CPU time 10.96 seconds
Started Oct 12 02:29:44 PM UTC 24
Finished Oct 12 02:29:56 PM UTC 24
Peak memory 231332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195002927 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.195002927
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/31.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_all.374816408
Short name T716
Test name
Test status
Simulation time 5208121046 ps
CPU time 35.21 seconds
Started Oct 12 02:29:35 PM UTC 24
Finished Oct 12 02:30:12 PM UTC 24
Peak memory 227372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374816408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.374816408
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/31.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.2710787838
Short name T694
Test name
Test status
Simulation time 630988389 ps
CPU time 5.65 seconds
Started Oct 12 02:29:35 PM UTC 24
Finished Oct 12 02:29:42 PM UTC 24
Peak memory 227496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710787838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2710787838
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/31.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_rw.1714493908
Short name T697
Test name
Test status
Simulation time 952478056 ps
CPU time 6.01 seconds
Started Oct 12 02:29:37 PM UTC 24
Finished Oct 12 02:29:44 PM UTC 24
Peak memory 227296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714493908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1714493908
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/31.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.354611186
Short name T693
Test name
Test status
Simulation time 134579868 ps
CPU time 1.29 seconds
Started Oct 12 02:29:36 PM UTC 24
Finished Oct 12 02:29:39 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354611186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.354611186
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/31.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_upload.2746104368
Short name T731
Test name
Test status
Simulation time 31039574132 ps
CPU time 50.76 seconds
Started Oct 12 02:29:41 PM UTC 24
Finished Oct 12 02:30:34 PM UTC 24
Peak memory 245024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746104368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2746104368
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/31.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_alert_test.194457921
Short name T721
Test name
Test status
Simulation time 111062159 ps
CPU time 1.13 seconds
Started Oct 12 02:30:20 PM UTC 24
Finished Oct 12 02:30:22 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194457921 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.194457921
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/32.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_cfg_cmd.3665522146
Short name T718
Test name
Test status
Simulation time 616523636 ps
CPU time 7.37 seconds
Started Oct 12 02:30:09 PM UTC 24
Finished Oct 12 02:30:18 PM UTC 24
Peak memory 244896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665522146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3665522146
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/32.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_csb_read.3623005608
Short name T706
Test name
Test status
Simulation time 58229106 ps
CPU time 1.16 seconds
Started Oct 12 02:29:55 PM UTC 24
Finished Oct 12 02:29:58 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623005608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3623005608
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/32.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_all.3367556722
Short name T905
Test name
Test status
Simulation time 71170595685 ps
CPU time 361.56 seconds
Started Oct 12 02:30:12 PM UTC 24
Finished Oct 12 02:36:19 PM UTC 24
Peak memory 261668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367556722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3367556722
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/32.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.3938450711
Short name T791
Test name
Test status
Simulation time 62164047604 ps
CPU time 130.35 seconds
Started Oct 12 02:30:13 PM UTC 24
Finished Oct 12 02:32:26 PM UTC 24
Peak memory 261476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938450711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3938450711
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.1781633213
Short name T254
Test name
Test status
Simulation time 39305196376 ps
CPU time 251.71 seconds
Started Oct 12 02:30:13 PM UTC 24
Finished Oct 12 02:34:29 PM UTC 24
Peak memory 245152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781633213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.1781633213
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode.2460124909
Short name T719
Test name
Test status
Simulation time 355098207 ps
CPU time 8.69 seconds
Started Oct 12 02:30:10 PM UTC 24
Finished Oct 12 02:30:21 PM UTC 24
Peak memory 234920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460124909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2460124909
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/32.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.460757834
Short name T762
Test name
Test status
Simulation time 39702792653 ps
CPU time 76.59 seconds
Started Oct 12 02:30:10 PM UTC 24
Finished Oct 12 02:31:29 PM UTC 24
Peak memory 261536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460757834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.460757834
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_intercept.1440089886
Short name T711
Test name
Test status
Simulation time 675691879 ps
CPU time 5.25 seconds
Started Oct 12 02:30:01 PM UTC 24
Finished Oct 12 02:30:08 PM UTC 24
Peak memory 234680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440089886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1440089886
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/32.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_mailbox.3404479225
Short name T720
Test name
Test status
Simulation time 1410883245 ps
CPU time 13.13 seconds
Started Oct 12 02:30:07 PM UTC 24
Finished Oct 12 02:30:21 PM UTC 24
Peak memory 244916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404479225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3404479225
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/32.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.3620911487
Short name T714
Test name
Test status
Simulation time 211777761 ps
CPU time 7.18 seconds
Started Oct 12 02:30:01 PM UTC 24
Finished Oct 12 02:30:10 PM UTC 24
Peak memory 251060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620911487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.3620911487
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/32.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.3166671220
Short name T713
Test name
Test status
Simulation time 836686202 ps
CPU time 8.61 seconds
Started Oct 12 02:29:59 PM UTC 24
Finished Oct 12 02:30:09 PM UTC 24
Peak memory 244896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166671220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3166671220
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/32.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.1329352176
Short name T722
Test name
Test status
Simulation time 951214263 ps
CPU time 11.02 seconds
Started Oct 12 02:30:11 PM UTC 24
Finished Oct 12 02:30:23 PM UTC 24
Peak memory 233352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329352176 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.1329352176
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/32.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.3496147006
Short name T181
Test name
Test status
Simulation time 43533298994 ps
CPU time 501.46 seconds
Started Oct 12 02:30:18 PM UTC 24
Finished Oct 12 02:38:46 PM UTC 24
Peak memory 300380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496147006 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.3496147006
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/32.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_all.2244545816
Short name T707
Test name
Test status
Simulation time 13659722 ps
CPU time 1.07 seconds
Started Oct 12 02:29:57 PM UTC 24
Finished Oct 12 02:30:00 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244545816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2244545816
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/32.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.4083635855
Short name T712
Test name
Test status
Simulation time 4095790130 ps
CPU time 9.76 seconds
Started Oct 12 02:29:57 PM UTC 24
Finished Oct 12 02:30:09 PM UTC 24
Peak memory 227372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083635855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.4083635855
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/32.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_rw.2758947534
Short name T710
Test name
Test status
Simulation time 510450388 ps
CPU time 6.25 seconds
Started Oct 12 02:29:59 PM UTC 24
Finished Oct 12 02:30:06 PM UTC 24
Peak memory 227288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758947534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2758947534
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/32.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.1017486850
Short name T708
Test name
Test status
Simulation time 65473777 ps
CPU time 1.46 seconds
Started Oct 12 02:29:58 PM UTC 24
Finished Oct 12 02:30:00 PM UTC 24
Peak memory 216516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017486850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1017486850
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/32.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/32.spi_device_upload.2918585257
Short name T247
Test name
Test status
Simulation time 595265018 ps
CPU time 9.62 seconds
Started Oct 12 02:30:08 PM UTC 24
Finished Oct 12 02:30:19 PM UTC 24
Peak memory 244980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918585257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2918585257
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/32.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/33.spi_device_alert_test.3624603792
Short name T740
Test name
Test status
Simulation time 65878537 ps
CPU time 1.11 seconds
Started Oct 12 02:30:43 PM UTC 24
Finished Oct 12 02:30:46 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624603792 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.3624603792
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/33.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/33.spi_device_cfg_cmd.3141276516
Short name T732
Test name
Test status
Simulation time 31896094 ps
CPU time 2.88 seconds
Started Oct 12 02:30:32 PM UTC 24
Finished Oct 12 02:30:36 PM UTC 24
Peak memory 234596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141276516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3141276516
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/33.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/33.spi_device_csb_read.851434983
Short name T724
Test name
Test status
Simulation time 59598878 ps
CPU time 1.19 seconds
Started Oct 12 02:30:22 PM UTC 24
Finished Oct 12 02:30:24 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851434983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.851434983
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/33.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_all.3352909508
Short name T776
Test name
Test status
Simulation time 11807810697 ps
CPU time 79.67 seconds
Started Oct 12 02:30:38 PM UTC 24
Finished Oct 12 02:31:59 PM UTC 24
Peak memory 251176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352909508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3352909508
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/33.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.322329939
Short name T356
Test name
Test status
Simulation time 7560133078 ps
CPU time 132.73 seconds
Started Oct 12 02:30:39 PM UTC 24
Finished Oct 12 02:32:54 PM UTC 24
Peak memory 277920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322329939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.322329939
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.2986101441
Short name T240
Test name
Test status
Simulation time 64889277384 ps
CPU time 73.15 seconds
Started Oct 12 02:30:43 PM UTC 24
Finished Oct 12 02:31:58 PM UTC 24
Peak memory 261644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986101441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.2986101441
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode.2934563750
Short name T736
Test name
Test status
Simulation time 261753880 ps
CPU time 7.74 seconds
Started Oct 12 02:30:33 PM UTC 24
Finished Oct 12 02:30:42 PM UTC 24
Peak memory 234648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934563750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2934563750
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/33.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.2581892394
Short name T752
Test name
Test status
Simulation time 7013589607 ps
CPU time 36.28 seconds
Started Oct 12 02:30:35 PM UTC 24
Finished Oct 12 02:31:13 PM UTC 24
Peak memory 267812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581892394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.2581892394
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/33.spi_device_intercept.299134409
Short name T734
Test name
Test status
Simulation time 562420644 ps
CPU time 9.01 seconds
Started Oct 12 02:30:27 PM UTC 24
Finished Oct 12 02:30:37 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299134409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.299134409
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/33.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/33.spi_device_mailbox.367203083
Short name T739
Test name
Test status
Simulation time 1322797979 ps
CPU time 15.25 seconds
Started Oct 12 02:30:28 PM UTC 24
Finished Oct 12 02:30:45 PM UTC 24
Peak memory 251104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367203083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.367203083
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/33.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.1626772430
Short name T728
Test name
Test status
Simulation time 398799986 ps
CPU time 3.49 seconds
Started Oct 12 02:30:26 PM UTC 24
Finished Oct 12 02:30:30 PM UTC 24
Peak memory 234680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626772430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.1626772430
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/33.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.1708286209
Short name T737
Test name
Test status
Simulation time 7214747322 ps
CPU time 16.72 seconds
Started Oct 12 02:30:25 PM UTC 24
Finished Oct 12 02:30:43 PM UTC 24
Peak memory 245276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708286209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1708286209
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/33.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.1467682691
Short name T745
Test name
Test status
Simulation time 912494603 ps
CPU time 13.67 seconds
Started Oct 12 02:30:37 PM UTC 24
Finished Oct 12 02:30:51 PM UTC 24
Peak memory 233120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467682691 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.1467682691
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/33.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.2049271220
Short name T742
Test name
Test status
Simulation time 140759003 ps
CPU time 1.47 seconds
Started Oct 12 02:30:43 PM UTC 24
Finished Oct 12 02:30:46 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049271220 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.2049271220
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/33.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_all.2555895851
Short name T741
Test name
Test status
Simulation time 5690514813 ps
CPU time 21.28 seconds
Started Oct 12 02:30:23 PM UTC 24
Finished Oct 12 02:30:46 PM UTC 24
Peak memory 227732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555895851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2555895851
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/33.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.3294548287
Short name T725
Test name
Test status
Simulation time 1523650792 ps
CPU time 2.43 seconds
Started Oct 12 02:30:22 PM UTC 24
Finished Oct 12 02:30:25 PM UTC 24
Peak memory 216920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294548287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3294548287
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/33.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_rw.2069477510
Short name T727
Test name
Test status
Simulation time 449205424 ps
CPU time 1.78 seconds
Started Oct 12 02:30:25 PM UTC 24
Finished Oct 12 02:30:27 PM UTC 24
Peak memory 216060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069477510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2069477510
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/33.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.1260722863
Short name T726
Test name
Test status
Simulation time 126215723 ps
CPU time 1.01 seconds
Started Oct 12 02:30:25 PM UTC 24
Finished Oct 12 02:30:27 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260722863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1260722863
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/33.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/33.spi_device_upload.3102078381
Short name T733
Test name
Test status
Simulation time 4076141876 ps
CPU time 6.43 seconds
Started Oct 12 02:30:30 PM UTC 24
Finished Oct 12 02:30:37 PM UTC 24
Peak memory 234916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102078381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3102078381
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/33.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_alert_test.2478737848
Short name T757
Test name
Test status
Simulation time 43202388 ps
CPU time 1.09 seconds
Started Oct 12 02:31:18 PM UTC 24
Finished Oct 12 02:31:21 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478737848 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.2478737848
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/34.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_cfg_cmd.835199655
Short name T750
Test name
Test status
Simulation time 92187832 ps
CPU time 3.68 seconds
Started Oct 12 02:30:56 PM UTC 24
Finished Oct 12 02:31:00 PM UTC 24
Peak memory 234608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835199655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.835199655
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/34.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_csb_read.633892250
Short name T743
Test name
Test status
Simulation time 17324555 ps
CPU time 1.17 seconds
Started Oct 12 02:30:46 PM UTC 24
Finished Oct 12 02:30:48 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633892250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.633892250
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/34.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_all.1056726578
Short name T365
Test name
Test status
Simulation time 416720192 ps
CPU time 10.52 seconds
Started Oct 12 02:31:08 PM UTC 24
Finished Oct 12 02:31:19 PM UTC 24
Peak memory 261540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056726578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1056726578
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/34.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.2466714868
Short name T860
Test name
Test status
Simulation time 78806915915 ps
CPU time 202.99 seconds
Started Oct 12 02:31:09 PM UTC 24
Finished Oct 12 02:34:35 PM UTC 24
Peak memory 261472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466714868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2466714868
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/34.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.3876000376
Short name T831
Test name
Test status
Simulation time 12434584252 ps
CPU time 140.1 seconds
Started Oct 12 02:31:14 PM UTC 24
Finished Oct 12 02:33:37 PM UTC 24
Peak memory 247080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876000376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.3876000376
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode.95938048
Short name T756
Test name
Test status
Simulation time 3442817167 ps
CPU time 20.45 seconds
Started Oct 12 02:30:57 PM UTC 24
Finished Oct 12 02:31:19 PM UTC 24
Peak memory 251364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95938048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.95938048
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/34.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.3844114731
Short name T241
Test name
Test status
Simulation time 23556918024 ps
CPU time 199.33 seconds
Started Oct 12 02:30:57 PM UTC 24
Finished Oct 12 02:34:20 PM UTC 24
Peak memory 261416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844114731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.3844114731
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_intercept.322947250
Short name T753
Test name
Test status
Simulation time 13415668067 ps
CPU time 20.94 seconds
Started Oct 12 02:30:52 PM UTC 24
Finished Oct 12 02:31:14 PM UTC 24
Peak memory 234740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322947250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.322947250
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/34.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_mailbox.2068294631
Short name T774
Test name
Test status
Simulation time 23500571957 ps
CPU time 59.26 seconds
Started Oct 12 02:30:53 PM UTC 24
Finished Oct 12 02:31:54 PM UTC 24
Peak memory 261412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068294631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2068294631
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/34.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.537911983
Short name T755
Test name
Test status
Simulation time 4312180566 ps
CPU time 26.88 seconds
Started Oct 12 02:30:51 PM UTC 24
Finished Oct 12 02:31:19 PM UTC 24
Peak memory 245028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537911983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.537911983
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/34.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.2994468249
Short name T746
Test name
Test status
Simulation time 93239094 ps
CPU time 3.02 seconds
Started Oct 12 02:30:49 PM UTC 24
Finished Oct 12 02:30:53 PM UTC 24
Peak memory 234644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994468249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2994468249
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/34.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.256642435
Short name T758
Test name
Test status
Simulation time 972190916 ps
CPU time 17.91 seconds
Started Oct 12 02:31:01 PM UTC 24
Finished Oct 12 02:31:21 PM UTC 24
Peak memory 233228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256642435 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.256642435
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/34.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.2755735047
Short name T179
Test name
Test status
Simulation time 38266060352 ps
CPU time 363.55 seconds
Started Oct 12 02:31:15 PM UTC 24
Finished Oct 12 02:37:24 PM UTC 24
Peak memory 263624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755735047 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.2755735047
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/34.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_all.3797414736
Short name T748
Test name
Test status
Simulation time 296455933 ps
CPU time 6.85 seconds
Started Oct 12 02:30:47 PM UTC 24
Finished Oct 12 02:30:55 PM UTC 24
Peak memory 227304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797414736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3797414736
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/34.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.3646764123
Short name T749
Test name
Test status
Simulation time 1543402683 ps
CPU time 9.15 seconds
Started Oct 12 02:30:46 PM UTC 24
Finished Oct 12 02:30:56 PM UTC 24
Peak memory 227496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646764123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3646764123
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/34.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_rw.1257844073
Short name T747
Test name
Test status
Simulation time 256635340 ps
CPU time 4.7 seconds
Started Oct 12 02:30:47 PM UTC 24
Finished Oct 12 02:30:53 PM UTC 24
Peak memory 227300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257844073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1257844073
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/34.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.3169114751
Short name T744
Test name
Test status
Simulation time 121304045 ps
CPU time 1.4 seconds
Started Oct 12 02:30:47 PM UTC 24
Finished Oct 12 02:30:50 PM UTC 24
Peak memory 216516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169114751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3169114751
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/34.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/34.spi_device_upload.1819168777
Short name T751
Test name
Test status
Simulation time 1883765756 ps
CPU time 10.73 seconds
Started Oct 12 02:30:55 PM UTC 24
Finished Oct 12 02:31:06 PM UTC 24
Peak memory 234720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819168777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1819168777
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/34.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_alert_test.1874444364
Short name T772
Test name
Test status
Simulation time 40396803 ps
CPU time 1.12 seconds
Started Oct 12 02:31:45 PM UTC 24
Finished Oct 12 02:31:47 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874444364 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.1874444364
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/35.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_cfg_cmd.1211361800
Short name T767
Test name
Test status
Simulation time 28997790 ps
CPU time 3.16 seconds
Started Oct 12 02:31:33 PM UTC 24
Finished Oct 12 02:31:38 PM UTC 24
Peak memory 244536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211361800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1211361800
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/35.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_csb_read.2201804421
Short name T759
Test name
Test status
Simulation time 22679573 ps
CPU time 1.16 seconds
Started Oct 12 02:31:20 PM UTC 24
Finished Oct 12 02:31:22 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201804421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2201804421
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/35.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.946599525
Short name T814
Test name
Test status
Simulation time 8774989399 ps
CPU time 82.8 seconds
Started Oct 12 02:31:39 PM UTC 24
Finished Oct 12 02:33:04 PM UTC 24
Peak memory 261672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946599525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.946599525
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/35.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.1145248715
Short name T285
Test name
Test status
Simulation time 438725664733 ps
CPU time 616.13 seconds
Started Oct 12 02:31:39 PM UTC 24
Finished Oct 12 02:42:03 PM UTC 24
Peak memory 300444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145248715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1145248715
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.1266407968
Short name T819
Test name
Test status
Simulation time 24437788533 ps
CPU time 88.29 seconds
Started Oct 12 02:31:41 PM UTC 24
Finished Oct 12 02:33:11 PM UTC 24
Peak memory 263776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266407968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.1266407968
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode.4203664821
Short name T769
Test name
Test status
Simulation time 68875714 ps
CPU time 4.15 seconds
Started Oct 12 02:31:36 PM UTC 24
Finished Oct 12 02:31:41 PM UTC 24
Peak memory 244964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203664821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.4203664821
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/35.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.135658307
Short name T846
Test name
Test status
Simulation time 45038891056 ps
CPU time 156.01 seconds
Started Oct 12 02:31:37 PM UTC 24
Finished Oct 12 02:34:16 PM UTC 24
Peak memory 261732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135658307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.135658307
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_intercept.3025029544
Short name T765
Test name
Test status
Simulation time 380729632 ps
CPU time 3.35 seconds
Started Oct 12 02:31:30 PM UTC 24
Finished Oct 12 02:31:35 PM UTC 24
Peak memory 234968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025029544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3025029544
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/35.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_mailbox.3015080596
Short name T766
Test name
Test status
Simulation time 161259691 ps
CPU time 4.23 seconds
Started Oct 12 02:31:30 PM UTC 24
Finished Oct 12 02:31:36 PM UTC 24
Peak memory 244904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015080596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3015080596
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/35.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.1644858388
Short name T334
Test name
Test status
Simulation time 393106355 ps
CPU time 10.97 seconds
Started Oct 12 02:31:26 PM UTC 24
Finished Oct 12 02:31:38 PM UTC 24
Peak memory 247264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644858388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.1644858388
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/35.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.2488051962
Short name T768
Test name
Test status
Simulation time 3575740393 ps
CPU time 13.23 seconds
Started Oct 12 02:31:23 PM UTC 24
Finished Oct 12 02:31:38 PM UTC 24
Peak memory 235000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488051962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2488051962
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/35.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.590902612
Short name T770
Test name
Test status
Simulation time 84050727 ps
CPU time 4.86 seconds
Started Oct 12 02:31:38 PM UTC 24
Finished Oct 12 02:31:44 PM UTC 24
Peak memory 233176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590902612 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.590902612
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/35.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.304422296
Short name T364
Test name
Test status
Simulation time 130580939882 ps
CPU time 355.75 seconds
Started Oct 12 02:31:42 PM UTC 24
Finished Oct 12 02:37:43 PM UTC 24
Peak memory 279912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304422296 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.304422296
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/35.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_all.615541738
Short name T771
Test name
Test status
Simulation time 6413520948 ps
CPU time 25.6 seconds
Started Oct 12 02:31:20 PM UTC 24
Finished Oct 12 02:31:47 PM UTC 24
Peak memory 231528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615541738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.615541738
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/35.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.596553505
Short name T761
Test name
Test status
Simulation time 5405891524 ps
CPU time 7.82 seconds
Started Oct 12 02:31:20 PM UTC 24
Finished Oct 12 02:31:29 PM UTC 24
Peak memory 227432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596553505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.596553505
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/35.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_rw.1382101351
Short name T763
Test name
Test status
Simulation time 358868782 ps
CPU time 5.75 seconds
Started Oct 12 02:31:22 PM UTC 24
Finished Oct 12 02:31:29 PM UTC 24
Peak memory 227500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382101351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1382101351
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/35.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.3253998476
Short name T760
Test name
Test status
Simulation time 33867611 ps
CPU time 1.27 seconds
Started Oct 12 02:31:22 PM UTC 24
Finished Oct 12 02:31:25 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253998476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3253998476
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/35.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/35.spi_device_upload.2541050660
Short name T786
Test name
Test status
Simulation time 7821970207 ps
CPU time 49.05 seconds
Started Oct 12 02:31:30 PM UTC 24
Finished Oct 12 02:32:21 PM UTC 24
Peak memory 251168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541050660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2541050660
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/35.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_alert_test.2626671149
Short name T730
Test name
Test status
Simulation time 17832272 ps
CPU time 1.09 seconds
Started Oct 12 02:32:22 PM UTC 24
Finished Oct 12 02:32:24 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626671149 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.2626671149
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/36.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_cfg_cmd.2988523382
Short name T787
Test name
Test status
Simulation time 4279582588 ps
CPU time 7.2 seconds
Started Oct 12 02:32:14 PM UTC 24
Finished Oct 12 02:32:22 PM UTC 24
Peak memory 234744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988523382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2988523382
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/36.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_csb_read.3533504590
Short name T773
Test name
Test status
Simulation time 15522855 ps
CPU time 1.16 seconds
Started Oct 12 02:31:47 PM UTC 24
Finished Oct 12 02:31:50 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533504590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3533504590
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/36.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_all.2200193927
Short name T1008
Test name
Test status
Simulation time 49177799572 ps
CPU time 421.31 seconds
Started Oct 12 02:32:16 PM UTC 24
Finished Oct 12 02:39:23 PM UTC 24
Peak memory 267616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200193927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2200193927
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/36.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.633661852
Short name T178
Test name
Test status
Simulation time 56488097580 ps
CPU time 109.26 seconds
Started Oct 12 02:32:20 PM UTC 24
Finished Oct 12 02:34:11 PM UTC 24
Peak memory 265560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633661852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.633661852
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode.3385537619
Short name T785
Test name
Test status
Simulation time 286492864 ps
CPU time 5.12 seconds
Started Oct 12 02:32:14 PM UTC 24
Finished Oct 12 02:32:20 PM UTC 24
Peak memory 248944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385537619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3385537619
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/36.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.2745471444
Short name T806
Test name
Test status
Simulation time 4776553864 ps
CPU time 39.95 seconds
Started Oct 12 02:32:16 PM UTC 24
Finished Oct 12 02:32:57 PM UTC 24
Peak memory 251160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745471444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.2745471444
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_intercept.1769600168
Short name T779
Test name
Test status
Simulation time 124226147 ps
CPU time 4.92 seconds
Started Oct 12 02:32:02 PM UTC 24
Finished Oct 12 02:32:08 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769600168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1769600168
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/36.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_mailbox.2247585307
Short name T783
Test name
Test status
Simulation time 3199438235 ps
CPU time 7.37 seconds
Started Oct 12 02:32:07 PM UTC 24
Finished Oct 12 02:32:15 PM UTC 24
Peak memory 245236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247585307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2247585307
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/36.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.2772438815
Short name T790
Test name
Test status
Simulation time 20287838661 ps
CPU time 23.67 seconds
Started Oct 12 02:32:01 PM UTC 24
Finished Oct 12 02:32:25 PM UTC 24
Peak memory 245088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772438815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.2772438815
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/36.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.2379707560
Short name T784
Test name
Test status
Simulation time 538897026 ps
CPU time 15.5 seconds
Started Oct 12 02:31:59 PM UTC 24
Finished Oct 12 02:32:16 PM UTC 24
Peak memory 244916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379707560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2379707560
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/36.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.1636604185
Short name T794
Test name
Test status
Simulation time 756698549 ps
CPU time 11.35 seconds
Started Oct 12 02:32:16 PM UTC 24
Finished Oct 12 02:32:29 PM UTC 24
Peak memory 229024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636604185 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.1636604185
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/36.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.3307278217
Short name T203
Test name
Test status
Simulation time 70172364 ps
CPU time 1.68 seconds
Started Oct 12 02:32:21 PM UTC 24
Finished Oct 12 02:32:24 PM UTC 24
Peak memory 215940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307278217 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.3307278217
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/36.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_all.1102174950
Short name T780
Test name
Test status
Simulation time 3823630034 ps
CPU time 20.8 seconds
Started Oct 12 02:31:51 PM UTC 24
Finished Oct 12 02:32:13 PM UTC 24
Peak memory 227372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102174950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1102174950
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/36.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.1445446026
Short name T781
Test name
Test status
Simulation time 10372367080 ps
CPU time 25.01 seconds
Started Oct 12 02:31:49 PM UTC 24
Finished Oct 12 02:32:15 PM UTC 24
Peak memory 227796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445446026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1445446026
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/36.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_rw.3548431497
Short name T777
Test name
Test status
Simulation time 16163619 ps
CPU time 1.09 seconds
Started Oct 12 02:31:58 PM UTC 24
Finished Oct 12 02:32:00 PM UTC 24
Peak memory 213472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548431497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3548431497
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/36.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.2427424699
Short name T775
Test name
Test status
Simulation time 80498287 ps
CPU time 1.49 seconds
Started Oct 12 02:31:55 PM UTC 24
Finished Oct 12 02:31:57 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427424699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2427424699
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/36.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_upload.990543779
Short name T788
Test name
Test status
Simulation time 1469343413 ps
CPU time 14.69 seconds
Started Oct 12 02:32:09 PM UTC 24
Finished Oct 12 02:32:25 PM UTC 24
Peak memory 244912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990543779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.990543779
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/36.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_alert_test.2473880550
Short name T804
Test name
Test status
Simulation time 66910506 ps
CPU time 1.11 seconds
Started Oct 12 02:32:51 PM UTC 24
Finished Oct 12 02:32:53 PM UTC 24
Peak memory 213464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473880550 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.2473880550
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/37.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_cfg_cmd.1397665493
Short name T800
Test name
Test status
Simulation time 981840853 ps
CPU time 14.11 seconds
Started Oct 12 02:32:30 PM UTC 24
Finished Oct 12 02:32:45 PM UTC 24
Peak memory 234932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397665493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1397665493
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/37.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_csb_read.657382331
Short name T789
Test name
Test status
Simulation time 58910895 ps
CPU time 1.17 seconds
Started Oct 12 02:32:23 PM UTC 24
Finished Oct 12 02:32:25 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657382331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.657382331
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/37.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.3231829092
Short name T809
Test name
Test status
Simulation time 2794658638 ps
CPU time 13.99 seconds
Started Oct 12 02:32:45 PM UTC 24
Finished Oct 12 02:33:00 PM UTC 24
Peak memory 261476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231829092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3231829092
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/37.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.1634267089
Short name T276
Test name
Test status
Simulation time 8997102878 ps
CPU time 133.93 seconds
Started Oct 12 02:32:46 PM UTC 24
Finished Oct 12 02:35:03 PM UTC 24
Peak memory 284264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634267089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1634267089
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/37.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.3787810873
Short name T369
Test name
Test status
Simulation time 2585994549 ps
CPU time 36.69 seconds
Started Oct 12 02:32:47 PM UTC 24
Finished Oct 12 02:33:26 PM UTC 24
Peak memory 245088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787810873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.3787810873
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.1966787890
Short name T866
Test name
Test status
Simulation time 17342953293 ps
CPU time 129.27 seconds
Started Oct 12 02:32:36 PM UTC 24
Finished Oct 12 02:34:47 PM UTC 24
Peak memory 267620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966787890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.1966787890
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_intercept.998665533
Short name T797
Test name
Test status
Simulation time 673233221 ps
CPU time 5.86 seconds
Started Oct 12 02:32:28 PM UTC 24
Finished Oct 12 02:32:34 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998665533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.998665533
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/37.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_mailbox.2188254
Short name T827
Test name
Test status
Simulation time 44359901038 ps
CPU time 57.45 seconds
Started Oct 12 02:32:29 PM UTC 24
Finished Oct 12 02:33:28 PM UTC 24
Peak memory 245348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM
_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_devi
ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2188254
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/37.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.2786547196
Short name T798
Test name
Test status
Simulation time 567157328 ps
CPU time 9.34 seconds
Started Oct 12 02:32:28 PM UTC 24
Finished Oct 12 02:32:38 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786547196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.2786547196
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/37.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.2818915712
Short name T796
Test name
Test status
Simulation time 469920022 ps
CPU time 3.19 seconds
Started Oct 12 02:32:27 PM UTC 24
Finished Oct 12 02:32:32 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818915712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2818915712
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/37.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.2520178727
Short name T801
Test name
Test status
Simulation time 550714036 ps
CPU time 6.09 seconds
Started Oct 12 02:32:39 PM UTC 24
Finished Oct 12 02:32:46 PM UTC 24
Peak memory 231148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520178727 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.2520178727
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/37.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.609870019
Short name T803
Test name
Test status
Simulation time 200694547 ps
CPU time 1.68 seconds
Started Oct 12 02:32:49 PM UTC 24
Finished Oct 12 02:32:51 PM UTC 24
Peak memory 216328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609870019 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.609870019
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/37.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_all.1223297420
Short name T813
Test name
Test status
Simulation time 28529465785 ps
CPU time 37.7 seconds
Started Oct 12 02:32:25 PM UTC 24
Finished Oct 12 02:33:04 PM UTC 24
Peak memory 227476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223297420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1223297420
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/37.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.2930137515
Short name T799
Test name
Test status
Simulation time 12073102138 ps
CPU time 17.84 seconds
Started Oct 12 02:32:25 PM UTC 24
Finished Oct 12 02:32:44 PM UTC 24
Peak memory 227364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930137515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2930137515
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/37.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_rw.4012000514
Short name T793
Test name
Test status
Simulation time 32918579 ps
CPU time 1.21 seconds
Started Oct 12 02:32:26 PM UTC 24
Finished Oct 12 02:32:28 PM UTC 24
Peak memory 216392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012000514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.4012000514
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/37.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.2936683632
Short name T795
Test name
Test status
Simulation time 114923486 ps
CPU time 1.71 seconds
Started Oct 12 02:32:26 PM UTC 24
Finished Oct 12 02:32:29 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936683632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2936683632
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/37.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_upload.1871586129
Short name T802
Test name
Test status
Simulation time 4340955564 ps
CPU time 18.91 seconds
Started Oct 12 02:32:30 PM UTC 24
Finished Oct 12 02:32:50 PM UTC 24
Peak memory 234848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871586129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1871586129
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/37.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_alert_test.1174272051
Short name T820
Test name
Test status
Simulation time 44703351 ps
CPU time 1.08 seconds
Started Oct 12 02:33:12 PM UTC 24
Finished Oct 12 02:33:14 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174272051 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.1174272051
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/38.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_cfg_cmd.1142429001
Short name T815
Test name
Test status
Simulation time 34415552 ps
CPU time 2.16 seconds
Started Oct 12 02:33:04 PM UTC 24
Finished Oct 12 02:33:08 PM UTC 24
Peak memory 234712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142429001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1142429001
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/38.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_csb_read.1775588594
Short name T805
Test name
Test status
Simulation time 21170929 ps
CPU time 1.25 seconds
Started Oct 12 02:32:52 PM UTC 24
Finished Oct 12 02:32:54 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775588594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1775588594
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/38.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_all.1527817554
Short name T825
Test name
Test status
Simulation time 554218292 ps
CPU time 14.21 seconds
Started Oct 12 02:33:09 PM UTC 24
Finished Oct 12 02:33:25 PM UTC 24
Peak memory 248996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527817554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1527817554
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/38.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.4204607779
Short name T884
Test name
Test status
Simulation time 5923462444 ps
CPU time 127.95 seconds
Started Oct 12 02:33:09 PM UTC 24
Finished Oct 12 02:35:20 PM UTC 24
Peak memory 277868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204607779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.4204607779
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/38.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.1186148395
Short name T354
Test name
Test status
Simulation time 10164989222 ps
CPU time 100.7 seconds
Started Oct 12 02:33:10 PM UTC 24
Finished Oct 12 02:34:53 PM UTC 24
Peak memory 277912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186148395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.1186148395
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode.1456946110
Short name T817
Test name
Test status
Simulation time 116807666 ps
CPU time 3.48 seconds
Started Oct 12 02:33:04 PM UTC 24
Finished Oct 12 02:33:09 PM UTC 24
Peak memory 245216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456946110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1456946110
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/38.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.32319691
Short name T904
Test name
Test status
Simulation time 34244910161 ps
CPU time 188.96 seconds
Started Oct 12 02:33:06 PM UTC 24
Finished Oct 12 02:36:18 PM UTC 24
Peak memory 261720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32319691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.32319691
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_intercept.730795873
Short name T818
Test name
Test status
Simulation time 494055750 ps
CPU time 6.95 seconds
Started Oct 12 02:33:02 PM UTC 24
Finished Oct 12 02:33:10 PM UTC 24
Peak memory 234720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730795873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.730795873
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/38.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_mailbox.2068413183
Short name T850
Test name
Test status
Simulation time 30273171065 ps
CPU time 78.26 seconds
Started Oct 12 02:33:02 PM UTC 24
Finished Oct 12 02:34:22 PM UTC 24
Peak memory 245084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068413183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2068413183
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/38.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.408039607
Short name T812
Test name
Test status
Simulation time 136825979 ps
CPU time 3.15 seconds
Started Oct 12 02:32:59 PM UTC 24
Finished Oct 12 02:33:04 PM UTC 24
Peak memory 245112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408039607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.408039607
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/38.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.2028957709
Short name T830
Test name
Test status
Simulation time 50232054036 ps
CPU time 33.91 seconds
Started Oct 12 02:32:59 PM UTC 24
Finished Oct 12 02:33:35 PM UTC 24
Peak memory 245280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028957709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2028957709
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/38.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.2149197022
Short name T822
Test name
Test status
Simulation time 1853651202 ps
CPU time 12.27 seconds
Started Oct 12 02:33:06 PM UTC 24
Finished Oct 12 02:33:19 PM UTC 24
Peak memory 229024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149197022 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.2149197022
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/38.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.2840527432
Short name T891
Test name
Test status
Simulation time 5035594024 ps
CPU time 140.72 seconds
Started Oct 12 02:33:12 PM UTC 24
Finished Oct 12 02:35:35 PM UTC 24
Peak memory 277860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840527432 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.2840527432
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/38.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_all.3652476535
Short name T807
Test name
Test status
Simulation time 11705533 ps
CPU time 1.13 seconds
Started Oct 12 02:32:56 PM UTC 24
Finished Oct 12 02:32:58 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652476535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3652476535
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/38.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.2432443200
Short name T810
Test name
Test status
Simulation time 2438081515 ps
CPU time 5.28 seconds
Started Oct 12 02:32:54 PM UTC 24
Finished Oct 12 02:33:01 PM UTC 24
Peak memory 227440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432443200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2432443200
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/38.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_rw.1645463729
Short name T811
Test name
Test status
Simulation time 13301019 ps
CPU time 1.09 seconds
Started Oct 12 02:32:59 PM UTC 24
Finished Oct 12 02:33:01 PM UTC 24
Peak memory 213400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645463729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1645463729
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/38.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.2853333162
Short name T808
Test name
Test status
Simulation time 149405957 ps
CPU time 1.34 seconds
Started Oct 12 02:32:56 PM UTC 24
Finished Oct 12 02:32:58 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853333162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2853333162
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/38.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/38.spi_device_upload.2664434602
Short name T816
Test name
Test status
Simulation time 1688261037 ps
CPU time 5.53 seconds
Started Oct 12 02:33:02 PM UTC 24
Finished Oct 12 02:33:09 PM UTC 24
Peak memory 244980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664434602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2664434602
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/38.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_alert_test.3588790375
Short name T836
Test name
Test status
Simulation time 42196074 ps
CPU time 1.11 seconds
Started Oct 12 02:33:49 PM UTC 24
Finished Oct 12 02:33:51 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588790375 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.3588790375
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/39.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_cfg_cmd.1416935919
Short name T833
Test name
Test status
Simulation time 1851407943 ps
CPU time 5.51 seconds
Started Oct 12 02:33:33 PM UTC 24
Finished Oct 12 02:33:40 PM UTC 24
Peak memory 245156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416935919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1416935919
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/39.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_csb_read.899351430
Short name T821
Test name
Test status
Simulation time 19837044 ps
CPU time 1.23 seconds
Started Oct 12 02:33:13 PM UTC 24
Finished Oct 12 02:33:15 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899351430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.899351430
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/39.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.1612973669
Short name T1034
Test name
Test status
Simulation time 319476616261 ps
CPU time 603.4 seconds
Started Oct 12 02:33:39 PM UTC 24
Finished Oct 12 02:43:50 PM UTC 24
Peak memory 275876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612973669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1612973669
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/39.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.3866668285
Short name T852
Test name
Test status
Simulation time 25729575436 ps
CPU time 42.87 seconds
Started Oct 12 02:33:41 PM UTC 24
Finished Oct 12 02:34:26 PM UTC 24
Peak memory 247132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866668285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3866668285
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/39.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.2463028321
Short name T930
Test name
Test status
Simulation time 25343416658 ps
CPU time 214.52 seconds
Started Oct 12 02:33:43 PM UTC 24
Finished Oct 12 02:37:21 PM UTC 24
Peak memory 245144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463028321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.2463028321
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.424839277
Short name T834
Test name
Test status
Simulation time 451878581 ps
CPU time 5.51 seconds
Started Oct 12 02:33:35 PM UTC 24
Finished Oct 12 02:33:42 PM UTC 24
Peak memory 244892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424839277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.424839277
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/39.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.3100002842
Short name T832
Test name
Test status
Simulation time 55112134 ps
CPU time 1.55 seconds
Started Oct 12 02:33:36 PM UTC 24
Finished Oct 12 02:33:38 PM UTC 24
Peak memory 225164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100002842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.3100002842
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_intercept.4186916368
Short name T828
Test name
Test status
Simulation time 67628638 ps
CPU time 4.3 seconds
Started Oct 12 02:33:27 PM UTC 24
Finished Oct 12 02:33:32 PM UTC 24
Peak memory 241964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186916368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.4186916368
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/39.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_mailbox.1604619325
Short name T870
Test name
Test status
Simulation time 46608043077 ps
CPU time 91.49 seconds
Started Oct 12 02:33:27 PM UTC 24
Finished Oct 12 02:35:00 PM UTC 24
Peak memory 244984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604619325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1604619325
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/39.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.1900787683
Short name T835
Test name
Test status
Simulation time 31973163836 ps
CPU time 20.36 seconds
Started Oct 12 02:33:27 PM UTC 24
Finished Oct 12 02:33:48 PM UTC 24
Peak memory 245280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900787683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.1900787683
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/39.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.1580962244
Short name T829
Test name
Test status
Simulation time 5335005848 ps
CPU time 9.76 seconds
Started Oct 12 02:33:23 PM UTC 24
Finished Oct 12 02:33:34 PM UTC 24
Peak memory 245364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580962244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1580962244
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/39.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.203906570
Short name T838
Test name
Test status
Simulation time 1044843033 ps
CPU time 16.41 seconds
Started Oct 12 02:33:38 PM UTC 24
Finished Oct 12 02:33:55 PM UTC 24
Peak memory 233228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203906570 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.203906570
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/39.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.1720434195
Short name T1004
Test name
Test status
Simulation time 45916822997 ps
CPU time 325.66 seconds
Started Oct 12 02:33:47 PM UTC 24
Finished Oct 12 02:39:16 PM UTC 24
Peak memory 263520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720434195 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.1720434195
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/39.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.1504710190
Short name T840
Test name
Test status
Simulation time 1456084024 ps
CPU time 40 seconds
Started Oct 12 02:33:17 PM UTC 24
Finished Oct 12 02:33:58 PM UTC 24
Peak memory 227308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504710190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1504710190
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/39.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.3274645046
Short name T823
Test name
Test status
Simulation time 1479008642 ps
CPU time 5.03 seconds
Started Oct 12 02:33:15 PM UTC 24
Finished Oct 12 02:33:21 PM UTC 24
Peak memory 227308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274645046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3274645046
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/39.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_rw.3962052601
Short name T826
Test name
Test status
Simulation time 11353551 ps
CPU time 1.09 seconds
Started Oct 12 02:33:23 PM UTC 24
Finished Oct 12 02:33:25 PM UTC 24
Peak memory 213472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962052601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3962052601
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/39.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.747457412
Short name T824
Test name
Test status
Simulation time 85807161 ps
CPU time 1.56 seconds
Started Oct 12 02:33:20 PM UTC 24
Finished Oct 12 02:33:22 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747457412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.747457412
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/39.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/39.spi_device_upload.998190488
Short name T839
Test name
Test status
Simulation time 2984348143 ps
CPU time 26.34 seconds
Started Oct 12 02:33:29 PM UTC 24
Finished Oct 12 02:33:57 PM UTC 24
Peak memory 251232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998190488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.998190488
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/39.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.619469743
Short name T107
Test name
Test status
Simulation time 17915425 ps
CPU time 0.85 seconds
Started Oct 12 02:19:14 PM UTC 24
Finished Oct 12 02:19:16 PM UTC 24
Peak memory 213464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619469743 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.619469743
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.3041205116
Short name T405
Test name
Test status
Simulation time 18787196902 ps
CPU time 15.07 seconds
Started Oct 12 02:19:09 PM UTC 24
Finished Oct 12 02:19:25 PM UTC 24
Peak memory 234840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041205116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3041205116
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.3328431824
Short name T403
Test name
Test status
Simulation time 157935769 ps
CPU time 1.07 seconds
Started Oct 12 02:19:04 PM UTC 24
Finished Oct 12 02:19:06 PM UTC 24
Peak memory 213544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328431824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3328431824
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.3522615909
Short name T68
Test name
Test status
Simulation time 58170207215 ps
CPU time 126.36 seconds
Started Oct 12 02:19:10 PM UTC 24
Finished Oct 12 02:21:19 PM UTC 24
Peak memory 261380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522615909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3522615909
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.3413031417
Short name T385
Test name
Test status
Simulation time 43649593774 ps
CPU time 174.4 seconds
Started Oct 12 02:19:11 PM UTC 24
Finished Oct 12 02:22:09 PM UTC 24
Peak memory 251276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413031417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3413031417
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.3154362952
Short name T226
Test name
Test status
Simulation time 217128724808 ps
CPU time 237.55 seconds
Started Oct 12 02:19:09 PM UTC 24
Finished Oct 12 02:23:11 PM UTC 24
Peak memory 267620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154362952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.3154362952
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.220534920
Short name T77
Test name
Test status
Simulation time 279037416 ps
CPU time 4.02 seconds
Started Oct 12 02:19:08 PM UTC 24
Finished Oct 12 02:19:13 PM UTC 24
Peak memory 234720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220534920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.220534920
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.4231937739
Short name T269
Test name
Test status
Simulation time 71521019000 ps
CPU time 66.89 seconds
Started Oct 12 02:19:08 PM UTC 24
Finished Oct 12 02:20:16 PM UTC 24
Peak memory 261408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231937739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4231937739
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.2594920173
Short name T404
Test name
Test status
Simulation time 60026984 ps
CPU time 1.59 seconds
Started Oct 12 02:19:05 PM UTC 24
Finished Oct 12 02:19:08 PM UTC 24
Peak memory 228880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594920173 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_parity.2594920173
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.1731391957
Short name T69
Test name
Test status
Simulation time 13163603625 ps
CPU time 17.95 seconds
Started Oct 12 02:19:07 PM UTC 24
Finished Oct 12 02:19:26 PM UTC 24
Peak memory 234908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731391957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.1731391957
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.3317804610
Short name T76
Test name
Test status
Simulation time 1571003592 ps
CPU time 3.6 seconds
Started Oct 12 02:19:07 PM UTC 24
Finished Oct 12 02:19:11 PM UTC 24
Peak memory 234624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317804610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3317804610
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.2251872027
Short name T80
Test name
Test status
Simulation time 1000923152 ps
CPU time 6.75 seconds
Started Oct 12 02:19:10 PM UTC 24
Finished Oct 12 02:19:18 PM UTC 24
Peak memory 233320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251872027 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.2251872027
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.824292177
Short name T39
Test name
Test status
Simulation time 66474161 ps
CPU time 1.64 seconds
Started Oct 12 02:19:13 PM UTC 24
Finished Oct 12 02:19:15 PM UTC 24
Peak memory 256904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824292177 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.824292177
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.1722641189
Short name T38
Test name
Test status
Simulation time 154335301 ps
CPU time 1.13 seconds
Started Oct 12 02:19:11 PM UTC 24
Finished Oct 12 02:19:14 PM UTC 24
Peak memory 226164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722641189 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.1722641189
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.2063681521
Short name T78
Test name
Test status
Simulation time 504549253 ps
CPU time 7.15 seconds
Started Oct 12 02:19:05 PM UTC 24
Finished Oct 12 02:19:14 PM UTC 24
Peak memory 227556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063681521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2063681521
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2418791275
Short name T118
Test name
Test status
Simulation time 515586268 ps
CPU time 4.42 seconds
Started Oct 12 02:19:05 PM UTC 24
Finished Oct 12 02:19:11 PM UTC 24
Peak memory 227220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418791275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2418791275
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.3718282180
Short name T27
Test name
Test status
Simulation time 200313937 ps
CPU time 1.58 seconds
Started Oct 12 02:19:07 PM UTC 24
Finished Oct 12 02:19:09 PM UTC 24
Peak memory 216684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718282180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3718282180
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.3865958693
Short name T120
Test name
Test status
Simulation time 58093891 ps
CPU time 1.28 seconds
Started Oct 12 02:19:05 PM UTC 24
Finished Oct 12 02:19:08 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865958693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3865958693
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.1224311301
Short name T79
Test name
Test status
Simulation time 1913754279 ps
CPU time 7.87 seconds
Started Oct 12 02:19:08 PM UTC 24
Finished Oct 12 02:19:17 PM UTC 24
Peak memory 234720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224311301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1224311301
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/4.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.2203674922
Short name T854
Test name
Test status
Simulation time 13865793 ps
CPU time 1.05 seconds
Started Oct 12 02:34:27 PM UTC 24
Finished Oct 12 02:34:29 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203674922 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.2203674922
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/40.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_cfg_cmd.2474494068
Short name T849
Test name
Test status
Simulation time 174446466 ps
CPU time 5.01 seconds
Started Oct 12 02:34:15 PM UTC 24
Finished Oct 12 02:34:21 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474494068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2474494068
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/40.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_csb_read.1956331549
Short name T837
Test name
Test status
Simulation time 163395363 ps
CPU time 1.16 seconds
Started Oct 12 02:33:52 PM UTC 24
Finished Oct 12 02:33:54 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956331549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1956331549
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/40.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.342355400
Short name T915
Test name
Test status
Simulation time 64693882055 ps
CPU time 141.12 seconds
Started Oct 12 02:34:21 PM UTC 24
Finished Oct 12 02:36:45 PM UTC 24
Peak memory 251492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342355400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.342355400
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/40.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.966814100
Short name T948
Test name
Test status
Simulation time 101900524288 ps
CPU time 208.77 seconds
Started Oct 12 02:34:22 PM UTC 24
Finished Oct 12 02:37:54 PM UTC 24
Peak memory 261788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966814100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.966814100
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.2205847249
Short name T885
Test name
Test status
Simulation time 8328457011 ps
CPU time 56.29 seconds
Started Oct 12 02:34:23 PM UTC 24
Finished Oct 12 02:35:21 PM UTC 24
Peak memory 265868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205847249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.2205847249
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.1895110762
Short name T851
Test name
Test status
Simulation time 386320400 ps
CPU time 5.76 seconds
Started Oct 12 02:34:16 PM UTC 24
Finished Oct 12 02:34:23 PM UTC 24
Peak memory 245212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895110762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1895110762
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/40.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.3966422255
Short name T918
Test name
Test status
Simulation time 9749342141 ps
CPU time 144.97 seconds
Started Oct 12 02:34:18 PM UTC 24
Finished Oct 12 02:36:45 PM UTC 24
Peak memory 261408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966422255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.3966422255
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_intercept.2071894124
Short name T862
Test name
Test status
Simulation time 9672607861 ps
CPU time 27.51 seconds
Started Oct 12 02:34:10 PM UTC 24
Finished Oct 12 02:34:38 PM UTC 24
Peak memory 234744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071894124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2071894124
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/40.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.1159148055
Short name T847
Test name
Test status
Simulation time 350052918 ps
CPU time 3.68 seconds
Started Oct 12 02:34:12 PM UTC 24
Finished Oct 12 02:34:16 PM UTC 24
Peak memory 244964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159148055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1159148055
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/40.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.2969519462
Short name T845
Test name
Test status
Simulation time 2806861844 ps
CPU time 7.79 seconds
Started Oct 12 02:34:05 PM UTC 24
Finished Oct 12 02:34:14 PM UTC 24
Peak memory 235124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969519462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.2969519462
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/40.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.946892093
Short name T843
Test name
Test status
Simulation time 180294956 ps
CPU time 6.77 seconds
Started Oct 12 02:34:01 PM UTC 24
Finished Oct 12 02:34:09 PM UTC 24
Peak memory 234620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946892093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.946892093
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/40.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.2556993683
Short name T857
Test name
Test status
Simulation time 1201113721 ps
CPU time 10.17 seconds
Started Oct 12 02:34:21 PM UTC 24
Finished Oct 12 02:34:32 PM UTC 24
Peak memory 233180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556993683 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.2556993683
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/40.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.2823812714
Short name T853
Test name
Test status
Simulation time 90465177 ps
CPU time 1.47 seconds
Started Oct 12 02:34:25 PM UTC 24
Finished Oct 12 02:34:27 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823812714 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.2823812714
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/40.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.2228468455
Short name T844
Test name
Test status
Simulation time 409464152 ps
CPU time 14.31 seconds
Started Oct 12 02:33:57 PM UTC 24
Finished Oct 12 02:34:12 PM UTC 24
Peak memory 227288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228468455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2228468455
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/40.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.3802646837
Short name T848
Test name
Test status
Simulation time 4716666254 ps
CPU time 23.12 seconds
Started Oct 12 02:33:55 PM UTC 24
Finished Oct 12 02:34:20 PM UTC 24
Peak memory 227324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802646837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3802646837
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/40.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_rw.2055334297
Short name T842
Test name
Test status
Simulation time 141478609 ps
CPU time 4.29 seconds
Started Oct 12 02:33:59 PM UTC 24
Finished Oct 12 02:34:04 PM UTC 24
Peak memory 227308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055334297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2055334297
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/40.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.1826017475
Short name T841
Test name
Test status
Simulation time 24693396 ps
CPU time 1.22 seconds
Started Oct 12 02:33:58 PM UTC 24
Finished Oct 12 02:34:00 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826017475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1826017475
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/40.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.2837131245
Short name T856
Test name
Test status
Simulation time 5118426111 ps
CPU time 17.18 seconds
Started Oct 12 02:34:13 PM UTC 24
Finished Oct 12 02:34:31 PM UTC 24
Peak memory 245028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837131245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2837131245
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/40.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.2902470256
Short name T871
Test name
Test status
Simulation time 12849466 ps
CPU time 1.12 seconds
Started Oct 12 02:34:59 PM UTC 24
Finished Oct 12 02:35:01 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902470256 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.2902470256
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/41.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.1038265254
Short name T868
Test name
Test status
Simulation time 4087917173 ps
CPU time 12.43 seconds
Started Oct 12 02:34:41 PM UTC 24
Finished Oct 12 02:34:55 PM UTC 24
Peak memory 235104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038265254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1038265254
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/41.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.2206136573
Short name T855
Test name
Test status
Simulation time 24094659 ps
CPU time 1.2 seconds
Started Oct 12 02:34:28 PM UTC 24
Finished Oct 12 02:34:30 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206136573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2206136573
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/41.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.813463299
Short name T989
Test name
Test status
Simulation time 141448722533 ps
CPU time 250.04 seconds
Started Oct 12 02:34:49 PM UTC 24
Finished Oct 12 02:39:03 PM UTC 24
Peak memory 276008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813463299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.813463299
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/41.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.90203719
Short name T1000
Test name
Test status
Simulation time 94628789586 ps
CPU time 256.38 seconds
Started Oct 12 02:34:51 PM UTC 24
Finished Oct 12 02:39:11 PM UTC 24
Peak memory 261448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90203719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.90203719
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.1717861517
Short name T900
Test name
Test status
Simulation time 2922864785 ps
CPU time 59.93 seconds
Started Oct 12 02:34:54 PM UTC 24
Finished Oct 12 02:35:56 PM UTC 24
Peak memory 261472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717861517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.1717861517
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.1475391989
Short name T377
Test name
Test status
Simulation time 14183981290 ps
CPU time 25.12 seconds
Started Oct 12 02:34:45 PM UTC 24
Finished Oct 12 02:35:11 PM UTC 24
Peak memory 251232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475391989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1475391989
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/41.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.3471302152
Short name T1032
Test name
Test status
Simulation time 246217770626 ps
CPU time 475.82 seconds
Started Oct 12 02:34:45 PM UTC 24
Finished Oct 12 02:42:47 PM UTC 24
Peak memory 261728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471302152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.3471302152
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.2891303106
Short name T865
Test name
Test status
Simulation time 1621299494 ps
CPU time 9.34 seconds
Started Oct 12 02:34:37 PM UTC 24
Finished Oct 12 02:34:47 PM UTC 24
Peak memory 234716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891303106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2891303106
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/41.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.2894258109
Short name T896
Test name
Test status
Simulation time 22383093950 ps
CPU time 69.73 seconds
Started Oct 12 02:34:37 PM UTC 24
Finished Oct 12 02:35:48 PM UTC 24
Peak memory 251172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894258109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2894258109
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/41.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.262672907
Short name T873
Test name
Test status
Simulation time 4353748232 ps
CPU time 25.89 seconds
Started Oct 12 02:34:35 PM UTC 24
Finished Oct 12 02:35:02 PM UTC 24
Peak memory 245044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262672907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.262672907
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/41.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.3505101026
Short name T872
Test name
Test status
Simulation time 25288017324 ps
CPU time 27.86 seconds
Started Oct 12 02:34:33 PM UTC 24
Finished Oct 12 02:35:02 PM UTC 24
Peak memory 251116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505101026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3505101026
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/41.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.2720335030
Short name T869
Test name
Test status
Simulation time 894053988 ps
CPU time 8.68 seconds
Started Oct 12 02:34:48 PM UTC 24
Finished Oct 12 02:34:58 PM UTC 24
Peak memory 233164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720335030 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.2720335030
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/41.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.4075067839
Short name T89
Test name
Test status
Simulation time 383546826117 ps
CPU time 841.18 seconds
Started Oct 12 02:34:56 PM UTC 24
Finished Oct 12 02:49:07 PM UTC 24
Peak memory 302372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075067839 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.4075067839
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/41.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.3272454967
Short name T867
Test name
Test status
Simulation time 11212497506 ps
CPU time 18.45 seconds
Started Oct 12 02:34:31 PM UTC 24
Finished Oct 12 02:34:50 PM UTC 24
Peak memory 227372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272454967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3272454967
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/41.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.2299576143
Short name T863
Test name
Test status
Simulation time 8776026674 ps
CPU time 8.19 seconds
Started Oct 12 02:34:30 PM UTC 24
Finished Oct 12 02:34:40 PM UTC 24
Peak memory 227428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299576143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2299576143
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/41.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.1812945984
Short name T861
Test name
Test status
Simulation time 83209368 ps
CPU time 1.61 seconds
Started Oct 12 02:34:33 PM UTC 24
Finished Oct 12 02:34:36 PM UTC 24
Peak memory 216392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812945984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1812945984
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/41.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.682856150
Short name T858
Test name
Test status
Simulation time 70618321 ps
CPU time 1.47 seconds
Started Oct 12 02:34:32 PM UTC 24
Finished Oct 12 02:34:34 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682856150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.682856150
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/41.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.2663469226
Short name T864
Test name
Test status
Simulation time 238538162 ps
CPU time 3.08 seconds
Started Oct 12 02:34:39 PM UTC 24
Finished Oct 12 02:34:43 PM UTC 24
Peak memory 234664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663469226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2663469226
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/41.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.3979190069
Short name T888
Test name
Test status
Simulation time 36502586 ps
CPU time 1.11 seconds
Started Oct 12 02:35:28 PM UTC 24
Finished Oct 12 02:35:30 PM UTC 24
Peak memory 213464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979190069 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.3979190069
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/42.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3963732765
Short name T881
Test name
Test status
Simulation time 84506361 ps
CPU time 2.97 seconds
Started Oct 12 02:35:14 PM UTC 24
Finished Oct 12 02:35:18 PM UTC 24
Peak memory 244956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963732765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3963732765
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/42.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.58595952
Short name T874
Test name
Test status
Simulation time 20934012 ps
CPU time 1.24 seconds
Started Oct 12 02:35:01 PM UTC 24
Finished Oct 12 02:35:04 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58595952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.58595952
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/42.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.728424570
Short name T368
Test name
Test status
Simulation time 33576812164 ps
CPU time 121.51 seconds
Started Oct 12 02:35:21 PM UTC 24
Finished Oct 12 02:37:25 PM UTC 24
Peak memory 265508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728424570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.728424570
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/42.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.46955243
Short name T367
Test name
Test status
Simulation time 2597665488 ps
CPU time 76.65 seconds
Started Oct 12 02:35:21 PM UTC 24
Finished Oct 12 02:36:40 PM UTC 24
Peak memory 261768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46955243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.46955243
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.104497123
Short name T1027
Test name
Test status
Simulation time 124812687399 ps
CPU time 342.42 seconds
Started Oct 12 02:35:22 PM UTC 24
Finished Oct 12 02:41:10 PM UTC 24
Peak memory 267936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104497123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.104497123
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.3571355877
Short name T890
Test name
Test status
Simulation time 2302108006 ps
CPU time 15.93 seconds
Started Oct 12 02:35:16 PM UTC 24
Finished Oct 12 02:35:34 PM UTC 24
Peak memory 261412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571355877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3571355877
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/42.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.3773373654
Short name T925
Test name
Test status
Simulation time 89824283310 ps
CPU time 105.56 seconds
Started Oct 12 02:35:19 PM UTC 24
Finished Oct 12 02:37:06 PM UTC 24
Peak memory 263464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773373654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.3773373654
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.3184367886
Short name T879
Test name
Test status
Simulation time 732112951 ps
CPU time 6.61 seconds
Started Oct 12 02:35:07 PM UTC 24
Finished Oct 12 02:35:15 PM UTC 24
Peak memory 244904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184367886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3184367886
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/42.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.703755795
Short name T897
Test name
Test status
Simulation time 9433735175 ps
CPU time 41.67 seconds
Started Oct 12 02:35:10 PM UTC 24
Finished Oct 12 02:35:53 PM UTC 24
Peak memory 239836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703755795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.703755795
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/42.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.1479263838
Short name T887
Test name
Test status
Simulation time 3259002103 ps
CPU time 20.06 seconds
Started Oct 12 02:35:07 PM UTC 24
Finished Oct 12 02:35:29 PM UTC 24
Peak memory 234748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479263838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.1479263838
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/42.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.27888986
Short name T877
Test name
Test status
Simulation time 138159599 ps
CPU time 2.58 seconds
Started Oct 12 02:35:05 PM UTC 24
Finished Oct 12 02:35:09 PM UTC 24
Peak memory 234276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27888986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.27888986
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/42.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2965779193
Short name T886
Test name
Test status
Simulation time 465983129 ps
CPU time 6 seconds
Started Oct 12 02:35:20 PM UTC 24
Finished Oct 12 02:35:27 PM UTC 24
Peak memory 231072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965779193 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.2965779193
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/42.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.1733673744
Short name T882
Test name
Test status
Simulation time 18315247727 ps
CPU time 14.87 seconds
Started Oct 12 02:35:04 PM UTC 24
Finished Oct 12 02:35:20 PM UTC 24
Peak memory 227732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733673744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1733673744
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/42.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.1716238605
Short name T878
Test name
Test status
Simulation time 3746661998 ps
CPU time 8.89 seconds
Started Oct 12 02:35:02 PM UTC 24
Finished Oct 12 02:35:13 PM UTC 24
Peak memory 227372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716238605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1716238605
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/42.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.4157801902
Short name T875
Test name
Test status
Simulation time 31342675 ps
CPU time 1.45 seconds
Started Oct 12 02:35:04 PM UTC 24
Finished Oct 12 02:35:06 PM UTC 24
Peak memory 216392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157801902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.4157801902
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/42.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.353893772
Short name T876
Test name
Test status
Simulation time 75739587 ps
CPU time 1.48 seconds
Started Oct 12 02:35:04 PM UTC 24
Finished Oct 12 02:35:07 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353893772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.353893772
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/42.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.1997795869
Short name T883
Test name
Test status
Simulation time 1439926288 ps
CPU time 7.39 seconds
Started Oct 12 02:35:12 PM UTC 24
Finished Oct 12 02:35:20 PM UTC 24
Peak memory 245116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997795869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1997795869
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/42.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.205031087
Short name T906
Test name
Test status
Simulation time 22811193 ps
CPU time 1.13 seconds
Started Oct 12 02:36:19 PM UTC 24
Finished Oct 12 02:36:21 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205031087 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.205031087
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/43.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.1339802944
Short name T903
Test name
Test status
Simulation time 929370646 ps
CPU time 13.61 seconds
Started Oct 12 02:35:54 PM UTC 24
Finished Oct 12 02:36:09 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339802944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1339802944
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/43.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.3216932398
Short name T889
Test name
Test status
Simulation time 41373875 ps
CPU time 1.2 seconds
Started Oct 12 02:35:30 PM UTC 24
Finished Oct 12 02:35:32 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216932398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3216932398
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/43.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.3529452765
Short name T366
Test name
Test status
Simulation time 40394898150 ps
CPU time 153.7 seconds
Started Oct 12 02:36:02 PM UTC 24
Finished Oct 12 02:38:38 PM UTC 24
Peak memory 283936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529452765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3529452765
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/43.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.2131034444
Short name T363
Test name
Test status
Simulation time 1065272770 ps
CPU time 9.04 seconds
Started Oct 12 02:36:06 PM UTC 24
Finished Oct 12 02:36:16 PM UTC 24
Peak memory 234896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131034444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2131034444
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.2783138781
Short name T935
Test name
Test status
Simulation time 12357709347 ps
CPU time 78.86 seconds
Started Oct 12 02:36:09 PM UTC 24
Finished Oct 12 02:37:30 PM UTC 24
Peak memory 245304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783138781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.2783138781
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.613383537
Short name T902
Test name
Test status
Simulation time 1183770512 ps
CPU time 9.21 seconds
Started Oct 12 02:35:55 PM UTC 24
Finished Oct 12 02:36:06 PM UTC 24
Peak memory 244904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613383537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.613383537
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/43.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.3804662449
Short name T931
Test name
Test status
Simulation time 36861845008 ps
CPU time 88.17 seconds
Started Oct 12 02:35:56 PM UTC 24
Finished Oct 12 02:37:26 PM UTC 24
Peak memory 261468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804662449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.3804662449
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.150942599
Short name T898
Test name
Test status
Simulation time 1709218997 ps
CPU time 11.97 seconds
Started Oct 12 02:35:41 PM UTC 24
Finished Oct 12 02:35:54 PM UTC 24
Peak memory 244896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150942599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.150942599
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/43.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.2488609065
Short name T911
Test name
Test status
Simulation time 11165758255 ps
CPU time 44.31 seconds
Started Oct 12 02:35:46 PM UTC 24
Finished Oct 12 02:36:32 PM UTC 24
Peak memory 245024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488609065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2488609065
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/43.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.3100728972
Short name T901
Test name
Test status
Simulation time 11353811354 ps
CPU time 20.68 seconds
Started Oct 12 02:35:39 PM UTC 24
Finished Oct 12 02:36:01 PM UTC 24
Peak memory 245348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100728972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.3100728972
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/43.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.1062244093
Short name T895
Test name
Test status
Simulation time 1695714240 ps
CPU time 6.13 seconds
Started Oct 12 02:35:38 PM UTC 24
Finished Oct 12 02:35:45 PM UTC 24
Peak memory 244980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062244093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1062244093
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/43.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.2136795675
Short name T912
Test name
Test status
Simulation time 2580794947 ps
CPU time 33.98 seconds
Started Oct 12 02:35:58 PM UTC 24
Finished Oct 12 02:36:33 PM UTC 24
Peak memory 233356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136795675 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.2136795675
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/43.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.283058361
Short name T90
Test name
Test status
Simulation time 67701753704 ps
CPU time 854.93 seconds
Started Oct 12 02:36:17 PM UTC 24
Finished Oct 12 02:50:43 PM UTC 24
Peak memory 286132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283058361 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.283058361
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/43.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.1536827178
Short name T899
Test name
Test status
Simulation time 2601464192 ps
CPU time 20.33 seconds
Started Oct 12 02:35:33 PM UTC 24
Finished Oct 12 02:35:55 PM UTC 24
Peak memory 227688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536827178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1536827178
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/43.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.296484415
Short name T894
Test name
Test status
Simulation time 2254435968 ps
CPU time 7.89 seconds
Started Oct 12 02:35:31 PM UTC 24
Finished Oct 12 02:35:40 PM UTC 24
Peak memory 227376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296484415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.296484415
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/43.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.4115978928
Short name T893
Test name
Test status
Simulation time 199648817 ps
CPU time 1.82 seconds
Started Oct 12 02:35:36 PM UTC 24
Finished Oct 12 02:35:38 PM UTC 24
Peak memory 216352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115978928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.4115978928
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/43.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.2945322198
Short name T892
Test name
Test status
Simulation time 101571390 ps
CPU time 1.27 seconds
Started Oct 12 02:35:35 PM UTC 24
Finished Oct 12 02:35:37 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945322198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2945322198
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/43.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.2931787834
Short name T907
Test name
Test status
Simulation time 16157494140 ps
CPU time 31.75 seconds
Started Oct 12 02:35:49 PM UTC 24
Finished Oct 12 02:36:22 PM UTC 24
Peak memory 234908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931787834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2931787834
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/43.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.1706693166
Short name T859
Test name
Test status
Simulation time 13867136 ps
CPU time 1.14 seconds
Started Oct 12 02:36:55 PM UTC 24
Finished Oct 12 02:36:57 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706693166 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.1706693166
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/44.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.765121207
Short name T917
Test name
Test status
Simulation time 164200506 ps
CPU time 2.88 seconds
Started Oct 12 02:36:41 PM UTC 24
Finished Oct 12 02:36:45 PM UTC 24
Peak memory 245092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765121207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.765121207
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/44.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.2453572172
Short name T908
Test name
Test status
Simulation time 20069807 ps
CPU time 1.19 seconds
Started Oct 12 02:36:20 PM UTC 24
Finished Oct 12 02:36:22 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453572172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2453572172
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/44.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.2267520588
Short name T919
Test name
Test status
Simulation time 54496371 ps
CPU time 1.06 seconds
Started Oct 12 02:36:47 PM UTC 24
Finished Oct 12 02:36:49 PM UTC 24
Peak memory 225096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267520588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2267520588
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/44.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1781321008
Short name T86
Test name
Test status
Simulation time 49554699422 ps
CPU time 462.17 seconds
Started Oct 12 02:36:50 PM UTC 24
Finished Oct 12 02:44:39 PM UTC 24
Peak memory 263900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781321008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1781321008
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.4229441635
Short name T1016
Test name
Test status
Simulation time 50322466197 ps
CPU time 168.55 seconds
Started Oct 12 02:36:52 PM UTC 24
Finished Oct 12 02:39:44 PM UTC 24
Peak memory 263780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229441635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.4229441635
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.939181995
Short name T946
Test name
Test status
Simulation time 16395390263 ps
CPU time 63.88 seconds
Started Oct 12 02:36:45 PM UTC 24
Finished Oct 12 02:37:51 PM UTC 24
Peak memory 251496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939181995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.939181995
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/44.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.1426447986
Short name T964
Test name
Test status
Simulation time 19902606890 ps
CPU time 97.62 seconds
Started Oct 12 02:36:45 PM UTC 24
Finished Oct 12 02:38:25 PM UTC 24
Peak memory 265512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426447986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.1426447986
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.3136650678
Short name T914
Test name
Test status
Simulation time 90035918 ps
CPU time 3.52 seconds
Started Oct 12 02:36:34 PM UTC 24
Finished Oct 12 02:36:39 PM UTC 24
Peak memory 229528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136650678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3136650678
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/44.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.3906654507
Short name T929
Test name
Test status
Simulation time 13353942062 ps
CPU time 40.55 seconds
Started Oct 12 02:36:39 PM UTC 24
Finished Oct 12 02:37:21 PM UTC 24
Peak memory 234852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906654507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3906654507
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/44.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2966284626
Short name T923
Test name
Test status
Simulation time 2837814304 ps
CPU time 20.14 seconds
Started Oct 12 02:36:33 PM UTC 24
Finished Oct 12 02:36:55 PM UTC 24
Peak memory 244980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966284626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.2966284626
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/44.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.1837097470
Short name T913
Test name
Test status
Simulation time 385540592 ps
CPU time 6.11 seconds
Started Oct 12 02:36:30 PM UTC 24
Finished Oct 12 02:36:37 PM UTC 24
Peak memory 234844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837097470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1837097470
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/44.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.762368387
Short name T922
Test name
Test status
Simulation time 409331004 ps
CPU time 5.94 seconds
Started Oct 12 02:36:47 PM UTC 24
Finished Oct 12 02:36:54 PM UTC 24
Peak memory 228904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762368387 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.762368387
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/44.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.3371457284
Short name T87
Test name
Test status
Simulation time 110578586449 ps
CPU time 568.35 seconds
Started Oct 12 02:36:55 PM UTC 24
Finished Oct 12 02:46:31 PM UTC 24
Peak memory 280216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371457284 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.3371457284
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/44.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.94923918
Short name T920
Test name
Test status
Simulation time 1937938282 ps
CPU time 26.06 seconds
Started Oct 12 02:36:23 PM UTC 24
Finished Oct 12 02:36:51 PM UTC 24
Peak memory 227504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94923918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.94923918
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/44.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.170343338
Short name T916
Test name
Test status
Simulation time 13919050373 ps
CPU time 21.43 seconds
Started Oct 12 02:36:22 PM UTC 24
Finished Oct 12 02:36:45 PM UTC 24
Peak memory 227456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170343338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.170343338
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/44.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.390733382
Short name T910
Test name
Test status
Simulation time 73699408 ps
CPU time 1.65 seconds
Started Oct 12 02:36:27 PM UTC 24
Finished Oct 12 02:36:29 PM UTC 24
Peak memory 226484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390733382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.390733382
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/44.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.3541547593
Short name T909
Test name
Test status
Simulation time 46533162 ps
CPU time 1.01 seconds
Started Oct 12 02:36:24 PM UTC 24
Finished Oct 12 02:36:25 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541547593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3541547593
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/44.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.905594024
Short name T926
Test name
Test status
Simulation time 4085793612 ps
CPU time 26.23 seconds
Started Oct 12 02:36:40 PM UTC 24
Finished Oct 12 02:37:07 PM UTC 24
Peak memory 251428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905594024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.905594024
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/44.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.35389336
Short name T938
Test name
Test status
Simulation time 36658447 ps
CPU time 1.11 seconds
Started Oct 12 02:37:35 PM UTC 24
Finished Oct 12 02:37:37 PM UTC 24
Peak memory 211416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35389336 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.35389336
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/45.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.3296881407
Short name T934
Test name
Test status
Simulation time 243535991 ps
CPU time 3.89 seconds
Started Oct 12 02:37:25 PM UTC 24
Finished Oct 12 02:37:30 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296881407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3296881407
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/45.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.141775356
Short name T924
Test name
Test status
Simulation time 279206600 ps
CPU time 1.15 seconds
Started Oct 12 02:36:56 PM UTC 24
Finished Oct 12 02:36:58 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141775356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.141775356
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/45.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.3701137634
Short name T947
Test name
Test status
Simulation time 1128473353 ps
CPU time 21.6 seconds
Started Oct 12 02:37:30 PM UTC 24
Finished Oct 12 02:37:53 PM UTC 24
Peak memory 234676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701137634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3701137634
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/45.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.3536144919
Short name T993
Test name
Test status
Simulation time 16613097563 ps
CPU time 92.38 seconds
Started Oct 12 02:37:31 PM UTC 24
Finished Oct 12 02:39:05 PM UTC 24
Peak memory 279884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536144919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3536144919
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.651714367
Short name T1031
Test name
Test status
Simulation time 262064702154 ps
CPU time 271.87 seconds
Started Oct 12 02:37:31 PM UTC 24
Finished Oct 12 02:42:07 PM UTC 24
Peak memory 294368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651714367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.651714367
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.2901210285
Short name T941
Test name
Test status
Simulation time 2230777288 ps
CPU time 11.45 seconds
Started Oct 12 02:37:26 PM UTC 24
Finished Oct 12 02:37:39 PM UTC 24
Peak memory 234784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901210285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2901210285
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/45.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.1205754720
Short name T1022
Test name
Test status
Simulation time 50123239102 ps
CPU time 167.29 seconds
Started Oct 12 02:37:28 PM UTC 24
Finished Oct 12 02:40:17 PM UTC 24
Peak memory 267560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205754720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.1205754720
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.1602165215
Short name T951
Test name
Test status
Simulation time 3335570878 ps
CPU time 38.29 seconds
Started Oct 12 02:37:21 PM UTC 24
Finished Oct 12 02:38:01 PM UTC 24
Peak memory 245044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602165215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1602165215
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/45.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.3623170222
Short name T937
Test name
Test status
Simulation time 876314923 ps
CPU time 11.1 seconds
Started Oct 12 02:37:23 PM UTC 24
Finished Oct 12 02:37:35 PM UTC 24
Peak memory 234724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623170222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3623170222
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/45.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.2754843893
Short name T353
Test name
Test status
Simulation time 1402362039 ps
CPU time 18.82 seconds
Started Oct 12 02:37:12 PM UTC 24
Finished Oct 12 02:37:32 PM UTC 24
Peak memory 245048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754843893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.2754843893
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/45.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.1450652980
Short name T949
Test name
Test status
Simulation time 7777567404 ps
CPU time 45.03 seconds
Started Oct 12 02:37:11 PM UTC 24
Finished Oct 12 02:37:57 PM UTC 24
Peak memory 245408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450652980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1450652980
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/45.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.1192986176
Short name T936
Test name
Test status
Simulation time 746466983 ps
CPU time 5.11 seconds
Started Oct 12 02:37:28 PM UTC 24
Finished Oct 12 02:37:34 PM UTC 24
Peak memory 231176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192986176 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.1192986176
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/45.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.2425219397
Short name T988
Test name
Test status
Simulation time 40706059950 ps
CPU time 85.23 seconds
Started Oct 12 02:37:33 PM UTC 24
Finished Oct 12 02:39:00 PM UTC 24
Peak memory 245112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425219397 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.2425219397
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/45.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.3352747531
Short name T939
Test name
Test status
Simulation time 23434886017 ps
CPU time 36.15 seconds
Started Oct 12 02:36:59 PM UTC 24
Finished Oct 12 02:37:37 PM UTC 24
Peak memory 227732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352747531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3352747531
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/45.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.1670278338
Short name T932
Test name
Test status
Simulation time 22611598810 ps
CPU time 26.68 seconds
Started Oct 12 02:36:58 PM UTC 24
Finished Oct 12 02:37:27 PM UTC 24
Peak memory 227732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670278338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1670278338
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/45.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.3495306556
Short name T928
Test name
Test status
Simulation time 89054568 ps
CPU time 1.5 seconds
Started Oct 12 02:37:09 PM UTC 24
Finished Oct 12 02:37:11 PM UTC 24
Peak memory 216060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495306556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3495306556
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/45.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.2241944012
Short name T927
Test name
Test status
Simulation time 463337718 ps
CPU time 1.3 seconds
Started Oct 12 02:37:08 PM UTC 24
Finished Oct 12 02:37:10 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241944012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2241944012
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/45.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.593751683
Short name T933
Test name
Test status
Simulation time 235055815 ps
CPU time 2.7 seconds
Started Oct 12 02:37:25 PM UTC 24
Finished Oct 12 02:37:29 PM UTC 24
Peak memory 245144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593751683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.593751683
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/45.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.2850388026
Short name T957
Test name
Test status
Simulation time 59011093 ps
CPU time 1.07 seconds
Started Oct 12 02:38:06 PM UTC 24
Finished Oct 12 02:38:08 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850388026 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.2850388026
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/46.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.3997750823
Short name T950
Test name
Test status
Simulation time 172496828 ps
CPU time 5.64 seconds
Started Oct 12 02:37:53 PM UTC 24
Finished Oct 12 02:37:59 PM UTC 24
Peak memory 245112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997750823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3997750823
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/46.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.3324831482
Short name T940
Test name
Test status
Simulation time 14940041 ps
CPU time 1.14 seconds
Started Oct 12 02:37:36 PM UTC 24
Finished Oct 12 02:37:38 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324831482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3324831482
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/46.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.2429750687
Short name T979
Test name
Test status
Simulation time 3175108064 ps
CPU time 51.79 seconds
Started Oct 12 02:38:01 PM UTC 24
Finished Oct 12 02:38:54 PM UTC 24
Peak memory 261732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429750687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2429750687
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/46.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.1910484466
Short name T1011
Test name
Test status
Simulation time 12615371688 ps
CPU time 90.67 seconds
Started Oct 12 02:38:02 PM UTC 24
Finished Oct 12 02:39:34 PM UTC 24
Peak memory 277920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910484466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1910484466
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/46.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.2115919507
Short name T355
Test name
Test status
Simulation time 53475327615 ps
CPU time 192.77 seconds
Started Oct 12 02:38:04 PM UTC 24
Finished Oct 12 02:41:20 PM UTC 24
Peak memory 280156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115919507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.2115919507
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.549337157
Short name T955
Test name
Test status
Simulation time 1085248939 ps
CPU time 9.14 seconds
Started Oct 12 02:37:54 PM UTC 24
Finished Oct 12 02:38:04 PM UTC 24
Peak memory 234656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549337157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.549337157
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/46.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.707496999
Short name T974
Test name
Test status
Simulation time 2849247323 ps
CPU time 50.17 seconds
Started Oct 12 02:37:55 PM UTC 24
Finished Oct 12 02:38:47 PM UTC 24
Peak memory 251176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707496999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.707496999
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.4051453077
Short name T944
Test name
Test status
Simulation time 175151526 ps
CPU time 4.9 seconds
Started Oct 12 02:37:44 PM UTC 24
Finished Oct 12 02:37:50 PM UTC 24
Peak memory 234712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051453077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.4051453077
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/46.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.1280436317
Short name T956
Test name
Test status
Simulation time 3161122097 ps
CPU time 13.5 seconds
Started Oct 12 02:37:52 PM UTC 24
Finished Oct 12 02:38:06 PM UTC 24
Peak memory 263460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280436317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1280436317
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/46.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.1100117104
Short name T967
Test name
Test status
Simulation time 4757018571 ps
CPU time 40.99 seconds
Started Oct 12 02:37:44 PM UTC 24
Finished Oct 12 02:38:27 PM UTC 24
Peak memory 251188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100117104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.1100117104
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/46.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.3451571933
Short name T966
Test name
Test status
Simulation time 6499660497 ps
CPU time 41.95 seconds
Started Oct 12 02:37:43 PM UTC 24
Finished Oct 12 02:38:26 PM UTC 24
Peak memory 245088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451571933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3451571933
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/46.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.2272233137
Short name T954
Test name
Test status
Simulation time 219202343 ps
CPU time 4.59 seconds
Started Oct 12 02:37:58 PM UTC 24
Finished Oct 12 02:38:04 PM UTC 24
Peak memory 233164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272233137 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.2272233137
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/46.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.1606421647
Short name T1020
Test name
Test status
Simulation time 26155804434 ps
CPU time 117.92 seconds
Started Oct 12 02:38:04 PM UTC 24
Finished Oct 12 02:40:04 PM UTC 24
Peak memory 261536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606421647 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.1606421647
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/46.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.1143412006
Short name T953
Test name
Test status
Simulation time 6180569994 ps
CPU time 23.75 seconds
Started Oct 12 02:37:38 PM UTC 24
Finished Oct 12 02:38:03 PM UTC 24
Peak memory 227732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143412006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1143412006
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/46.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.2062508893
Short name T945
Test name
Test status
Simulation time 1849814874 ps
CPU time 11.17 seconds
Started Oct 12 02:37:38 PM UTC 24
Finished Oct 12 02:37:50 PM UTC 24
Peak memory 227276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062508893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2062508893
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/46.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.1022644030
Short name T943
Test name
Test status
Simulation time 127686007 ps
CPU time 2.75 seconds
Started Oct 12 02:37:40 PM UTC 24
Finished Oct 12 02:37:43 PM UTC 24
Peak memory 227500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022644030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1022644030
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/46.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.2569833361
Short name T942
Test name
Test status
Simulation time 132519370 ps
CPU time 1.18 seconds
Started Oct 12 02:37:40 PM UTC 24
Finished Oct 12 02:37:42 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569833361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2569833361
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/46.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.2827510778
Short name T952
Test name
Test status
Simulation time 3898529389 ps
CPU time 10.05 seconds
Started Oct 12 02:37:52 PM UTC 24
Finished Oct 12 02:38:03 PM UTC 24
Peak memory 234788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827510778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2827510778
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/46.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.1642137980
Short name T973
Test name
Test status
Simulation time 76176681 ps
CPU time 1.08 seconds
Started Oct 12 02:38:43 PM UTC 24
Finished Oct 12 02:38:45 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642137980 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.1642137980
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/47.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.2839670327
Short name T970
Test name
Test status
Simulation time 5902563666 ps
CPU time 9.01 seconds
Started Oct 12 02:38:27 PM UTC 24
Finished Oct 12 02:38:37 PM UTC 24
Peak memory 245024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839670327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2839670327
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/47.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.34801269
Short name T958
Test name
Test status
Simulation time 65153388 ps
CPU time 1.24 seconds
Started Oct 12 02:38:06 PM UTC 24
Finished Oct 12 02:38:08 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34801269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.34801269
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/47.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.2450592071
Short name T985
Test name
Test status
Simulation time 1497857681 ps
CPU time 27.39 seconds
Started Oct 12 02:38:30 PM UTC 24
Finished Oct 12 02:38:59 PM UTC 24
Peak memory 251096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450592071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2450592071
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/47.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3370613133
Short name T284
Test name
Test status
Simulation time 29707792342 ps
CPU time 115.63 seconds
Started Oct 12 02:38:37 PM UTC 24
Finished Oct 12 02:40:35 PM UTC 24
Peak memory 277860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370613133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3370613133
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.3451738264
Short name T1028
Test name
Test status
Simulation time 9831313711 ps
CPU time 159.34 seconds
Started Oct 12 02:38:38 PM UTC 24
Finished Oct 12 02:41:20 PM UTC 24
Peak memory 267620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451738264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.3451738264
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.2541888463
Short name T972
Test name
Test status
Simulation time 3268687533 ps
CPU time 17.06 seconds
Started Oct 12 02:38:27 PM UTC 24
Finished Oct 12 02:38:45 PM UTC 24
Peak memory 247328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541888463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2541888463
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/47.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.3701716540
Short name T975
Test name
Test status
Simulation time 613635658 ps
CPU time 19.56 seconds
Started Oct 12 02:38:27 PM UTC 24
Finished Oct 12 02:38:48 PM UTC 24
Peak memory 234912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701716540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.3701716540
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.98754237
Short name T963
Test name
Test status
Simulation time 261732040 ps
CPU time 5.98 seconds
Started Oct 12 02:38:18 PM UTC 24
Finished Oct 12 02:38:25 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98754237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.98754237
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/47.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.2455318397
Short name T971
Test name
Test status
Simulation time 1138319980 ps
CPU time 19.65 seconds
Started Oct 12 02:38:21 PM UTC 24
Finished Oct 12 02:38:43 PM UTC 24
Peak memory 244856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455318397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2455318397
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/47.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.3295509244
Short name T968
Test name
Test status
Simulation time 11930156241 ps
CPU time 12.27 seconds
Started Oct 12 02:38:16 PM UTC 24
Finished Oct 12 02:38:29 PM UTC 24
Peak memory 234848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295509244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.3295509244
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/47.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.2272648679
Short name T965
Test name
Test status
Simulation time 996644427 ps
CPU time 10.24 seconds
Started Oct 12 02:38:15 PM UTC 24
Finished Oct 12 02:38:26 PM UTC 24
Peak memory 234612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272648679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2272648679
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/47.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.247231256
Short name T969
Test name
Test status
Simulation time 222384833 ps
CPU time 6.44 seconds
Started Oct 12 02:38:28 PM UTC 24
Finished Oct 12 02:38:36 PM UTC 24
Peak memory 231084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247231256 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.247231256
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/47.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.712698619
Short name T962
Test name
Test status
Simulation time 2296696250 ps
CPU time 10.14 seconds
Started Oct 12 02:38:09 PM UTC 24
Finished Oct 12 02:38:20 PM UTC 24
Peak memory 227368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712698619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.712698619
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/47.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.2464424147
Short name T960
Test name
Test status
Simulation time 1533333522 ps
CPU time 5.41 seconds
Started Oct 12 02:38:07 PM UTC 24
Finished Oct 12 02:38:13 PM UTC 24
Peak memory 227208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464424147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2464424147
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/47.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.888766735
Short name T961
Test name
Test status
Simulation time 102551088 ps
CPU time 1.48 seconds
Started Oct 12 02:38:12 PM UTC 24
Finished Oct 12 02:38:15 PM UTC 24
Peak memory 216068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888766735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.888766735
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/47.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.613349468
Short name T959
Test name
Test status
Simulation time 25397160 ps
CPU time 0.94 seconds
Started Oct 12 02:38:09 PM UTC 24
Finished Oct 12 02:38:11 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613349468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.613349468
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/47.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.785665253
Short name T983
Test name
Test status
Simulation time 23937148293 ps
CPU time 29.63 seconds
Started Oct 12 02:38:27 PM UTC 24
Finished Oct 12 02:38:58 PM UTC 24
Peak memory 234744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785665253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.785665253
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/47.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.2850919184
Short name T990
Test name
Test status
Simulation time 35844829 ps
CPU time 1.13 seconds
Started Oct 12 02:39:02 PM UTC 24
Finished Oct 12 02:39:04 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850919184 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.2850919184
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/48.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.84872299
Short name T991
Test name
Test status
Simulation time 348720530 ps
CPU time 7.62 seconds
Started Oct 12 02:38:56 PM UTC 24
Finished Oct 12 02:39:04 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84872299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.84872299
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/48.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.2095297695
Short name T976
Test name
Test status
Simulation time 20387189 ps
CPU time 1.19 seconds
Started Oct 12 02:38:47 PM UTC 24
Finished Oct 12 02:38:49 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095297695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2095297695
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/48.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.22941910
Short name T1033
Test name
Test status
Simulation time 36637631829 ps
CPU time 276.88 seconds
Started Oct 12 02:38:59 PM UTC 24
Finished Oct 12 02:43:40 PM UTC 24
Peak memory 263724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22941910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.22941910
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/48.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.2031072482
Short name T1024
Test name
Test status
Simulation time 3180684670 ps
CPU time 95.84 seconds
Started Oct 12 02:39:01 PM UTC 24
Finished Oct 12 02:40:39 PM UTC 24
Peak memory 265744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031072482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2031072482
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.605766053
Short name T992
Test name
Test status
Simulation time 1218242893 ps
CPU time 3.45 seconds
Started Oct 12 02:39:01 PM UTC 24
Finished Oct 12 02:39:05 PM UTC 24
Peak memory 233456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605766053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.605766053
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.4128161557
Short name T1018
Test name
Test status
Simulation time 3120100995 ps
CPU time 54.32 seconds
Started Oct 12 02:38:56 PM UTC 24
Finished Oct 12 02:39:52 PM UTC 24
Peak memory 251228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128161557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.4128161557
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/48.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.3910074110
Short name T1029
Test name
Test status
Simulation time 68411933336 ps
CPU time 153.51 seconds
Started Oct 12 02:38:59 PM UTC 24
Finished Oct 12 02:41:35 PM UTC 24
Peak memory 261412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910074110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.3910074110
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.1633779126
Short name T986
Test name
Test status
Simulation time 233239196 ps
CPU time 6.56 seconds
Started Oct 12 02:38:52 PM UTC 24
Finished Oct 12 02:39:00 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633779126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1633779126
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/48.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.1626438902
Short name T984
Test name
Test status
Simulation time 1855040801 ps
CPU time 5.14 seconds
Started Oct 12 02:38:52 PM UTC 24
Finished Oct 12 02:38:58 PM UTC 24
Peak memory 244916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626438902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1626438902
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/48.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.2564032525
Short name T982
Test name
Test status
Simulation time 2109736957 ps
CPU time 6.76 seconds
Started Oct 12 02:38:50 PM UTC 24
Finished Oct 12 02:38:57 PM UTC 24
Peak memory 234612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564032525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.2564032525
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/48.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.3831065059
Short name T995
Test name
Test status
Simulation time 16395668906 ps
CPU time 17.55 seconds
Started Oct 12 02:38:50 PM UTC 24
Finished Oct 12 02:39:08 PM UTC 24
Peak memory 251184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831065059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3831065059
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/48.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.3257699507
Short name T1005
Test name
Test status
Simulation time 1655868345 ps
CPU time 16.27 seconds
Started Oct 12 02:38:59 PM UTC 24
Finished Oct 12 02:39:17 PM UTC 24
Peak memory 231172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257699507 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.3257699507
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/48.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.744262495
Short name T1015
Test name
Test status
Simulation time 3759394679 ps
CPU time 38.47 seconds
Started Oct 12 02:39:01 PM UTC 24
Finished Oct 12 02:39:41 PM UTC 24
Peak memory 261556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744262495 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.744262495
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/48.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.2829746370
Short name T1013
Test name
Test status
Simulation time 2931985860 ps
CPU time 46.91 seconds
Started Oct 12 02:38:48 PM UTC 24
Finished Oct 12 02:39:37 PM UTC 24
Peak memory 227416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829746370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2829746370
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/48.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.1412882058
Short name T981
Test name
Test status
Simulation time 1080916374 ps
CPU time 7.12 seconds
Started Oct 12 02:38:47 PM UTC 24
Finished Oct 12 02:38:55 PM UTC 24
Peak memory 227280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412882058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1412882058
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/48.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.4213650205
Short name T978
Test name
Test status
Simulation time 72332780 ps
CPU time 1.53 seconds
Started Oct 12 02:38:48 PM UTC 24
Finished Oct 12 02:38:51 PM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213650205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.4213650205
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/48.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.3618506100
Short name T977
Test name
Test status
Simulation time 72131708 ps
CPU time 1.22 seconds
Started Oct 12 02:38:48 PM UTC 24
Finished Oct 12 02:38:50 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618506100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3618506100
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/48.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.783617432
Short name T987
Test name
Test status
Simulation time 1295663966 ps
CPU time 3.36 seconds
Started Oct 12 02:38:56 PM UTC 24
Finished Oct 12 02:39:00 PM UTC 24
Peak memory 234680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783617432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.783617432
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/48.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.4157675773
Short name T1009
Test name
Test status
Simulation time 11280654 ps
CPU time 1.15 seconds
Started Oct 12 02:39:23 PM UTC 24
Finished Oct 12 02:39:25 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157675773 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.4157675773
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/49.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.2533757627
Short name T1006
Test name
Test status
Simulation time 1043509908 ps
CPU time 6.2 seconds
Started Oct 12 02:39:12 PM UTC 24
Finished Oct 12 02:39:20 PM UTC 24
Peak memory 244900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533757627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2533757627
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/49.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.2862762807
Short name T994
Test name
Test status
Simulation time 15217292 ps
CPU time 1.18 seconds
Started Oct 12 02:39:03 PM UTC 24
Finished Oct 12 02:39:05 PM UTC 24
Peak memory 213540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862762807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2862762807
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/49.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.3415370249
Short name T85
Test name
Test status
Simulation time 78039875329 ps
CPU time 304.66 seconds
Started Oct 12 02:39:17 PM UTC 24
Finished Oct 12 02:44:26 PM UTC 24
Peak memory 267616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415370249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3415370249
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/49.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.2411426629
Short name T1030
Test name
Test status
Simulation time 27365064001 ps
CPU time 150.1 seconds
Started Oct 12 02:39:18 PM UTC 24
Finished Oct 12 02:41:51 PM UTC 24
Peak memory 261600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411426629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2411426629
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.3738836308
Short name T399
Test name
Test status
Simulation time 15819186570 ps
CPU time 210.45 seconds
Started Oct 12 02:39:18 PM UTC 24
Finished Oct 12 02:42:52 PM UTC 24
Peak memory 277860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738836308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.3738836308
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.3060043482
Short name T1012
Test name
Test status
Simulation time 3137777828 ps
CPU time 21.11 seconds
Started Oct 12 02:39:12 PM UTC 24
Finished Oct 12 02:39:35 PM UTC 24
Peak memory 249500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060043482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3060043482
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/49.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.3315616567
Short name T1023
Test name
Test status
Simulation time 50092338962 ps
CPU time 66.27 seconds
Started Oct 12 02:39:15 PM UTC 24
Finished Oct 12 02:40:23 PM UTC 24
Peak memory 251232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315616567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.3315616567
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.3952089699
Short name T1007
Test name
Test status
Simulation time 487978722 ps
CPU time 11.58 seconds
Started Oct 12 02:39:10 PM UTC 24
Finished Oct 12 02:39:22 PM UTC 24
Peak memory 241708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952089699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3952089699
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/49.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.2653757225
Short name T1003
Test name
Test status
Simulation time 172185356 ps
CPU time 3.79 seconds
Started Oct 12 02:39:11 PM UTC 24
Finished Oct 12 02:39:16 PM UTC 24
Peak memory 244980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653757225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2653757225
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/49.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.4227695542
Short name T1001
Test name
Test status
Simulation time 986760107 ps
CPU time 2.81 seconds
Started Oct 12 02:39:09 PM UTC 24
Finished Oct 12 02:39:13 PM UTC 24
Peak memory 233196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227695542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.4227695542
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/49.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.1449099527
Short name T999
Test name
Test status
Simulation time 529950809 ps
CPU time 2.86 seconds
Started Oct 12 02:39:07 PM UTC 24
Finished Oct 12 02:39:11 PM UTC 24
Peak memory 234740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449099527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1449099527
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/49.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.870314104
Short name T1010
Test name
Test status
Simulation time 722379363 ps
CPU time 14.73 seconds
Started Oct 12 02:39:16 PM UTC 24
Finished Oct 12 02:39:32 PM UTC 24
Peak memory 231200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870314104 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.870314104
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/49.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.3450436071
Short name T1025
Test name
Test status
Simulation time 29111932117 ps
CPU time 97.17 seconds
Started Oct 12 02:39:21 PM UTC 24
Finished Oct 12 02:41:00 PM UTC 24
Peak memory 261480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450436071 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.3450436071
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/49.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.1846646540
Short name T1014
Test name
Test status
Simulation time 4168326566 ps
CPU time 30.6 seconds
Started Oct 12 02:39:06 PM UTC 24
Finished Oct 12 02:39:38 PM UTC 24
Peak memory 229524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846646540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1846646540
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/49.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.2131311465
Short name T996
Test name
Test status
Simulation time 183598846 ps
CPU time 1.92 seconds
Started Oct 12 02:39:06 PM UTC 24
Finished Oct 12 02:39:09 PM UTC 24
Peak memory 216392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131311465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2131311465
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/49.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.3817434672
Short name T997
Test name
Test status
Simulation time 44134315 ps
CPU time 1.1 seconds
Started Oct 12 02:39:07 PM UTC 24
Finished Oct 12 02:39:09 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817434672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3817434672
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/49.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2902157118
Short name T998
Test name
Test status
Simulation time 1292744336 ps
CPU time 1.6 seconds
Started Oct 12 02:39:07 PM UTC 24
Finished Oct 12 02:39:10 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902157118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2902157118
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/49.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.2535408108
Short name T1002
Test name
Test status
Simulation time 1106047820 ps
CPU time 3.15 seconds
Started Oct 12 02:39:11 PM UTC 24
Finished Oct 12 02:39:15 PM UTC 24
Peak memory 234976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535408108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2535408108
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/49.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.1040599971
Short name T406
Test name
Test status
Simulation time 196677543 ps
CPU time 1.15 seconds
Started Oct 12 02:19:25 PM UTC 24
Finished Oct 12 02:19:28 PM UTC 24
Peak memory 213464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040599971 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1040599971
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.2221936916
Short name T326
Test name
Test status
Simulation time 264034841 ps
CPU time 3.92 seconds
Started Oct 12 02:19:19 PM UTC 24
Finished Oct 12 02:19:24 PM UTC 24
Peak memory 245168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221936916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2221936916
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.2189130141
Short name T108
Test name
Test status
Simulation time 45896359 ps
CPU time 1.15 seconds
Started Oct 12 02:19:14 PM UTC 24
Finished Oct 12 02:19:16 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189130141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2189130141
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.2971122025
Short name T231
Test name
Test status
Simulation time 131453719356 ps
CPU time 556.36 seconds
Started Oct 12 02:19:21 PM UTC 24
Finished Oct 12 02:28:44 PM UTC 24
Peak memory 277868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971122025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2971122025
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.2891249654
Short name T92
Test name
Test status
Simulation time 9353724677 ps
CPU time 51.85 seconds
Started Oct 12 02:19:22 PM UTC 24
Finished Oct 12 02:20:16 PM UTC 24
Peak memory 251192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891249654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2891249654
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2645745047
Short name T481
Test name
Test status
Simulation time 23790752809 ps
CPU time 223.6 seconds
Started Oct 12 02:19:22 PM UTC 24
Finished Oct 12 02:23:09 PM UTC 24
Peak memory 261792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645745047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.2645745047
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.4263035003
Short name T209
Test name
Test status
Simulation time 5617912072 ps
CPU time 11.69 seconds
Started Oct 12 02:19:20 PM UTC 24
Finished Oct 12 02:19:33 PM UTC 24
Peak memory 234796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263035003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.4263035003
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.2788230795
Short name T127
Test name
Test status
Simulation time 344272043 ps
CPU time 6.23 seconds
Started Oct 12 02:19:18 PM UTC 24
Finished Oct 12 02:19:25 PM UTC 24
Peak memory 245104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788230795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2788230795
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.2832992231
Short name T125
Test name
Test status
Simulation time 1714357990 ps
CPU time 11.66 seconds
Started Oct 12 02:19:19 PM UTC 24
Finished Oct 12 02:19:32 PM UTC 24
Peak memory 234724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832992231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2832992231
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.501716674
Short name T109
Test name
Test status
Simulation time 26773251 ps
CPU time 1.51 seconds
Started Oct 12 02:19:15 PM UTC 24
Finished Oct 12 02:19:18 PM UTC 24
Peak memory 228936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501716674 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mem_parity.501716674
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.3161300149
Short name T59
Test name
Test status
Simulation time 633047986 ps
CPU time 10.4 seconds
Started Oct 12 02:19:17 PM UTC 24
Finished Oct 12 02:19:29 PM UTC 24
Peak memory 249060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161300149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.3161300149
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.3203137274
Short name T128
Test name
Test status
Simulation time 4419432929 ps
CPU time 10.75 seconds
Started Oct 12 02:19:16 PM UTC 24
Finished Oct 12 02:19:28 PM UTC 24
Peak memory 245092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203137274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3203137274
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.3836653784
Short name T184
Test name
Test status
Simulation time 2461720375 ps
CPU time 8.7 seconds
Started Oct 12 02:19:21 PM UTC 24
Finished Oct 12 02:19:31 PM UTC 24
Peak memory 231208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836653784 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.3836653784
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.1179792594
Short name T392
Test name
Test status
Simulation time 1715677055 ps
CPU time 26.28 seconds
Started Oct 12 02:19:16 PM UTC 24
Finished Oct 12 02:19:44 PM UTC 24
Peak memory 227408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179792594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1179792594
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2251475126
Short name T97
Test name
Test status
Simulation time 2000171935 ps
CPU time 4.64 seconds
Started Oct 12 02:19:15 PM UTC 24
Finished Oct 12 02:19:21 PM UTC 24
Peak memory 227288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251475126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2251475126
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.4131931720
Short name T82
Test name
Test status
Simulation time 102602400 ps
CPU time 2.58 seconds
Started Oct 12 02:19:16 PM UTC 24
Finished Oct 12 02:19:20 PM UTC 24
Peak memory 227284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131931720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.4131931720
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.1375454624
Short name T81
Test name
Test status
Simulation time 64647098 ps
CPU time 1.04 seconds
Started Oct 12 02:19:16 PM UTC 24
Finished Oct 12 02:19:18 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375454624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1375454624
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.2625544814
Short name T140
Test name
Test status
Simulation time 302999996 ps
CPU time 6.32 seconds
Started Oct 12 02:19:19 PM UTC 24
Finished Oct 12 02:19:26 PM UTC 24
Peak memory 245152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625544814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2625544814
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/5.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.4146561548
Short name T411
Test name
Test status
Simulation time 50945559 ps
CPU time 1.13 seconds
Started Oct 12 02:19:45 PM UTC 24
Finished Oct 12 02:19:48 PM UTC 24
Peak memory 215632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146561548 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.4146561548
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.274226396
Short name T121
Test name
Test status
Simulation time 794755804 ps
CPU time 9.35 seconds
Started Oct 12 02:19:33 PM UTC 24
Finished Oct 12 02:19:44 PM UTC 24
Peak memory 234712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274226396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.274226396
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.3793621696
Short name T407
Test name
Test status
Simulation time 15484482 ps
CPU time 1.19 seconds
Started Oct 12 02:19:27 PM UTC 24
Finished Oct 12 02:19:29 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793621696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3793621696
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.1282247479
Short name T214
Test name
Test status
Simulation time 4105098747 ps
CPU time 14.44 seconds
Started Oct 12 02:19:41 PM UTC 24
Finished Oct 12 02:19:56 PM UTC 24
Peak memory 245320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282247479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1282247479
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.596070972
Short name T185
Test name
Test status
Simulation time 771528514 ps
CPU time 13.19 seconds
Started Oct 12 02:19:34 PM UTC 24
Finished Oct 12 02:19:49 PM UTC 24
Peak memory 247000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596070972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.596070972
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.3349849019
Short name T296
Test name
Test status
Simulation time 28430605413 ps
CPU time 267.37 seconds
Started Oct 12 02:19:40 PM UTC 24
Finished Oct 12 02:24:11 PM UTC 24
Peak memory 261448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349849019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.3349849019
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.1564234017
Short name T100
Test name
Test status
Simulation time 10192999688 ps
CPU time 34.19 seconds
Started Oct 12 02:19:32 PM UTC 24
Finished Oct 12 02:20:08 PM UTC 24
Peak memory 241892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564234017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1564234017
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.1451587745
Short name T417
Test name
Test status
Simulation time 6748194437 ps
CPU time 20.7 seconds
Started Oct 12 02:19:32 PM UTC 24
Finished Oct 12 02:19:54 PM UTC 24
Peak memory 244980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451587745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1451587745
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.3972476156
Short name T408
Test name
Test status
Simulation time 32225636 ps
CPU time 1.55 seconds
Started Oct 12 02:19:27 PM UTC 24
Finished Oct 12 02:19:29 PM UTC 24
Peak memory 229004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972476156 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mem_parity.3972476156
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1190970633
Short name T70
Test name
Test status
Simulation time 17152946923 ps
CPU time 26.11 seconds
Started Oct 12 02:19:30 PM UTC 24
Finished Oct 12 02:19:57 PM UTC 24
Peak memory 244988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190970633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.1190970633
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.1143257169
Short name T186
Test name
Test status
Simulation time 5713398224 ps
CPU time 9.6 seconds
Started Oct 12 02:19:40 PM UTC 24
Finished Oct 12 02:19:50 PM UTC 24
Peak memory 231432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143257169 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.1143257169
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.3262304941
Short name T198
Test name
Test status
Simulation time 123086388131 ps
CPU time 229.25 seconds
Started Oct 12 02:19:43 PM UTC 24
Finished Oct 12 02:23:37 PM UTC 24
Peak memory 267688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262304941 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.3262304941
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.3521574331
Short name T394
Test name
Test status
Simulation time 15482951450 ps
CPU time 55.43 seconds
Started Oct 12 02:19:29 PM UTC 24
Finished Oct 12 02:20:26 PM UTC 24
Peak memory 227536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521574331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3521574331
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.2021589919
Short name T410
Test name
Test status
Simulation time 11933033839 ps
CPU time 11.38 seconds
Started Oct 12 02:19:27 PM UTC 24
Finished Oct 12 02:19:39 PM UTC 24
Peak memory 227364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021589919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2021589919
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.3438192937
Short name T396
Test name
Test status
Simulation time 570990804 ps
CPU time 7.37 seconds
Started Oct 12 02:19:30 PM UTC 24
Finished Oct 12 02:19:38 PM UTC 24
Peak memory 227240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438192937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3438192937
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.4206256710
Short name T409
Test name
Test status
Simulation time 93529873 ps
CPU time 1.36 seconds
Started Oct 12 02:19:29 PM UTC 24
Finished Oct 12 02:19:31 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206256710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.4206256710
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.707838146
Short name T141
Test name
Test status
Simulation time 327570650 ps
CPU time 5.41 seconds
Started Oct 12 02:19:32 PM UTC 24
Finished Oct 12 02:19:39 PM UTC 24
Peak memory 234988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707838146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.707838146
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/6.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.792614054
Short name T419
Test name
Test status
Simulation time 16391379 ps
CPU time 1.14 seconds
Started Oct 12 02:20:06 PM UTC 24
Finished Oct 12 02:20:08 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792614054 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.792614054
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.1653241101
Short name T316
Test name
Test status
Simulation time 182497072 ps
CPU time 3.15 seconds
Started Oct 12 02:19:56 PM UTC 24
Finished Oct 12 02:20:00 PM UTC 24
Peak memory 245152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653241101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1653241101
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.4200554349
Short name T412
Test name
Test status
Simulation time 74048736 ps
CPU time 1.2 seconds
Started Oct 12 02:19:45 PM UTC 24
Finished Oct 12 02:19:48 PM UTC 24
Peak memory 213468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200554349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.4200554349
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.190300292
Short name T297
Test name
Test status
Simulation time 16697750815 ps
CPU time 196.83 seconds
Started Oct 12 02:20:00 PM UTC 24
Finished Oct 12 02:23:21 PM UTC 24
Peak memory 251232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190300292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.190300292
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.1003964186
Short name T370
Test name
Test status
Simulation time 4150724589 ps
CPU time 28.44 seconds
Started Oct 12 02:19:57 PM UTC 24
Finished Oct 12 02:20:27 PM UTC 24
Peak memory 251184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003964186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1003964186
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.3925543801
Short name T93
Test name
Test status
Simulation time 11468963265 ps
CPU time 20.27 seconds
Started Oct 12 02:19:58 PM UTC 24
Finished Oct 12 02:20:20 PM UTC 24
Peak memory 249124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925543801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.3925543801
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.1875678890
Short name T210
Test name
Test status
Simulation time 126930286 ps
CPU time 5.78 seconds
Started Oct 12 02:19:53 PM UTC 24
Finished Oct 12 02:20:00 PM UTC 24
Peak memory 244912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875678890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1875678890
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.3218863749
Short name T418
Test name
Test status
Simulation time 122706326 ps
CPU time 4.29 seconds
Started Oct 12 02:19:55 PM UTC 24
Finished Oct 12 02:20:00 PM UTC 24
Peak memory 244976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218863749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3218863749
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.621600343
Short name T413
Test name
Test status
Simulation time 14585244 ps
CPU time 1.51 seconds
Started Oct 12 02:19:45 PM UTC 24
Finished Oct 12 02:19:48 PM UTC 24
Peak memory 228316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621600343 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mem_parity.621600343
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.1312577873
Short name T66
Test name
Test status
Simulation time 4959053343 ps
CPU time 6.1 seconds
Started Oct 12 02:19:53 PM UTC 24
Finished Oct 12 02:20:00 PM UTC 24
Peak memory 235064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312577873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.1312577873
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.201547884
Short name T129
Test name
Test status
Simulation time 981739246 ps
CPU time 9.49 seconds
Started Oct 12 02:19:52 PM UTC 24
Finished Oct 12 02:20:02 PM UTC 24
Peak memory 245208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201547884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.201547884
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3778215325
Short name T122
Test name
Test status
Simulation time 259478385 ps
CPU time 5.5 seconds
Started Oct 12 02:20:00 PM UTC 24
Finished Oct 12 02:20:07 PM UTC 24
Peak memory 233484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778215325 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.3778215325
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.4273191017
Short name T51
Test name
Test status
Simulation time 24382522986 ps
CPU time 164.32 seconds
Started Oct 12 02:20:04 PM UTC 24
Finished Oct 12 02:22:51 PM UTC 24
Peak memory 261596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273191017 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.4273191017
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.2666402222
Short name T383
Test name
Test status
Simulation time 196122323 ps
CPU time 4.29 seconds
Started Oct 12 02:19:49 PM UTC 24
Finished Oct 12 02:19:55 PM UTC 24
Peak memory 227280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666402222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2666402222
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.2334242669
Short name T416
Test name
Test status
Simulation time 223299423 ps
CPU time 3.4 seconds
Started Oct 12 02:19:49 PM UTC 24
Finished Oct 12 02:19:54 PM UTC 24
Peak memory 227348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334242669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2334242669
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.3497194870
Short name T415
Test name
Test status
Simulation time 35093388 ps
CPU time 1.83 seconds
Started Oct 12 02:19:49 PM UTC 24
Finished Oct 12 02:19:52 PM UTC 24
Peak memory 215500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497194870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3497194870
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1335091660
Short name T414
Test name
Test status
Simulation time 35786232 ps
CPU time 1.16 seconds
Started Oct 12 02:19:49 PM UTC 24
Finished Oct 12 02:19:52 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335091660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1335091660
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.1432392998
Short name T211
Test name
Test status
Simulation time 7212356095 ps
CPU time 10.97 seconds
Started Oct 12 02:19:55 PM UTC 24
Finished Oct 12 02:20:07 PM UTC 24
Peak memory 235044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432392998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1432392998
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/7.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.558095958
Short name T426
Test name
Test status
Simulation time 108216170 ps
CPU time 1.04 seconds
Started Oct 12 02:20:28 PM UTC 24
Finished Oct 12 02:20:30 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558095958 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.558095958
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.1737325772
Short name T319
Test name
Test status
Simulation time 317400097 ps
CPU time 8.13 seconds
Started Oct 12 02:20:17 PM UTC 24
Finished Oct 12 02:20:26 PM UTC 24
Peak memory 234608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737325772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1737325772
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.1158353042
Short name T420
Test name
Test status
Simulation time 125172785 ps
CPU time 1.2 seconds
Started Oct 12 02:20:07 PM UTC 24
Finished Oct 12 02:20:09 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158353042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1158353042
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.2078777732
Short name T295
Test name
Test status
Simulation time 76082074983 ps
CPU time 303.84 seconds
Started Oct 12 02:20:26 PM UTC 24
Finished Oct 12 02:25:34 PM UTC 24
Peak memory 261428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078777732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2078777732
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.3039489545
Short name T384
Test name
Test status
Simulation time 11976494714 ps
CPU time 29.75 seconds
Started Oct 12 02:20:27 PM UTC 24
Finished Oct 12 02:20:58 PM UTC 24
Peak memory 229516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039489545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3039489545
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2274382603
Short name T65
Test name
Test status
Simulation time 1600841408 ps
CPU time 25.51 seconds
Started Oct 12 02:20:27 PM UTC 24
Finished Oct 12 02:20:54 PM UTC 24
Peak memory 251292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274382603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.2274382603
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.2267200400
Short name T430
Test name
Test status
Simulation time 4483760572 ps
CPU time 19.25 seconds
Started Oct 12 02:20:18 PM UTC 24
Finished Oct 12 02:20:38 PM UTC 24
Peak memory 235064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267200400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2267200400
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.1283349718
Short name T71
Test name
Test status
Simulation time 16819488039 ps
CPU time 83.89 seconds
Started Oct 12 02:20:19 PM UTC 24
Finished Oct 12 02:21:45 PM UTC 24
Peak memory 261544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283349718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.1283349718
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.2223733505
Short name T212
Test name
Test status
Simulation time 109922249 ps
CPU time 3.8 seconds
Started Oct 12 02:20:13 PM UTC 24
Finished Oct 12 02:20:18 PM UTC 24
Peak memory 234732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223733505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2223733505
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.1247872588
Short name T292
Test name
Test status
Simulation time 25431371477 ps
CPU time 84.87 seconds
Started Oct 12 02:20:17 PM UTC 24
Finished Oct 12 02:21:43 PM UTC 24
Peak memory 245080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247872588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1247872588
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.206509516
Short name T421
Test name
Test status
Simulation time 33912478 ps
CPU time 1.63 seconds
Started Oct 12 02:20:08 PM UTC 24
Finished Oct 12 02:20:11 PM UTC 24
Peak memory 228936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206509516 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mem_parity.206509516
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.3181254272
Short name T423
Test name
Test status
Simulation time 94693570 ps
CPU time 3.1 seconds
Started Oct 12 02:20:11 PM UTC 24
Finished Oct 12 02:20:15 PM UTC 24
Peak memory 233200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181254272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3181254272
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.4105631603
Short name T425
Test name
Test status
Simulation time 489442904 ps
CPU time 5.35 seconds
Started Oct 12 02:20:21 PM UTC 24
Finished Oct 12 02:20:27 PM UTC 24
Peak memory 233296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105631603 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.4105631603
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.2319235627
Short name T40
Test name
Test status
Simulation time 38696786 ps
CPU time 1.36 seconds
Started Oct 12 02:20:28 PM UTC 24
Finished Oct 12 02:20:31 PM UTC 24
Peak memory 213480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319235627 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.2319235627
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.4102788454
Short name T390
Test name
Test status
Simulation time 24638673023 ps
CPU time 42.89 seconds
Started Oct 12 02:20:09 PM UTC 24
Finished Oct 12 02:20:53 PM UTC 24
Peak memory 227412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102788454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.4102788454
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.1767542169
Short name T424
Test name
Test status
Simulation time 712132977 ps
CPU time 6.5 seconds
Started Oct 12 02:20:08 PM UTC 24
Finished Oct 12 02:20:15 PM UTC 24
Peak memory 227496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767542169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1767542169
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.958547
Short name T398
Test name
Test status
Simulation time 11779088 ps
CPU time 1.17 seconds
Started Oct 12 02:20:10 PM UTC 24
Finished Oct 12 02:20:12 PM UTC 24
Peak memory 215860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_
TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device
_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.958547
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3216651882
Short name T422
Test name
Test status
Simulation time 80833515 ps
CPU time 1.57 seconds
Started Oct 12 02:20:09 PM UTC 24
Finished Oct 12 02:20:12 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216651882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3216651882
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.17192078
Short name T286
Test name
Test status
Simulation time 5021910057 ps
CPU time 7.37 seconds
Started Oct 12 02:20:17 PM UTC 24
Finished Oct 12 02:20:25 PM UTC 24
Peak memory 235000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17192078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_devi
ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.17192078
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/8.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.2900667042
Short name T431
Test name
Test status
Simulation time 21543189 ps
CPU time 1.11 seconds
Started Oct 12 02:20:57 PM UTC 24
Finished Oct 12 02:21:00 PM UTC 24
Peak memory 213464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900667042 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2900667042
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1313976371
Short name T123
Test name
Test status
Simulation time 931635257 ps
CPU time 9.17 seconds
Started Oct 12 02:20:47 PM UTC 24
Finished Oct 12 02:20:57 PM UTC 24
Peak memory 244896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313976371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1313976371
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.4176538260
Short name T427
Test name
Test status
Simulation time 13579397 ps
CPU time 1.18 seconds
Started Oct 12 02:20:31 PM UTC 24
Finished Oct 12 02:20:34 PM UTC 24
Peak memory 213476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176538260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.4176538260
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.1005893504
Short name T205
Test name
Test status
Simulation time 3767594318 ps
CPU time 112.07 seconds
Started Oct 12 02:20:54 PM UTC 24
Finished Oct 12 02:22:48 PM UTC 24
Peak memory 275640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005893504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1005893504
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.2200320563
Short name T309
Test name
Test status
Simulation time 25188621432 ps
CPU time 213.5 seconds
Started Oct 12 02:20:55 PM UTC 24
Finished Oct 12 02:24:32 PM UTC 24
Peak memory 249140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200320563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2200320563
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.186968079
Short name T176
Test name
Test status
Simulation time 148815748924 ps
CPU time 327 seconds
Started Oct 12 02:20:55 PM UTC 24
Finished Oct 12 02:26:26 PM UTC 24
Peak memory 267668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186968079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.186968079
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.3122708354
Short name T439
Test name
Test status
Simulation time 9056535274 ps
CPU time 30.19 seconds
Started Oct 12 02:20:52 PM UTC 24
Finished Oct 12 02:21:23 PM UTC 24
Peak memory 245152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122708354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3122708354
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.3669892702
Short name T227
Test name
Test status
Simulation time 40436356048 ps
CPU time 134.44 seconds
Started Oct 12 02:20:54 PM UTC 24
Finished Oct 12 02:23:11 PM UTC 24
Peak memory 267616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669892702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.3669892702
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.2616426454
Short name T278
Test name
Test status
Simulation time 3701704434 ps
CPU time 13.34 seconds
Started Oct 12 02:20:38 PM UTC 24
Finished Oct 12 02:20:53 PM UTC 24
Peak memory 245040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616426454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2616426454
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.1616697066
Short name T271
Test name
Test status
Simulation time 2586189087 ps
CPU time 13.59 seconds
Started Oct 12 02:20:40 PM UTC 24
Finished Oct 12 02:20:54 PM UTC 24
Peak memory 249124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616697066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1616697066
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.2501378164
Short name T428
Test name
Test status
Simulation time 34401951 ps
CPU time 1.59 seconds
Started Oct 12 02:20:32 PM UTC 24
Finished Oct 12 02:20:34 PM UTC 24
Peak memory 229004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501378164 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mem_parity.2501378164
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_mem_parity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1281116204
Short name T332
Test name
Test status
Simulation time 2035251881 ps
CPU time 15.79 seconds
Started Oct 12 02:20:37 PM UTC 24
Finished Oct 12 02:20:54 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281116204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.1281116204
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.3423280295
Short name T213
Test name
Test status
Simulation time 9608398513 ps
CPU time 26.23 seconds
Started Oct 12 02:20:35 PM UTC 24
Finished Oct 12 02:21:03 PM UTC 24
Peak memory 251428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423280295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3423280295
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.1845550723
Short name T436
Test name
Test status
Simulation time 737258355 ps
CPU time 11.87 seconds
Started Oct 12 02:20:54 PM UTC 24
Finished Oct 12 02:21:07 PM UTC 24
Peak memory 232836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845550723 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.1845550723
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.3944469751
Short name T1026
Test name
Test status
Simulation time 415708151939 ps
CPU time 1199.17 seconds
Started Oct 12 02:20:55 PM UTC 24
Finished Oct 12 02:41:08 PM UTC 24
Peak memory 310620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944469751 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.3944469751
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.2646862024
Short name T393
Test name
Test status
Simulation time 75717376750 ps
CPU time 69.54 seconds
Started Oct 12 02:20:34 PM UTC 24
Finished Oct 12 02:21:45 PM UTC 24
Peak memory 227412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646862024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2646862024
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.3767952550
Short name T434
Test name
Test status
Simulation time 19857934106 ps
CPU time 30.54 seconds
Started Oct 12 02:20:33 PM UTC 24
Finished Oct 12 02:21:04 PM UTC 24
Peak memory 227624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767952550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3767952550
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.540233859
Short name T397
Test name
Test status
Simulation time 23414042 ps
CPU time 2.03 seconds
Started Oct 12 02:20:35 PM UTC 24
Finished Oct 12 02:20:38 PM UTC 24
Peak memory 227352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540233859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.540233859
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.3048665860
Short name T429
Test name
Test status
Simulation time 222652007 ps
CPU time 1.42 seconds
Started Oct 12 02:20:35 PM UTC 24
Finished Oct 12 02:20:38 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048665860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3048665860
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.2347897510
Short name T258
Test name
Test status
Simulation time 1191184798 ps
CPU time 10.36 seconds
Started Oct 12 02:20:40 PM UTC 24
Finished Oct 12 02:20:51 PM UTC 24
Peak memory 234928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347897510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2347897510
Directory /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/9.spi_device_upload/latest
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