| T483 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_all.393479538 |
|
|
Feb 08 06:33:36 PM UTC 25 |
Feb 08 06:33:38 PM UTC 25 |
25063160 ps |
| T484 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.2703204975 |
|
|
Feb 08 06:33:36 PM UTC 25 |
Feb 08 06:33:38 PM UTC 25 |
164744154 ps |
| T485 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.934711598 |
|
|
Feb 08 06:33:14 PM UTC 25 |
Feb 08 06:33:39 PM UTC 25 |
4885291309 ps |
| T486 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_rw.3979034462 |
|
|
Feb 08 06:33:37 PM UTC 25 |
Feb 08 06:33:39 PM UTC 25 |
16146200 ps |
| T487 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.1342930644 |
|
|
Feb 08 06:33:28 PM UTC 25 |
Feb 08 06:33:40 PM UTC 25 |
742764543 ps |
| T408 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.684200999 |
|
|
Feb 08 06:32:59 PM UTC 25 |
Feb 08 06:33:40 PM UTC 25 |
4408023115 ps |
| T398 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.208657067 |
|
|
Feb 08 06:32:33 PM UTC 25 |
Feb 08 06:33:43 PM UTC 25 |
18308805847 ps |
| T488 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode.4069156540 |
|
|
Feb 08 06:33:26 PM UTC 25 |
Feb 08 06:33:43 PM UTC 25 |
673776412 ps |
| T356 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_upload.3853264873 |
|
|
Feb 08 06:33:39 PM UTC 25 |
Feb 08 06:33:44 PM UTC 25 |
449551950 ps |
| T316 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_cfg_cmd.3113917373 |
|
|
Feb 08 06:33:40 PM UTC 25 |
Feb 08 06:33:45 PM UTC 25 |
396156908 ps |
| T236 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.1137400656 |
|
|
Feb 08 06:33:39 PM UTC 25 |
Feb 08 06:33:45 PM UTC 25 |
829822569 ps |
| T489 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.4171153543 |
|
|
Feb 08 06:33:35 PM UTC 25 |
Feb 08 06:33:47 PM UTC 25 |
5333097918 ps |
| T347 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_intercept.3706850220 |
|
|
Feb 08 06:33:39 PM UTC 25 |
Feb 08 06:33:48 PM UTC 25 |
1307880813 ps |
| T490 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode.3252089406 |
|
|
Feb 08 06:33:41 PM UTC 25 |
Feb 08 06:33:49 PM UTC 25 |
407670952 ps |
| T491 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_alert_test.127806188 |
|
|
Feb 08 06:33:48 PM UTC 25 |
Feb 08 06:33:50 PM UTC 25 |
114946056 ps |
| T492 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.3875060343 |
|
|
Feb 08 06:33:44 PM UTC 25 |
Feb 08 06:33:50 PM UTC 25 |
129567415 ps |
| T261 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.2444692704 |
|
|
Feb 08 06:32:10 PM UTC 25 |
Feb 08 06:33:51 PM UTC 25 |
8303098187 ps |
| T493 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_csb_read.4268390082 |
|
|
Feb 08 06:33:49 PM UTC 25 |
Feb 08 06:33:51 PM UTC 25 |
23004984 ps |
| T223 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.2260249880 |
|
|
Feb 08 06:32:07 PM UTC 25 |
Feb 08 06:33:51 PM UTC 25 |
22695016489 ps |
| T494 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mem_parity.646386731 |
|
|
Feb 08 06:33:50 PM UTC 25 |
Feb 08 06:33:53 PM UTC 25 |
105259383 ps |
| T495 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.3079619259 |
|
|
Feb 08 06:33:51 PM UTC 25 |
Feb 08 06:33:54 PM UTC 25 |
65059835 ps |
| T205 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.2247004278 |
|
|
Feb 08 06:33:06 PM UTC 25 |
Feb 08 06:33:56 PM UTC 25 |
2480126114 ps |
| T496 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_rw.3101099216 |
|
|
Feb 08 06:33:52 PM UTC 25 |
Feb 08 06:33:56 PM UTC 25 |
254054088 ps |
| T103 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.4225349543 |
|
|
Feb 08 06:31:26 PM UTC 25 |
Feb 08 06:33:56 PM UTC 25 |
19340485506 ps |
| T276 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mailbox.3903605264 |
|
|
Feb 08 06:33:25 PM UTC 25 |
Feb 08 06:33:59 PM UTC 25 |
1449575898 ps |
| T237 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.2621703946 |
|
|
Feb 08 06:31:01 PM UTC 25 |
Feb 08 06:33:59 PM UTC 25 |
77391331707 ps |
| T325 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_intercept.1912399657 |
|
|
Feb 08 06:33:54 PM UTC 25 |
Feb 08 06:34:01 PM UTC 25 |
308916572 ps |
| T326 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.910718244 |
|
|
Feb 08 06:33:38 PM UTC 25 |
Feb 08 06:34:01 PM UTC 25 |
5686866928 ps |
| T224 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.3916876915 |
|
|
Feb 08 06:31:23 PM UTC 25 |
Feb 08 06:34:02 PM UTC 25 |
31104121524 ps |
| T497 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_cfg_cmd.2991340178 |
|
|
Feb 08 06:33:58 PM UTC 25 |
Feb 08 06:34:02 PM UTC 25 |
62826207 ps |
| T498 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.1935834184 |
|
|
Feb 08 06:33:41 PM UTC 25 |
Feb 08 06:34:03 PM UTC 25 |
3215807561 ps |
| T499 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_alert_test.2334520469 |
|
|
Feb 08 06:34:04 PM UTC 25 |
Feb 08 06:34:06 PM UTC 25 |
31289278 ps |
| T248 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.3160739559 |
|
|
Feb 08 06:32:11 PM UTC 25 |
Feb 08 06:34:08 PM UTC 25 |
6783469265 ps |
| T500 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.10991187 |
|
|
Feb 08 06:34:00 PM UTC 25 |
Feb 08 06:34:09 PM UTC 25 |
582357257 ps |
| T501 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_csb_read.2863261766 |
|
|
Feb 08 06:34:07 PM UTC 25 |
Feb 08 06:34:09 PM UTC 25 |
14339013 ps |
| T297 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.2071540058 |
|
|
Feb 08 06:33:27 PM UTC 25 |
Feb 08 06:34:10 PM UTC 25 |
9512169439 ps |
| T322 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mailbox.4182101639 |
|
|
Feb 08 06:33:39 PM UTC 25 |
Feb 08 06:34:10 PM UTC 25 |
1983412767 ps |
| T299 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.2601067754 |
|
|
Feb 08 06:32:29 PM UTC 25 |
Feb 08 06:34:11 PM UTC 25 |
13397050758 ps |
| T502 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mem_parity.1820024094 |
|
|
Feb 08 06:34:09 PM UTC 25 |
Feb 08 06:34:12 PM UTC 25 |
66514829 ps |
| T503 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.2743049024 |
|
|
Feb 08 06:33:51 PM UTC 25 |
Feb 08 06:34:12 PM UTC 25 |
7361097712 ps |
| T504 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.3904521654 |
|
|
Feb 08 06:34:10 PM UTC 25 |
Feb 08 06:34:13 PM UTC 25 |
68345390 ps |
| T505 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.3043681057 |
|
|
Feb 08 06:32:53 PM UTC 25 |
Feb 08 06:34:14 PM UTC 25 |
13934400563 ps |
| T506 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_rw.603841698 |
|
|
Feb 08 06:34:11 PM UTC 25 |
Feb 08 06:34:15 PM UTC 25 |
127680079 ps |
| T346 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.2708071210 |
|
|
Feb 08 06:33:53 PM UTC 25 |
Feb 08 06:34:15 PM UTC 25 |
24421218015 ps |
| T291 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mailbox.2116700490 |
|
|
Feb 08 06:33:56 PM UTC 25 |
Feb 08 06:34:16 PM UTC 25 |
3073259894 ps |
| T507 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.2911414374 |
|
|
Feb 08 06:34:13 PM UTC 25 |
Feb 08 06:34:17 PM UTC 25 |
65170591 ps |
| T357 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.1209976250 |
|
|
Feb 08 06:34:12 PM UTC 25 |
Feb 08 06:34:17 PM UTC 25 |
3283937502 ps |
| T508 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.2461718200 |
|
|
Feb 08 06:34:02 PM UTC 25 |
Feb 08 06:34:18 PM UTC 25 |
6956171287 ps |
| T396 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode.1950068570 |
|
|
Feb 08 06:34:00 PM UTC 25 |
Feb 08 06:34:19 PM UTC 25 |
864206617 ps |
| T250 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_upload.1474531107 |
|
|
Feb 08 06:33:58 PM UTC 25 |
Feb 08 06:34:20 PM UTC 25 |
5201409010 ps |
| T293 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.1091654354 |
|
|
Feb 08 06:33:09 PM UTC 25 |
Feb 08 06:34:22 PM UTC 25 |
8250950460 ps |
| T509 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.3128624665 |
|
|
Feb 08 06:34:09 PM UTC 25 |
Feb 08 06:34:22 PM UTC 25 |
2457408750 ps |
| T114 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_intercept.3320222407 |
|
|
Feb 08 06:34:13 PM UTC 25 |
Feb 08 06:34:22 PM UTC 25 |
690388010 ps |
| T510 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_alert_test.453796424 |
|
|
Feb 08 06:34:21 PM UTC 25 |
Feb 08 06:34:24 PM UTC 25 |
25684959 ps |
| T511 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_csb_read.4215729649 |
|
|
Feb 08 06:34:22 PM UTC 25 |
Feb 08 06:34:25 PM UTC 25 |
53917806 ps |
| T77 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.3191169114 |
|
|
Feb 08 06:31:01 PM UTC 25 |
Feb 08 06:34:25 PM UTC 25 |
14127669880 ps |
| T80 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mem_parity.4270666927 |
|
|
Feb 08 06:34:23 PM UTC 25 |
Feb 08 06:34:25 PM UTC 25 |
33195261 ps |
| T81 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode.326071460 |
|
|
Feb 08 06:34:16 PM UTC 25 |
Feb 08 06:34:26 PM UTC 25 |
485748682 ps |
| T82 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.1672722106 |
|
|
Feb 08 06:34:18 PM UTC 25 |
Feb 08 06:34:26 PM UTC 25 |
1064675064 ps |
| T83 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.17086958 |
|
|
Feb 08 06:33:52 PM UTC 25 |
Feb 08 06:34:27 PM UTC 25 |
25355964268 ps |
| T84 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.270570992 |
|
|
Feb 08 06:34:26 PM UTC 25 |
Feb 08 06:34:28 PM UTC 25 |
146200162 ps |
| T85 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_rw.3820572743 |
|
|
Feb 08 06:34:26 PM UTC 25 |
Feb 08 06:34:29 PM UTC 25 |
221683703 ps |
| T86 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.3098184200 |
|
|
Feb 08 06:34:23 PM UTC 25 |
Feb 08 06:34:29 PM UTC 25 |
533067887 ps |
| T87 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.2072625638 |
|
|
Feb 08 06:34:26 PM UTC 25 |
Feb 08 06:34:29 PM UTC 25 |
51852065 ps |
| T88 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_cfg_cmd.175090361 |
|
|
Feb 08 06:34:16 PM UTC 25 |
Feb 08 06:34:32 PM UTC 25 |
1316961075 ps |
| T512 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_upload.1585249853 |
|
|
Feb 08 06:34:15 PM UTC 25 |
Feb 08 06:34:32 PM UTC 25 |
13973962299 ps |
| T231 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_intercept.2665590253 |
|
|
Feb 08 06:34:27 PM UTC 25 |
Feb 08 06:34:34 PM UTC 25 |
150947000 ps |
| T43 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.1119620177 |
|
|
Feb 08 06:32:34 PM UTC 25 |
Feb 08 06:34:34 PM UTC 25 |
7075694126 ps |
| T409 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_all.2295269634 |
|
|
Feb 08 06:33:51 PM UTC 25 |
Feb 08 06:34:34 PM UTC 25 |
7692998702 ps |
| T513 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_all.3342065622 |
|
|
Feb 08 06:34:25 PM UTC 25 |
Feb 08 06:34:35 PM UTC 25 |
2011685513 ps |
| T320 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_cfg_cmd.1006117015 |
|
|
Feb 08 06:34:29 PM UTC 25 |
Feb 08 06:34:36 PM UTC 25 |
127954233 ps |
| T514 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_all.3632050576 |
|
|
Feb 08 06:33:08 PM UTC 25 |
Feb 08 06:34:37 PM UTC 25 |
27903393464 ps |
| T515 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode.1771572811 |
|
|
Feb 08 06:34:30 PM UTC 25 |
Feb 08 06:34:37 PM UTC 25 |
284486403 ps |
| T318 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_upload.3960787430 |
|
|
Feb 08 06:34:29 PM UTC 25 |
Feb 08 06:34:38 PM UTC 25 |
267673595 ps |
| T516 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_alert_test.2733013197 |
|
|
Feb 08 06:34:36 PM UTC 25 |
Feb 08 06:34:38 PM UTC 25 |
51558857 ps |
| T517 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_csb_read.520479950 |
|
|
Feb 08 06:34:37 PM UTC 25 |
Feb 08 06:34:39 PM UTC 25 |
76952855 ps |
| T518 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mem_parity.2263868825 |
|
|
Feb 08 06:34:38 PM UTC 25 |
Feb 08 06:34:41 PM UTC 25 |
17495920 ps |
| T519 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.208389370 |
|
|
Feb 08 06:34:32 PM UTC 25 |
Feb 08 06:34:41 PM UTC 25 |
597527037 ps |
| T520 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.2856961353 |
|
|
Feb 08 06:32:52 PM UTC 25 |
Feb 08 06:34:41 PM UTC 25 |
5991008218 ps |
| T521 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.3139688208 |
|
|
Feb 08 06:34:39 PM UTC 25 |
Feb 08 06:34:41 PM UTC 25 |
108512145 ps |
| T202 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.677411715 |
|
|
Feb 08 06:33:30 PM UTC 25 |
Feb 08 06:34:42 PM UTC 25 |
2353932063 ps |
| T287 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_all.435176558 |
|
|
Feb 08 06:34:03 PM UTC 25 |
Feb 08 06:34:43 PM UTC 25 |
3782767571 ps |
| T522 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.3762531786 |
|
|
Feb 08 06:34:38 PM UTC 25 |
Feb 08 06:34:43 PM UTC 25 |
577696827 ps |
| T523 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2944770981 |
|
|
Feb 08 06:34:19 PM UTC 25 |
Feb 08 06:34:43 PM UTC 25 |
14241443322 ps |
| T524 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.2760594443 |
|
|
Feb 08 06:34:41 PM UTC 25 |
Feb 08 06:34:46 PM UTC 25 |
33860186 ps |
| T200 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.811391501 |
|
|
Feb 08 06:32:35 PM UTC 25 |
Feb 08 06:34:46 PM UTC 25 |
30353167943 ps |
| T525 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_rw.2153499308 |
|
|
Feb 08 06:34:40 PM UTC 25 |
Feb 08 06:34:46 PM UTC 25 |
209907254 ps |
| T526 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_all.777268621 |
|
|
Feb 08 06:34:39 PM UTC 25 |
Feb 08 06:34:50 PM UTC 25 |
616501554 ps |
| T527 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_intercept.3105474724 |
|
|
Feb 08 06:34:42 PM UTC 25 |
Feb 08 06:34:51 PM UTC 25 |
176185452 ps |
| T289 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.3327373795 |
|
|
Feb 08 06:34:19 PM UTC 25 |
Feb 08 06:34:55 PM UTC 25 |
3806878747 ps |
| T528 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.2259260652 |
|
|
Feb 08 06:34:47 PM UTC 25 |
Feb 08 06:34:55 PM UTC 25 |
522052150 ps |
| T246 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_upload.2332028783 |
|
|
Feb 08 06:34:42 PM UTC 25 |
Feb 08 06:34:56 PM UTC 25 |
9500666669 ps |
| T529 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_all.2734731099 |
|
|
Feb 08 06:34:10 PM UTC 25 |
Feb 08 06:34:56 PM UTC 25 |
11193386549 ps |
| T530 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_alert_test.4233015056 |
|
|
Feb 08 06:34:56 PM UTC 25 |
Feb 08 06:34:58 PM UTC 25 |
12732789 ps |
| T333 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.1482338319 |
|
|
Feb 08 06:34:27 PM UTC 25 |
Feb 08 06:34:58 PM UTC 25 |
4421237414 ps |
| T531 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_csb_read.1526789430 |
|
|
Feb 08 06:34:56 PM UTC 25 |
Feb 08 06:34:59 PM UTC 25 |
15987823 ps |
| T354 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_cfg_cmd.931404124 |
|
|
Feb 08 06:34:43 PM UTC 25 |
Feb 08 06:34:59 PM UTC 25 |
998065817 ps |
| T532 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mem_parity.2517125671 |
|
|
Feb 08 06:34:57 PM UTC 25 |
Feb 08 06:35:00 PM UTC 25 |
69245918 ps |
| T285 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.1275353993 |
|
|
Feb 08 06:34:42 PM UTC 25 |
Feb 08 06:35:00 PM UTC 25 |
9955140778 ps |
| T533 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.941662603 |
|
|
Feb 08 06:34:59 PM UTC 25 |
Feb 08 06:35:02 PM UTC 25 |
145791945 ps |
| T534 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_rw.1383176174 |
|
|
Feb 08 06:34:59 PM UTC 25 |
Feb 08 06:35:03 PM UTC 25 |
124355778 ps |
| T360 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mailbox.1404817755 |
|
|
Feb 08 06:34:14 PM UTC 25 |
Feb 08 06:35:03 PM UTC 25 |
5062616879 ps |
| T535 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode.1184136076 |
|
|
Feb 08 06:34:44 PM UTC 25 |
Feb 08 06:35:05 PM UTC 25 |
738468347 ps |
| T536 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.2879731705 |
|
|
Feb 08 06:35:00 PM UTC 25 |
Feb 08 06:35:05 PM UTC 25 |
475853887 ps |
| T308 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_cfg_cmd.2677473102 |
|
|
Feb 08 06:35:04 PM UTC 25 |
Feb 08 06:35:09 PM UTC 25 |
214957482 ps |
| T537 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.3517807383 |
|
|
Feb 08 06:34:51 PM UTC 25 |
Feb 08 06:35:10 PM UTC 25 |
1810006797 ps |
| T313 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_intercept.3775740391 |
|
|
Feb 08 06:35:01 PM UTC 25 |
Feb 08 06:35:12 PM UTC 25 |
358020991 ps |
| T199 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.1508296538 |
|
|
Feb 08 06:33:46 PM UTC 25 |
Feb 08 06:35:16 PM UTC 25 |
6810368550 ps |
| T257 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.1672308458 |
|
|
Feb 08 06:35:00 PM UTC 25 |
Feb 08 06:35:17 PM UTC 25 |
6016949307 ps |
| T538 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_all.1809558662 |
|
|
Feb 08 06:34:59 PM UTC 25 |
Feb 08 06:35:17 PM UTC 25 |
16490882465 ps |
| T288 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.3378886274 |
|
|
Feb 08 06:33:11 PM UTC 25 |
Feb 08 06:35:19 PM UTC 25 |
10137738660 ps |
| T539 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.2709642080 |
|
|
Feb 08 06:33:29 PM UTC 25 |
Feb 08 06:35:19 PM UTC 25 |
23993929876 ps |
| T540 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_alert_test.251045558 |
|
|
Feb 08 06:35:18 PM UTC 25 |
Feb 08 06:35:20 PM UTC 25 |
15099182 ps |
| T541 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_stress_all.207028577 |
|
|
Feb 08 06:35:18 PM UTC 25 |
Feb 08 06:35:21 PM UTC 25 |
111074561 ps |
| T542 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_csb_read.3250399614 |
|
|
Feb 08 06:35:20 PM UTC 25 |
Feb 08 06:35:23 PM UTC 25 |
21046886 ps |
| T543 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.1193692288 |
|
|
Feb 08 06:35:21 PM UTC 25 |
Feb 08 06:35:24 PM UTC 25 |
63192428 ps |
| T544 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.4240421278 |
|
|
Feb 08 06:34:57 PM UTC 25 |
Feb 08 06:35:24 PM UTC 25 |
19837699161 ps |
| T348 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mailbox.3896214334 |
|
|
Feb 08 06:34:28 PM UTC 25 |
Feb 08 06:35:25 PM UTC 25 |
49002365183 ps |
| T545 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_rw.3904163169 |
|
|
Feb 08 06:35:24 PM UTC 25 |
Feb 08 06:35:27 PM UTC 25 |
259986047 ps |
| T546 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.2425284282 |
|
|
Feb 08 06:35:10 PM UTC 25 |
Feb 08 06:35:29 PM UTC 25 |
1665930161 ps |
| T184 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.1081434912 |
|
|
Feb 08 06:29:46 PM UTC 25 |
Feb 08 06:35:31 PM UTC 25 |
58841719002 ps |
| T547 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_upload.302080852 |
|
|
Feb 08 06:35:04 PM UTC 25 |
Feb 08 06:35:36 PM UTC 25 |
24924955383 ps |
| T242 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_upload.720188176 |
|
|
Feb 08 06:35:29 PM UTC 25 |
Feb 08 06:35:36 PM UTC 25 |
554879555 ps |
| T309 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.2113076634 |
|
|
Feb 08 06:34:47 PM UTC 25 |
Feb 08 06:35:37 PM UTC 25 |
6944718962 ps |
| T324 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_intercept.3814920827 |
|
|
Feb 08 06:35:26 PM UTC 25 |
Feb 08 06:35:37 PM UTC 25 |
1048176263 ps |
| T548 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.1373436612 |
|
|
Feb 08 06:35:20 PM UTC 25 |
Feb 08 06:35:37 PM UTC 25 |
13110596305 ps |
| T292 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.114557250 |
|
|
Feb 08 06:35:25 PM UTC 25 |
Feb 08 06:35:39 PM UTC 25 |
3793492532 ps |
| T233 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.168477779 |
|
|
Feb 08 06:30:17 PM UTC 25 |
Feb 08 06:35:39 PM UTC 25 |
45331821702 ps |
| T549 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_mailbox.2197228590 |
|
|
Feb 08 06:35:28 PM UTC 25 |
Feb 08 06:35:40 PM UTC 25 |
386610441 ps |
| T332 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.2094119581 |
|
|
Feb 08 06:35:25 PM UTC 25 |
Feb 08 06:35:40 PM UTC 25 |
2509496405 ps |
| T550 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_alert_test.995871426 |
|
|
Feb 08 06:35:40 PM UTC 25 |
Feb 08 06:35:43 PM UTC 25 |
22695171 ps |
| T273 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.2826873629 |
|
|
Feb 08 06:32:53 PM UTC 25 |
Feb 08 06:35:43 PM UTC 25 |
56772239871 ps |
| T551 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode.2163272701 |
|
|
Feb 08 06:35:06 PM UTC 25 |
Feb 08 06:35:43 PM UTC 25 |
2472069106 ps |
| T552 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.1568314992 |
|
|
Feb 08 06:35:37 PM UTC 25 |
Feb 08 06:35:44 PM UTC 25 |
904099029 ps |
| T553 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_csb_read.3563562673 |
|
|
Feb 08 06:35:42 PM UTC 25 |
Feb 08 06:35:44 PM UTC 25 |
342387539 ps |
| T554 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.557896103 |
|
|
Feb 08 06:34:03 PM UTC 25 |
Feb 08 06:35:44 PM UTC 25 |
7652487950 ps |
| T555 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_all.3124378150 |
|
|
Feb 08 06:33:44 PM UTC 25 |
Feb 08 06:35:47 PM UTC 25 |
11848709393 ps |
| T556 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.1943441790 |
|
|
Feb 08 06:35:45 PM UTC 25 |
Feb 08 06:35:47 PM UTC 25 |
46835582 ps |
| T557 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.4090864414 |
|
|
Feb 08 06:35:44 PM UTC 25 |
Feb 08 06:35:47 PM UTC 25 |
1038928293 ps |
| T558 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode.3507883579 |
|
|
Feb 08 06:35:36 PM UTC 25 |
Feb 08 06:35:47 PM UTC 25 |
1197602779 ps |
| T559 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_rw.3191389798 |
|
|
Feb 08 06:35:45 PM UTC 25 |
Feb 08 06:35:48 PM UTC 25 |
60369852 ps |
| T228 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.1745817511 |
|
|
Feb 08 06:34:30 PM UTC 25 |
Feb 08 06:35:48 PM UTC 25 |
9710091189 ps |
| T338 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.1045012342 |
|
|
Feb 08 06:35:45 PM UTC 25 |
Feb 08 06:35:49 PM UTC 25 |
65700035 ps |
| T560 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_cfg_cmd.395488158 |
|
|
Feb 08 06:35:32 PM UTC 25 |
Feb 08 06:35:53 PM UTC 25 |
2352988552 ps |
| T561 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_cfg_cmd.882363861 |
|
|
Feb 08 06:35:48 PM UTC 25 |
Feb 08 06:35:53 PM UTC 25 |
83697833 ps |
| T286 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_mailbox.1221366306 |
|
|
Feb 08 06:35:48 PM UTC 25 |
Feb 08 06:35:53 PM UTC 25 |
185796138 ps |
| T358 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_upload.23693381 |
|
|
Feb 08 06:35:48 PM UTC 25 |
Feb 08 06:35:53 PM UTC 25 |
1343839381 ps |
| T390 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode.3309577964 |
|
|
Feb 08 06:35:48 PM UTC 25 |
Feb 08 06:35:56 PM UTC 25 |
121712108 ps |
| T562 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_stress_all.780933354 |
|
|
Feb 08 06:35:55 PM UTC 25 |
Feb 08 06:35:57 PM UTC 25 |
95952313 ps |
| T563 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_alert_test.3952187457 |
|
|
Feb 08 06:35:58 PM UTC 25 |
Feb 08 06:36:00 PM UTC 25 |
38187826 ps |
| T564 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_csb_read.3392340415 |
|
|
Feb 08 06:35:58 PM UTC 25 |
Feb 08 06:36:00 PM UTC 25 |
53455821 ps |
| T565 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_all.3433503097 |
|
|
Feb 08 06:36:01 PM UTC 25 |
Feb 08 06:36:03 PM UTC 25 |
27125246 ps |
| T566 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.245852557 |
|
|
Feb 08 06:36:04 PM UTC 25 |
Feb 08 06:36:06 PM UTC 25 |
49329240 ps |
| T567 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mailbox.2794003248 |
|
|
Feb 08 06:35:03 PM UTC 25 |
Feb 08 06:36:06 PM UTC 25 |
6448541657 ps |
| T234 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.434838797 |
|
|
Feb 08 06:33:46 PM UTC 25 |
Feb 08 06:36:08 PM UTC 25 |
25537922706 ps |
| T310 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_intercept.2154576114 |
|
|
Feb 08 06:35:48 PM UTC 25 |
Feb 08 06:36:09 PM UTC 25 |
2783390036 ps |
| T568 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_rw.1581498003 |
|
|
Feb 08 06:36:07 PM UTC 25 |
Feb 08 06:36:10 PM UTC 25 |
187882752 ps |
| T569 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.2218638586 |
|
|
Feb 08 06:36:07 PM UTC 25 |
Feb 08 06:36:11 PM UTC 25 |
754463903 ps |
| T570 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.493899243 |
|
|
Feb 08 06:35:50 PM UTC 25 |
Feb 08 06:36:13 PM UTC 25 |
2727686098 ps |
| T152 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.107127611 |
|
|
Feb 08 06:32:54 PM UTC 25 |
Feb 08 06:36:14 PM UTC 25 |
52215750159 ps |
| T153 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_all.2497485457 |
|
|
Feb 08 06:35:37 PM UTC 25 |
Feb 08 06:36:15 PM UTC 25 |
6150620369 ps |
| T154 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_all.2168097307 |
|
|
Feb 08 06:35:44 PM UTC 25 |
Feb 08 06:36:19 PM UTC 25 |
18834490968 ps |
| T155 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_intercept.304316846 |
|
|
Feb 08 06:36:10 PM UTC 25 |
Feb 08 06:36:19 PM UTC 25 |
417345452 ps |
| T156 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_all.211403094 |
|
|
Feb 08 06:35:21 PM UTC 25 |
Feb 08 06:36:19 PM UTC 25 |
7276961097 ps |
| T157 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_cfg_cmd.2174184827 |
|
|
Feb 08 06:36:13 PM UTC 25 |
Feb 08 06:36:19 PM UTC 25 |
431215223 ps |
| T158 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.979195248 |
|
|
Feb 08 06:36:09 PM UTC 25 |
Feb 08 06:36:21 PM UTC 25 |
813587995 ps |
| T159 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.2738010094 |
|
|
Feb 08 06:35:45 PM UTC 25 |
Feb 08 06:36:22 PM UTC 25 |
12967319431 ps |
| T160 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.2311705001 |
|
|
Feb 08 06:36:01 PM UTC 25 |
Feb 08 06:36:23 PM UTC 25 |
21662211357 ps |
| T161 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mailbox.662939336 |
|
|
Feb 08 06:34:42 PM UTC 25 |
Feb 08 06:36:24 PM UTC 25 |
8261991367 ps |
| T571 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_alert_test.934847091 |
|
|
Feb 08 06:36:23 PM UTC 25 |
Feb 08 06:36:25 PM UTC 25 |
30453946 ps |
| T572 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_csb_read.4195475693 |
|
|
Feb 08 06:36:24 PM UTC 25 |
Feb 08 06:36:26 PM UTC 25 |
23387842 ps |
| T573 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.3576204434 |
|
|
Feb 08 06:37:00 PM UTC 25 |
Feb 08 06:37:12 PM UTC 25 |
2205743612 ps |
| T574 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.1815575620 |
|
|
Feb 08 06:36:20 PM UTC 25 |
Feb 08 06:36:27 PM UTC 25 |
128965525 ps |
| T317 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1902575502 |
|
|
Feb 08 06:31:27 PM UTC 25 |
Feb 08 06:36:27 PM UTC 25 |
140685575770 ps |
| T575 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_upload.960059530 |
|
|
Feb 08 06:36:12 PM UTC 25 |
Feb 08 06:36:28 PM UTC 25 |
6610867559 ps |
| T576 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.1870168971 |
|
|
Feb 08 06:36:27 PM UTC 25 |
Feb 08 06:36:30 PM UTC 25 |
189536768 ps |
| T577 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode.622801390 |
|
|
Feb 08 06:36:15 PM UTC 25 |
Feb 08 06:36:30 PM UTC 25 |
1516455149 ps |
| T411 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_rw.1379509795 |
|
|
Feb 08 06:36:28 PM UTC 25 |
Feb 08 06:36:33 PM UTC 25 |
1053785351 ps |
| T578 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.1027187696 |
|
|
Feb 08 06:36:25 PM UTC 25 |
Feb 08 06:36:33 PM UTC 25 |
1563224756 ps |
| T579 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.3661818767 |
|
|
Feb 08 06:36:28 PM UTC 25 |
Feb 08 06:36:35 PM UTC 25 |
575927519 ps |
| T580 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.515902745 |
|
|
Feb 08 06:34:17 PM UTC 25 |
Feb 08 06:36:35 PM UTC 25 |
73320051632 ps |
| T581 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.3101142184 |
|
|
Feb 08 06:33:45 PM UTC 25 |
Feb 08 06:36:38 PM UTC 25 |
27513861781 ps |
| T582 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.2947837225 |
|
|
Feb 08 06:36:28 PM UTC 25 |
Feb 08 06:36:39 PM UTC 25 |
324435730 ps |
| T583 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_cfg_cmd.2864598775 |
|
|
Feb 08 06:36:34 PM UTC 25 |
Feb 08 06:36:39 PM UTC 25 |
425718781 ps |
| T314 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_intercept.966668812 |
|
|
Feb 08 06:36:30 PM UTC 25 |
Feb 08 06:36:43 PM UTC 25 |
1725336642 ps |
| T243 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.104805407 |
|
|
Feb 08 06:35:38 PM UTC 25 |
Feb 08 06:36:47 PM UTC 25 |
22733010819 ps |
| T584 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_mailbox.1079821830 |
|
|
Feb 08 06:36:31 PM UTC 25 |
Feb 08 06:36:48 PM UTC 25 |
640017242 ps |
| T294 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_all.1341570302 |
|
|
Feb 08 06:35:11 PM UTC 25 |
Feb 08 06:36:48 PM UTC 25 |
4118443479 ps |
| T249 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_all.3448662810 |
|
|
Feb 08 06:34:18 PM UTC 25 |
Feb 08 06:36:49 PM UTC 25 |
8734539381 ps |
| T585 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.3779079066 |
|
|
Feb 08 06:36:39 PM UTC 25 |
Feb 08 06:36:50 PM UTC 25 |
2068814267 ps |
| T586 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.580723728 |
|
|
Feb 08 06:34:03 PM UTC 25 |
Feb 08 06:36:50 PM UTC 25 |
27328339281 ps |
| T587 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_alert_test.2926387426 |
|
|
Feb 08 06:36:48 PM UTC 25 |
Feb 08 06:36:50 PM UTC 25 |
14867483 ps |
| T588 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_csb_read.1150766886 |
|
|
Feb 08 06:36:48 PM UTC 25 |
Feb 08 06:36:50 PM UTC 25 |
20574680 ps |
| T589 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.3279597485 |
|
|
Feb 08 06:36:50 PM UTC 25 |
Feb 08 06:36:53 PM UTC 25 |
336168909 ps |
| T590 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.2573210477 |
|
|
Feb 08 06:35:49 PM UTC 25 |
Feb 08 06:36:54 PM UTC 25 |
1911964478 ps |
| T591 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_rw.1543922102 |
|
|
Feb 08 06:36:52 PM UTC 25 |
Feb 08 06:36:54 PM UTC 25 |
19461588 ps |
| T235 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_stress_all.3129329862 |
|
|
Feb 08 06:35:40 PM UTC 25 |
Feb 08 06:36:55 PM UTC 25 |
2625897704 ps |
| T315 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_upload.3713501634 |
|
|
Feb 08 06:36:34 PM UTC 25 |
Feb 08 06:36:56 PM UTC 25 |
16638402449 ps |
| T592 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.1071281927 |
|
|
Feb 08 06:36:49 PM UTC 25 |
Feb 08 06:36:59 PM UTC 25 |
771319138 ps |
| T593 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_all.3129410859 |
|
|
Feb 08 06:36:26 PM UTC 25 |
Feb 08 06:36:59 PM UTC 25 |
9964576618 ps |
| T185 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/15.spi_device_stress_all.1316958552 |
|
|
Feb 08 06:34:03 PM UTC 25 |
Feb 08 06:36:59 PM UTC 25 |
52154820871 ps |
| T352 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_upload.1911399423 |
|
|
Feb 08 06:36:55 PM UTC 25 |
Feb 08 06:37:00 PM UTC 25 |
654961199 ps |
| T594 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_cfg_cmd.3111234548 |
|
|
Feb 08 06:36:56 PM UTC 25 |
Feb 08 06:37:01 PM UTC 25 |
317966082 ps |
| T595 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.2263632603 |
|
|
Feb 08 06:36:57 PM UTC 25 |
Feb 08 06:37:02 PM UTC 25 |
160843698 ps |
| T596 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.4286614274 |
|
|
Feb 08 06:37:00 PM UTC 25 |
Feb 08 06:37:02 PM UTC 25 |
22417517 ps |
| T597 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_intercept.4216070408 |
|
|
Feb 08 06:36:54 PM UTC 25 |
Feb 08 06:37:04 PM UTC 25 |
552764435 ps |
| T598 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.1903481922 |
|
|
Feb 08 06:36:20 PM UTC 25 |
Feb 08 06:37:05 PM UTC 25 |
5238854239 ps |
| T599 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_alert_test.2525163185 |
|
|
Feb 08 06:37:03 PM UTC 25 |
Feb 08 06:37:05 PM UTC 25 |
12770767 ps |
| T600 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_csb_read.1879577967 |
|
|
Feb 08 06:37:05 PM UTC 25 |
Feb 08 06:37:08 PM UTC 25 |
16666239 ps |
| T601 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.2655923214 |
|
|
Feb 08 06:36:52 PM UTC 25 |
Feb 08 06:37:08 PM UTC 25 |
2772102120 ps |
| T602 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.1833091043 |
|
|
Feb 08 06:37:09 PM UTC 25 |
Feb 08 06:37:11 PM UTC 25 |
133712500 ps |
| T337 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.2284084566 |
|
|
Feb 08 06:36:17 PM UTC 25 |
Feb 08 06:37:11 PM UTC 25 |
6652847136 ps |
| T603 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_rw.1538983472 |
|
|
Feb 08 06:37:09 PM UTC 25 |
Feb 08 06:37:12 PM UTC 25 |
32619063 ps |
| T290 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.3564274812 |
|
|
Feb 08 06:36:52 PM UTC 25 |
Feb 08 06:37:13 PM UTC 25 |
45707761605 ps |
| T295 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.2999654047 |
|
|
Feb 08 06:35:39 PM UTC 25 |
Feb 08 06:37:13 PM UTC 25 |
18124600632 ps |
| T361 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_mailbox.1431626340 |
|
|
Feb 08 06:36:11 PM UTC 25 |
Feb 08 06:37:13 PM UTC 25 |
6063845445 ps |
| T604 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_all.389463507 |
|
|
Feb 08 06:36:20 PM UTC 25 |
Feb 08 06:37:14 PM UTC 25 |
25934105548 ps |
| T605 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_all.3157199544 |
|
|
Feb 08 06:37:07 PM UTC 25 |
Feb 08 06:37:15 PM UTC 25 |
7870322692 ps |
| T270 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.3505570470 |
|
|
Feb 08 06:34:35 PM UTC 25 |
Feb 08 06:37:18 PM UTC 25 |
52521321653 ps |
| T606 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_all.3183612702 |
|
|
Feb 08 06:36:49 PM UTC 25 |
Feb 08 06:37:22 PM UTC 25 |
4751496288 ps |
| T607 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.2535505228 |
|
|
Feb 08 06:37:12 PM UTC 25 |
Feb 08 06:37:23 PM UTC 25 |
2757396784 ps |
| T256 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.1684134749 |
|
|
Feb 08 06:31:00 PM UTC 25 |
Feb 08 06:37:27 PM UTC 25 |
47769013104 ps |
| T608 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_upload.597853694 |
|
|
Feb 08 06:37:13 PM UTC 25 |
Feb 08 06:37:28 PM UTC 25 |
8436438297 ps |
| T609 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.3420308115 |
|
|
Feb 08 06:37:16 PM UTC 25 |
Feb 08 06:37:29 PM UTC 25 |
678844975 ps |
| T610 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_alert_test.3610576 |
|
|
Feb 08 06:37:29 PM UTC 25 |
Feb 08 06:37:31 PM UTC 25 |
12453700 ps |
| T611 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode.3684546315 |
|
|
Feb 08 06:37:14 PM UTC 25 |
Feb 08 06:37:31 PM UTC 25 |
2235187621 ps |
| T240 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/24.spi_device_mailbox.788421548 |
|
|
Feb 08 06:36:55 PM UTC 25 |
Feb 08 06:37:32 PM UTC 25 |
1916152927 ps |
| T612 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_csb_read.800407827 |
|
|
Feb 08 06:37:30 PM UTC 25 |
Feb 08 06:37:32 PM UTC 25 |
28761591 ps |
| T296 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_all.3313081338 |
|
|
Feb 08 06:36:40 PM UTC 25 |
Feb 08 06:37:35 PM UTC 25 |
3377114060 ps |
| T613 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_rw.1918745744 |
|
|
Feb 08 06:37:33 PM UTC 25 |
Feb 08 06:37:35 PM UTC 25 |
13049598 ps |
| T614 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.958413107 |
|
|
Feb 08 06:37:33 PM UTC 25 |
Feb 08 06:37:35 PM UTC 25 |
25371370 ps |
| T232 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.730809219 |
|
|
Feb 08 06:30:46 PM UTC 25 |
Feb 08 06:37:39 PM UTC 25 |
244576841555 ps |
| T615 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_all.270895824 |
|
|
Feb 08 06:37:18 PM UTC 25 |
Feb 08 06:37:40 PM UTC 25 |
5563902120 ps |
| T616 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.2482672799 |
|
|
Feb 08 06:37:36 PM UTC 25 |
Feb 08 06:37:40 PM UTC 25 |
279328290 ps |
| T341 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.1180884112 |
|
|
Feb 08 06:37:36 PM UTC 25 |
Feb 08 06:37:41 PM UTC 25 |
145368089 ps |
| T617 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_cfg_cmd.3250264658 |
|
|
Feb 08 06:37:14 PM UTC 25 |
Feb 08 06:37:41 PM UTC 25 |
6080940579 ps |
| T618 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_intercept.3056123623 |
|
|
Feb 08 06:37:13 PM UTC 25 |
Feb 08 06:37:41 PM UTC 25 |
13805271590 ps |
| T619 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_intercept.2628023350 |
|
|
Feb 08 06:37:36 PM UTC 25 |
Feb 08 06:37:42 PM UTC 25 |
857524099 ps |
| T620 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_all.3816181036 |
|
|
Feb 08 06:37:32 PM UTC 25 |
Feb 08 06:37:46 PM UTC 25 |
1694713995 ps |
| T621 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_cfg_cmd.2082131149 |
|
|
Feb 08 06:37:41 PM UTC 25 |
Feb 08 06:37:47 PM UTC 25 |
537800331 ps |
| T622 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.3478863930 |
|
|
Feb 08 06:37:22 PM UTC 25 |
Feb 08 06:37:51 PM UTC 25 |
27593822564 ps |
| T623 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.3201100788 |
|
|
Feb 08 06:37:07 PM UTC 25 |
Feb 08 06:37:51 PM UTC 25 |
15725320523 ps |
| T624 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.1580470662 |
|
|
Feb 08 06:37:32 PM UTC 25 |
Feb 08 06:37:52 PM UTC 25 |
9295616176 ps |
| T625 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.329973741 |
|
|
Feb 08 06:37:43 PM UTC 25 |
Feb 08 06:37:52 PM UTC 25 |
2582421300 ps |
| T626 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode.326619306 |
|
|
Feb 08 06:37:41 PM UTC 25 |
Feb 08 06:37:53 PM UTC 25 |
253917311 ps |
| T304 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_upload.4167614309 |
|
|
Feb 08 06:37:41 PM UTC 25 |
Feb 08 06:37:53 PM UTC 25 |
10275618236 ps |
| T627 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.3393756298 |
|
|
Feb 08 06:37:12 PM UTC 25 |
Feb 08 06:37:54 PM UTC 25 |
25159806223 ps |
| T628 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/26.spi_device_alert_test.2318670461 |
|
|
Feb 08 06:37:52 PM UTC 25 |
Feb 08 06:37:54 PM UTC 25 |
16258265 ps |
| T629 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_csb_read.2230654370 |
|
|
Feb 08 06:37:53 PM UTC 25 |
Feb 08 06:37:56 PM UTC 25 |
83112963 ps |
| T630 |
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.1204241719 |
|
|
Feb 08 06:37:54 PM UTC 25 |
Feb 08 06:37:57 PM UTC 25 |
131444222 ps |